Slave device, replaceable accessory and communication method

Abstract

Provided in the embodiments of the present application are a slave device, a replaceable accessory and a communication method. Upon detecting that a clock line remains in a high-level state for a preset first duration, the slave device considers that an I2C bus is in an idle state, and then pulls a data line down to a low-level state. During the period when the slave device pulls the data line down to the low-level state, no large abnormal fluctuation occurs on the data line, thereby preventing the slave device from erroneously recognizing a starting signal. It can be understood that during the period when the data line is pulled down to a low level by the slave device, a master device and the slave device cannot communicate with each other by means of the I2C bus. In order to avoid affecting normal communication requirements on the I2C bus, a release condition is set, and when the preset release condition is met, the data line is released, such that the data line returns to the high-level state, thereby allowing the master device and the slave device to communicate normally with each other by means of the I2C bus.

Description

Slave device, replaceable accessory and communication method

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 31, 2024, with application number 202410140754.0 and application name “A chip control method, chip and replaceable accessories”, and claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 13, 2024, with application number 202411845338.7 and application name “A slave device, replaceable accessories and communication method”. The entire contents of the above two Chinese patents are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a slave device, a replaceable accessory, and a communication method. Background Art

[0003] I2C (Inter-Integrated Circuit) is a serial communication protocol that allows multiple devices to be connected to an I2C bus, enabling communication between them. The I2C bus consists of a data line (SDA) for transmitting data signals and a clock line (SCL) for transmitting clock signals.

[0004] Devices connected to the I2C bus are categorized as master devices and slave devices. Master devices initiate communication on the I2C bus, while slave devices passively respond. Specifically, when the I2C bus is idle, both the data and clock lines remain high. When the master device needs to communicate with a slave device, it can generate a start signal by pulling the data line from a high state to a low state while the clock line remains high. To stop communication with a slave device, it can generate a stop signal by pulling the data line from a low state to a high state while the clock line remains high.

[0005] However, in actual applications, there may be some signal interference, causing abnormal fluctuations in the data line. For example, when a large voltage drop occurs on the data line, the slave device may mistakenly recognize the start signal.

[0006] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0007] In view of this, the present application provides a slave device, a replaceable accessory and a communication method, so as to solve the problem in the prior art that the slave device incorrectly recognizes the start signal due to signal interference.

[0008] In a first aspect, an embodiment of the present application provides a slave device, wherein the slave device is configured to be communicatively connected to a host device via at least a clock line and a data line on a bus, and when the bus is in an idle state, the host device outputs a high level, and the slave device is configured to:

[0009] When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state;

[0010] When a preset release condition is met, the data line is released, so that the data line returns to a high level state.

[0011] In a possible implementation of the first aspect, when a preset release condition is met, releasing the data line so that the data line returns to a high level state includes:

[0012] When detecting that the clock line switches from a high level state to a low level state, releasing the data line so that the data line returns to a high level state; or,

[0013] When the low level state of the data line continues for a second time period, the data line is released so that the data line returns to a high level state.

[0014] In a possible implementation manner of the first aspect, the slave device is further configured to:

[0015] Parsing the last instruction sent by the host device;

[0016] When a preset release condition is met, releasing the data line so that the data line returns to a high level state includes:

[0017] If the last instruction is a data line pull-down instruction, then when a preset release condition is met, the data line is released so that the data line returns to a high level state;

[0018] If the last instruction is not a data line pull-down instruction, releasing the data line after a preset time delay;

[0019] The data line pull-down instruction includes the second duration, and the preset time is less than the second duration.

[0020] In a possible implementation of the first aspect, if the last instruction is a data line pull-down instruction, releasing the data line when a preset release condition is met so that the data line returns to a high level state includes:

[0021] If the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction matches the address information of the slave device, then when a preset release condition is met, releasing the data line so that the data line returns to a high level state;

[0022] If the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction does not match the address information of the slave device, the data line is released after a preset time delay.

[0023] In a possible implementation of the first aspect, after detecting that the clock line is in a high level state for a preset first time period, pulling the data line down to a low level state includes:

[0024] The timing starts when a stop signal sent by the host device is received, and after the high level state of the clock line continues for a preset first time period, the data line is pulled down to a low level state.

[0025] In a second aspect, an embodiment of the present application provides a slave device, the slave device including a data interface and a clock interface, the data interface being connected to a host device via a data line in a bus, the clock interface being connected to the host device via a clock line in the bus, the clock interface being used to receive a clock signal from the host device, and the data interface being used to send or receive a data signal; when the bus is in an idle state, the clock interface and the data interface receive a high-level signal, the slave device further including an electronic module, the electronic module being used to:

[0026] When it is detected that the signal received by the clock interface is a high-level signal for a first duration, the data line is pulled down to a low-level state;

[0027] When it is detected that a preset release condition is met, the data line is released so that the data line returns to a high level state.

[0028] In a possible implementation of the second aspect, the electronic module includes:

[0029] a control unit configured to connect to the host device at least by using the clock interface through a clock line in the bus and by using the data interface through a data line in the bus;

[0030] The peripheral circuit is used to pull the data line down to a low level state when it detects that the clock line is in a high level state for a preset first period of time; and release the data line when a preset release condition is met, so that the data line returns to a high level state.

[0031] In a possible implementation of the second aspect, the peripheral circuit includes:

[0032] a trigger unit, wherein a first end of the trigger unit is electrically connected to the clock interface; the trigger unit is configured to output a first control signal at a second end when detecting that the clock line is in a high-level state for a preset first time period; and output a second control signal at a second end when detecting that the clock line switches from a high-level state to a low-level state;

[0033] A switch unit, wherein a first end of the switch unit is electrically connected to the data interface, and a second end of the switch unit is connected to a reference potential; a control end of the switch unit is electrically connected to the second end of the trigger unit, and the switch unit is configured to turn on the switch unit and pull the data line down to a low level state when the control end of the switch unit receives a first control signal output by the second end of the trigger unit; and to disconnect the switch unit and release the data line, so that the data line returns to a high level state when the control end of the switch unit receives a second control signal output by the second end of the trigger unit.

[0034] In a possible implementation of the second aspect, the triggering unit includes:

[0035] a first resistor, wherein a first end of the first resistor is electrically connected to the clock interface;

[0036] a capacitor, wherein a first end of the capacitor is electrically connected to the second end of the first resistor, and a second end of the capacitor is connected to a second reference potential;

[0037] The first end of the first resistor is the first end of the trigger unit, and the first end of the capacitor is the second end of the trigger unit.

[0038] In a possible implementation of the second aspect, the first end of the control unit is electrically connected to the controlled end of the trigger unit, and the control unit is further configured to control the first end of the control unit to switch from the first state to the second state when the low level state of the data line lasts for a second time period;

[0039] The trigger unit is also used to, when the first end of the control unit is in the first state, the controlled end of the trigger unit is in an uncontrolled state, and the trigger unit can realize the trigger function of the switch unit; when the first end of the control unit is in the second state, the controlled end of the trigger unit is in a controlled state, and the trigger unit cannot realize the trigger function of the switch unit, so that the switch unit remains in the disconnected state.

[0040] In a possible implementation of the second aspect, the triggering unit includes:

[0041] a first resistor, wherein a first end of the first resistor is electrically connected to the clock interface;

[0042] a second resistor, wherein a first end of the second resistor is electrically connected to a first end of the control unit;

[0043] a capacitor, wherein a first end of the capacitor is electrically connected to the second end of the first resistor and the second end of the second resistor, respectively, and a second end of the capacitor is connected to a second reference potential;

[0044] The first end of the first resistor is the first end of the trigger unit, the first end of the capacitor is the second end of the trigger unit, and the first end of the second resistor is the controlled end of the trigger unit.

[0045] In a possible implementation manner of the second aspect, the triggering unit further includes:

[0046] A unidirectional conducting unit, wherein a first end of the unidirectional conducting element is electrically connected to the clock interface, a second end of the unidirectional conducting element is electrically connected to the second end of the first resistor, and the second end of the unidirectional conducting element is unidirectionally conducting toward the first end of the unidirectional conducting element.

[0047] In a possible implementation of the second aspect, the switch unit includes:

[0048] a transistor, wherein a first terminal of the transistor is electrically connected to the data interface, a second terminal of the transistor is connected to a reference potential, and a control terminal of the transistor is electrically connected to the first terminal of the capacitor;

[0049] The first end of the transistor is the first end of the switch unit, the second end of the transistor is the second end of the switch unit, and the control end of the transistor is the control end of the switch unit.

[0050] In a possible implementation of the second aspect, the switch unit includes:

[0051] a third resistor, wherein a first end of the third resistor is electrically connected to the data interface, and a second end of the third resistor is electrically connected to the first end of the transistor;

[0052] Wherein, the first end of the third resistor is the first end of the switch unit.

[0053] In a third aspect, an embodiment of the present application provides a replaceable accessory, comprising the slave device described in any one of the first aspect above or the slave device described in any one of the second aspect above.

[0054] In a fourth aspect, an embodiment of the present application provides a communication method, applied to a slave device, wherein the slave device is configured to communicate with a host device via at least a clock line and a data line on a bus, and when the bus is in an idle state, the host device outputs a high level, characterized in that the method includes:

[0055] When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state;

[0056] When a preset release condition is met, the data line is released, so that the data line returns to a high level state.

[0057] Adopt the scheme provided by the embodiment of the present application, when the slave device detects that the clock line is in a high-level state for a preset first time length, it is considered that the I2C bus is in an idle state, and the data line is pulled down to a low-level state. During the period when the slave device pulls the data line down to the low-level state, no large abnormal fluctuations will be generated on the data line, thereby avoiding the slave device from mistakenly identifying the start signal. It is understandable that when the data line is pulled down to a low level by the slave device, the host device and the slave device cannot communicate through the I2C bus. In order to avoid affecting the normal communication requirements on the I2C bus, a release condition is set. When the preset release condition is met, the data line is released, so that the data line is restored to a high-level state, and the host device and the slave device can then communicate normally through the I2C bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0059] FIG1 is a block diagram of a communication system according to an embodiment of the present application;

[0060] FIG2A is a timing diagram of a start signal provided in an embodiment of the present application;

[0061] FIG2B is a timing diagram of a stop signal provided in an embodiment of the present application;

[0062] FIG3 is a flow chart of a communication method provided in an embodiment of the present application;

[0063] FIG4A is a timing diagram of an application scenario provided by an embodiment of the present application;

[0064] FIG4B is a timing diagram of another application scenario provided by an embodiment of the present application;

[0065] FIG5 is a flow chart of another communication method provided in an embodiment of the present application;

[0066] FIG6 is a flow chart of another communication method provided in an embodiment of the present application;

[0067] FIG7 is a flow chart of another communication method provided in an embodiment of the present application;

[0068] FIG8 is a structural block diagram of a slave device provided in an embodiment of the present application;

[0069] FIG9 is a structural block diagram of another slave device provided in an embodiment of the present application;

[0070] FIG10 is a structural block diagram of another slave device provided in an embodiment of the present application;

[0071] FIG11 is a structural block diagram of another slave device provided in an embodiment of the present application;

[0072] FIG12 is a structural block diagram of another slave device provided in an embodiment of the present application;

[0073] FIG13 is a structural block diagram of a replaceable accessory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0074] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0075] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0076] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0077] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0078] Referring to Figure 1, a block diagram of a communication system provided in an embodiment of the present application is shown. As shown in Figure 1, the communication system includes a host device and multiple slave devices connected to an I2C bus, and communication between the host device and the slave devices can be achieved through the I2C bus. Specifically, the I2C bus includes a data line and a clock line, wherein the data line is used to transmit data signals and the clock line is used to transmit clock signals. In addition, in actual applications, the I2C bus may also include a power line and a ground line (not shown in the figure), and the host device can power the slave device through the power line and the ground line.

[0079] It should be noted that Figure 1 is only one possible application scenario of the embodiment of the present application and should not be construed as limiting the scope of protection of the present application. For example, in some application scenarios, there may be only one slave device; or in some application scenarios, there may be multiple master devices; and so on.

[0080] In some possible implementations, the host device is an image forming device. Exemplarily, the image forming device may be an inkjet printer, a laser printer, a 3D printer, a label printer, a dot matrix printer, or the like. Furthermore, the image forming device includes an image forming control unit and an image forming unit, wherein the image forming control unit is used to control the image forming device as a whole, and the image forming unit is used to form an image on a conveyed sheet of paper under the control of the image forming control unit based on image data. The image forming control unit may be a system on a chip (SoC), which is a miniature system composed of multiple system components and is configured to control imaging processing operations of the image forming device, such as performing linear correction, noise reduction, bad pixel removal, detail enhancement, and other processing on image data, thereby improving the quality of the image output. The image forming control unit is also used to perform processing operations related to data transmission and reception, command transmission and reception, and image printing engine control, such as transmitting and receiving data, print engine control commands, and status through an interface unit (including but not limited to a USB port, a wired network port, a wireless network port, or other interfaces). Accordingly, the slave device may be a replaceable accessory installed on the image forming device, such as a consumable. Consumables are typically ink cartridges, toner cartridges, toner cartridges, toner cartridges, ribbon cartridges, etc. Consumables may also be other easily damaged components, parts, or units (such as paper boxes, etc.) that can be installed in an image forming device and require replacement, which also fall within the technical solutions corresponding to the consumables protected by this application.

[0081] In other possible implementations, the host device may be a computer. Accordingly, the slave device may be a replaceable accessory of the computer, such as a computer peripheral device. Computer peripheral devices include a mouse, keyboard, camera, and the like, which are not specifically limited in this embodiment of the present application.

[0082] In other possible implementations, the host device is a mobile terminal (e.g., a mobile phone, tablet computer, PDA, etc.). Correspondingly, the slave device may be a replaceable accessory of the mobile terminal, such as an accessory or peripheral device / apparatus of the mobile terminal. Accessories or peripheral devices / apparatus of the mobile terminal include lithium batteries, wearable devices, etc., which are not specifically limited in the embodiments of the present application.

[0083] In addition, the slave device may also refer to a circuit unit installed on a replaceable accessory, where the circuit unit is composed of one or more hardware circuits. In some embodiments, at least part of the one or more hardware circuits includes a processor.

[0084] The master device and the slave device need to be determined in specific scenarios. A master device in one scenario may be a slave device in another scenario. Similarly, a slave device in one scenario may be a master device in another scenario.

[0085] One possible implementation of consumables for image forming devices is a separate structure, comprising a detachable drum cartridge and a developer cartridge. The drum cartridge includes a photosensitive drum and a charging roller, while the developer cartridge includes a developer container, a developing roller, and a developer transport element. Another possible implementation is an integrated structure, for example, comprising a developer container, a developing roller, a developer transport element, a photosensitive drum, and a charging roller.

[0086] Furthermore, the consumables may also include only a housing and a developer container. It should be noted that the consumables may also be the aforementioned developer cartridge or drum cartridge. The aforementioned developer container is used to contain developers such as toner, and the developer conveying element is a component such as a powder feeding roller or a powder feeding screw for stirring and / or conveying toner. Of course, the aforementioned developer cartridge may also include only the aforementioned developer container, which is not limited here. Furthermore, the aforementioned developer cartridge may also include only the aforementioned developer container and the developer conveying element, which is not limited here.

[0087] In one possible implementation, the consumables may also include a powder cartridge and / or an imaging assembly, and the powder cartridge is used to transport toner to the imaging assembly when the toner contained in the imaging assembly is insufficient, so that the image forming device forms an image based on the toner transported by the imaging assembly. When the consumable is a powder cartridge, the consumable may include only a housing and a developer container, or may include a housing, a developer container, and a developer transport element, which is not limited in this embodiment of the present application. When the consumable is an imaging assembly, the consumable may include a housing, a developer container, a developer transport unit, a charging roller, a photosensitive drum, etc., which is not limited in this embodiment of the present application.

[0088] In the standard I2C protocol, when the I2C bus is idle, the master device outputs a high level, maintaining both the data and clock lines high. When the master device needs to communicate with a slave device, it can generate a start signal by pulling the data line from a high level to a low level while the clock line remains high, as shown in Figure 2A. When the master device needs to stop communicating with the slave device, it can generate a stop signal by pulling the data line from a low level to a high level while the clock line remains high, as shown in Figure 2B. However, in practical applications, signal interference may occur, causing abnormal fluctuations in the data line. For example, when the I2C bus is idle, both the data and clock lines remain high. If a large voltage drop occurs on the data line during this time, the slave device may mistakenly recognize the start signal.

[0089] In response to the above problems, an embodiment of the present application provides a communication method, when the slave device detects that the clock line is in a high-level state for a preset first period of time, it is considered that the I2C bus is in an idle state, and the data line is pulled down to a low-level state. During the period when the slave device pulls the data line down to the low-level state, no large abnormal fluctuations will be generated on the data line, thereby avoiding the slave device from mistakenly identifying the start signal. It is understandable that when the data line is pulled down to a low level by the slave device, the host device and the slave device cannot communicate through the I2C bus. In order to avoid affecting the normal communication needs on the I2C bus, a release condition is set. When the preset release condition is met, the data line is released, so that the data line returns to a high-level state, and the host device and the slave device can then communicate normally through the I2C bus. The following is a detailed description.

[0090] Referring to FIG3 , there is shown a flow chart of a communication method provided in an embodiment of the present application. This method can be applied to the slave device in the communication system described in FIG1 . The slave device communicates with the master device, and the slave device is configured to communicate with the master device via at least a clock line and a data line on a bus. When the bus is in an idle state, the master device outputs a high level, causing the clock line and the data line to remain in a high level state. As shown in FIG3 , the method includes:

[0091] Step S301: after detecting that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state.

[0092] In actual applications, the CPU of the slave device can usually only operate in a single thread and cannot process two things in parallel at the same time. Therefore, it is necessary to confirm that the current communication is completed after receiving a trigger signal of the communication protocol before starting to judge whether the data line needs to be lowered and then executing step S301.

[0093] As shown in Figures 4A and 4B, in the standard I2C protocol, after sending a byte of data, the sender releases the data line and waits for the receiver to pull down the data line to send an ACK signal (a low-level data bit). After completing the reception of a byte of data, the receiver pulls down the data line to send an ACK signal. If the data transmission is complete, the host device will pull up the data line from a low level state to a high level state when the clock line is in a high level state, generating a stop signal to indicate that communication has stopped. Therefore, in the embodiment of the present application, the determination of whether to pull down the data line can only be initiated after the slave device receives the stop signal. It is understandable that after the host device sends the stop signal, if the clock line remains in a high level state, it indicates that the I2C bus has entered an idle state. Therefore, in the embodiment of the present application, after receiving the stop signal, the slave device begins to detect the duration of the clock line in the high level state. When the duration of the clock line in the high level state reaches a preset first duration, it is confirmed that the I2C bus has entered an idle state and then pulls down the data line to a low level state.

[0094] In an embodiment of the present application, the slave device may start timing the first duration immediately after receiving the stop signal, i.e., the starting point of the first duration is the moment when the slave device receives the stop signal; or the slave device may delay timing the first duration for a certain period of time after receiving the stop signal, i.e., the starting point of the first duration is the moment when the slave device delays timing the first duration for a certain period of time after receiving the stop signal. It is understood that using the moment when the slave device receives the stop signal as the starting point of the first duration can improve the sensitivity of the slave device in determining the idle state of the I2C bus.

[0095] Exemplarily, the first duration can be 3ms, 4ms, etc.; or, the first duration can be represented by the number of cycles of the clock signal, for example, the first duration can be 0.5 cycles or 1 cycle, etc. It is understandable that when the first duration is set to be short, the slave device has a higher sensitivity to the judgment of the I2C bus idle state, but misjudgment may occur; when the first duration is set to be long, the slave device has a lower sensitivity to the judgment of the I2C bus idle state, but higher reliability. Therefore, those skilled in the art can set the size of the first duration according to actual needs, and the embodiments of the present application do not impose specific limitations on this.

[0096] In an embodiment of the present application, when a slave device receives a high-level signal via a clock line, it can detect the duration of the high-level signal received via the clock line. If it is detected that the duration of the high-level signal received via the clock line is a first duration, it indicates that the I2C bus is in an idle state. In some embodiments, to reduce the possibility of erroneously identifying the start signal, the data line can be pulled down to a low-level state. In this way, no large abnormal fluctuations will occur on the data line, thereby reducing the probability of the slave device erroneously identifying the start signal.

[0097] Step S302: When a preset release condition is met, the data line is released so that the data line returns to a high level state.

[0098] It is understood that when the data line is pulled low by the slave device, the master device and the slave device cannot communicate via the I2C bus. To avoid affecting normal communication on the I2C bus, a release condition needs to be set. When the preset release condition is met, the slave device can release the data line, causing the data line to return to a high state, and the master device and the slave device can then communicate normally via the I2C bus.

[0099] As a possible implementation, when it is detected that the clock line switches from a high level state to a low level state, the data line is released so that the data line returns to a high level state. That is, in an embodiment of the present application, the release condition can be: the clock line switches from a high level state to a low level state. For ease of explanation, this release condition is referred to as a "first release condition". Or, after the low level state of the data line continues for a second duration, the data line is released so that the data line returns to a high level state. That is, in an embodiment of the present application, the release condition can also be: the low level state of the data line continues for a second duration. For ease of explanation, this release condition is referred to as a "second release condition". That is, the preset release condition can be set to: the clock line switches from a high level state to a low level state, and / or, the low level state of the data line continues for a second duration.

[0100] At this time, when the preset release condition is met, releasing the data line so that the data line returns to a high level state includes:

[0101] When it is detected that the clock line switches from a high level state to a low level state, the data line is released so that the data line returns to a high level state. Alternatively, when the low level state of the data line lasts for a second time period, the data line is released so that the data line returns to a high level state.

[0102] Specifically, to avoid disrupting normal communication between the master and slave devices via the I2C bus, a release condition needs to be set when the data interface of the slave device is electrically connected to the fixed potential terminal. This condition disconnects the data interface from the fixed potential terminal, allowing normal communication between the master and slave devices via the I2C bus. The release condition can be configured to include: the clock line switching from a high-level state to a low-level state, and / or the data line remaining in the low-level state for a second duration.

[0103] That is, the preset release condition setting includes when the clock line switches from a high-level state to a low-level state. When the host device needs to transmit data, it will restore the clock signal on the clock line, that is, convert the high-level signal on the clock line into a pulse signal that switches between high and low levels. In order to avoid affecting the normal communication on the I2C bus, when the host device restores the clock signal on the clock line, the slave device needs to release the data line immediately. Therefore, the first release condition is set to: the clock line switches from a high-level state to a low-level state. For example, in the application scenario shown in Figure 4A, when the slave device pulls the data line low for a period of time t0, the slave device detects the falling edge of the clock signal, indicating that the first release condition is met, and then releases the data line, so that the data line returns to a high-level state, and the host device and the slave device can then communicate normally through the I2C bus.

[0104] And / or, the preset release condition includes when the low-level state of the data line lasts for a second time period, so that when the low-level state of the data line lasts for the second time period, the data line can be released, so that the data line can be restored to a high-level state. For example, in the application scenario shown in Figure 4B, when the slave device pulls the data line low for a time period t1, the pull-down time period is equal to the second time period, indicating that the second release condition is met, and the data line is released, so that the data line is restored to a high-level state, and the host device and the slave device can then communicate normally via the I2C bus.

[0105] The second duration may be data preset in the slave device, or data carried in a data line pull-down instruction sent by the host device to the slave device. An embodiment of "the host device sending a data line pull-down instruction to the slave device" is described in detail below.

[0106] It should be understood that when the preset release condition includes the clock line switching from a high-level state to a low-level state and the data line remaining in the low-level state for a second duration, then upon detecting that the clock line switches from a high-level state to a low-level state, or upon detecting that the data line remains in the low-level state for the second duration, the data line is released, allowing the data line to return to a high-level state, so that the host device and the slave device can then communicate normally via the I2C bus. In this way, the first release condition and the second release condition are set simultaneously, and when either release condition is met, the electrical connection between the data interface and the fixed potential terminal can be disconnected, releasing the data line, allowing the data line to return to a high-level state.

[0107] Exemplarily, in the application scenario shown in FIG4A , a first release condition and a second release condition are set simultaneously. When the slave device pulls down the position in the data line electrically connected to the data interface for a duration t0, the slave device detects the falling edge of the clock signal, i.e., the first release condition is satisfied. At this time, since the pull-down duration t0 is less than the second duration, the second release condition has not yet been satisfied. In the embodiment of the present application, the data line is directly released when the first release condition is satisfied, so that the data line returns to a high level state.

[0108] For example, in the application scenario shown in FIG4B , a first release condition and a second release condition are set simultaneously. When the slave device pulls the data line low for a duration t1, the duration of the pull-down is equal to the second duration, i.e., the second release condition is satisfied. At this time, since the slave device has not yet detected the falling edge of the clock signal, the first release condition has not yet been satisfied. In this embodiment of the present application, when the second release condition is satisfied, the data line is directly released, causing the data line to return to a high level state.

[0109] Under normal circumstances, according to the setting of the second time duration, the second release condition is usually met first, that is, the end time of the second time duration is usually earlier than the time when the clock signal is restored, so as to leave sufficient idle time for the data line to avoid affecting the reception of the first instruction by the slave device after the data line is released.

[0110] In summary, in an embodiment of the present application, when the slave device detects that the I2C bus is in an idle state after being in a high-level state for a preset first period of time, the data line is pulled down to a low-level state. During the period when the slave device pulls the data line down to the low-level state, no large abnormal fluctuations will occur on the data line, thereby avoiding the slave device from mistakenly identifying the start signal. In addition, in order to avoid affecting the normal communication on the I2C bus, a release condition is set. When the preset release condition is met, the data line is released, so that the data line returns to a high-level state, and the host device and the slave device can then communicate normally through the I2C bus.

[0111] Referring to Figure 5 , which is a flow chart of another communication method provided in an embodiment of the present application, the method can be applied to the communication system shown in Figure 1 , and as shown in Figure 5 , it mainly includes the following steps.

[0112] Step S501: The host device sends the last instruction to the slave device.

[0113] In one possible implementation, the slave device needs to execute a data line pull-down operation based on an instruction from the master device. The last instruction sent by the master device to the slave device may be a data line pull-down instruction or another instruction. The slave device can determine the instruction type only after parsing the instruction.

[0114] Step S502: After the slave device detects that the clock line is in a high level state for a preset first period of time, it pulls the data line down to a low level state.

[0115] In an embodiment of the present application, it takes a certain amount of time, for example, 5ms, for the slave device to parse a command. If the slave device determines whether the "clock line remains high for the first preset duration" condition is met after parsing the last command, the slave device's response speed will be slow. To improve the slave device's response speed, the slave device's parsing result of the last command sent by the master device is not considered. When it determines that the "clock line remains high for the first preset duration" condition is met, the data line is directly pulled down to a low state.

[0116] Step S503: The slave device parses the last instruction sent by the host device.

[0117] In an embodiment of the present application, the slave device parses the last instruction sent by the host device to determine whether the last instruction sent by the host device is a data line pull low instruction. If the last instruction is a data line pull low instruction, the last instruction generally includes a second duration, that is, the data line pull low instruction generally includes a second duration. Specifically, the last two bytes of the data line pull low instruction can be used to represent the second duration. For example, when the data line pull low instruction is 65 31 00 22 in hexadecimal, the last two bytes are 00 22, which is 34 in decimal, so the second duration is 34ms.

[0118] Step S504: If the last instruction is a data line pull-down instruction, then when it is detected that a preset release condition is met, the slave device releases the data line, so that the data line returns to a high level state.

[0119] If the last instruction is parsed as a data line pull-down instruction, the master device allows the slave device to execute the data line pull-down operation, and the slave device can maintain the data line pull-down state. When the preset release condition is met, the slave device releases the data line, causing the data line to return to a high level state. The specific details of the release condition can be found in the description above and are not repeated here for the sake of brevity.

[0120] In one possible implementation, the data line pull-down instruction may further include the address information of the target slave device, that is, the host device only allows the target slave device to perform the data line pull-down operation. In this case, after receiving the data line pull-down instruction, the slave device can obtain the address information of the target slave device carried in the data line pull-down instruction through the data line pull-down instruction, and determine whether the address information of the target slave device matches the address information of the slave device itself. It is understandable that if the address information of the target slave device matches the address information of the slave device itself, it indicates that the slave device is the target slave device, and the data line pull-down operation can be performed. If the address information of the target slave device does not match the address information of the slave device itself, it indicates that the slave device is not the target slave device, and the data line pull-down operation cannot be performed.

[0121] Among them, if the last instruction is a data line pull-down instruction, and the address information in the last instruction matches the address information of the slave device, it means that the host device allows the slave device to perform the data line pull-down operation, then the slave device can maintain the state of pulling the data line low, and when the preset release condition is met, release the data line, so that the data line returns to a high level state.

[0122] If the last instruction is a data line pull-down instruction, but the address information in the last instruction does not match the address information of the slave device, the master device will not allow the slave device to execute the data line pull-down operation. Since the slave device has already executed the data line pull-down operation in step S502, the slave device needs to release the data line immediately or release the data line after a preset delay.

[0123] For example, in the application scenario shown in Figure 1, the last instruction sent by the host device is a data line pull-down instruction. The address information of the target slave device in the data line pull-down instruction is the address information of slave device 2. That is, the host device instructs slave device 2 to perform the data line pull-down operation. It can be understood that all slave devices mounted on the I2C bus can receive the data line pull-down instruction sent by the host device.

[0124] When the slave device 2 receives the data line pull low instruction, it determines that the address information in the data line pull low instruction matches the address information of the slave device 2, indicating that the host device allows the slave device 2 to perform the data line pull low operation. Then the slave device 2 can keep the data line pulled low and release the data line when the preset release condition is met.

[0125] When other slave devices, such as slave device 1, receive the data line pull-down instruction, they determine that the address information in the data line pull-down instruction matches the address information of slave device 1, indicating that the host device does not allow slave device 1 to perform the data line pull-down operation. Then, slave device 1 releases the data line immediately, or releases the data line after a delay.

[0126] In one possible implementation, the slave device releases the data line after a delay of a preset time, specifically including: the slave device starts timing after executing the data line pull-down operation, and releases the data line after timing to the preset time, that is, achieving the effect of "releasing the data line after a delay of a period of time".

[0127] It should be noted that the preset time should be greater than the time required for the slave device to parse the last instruction.

[0128] Step S505: If the last instruction is not a data line pull-down instruction, the slave device releases the data line.

[0129] The preset time is shorter than the second time duration.

[0130] In this embodiment of the present application, if the last instruction is not a data line pull-down instruction, it means that the master device does not allow the slave device to execute the data line pull-down operation. Since the slave device has already executed the data line pull-down operation in step S502, the slave device needs to release the data line immediately or release the data line after a delay.

[0131] It should be noted that in some possible implementations, the slave device may not perform the data line pull-down operation based on the instruction of the host device. That is, when the slave device determines that the condition of "the clock line is in a high-level state for a preset first period of time" is met, it directly performs the data line pull-down operation without being restricted by other conditions.

[0132] Referring to Figure 6 , which is a flow chart of another communication method provided in an embodiment of the present application, the method can be applied to the host device described in Figure 1 , and as shown in Figure 6 , it mainly includes the following steps.

[0133] Step S601: The host device sends a data line pull-down instruction.

[0134] Specifically, the data line pull-down instruction includes a second duration and address information of a target slave device. The data line pull-down instruction is used to instruct the target slave device to electrically connect the data interface to the fixed potential terminal for the second duration. That is, the data line pull-down instruction is used to instruct the target slave device to pull the data line to a low-level state for the second duration. The target slave device is any one of the at least one slave devices.

[0135] It should be noted that the specific content of the target slave device pulling down the data line can be found in the above description, and for the sake of brevity, it will not be repeated here.

[0136] Step S602: Detect the duration of the low level state on the data line to obtain a third duration.

[0137] In an embodiment of the present application, if the target slave device is a legitimate device, it can usually correctly perform the pull-down operation of the data line, that is, it can usually pull the data line down to a low level state according to the instruction of the data line pull-down instruction, and continue for a second duration. If the target slave device is an illegal device, it cannot usually correctly perform the pull-down operation of the data line, that is, it will not usually pull the data line down to a low level state according to the instruction of the data line pull-down instruction, and continue for a second duration. Based on this principle, the host device can determine whether to pass the authentication of the target slave device by detecting the duration of the low level state on the data line (i.e., the pull-down duration). For ease of explanation, the duration of the low level state detected by the host device on the data line is referred to as the "third duration".

[0138] Step S603: If the third time length matches the second time length, the target slave device is authenticated.

[0139] Specifically, if the third duration matches the second duration, it indicates that the target slave device correctly performs the data line pull-down operation, and the target slave device is a legitimate device, and the authentication of the target slave device is passed.

[0140] Step S604: If the third time duration does not match the second time duration, the target slave device is not authenticated.

[0141] Specifically, if the third duration does not match the second duration, it indicates that the target slave device does not correctly execute the data line pull-down operation, and the target slave device is an illegal device, and the authentication of the target slave device fails.

[0142] In one possible implementation, the data line pull-down instruction may not include the address information of the target slave device, but only include the second duration. It is understood that, upon receiving the data line pull-down instruction, each slave device on the data line can execute the data line pull-down operation. It is understood that if any slave device correctly executes the data line pull-down operation, the third duration detected by the host device on the data line matches the second duration. If the third duration detected by the host device on the communication bus does not match the second duration, it indicates that all slave devices mounted on the communication bus are illegal devices.

[0143] In the embodiment of the present application, the host device authenticates the slave device based on the duration of the data line being pulled low, thereby preventing the slave device from mistakenly recognizing the start signal and ensuring the security of the communication process.

[0144] 7 is a flow chart of another communication method provided in an embodiment of the present application. The method can be applied to the host device described in FIG1 , and as shown in FIG7 , it mainly includes the following steps.

[0145] Step S701: The host device sends a data line pull-down instruction.

[0146] Specifically, the data line pull-down instruction includes the second duration and address information of the target slave device. The data line pull-down instruction is used to instruct the target slave device to pull the data line down to a low level state for the second duration, wherein the target slave device is any one of the at least one slave device.

[0147] It should be noted that the specific content of the target slave device executing the data line pull-down operation can be found in the above description, and for the sake of brevity, it will not be repeated here.

[0148] Step S702: When the data line is in a low level state, detecting the voltage value on the data line.

[0149] The data line being in a low level state may refer to a position in the data line electrically connected to the data interface being in a low level state.

[0150] Specifically, due to the presence of voltage-dividing resistors between the physical locations of multiple slave devices on the I2C bus, the voltage values ​​actually pulled down by slave devices at different physical locations can differ. Based on this principle, the physical location of a slave device can be determined. Specifically, the voltage value on the data line is detected when the data line is in a low state.

[0151] Step S703: Determine the physical location of the target slave device according to the voltage value.

[0152] It is understood that after the host device sends a data line pull-down instruction, the target slave device executes the data line pull-down operation. Therefore, the voltage value detected by the host device when the data line is in a low-level state reflects the physical location of the target slave device. Specifically, the host device may also have a mapping relationship between voltage values ​​and physical locations. After obtaining the voltage value, the host device can determine the physical location of the target slave device based on the voltage value and the mapping relationship between voltage values ​​and physical locations.

[0153] In an embodiment of the present application, the host device determines the physical location of the target slave device based on the voltage value of the data line when it is in a low level state, thereby preventing the slave device from mistakenly recognizing the start signal and identifying the physical location of the slave device.

[0154] Corresponding to the above method embodiment, an embodiment of the present application further provides a slave device, which is configured to communicate with a master device via at least a clock line and a data line on a bus. When the bus is in an idle state, the master device outputs a high level, causing the clock line and the data line to remain in a high state. The slave device is configured to execute some or all of the steps performed by the slave device in the above method embodiment.

[0155] For the specific contents involved in the embodiments of this application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0156] Corresponding to the above method embodiment, an embodiment of the present application further provides a host device, which is configured to communicate with at least one slave device via at least a clock line and a data line on a bus. When the bus is in an idle state, the host device outputs a high level, causing the clock line and the data line to remain in a high state. The host device is configured to execute some or all of the steps performed by the host device in the above method embodiment.

[0157] For the specific contents involved in the embodiments of this application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0158] It is understood that, in a specific implementation, the control logic in the above-described method embodiments can be implemented by software in a slave device. Furthermore, some or all of the control logic in the above-described method embodiments can also be implemented by designing corresponding hardware circuits. Specifically, the slave device includes an electronic module configured to execute some or all of the steps performed by the slave device in the above-described method embodiments.

[0159] For the specific contents involved in the embodiments of this application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0160] Referring to FIG8 , a block diagram of a slave device according to an embodiment of the present application is shown. The slave device communicates with a host device, and the slave device includes a data interface and a clock interface. The data interface is connected to the host device via a data line in a bus, and the clock interface is connected to the host device via a clock line in the bus. The clock interface is used to receive a clock signal from the host device, and the data interface is used to send or receive a data signal. When the bus is in an idle state, the clock interface and the data interface receive a high-level signal. The slave device also includes an electronic module, which is used to pull the data line down to a low-level state when it detects that the signal received by the clock interface is a high-level signal for a first duration.

[0161] When it is detected that the preset release condition is met, the data line is released so that the data line returns to a high level state.

[0162] As a possible implementation, as shown in FIG8 , the electronic module of the slave device includes a control unit 810 and peripheral circuits.

[0163] The control unit 810 is configured to connect to the host device using at least a clock interface via a clock line in the bus and a data interface via a data line in the bus. In this manner, the control unit 810 can receive clock signals from the host device via the clock interface and data signals from the host device via the data interface. Alternatively, the control unit 810 can send data signals to the host device via the data interface. When the bus is idle, the control unit 810 can receive high-level signals from the host device via the clock line via the clock interface and high-level signals from the host device via the data line via the data interface.

[0164] In some embodiments, the data interface can be represented by SDA and the clock interface can be represented by CLK to achieve communication connection between the slave device and the host device. In this way, the control unit 810 can connect the data line via the SDA interface and the clock line via the CLK interface, as shown in Figure 8. In other embodiments, the control unit 810 also includes a VCC interface and a GND interface. The VCC interface and the GND interface are used to connect the power line to provide power to the slave device. Exemplarily, the control unit 810 can be an MCU, FPGA, CPU, DSP, etc., and the embodiments of the present application do not impose specific limitations on this.

[0165] The peripheral circuit is used to pull the data line down to a low level state when it detects that the clock line is in a high level state for a preset first period of time; when a preset release condition is met, the data line is released so that the data line returns to a high level state.

[0166] For example, the peripheral circuit can detect that the signal received by the clock interface is a high-level signal, and when the duration of receiving the high-level signal is a first duration, the data line is pulled down to a low-level state; when the preset release condition is met, the data line is released so that the data line returns to a high-level state.

[0167] For the specific contents involved in the embodiments of this application, please refer to the description of the above embodiments. For the sake of brevity, they will not be repeated here.

[0168] 9 is a block diagram of another slave device according to an embodiment of the present application. As shown in FIG9 , based on the embodiment shown in FIG8 , the peripheral circuit of the embodiment of the present application specifically includes a trigger unit 820 and a switch unit 830 .

[0169] A first terminal 820A of the trigger unit 820 is electrically connected to the clock interface. The trigger unit 820 is configured to output a first control signal at its second terminal when detecting that a signal received by the clock interface is at a first level for a first duration. The trigger unit 820 outputs a second control signal at its second terminal when detecting that the signal received by the clock interface changes from the first level to a third level.

[0170] That is, the trigger unit 820 is configured as follows: when it is detected that the clock line is in a high-level state for a preset first period of time, the second end 820B of the trigger unit 820 outputs a first control signal; when it is detected that the clock line switches from a high-level state to a low-level state, the second end 820B of the trigger unit 820 outputs a second control signal.

[0171] The first end 830A of the switch unit 830 is electrically connected to the data interface, and the second end 830B of the switch unit 830 is connected to a reference potential. The control end of the switch unit 830 is electrically connected to the second end of the trigger unit 820. The switch unit 830 is configured to, when the control end of the switch unit 830 receives a first control signal output by the second end 820B of the trigger unit 820, turn on the switch unit 830 and pull the data line to a low level. For example, after the switch unit 830 is turned on, the data interface is electrically connected to the reference potential, thereby pulling the data line to a low level. When the control end of the switch unit 830 receives a second control signal output by the second end of the trigger unit 820, the switch unit 830 turns off, releasing the data line, and returning the data line to a high level. For example, after the switch unit 830 is turned off, the data interface is disconnected from the reference potential, thereby releasing the data line and returning the data interface to a state of receiving a second level signal.

[0172] It is understood that according to the above configuration of the trigger unit 820 and the switch unit 830, when the trigger unit 820 detects that the clock line is in a high-level state for a preset first duration, that is, when it detects that the clock interface has been continuously receiving a high-level signal for the first duration, it can output a first control signal to turn on the switch unit 830, thereby connecting the data interface to the reference potential and pulling the data line to a low-level state. When the trigger unit 820 detects that the signal received by the clock interface changes from a high-level signal to a low-level signal, that is, when it detects that the clock line switches from a high-level state to a low-level state (satisfying the first release condition), it can output a second control signal to turn off the switch unit 830, thereby disconnecting the electrical connection between the data interface and the reference potential, releasing the data line, and returning the data interface to a state of receiving the second-level signal.

[0173] That is to say, in the embodiment of the present application, the control logic of "when the clock line is in a high-level state for a preset first period of time, the data line is pulled down to a low-level state; when the clock line switches from a high-level state to a low-level state, the data line is released and the data line returns to a high-level state" can be implemented through the trigger unit 820 and the switch unit 830.

[0174] Referring to Figure 10 , which is a block diagram of another slave device according to an embodiment of the present application, as shown in Figure 10 , in this embodiment of the present application, trigger unit 820 includes a first resistor R1 and a capacitor C. A first end of the first resistor R1 is electrically connected to the clock interface. A first end of the capacitor C is electrically connected to a second end of the first resistor R1, and a second end of the capacitor C is connected to a reference potential.

[0175] The first end of the first resistor R1 is the first end 820A of the trigger unit 820 , and the first end of the capacitor C is the second end 820B of the trigger unit 820 .

[0176] The switch unit 830 includes a transistor T. A first terminal of the transistor T is electrically connected to the data interface, a second terminal of the transistor T is connected to the reference potential, and a control terminal of the transistor T is electrically connected to a first terminal of the capacitor C.

[0177] The first end of the transistor T is the first end 830A of the switch unit 830 , the second end of the transistor T is the second end 830B of the switch unit 830 , and the control end of the transistor T is the control end 830C of the switch unit 830 .

[0178] In this way, when the clock interface receives a high level signal, the first resistor R1 draws power through the clock terminal to charge the capacitor C. When the duration of the clock interface receiving the high level signal reaches the predetermined duration (first duration) required for the capacitor C to be fully charged, the capacitor C is fully charged. At this time, the voltage at the first end of the capacitor C can reach the on-voltage threshold of the transistor T, thereby turning on the transistor T, connecting the data interface to the reference potential, and discharging the data line through the third resistor R3 and the transistor T to the reference potential, thereby pulling the data line down to a low level state. When the signal received by the clock interface is a clock signal, the clock interface receives a low level signal (satisfying the first release condition), and the capacitor C discharges. When the voltage at the first end of the capacitor C is lower than the on-voltage threshold of the transistor T, the transistor T is turned off, so that the data interface is disconnected from the reference potential, releasing the control of the data line, and the data line is restored to a high level state.

[0179] In other words, the circuit structure of trigger unit 820 and switch unit 830 shown in FIG10 can implement the control logic of "pulling the data line down to a low level when the clock line remains in a high-level state for a preset first period of time; and releasing the data line and restoring it to a high level when the clock line switches from a high-level state to a low-level state." It should be noted that the first control signal output by second terminal 820B of trigger unit 820 is "the high-level signal generated by the first terminal of capacitor C," and the second control signal output by second terminal 820B of trigger unit 820 is "the low-level signal generated by the first terminal of capacitor C."

[0180] As a possible implementation, the trigger unit 820 further includes a diode D. The cathode of the diode D is electrically connected to the clock interface. The anode of the diode D is electrically connected to the first end of the capacitor C, as shown in FIG10 . Thus, when the capacitor C is discharged, the capacitor C can discharge to the clock interface through the first resistor R1 and the diode D. Since the discharge speed of the diode D is relatively fast after being turned on, the voltage at the first end of the capacitor C will drop rapidly, thereby increasing the cutoff speed of the transistor T and the speed at which the data interface is disconnected from the reference potential.

[0181] As a possible implementation, to improve the reliability of the switch module 830, the switch unit 830 further includes a third resistor R3, as shown in FIG10 . A first end of the third resistor R3 is electrically connected to the data interface, and a second end of the third resistor R3 is electrically connected to the first end of the transistor T. The third resistor R3 can be used to limit current to protect the transistor T and the data terminal.

[0182] In addition, in actual applications, those skilled in the art can adaptively adjust the circuit structure of the trigger unit 820 and / or the switch unit 830 shown in Figure 10 according to actual needs to achieve the same functions as the trigger unit 820 and / or the switch unit 830 in this application, which should all fall within the scope of protection of this application.

[0183] For example, other unidirectional conducting elements (e.g., transistors) may be used to replace the diode D in the trigger unit 820 shown in FIG10 . The connection relationship of the unidirectional conducting element in the circuit shown in FIG10 is as follows: a first end of the unidirectional conducting element is electrically connected to the clock interface, a second end of the unidirectional conducting element is electrically connected to the second end of the first resistor R1, and the second end of the unidirectional conducting element is unidirectionally conductive toward the first end of the unidirectional conducting element.

[0184] For another example, the unidirectional conductive element (diode D) in the trigger unit 820 shown in FIG10 is removed. It should be noted that since the unidirectional conductive element discharges quickly after being turned on, the provision of the unidirectional conductive element can increase the discharge speed of the capacitor C when the clock interface receives a low-level signal, thereby improving the response speed of the trigger unit 820.

[0185] For another example, the third resistor R3 in the switch unit 830 shown in Figure 10 is removed. It should be noted that when the third resistor R3 in the switch unit 830 is removed, the first end of the transistor T is directly connected to the data interface. At this time, the first end of the transistor T is the first end 830A of the switch unit 830. In addition, in the embodiment of the present application, the function of the third resistor R3 is to limit the current to prevent the data terminal from burning. However, when the reference potential connected to the second end 830B of the switch unit 830 is high (non-grounded), the current flowing through the data line itself will not be too large, so there is no need to worry about burning the data line. Therefore, in some application scenarios, removing the third resistor R3 in the switch unit 830 will not affect the operation of the entire circuit.

[0186] It should be noted that the above adjustments to the trigger unit 820 and the switch unit 830 shown in FIG10 are merely exemplary descriptions of the embodiments of the present application. Those skilled in the art may also make other adjustments to the trigger unit 820 and / or the switch unit 830 shown in FIG10 as needed, and the embodiments of the present application do not impose specific limitations thereto.

[0187] It is understandable that according to the circuit structure shown in Figures 9 and 10, it can only release the data line when the first release condition is met (the clock line switches from a high level state to a low level state). As mentioned above, in addition to the first release condition, a second release condition can also be set (the low level state of the data line lasts for a second duration). In order to enable the slave device to release the data line when the second release condition is met, the embodiment of the present application configures the second release condition in the control unit 810, and when the second release condition is met, the trigger unit 820 is intervened through an I / O port on the control unit 810, so that the second control signal output by the trigger unit 820 is released, thereby releasing the data line. Detailed description will be given below in conjunction with specific implementation methods.

[0188] Referring to Figure 11, a block diagram of the structure of another slave device provided in an embodiment of the present application. As shown in Figure 11, based on the embodiment shown in Figure 9, the control unit 810 in the embodiment of the present application further includes a first end 810A, and the first end 810A of the control unit 810 is an I / O port. The trigger unit 820 also includes a controlled end 820C, and the controlled end 820C of the trigger unit 820 is electrically connected to the first end 810A of the control unit 810. It can be understood that the control unit 810 can control the output state of the I / O port (for example, a floating state, a low level state, etc.), and thus can intervene in the trigger unit 820 through the output state of the first end 810A of the control unit 810.

[0189] Specifically, the first end 810A of the control unit 810 maintains a first state (for example, a floating state) by default. In the first state, the controlled end 810C of the control unit 810 is in an uncontrolled state, and the trigger unit 820 can realize the trigger function of the switch unit 830, that is, it can trigger the switch unit 830 to turn on and pull the data line down to a low level state. Specifically, the trigger unit 820 outputs a first control signal according to its own configuration after detecting that the clock line is in a high level state for a preset first time period, so that the switch unit 830 is turned on and the data line is pulled down to a low level state. In addition, in the uncontrolled state, when the trigger unit 820 detects that the clock line switches from a high level state to a low level state (meets the first release condition), it can also output a second control signal to disconnect the switch unit 830, release the data line, and restore the data line to a high level state.

[0190] When the control unit 810 detects that the low-level state of the data line continues for a second period of time (meeting the second release condition), the first end 810A of the control unit 810 is switched from the first state to the second state (for example, a low-level state). In the second state, the controlled end 810C of the control unit 810 is in a controlled state, and the trigger unit 820 cannot perform the triggering function on the switch unit 830, so that the switch unit 830 remains in the disconnected state. Specifically, the trigger unit 820 is no longer affected by the level state of the clock line. The trigger unit 820 continuously outputs the second control signal, the switch unit 830 is disconnected, the data line is released, and the data line remains in a high-level state. That is, in the embodiment of the present application, when either the first release condition or the second release condition is met, the data line is released, so that the data line returns to a high-level state.

[0191] In an embodiment of the present application, the control logic of "when the clock line is in a high-level state for a preset first period of time, the data line is pulled down to a low-level state; when the clock line switches from a high-level state to a low-level state, or when the low-level state of the data line continues for a second period of time, the data line is released and the data line returns to a high-level state" can be implemented through the control unit 810, the trigger unit 820 and the switch unit 830.

[0192] Refer to Figure 12, which is a structural block diagram of another slave device provided in an embodiment of the present application. As shown in Figure 12, in an embodiment of the present application, the trigger unit 820 includes a first resistor R1, a diode D, a second resistor R2 and a capacitor C. The first end of the first resistor R1 is electrically connected to the clock interface; the cathode of the diode D is electrically connected to the clock interface; the first end of the second resistor R2 is electrically connected to the first end of the control unit 810; the first end of the capacitor C is electrically connected to the second end of the first resistor R1, the anode of the diode D and the second end of the second resistor R2, respectively, and the second end of the capacitor C is connected to the reference potential. The switch unit 830 includes a third resistor R3 and a transistor T. The first end of the third resistor R3 is electrically connected to the data line; the first end of the transistor T is electrically connected to the second end of the third resistor R3, the second end of the transistor T is connected to the reference potential, and the control end of the transistor T is electrically connected to the first end of the capacitor C.

[0193] In an embodiment of the present application, the first end 810A of the control unit 810 remains in a floating state by default. It is understandable that when the first end 810A of the control unit 810 is in a floating state, it will not affect the trigger unit 820. Therefore, when the clock line is in a high level state, that is, when the clock interface receives a high level signal, the first resistor R1 takes power on the clock interface and continues to charge the capacitor C. When the duration of the clock interface receiving the high level signal reaches the set duration (first duration) required for the capacitor C to be fully charged, the capacitor C is fully charged. At this time, the voltage at the first end of the capacitor C can reach the turn-on voltage threshold of the transistor T, thereby turning on the transistor T, and the data interface is connected to the reference potential through the third resistor R3 and the transistor T, so that the data line is connected to the reference potential and discharged, thereby pulling the data line down to a low level state.

[0194] Thereafter, when the clock signal on the clock line is restored, a low-level signal is generated on the clock line (satisfying the first release condition), and capacitor C discharges to the clock line through first resistor R1 and diode D. Since diode D discharges rapidly after being turned on, the voltage at the first end of capacitor C decreases rapidly. When the voltage at the first end of capacitor C falls below the turn-on voltage threshold of transistor T, transistor T turns off, disconnecting the data interface from the reference potential and releasing control over the data line, causing the data line to return to a high-level state.

[0195] When the control unit 810 detects that the low-level state of the data line persists for a second duration (satisfying the second release condition), it switches the first terminal 810A of the control unit 810 from a floating state to a low-level state. At this point, the voltage at the first terminal of capacitor C rapidly decreases. When the voltage at the first terminal of capacitor C falls below the turn-on voltage threshold of transistor T, transistor T turns off, disconnecting the data interface from the reference potential and releasing control of the data line, causing the data line to remain in a high-level state.

[0196] That is to say, through the software configuration of the control unit 810 shown in Figure 12 and the circuit structure of the trigger unit 820 and the switch unit 830, the control logic of "when the clock line is in a high-level state for a preset first period of time, the data line is pulled down to a low-level state; when the clock line switches from a high-level state to a low-level state, or when the low-level state of the data line continues for a second period of time, the data line is released and the data line returns to a high-level state" can be implemented.

[0197] It should be noted that, in the embodiment of the present application, the first terminal 820A of the trigger unit 820 is "the first terminal of the first resistor R1 and the cathode of the diode D"; the second terminal 820B of the trigger unit 820 is "the first terminal of the capacitor C"; the controlled terminal 820C of the trigger unit 820 is "the first terminal of the second resistor R2"; the first terminal 830A of the switch unit 830 is "the first terminal of the third resistor R3"; the second terminal 830B of the switch unit 830 is "the second terminal of the transistor T"; and the control terminal 830C of the switch unit 830 is "the control terminal of the transistor T". The first state of the first terminal 810A of the control unit 810 is "high impedance state"; the second state of the first terminal 810A of the control unit 810 is "low level state". The first control signal output by the second terminal 820B of the trigger unit 820 is "the high level signal generated by the first terminal of the capacitor C"; and the second control signal output by the second terminal 820B of the trigger unit 820 is "the low level signal generated by the first terminal of the capacitor C".

[0198] In addition, in actual applications, those skilled in the art can adaptively adjust the circuit structure of the trigger unit 820 and / or the switch unit 830 shown in Figure 12 according to actual needs to achieve the same functions as the trigger unit 820 and / or the switch unit 830 in this application, which should all fall within the scope of protection of this application.

[0199] For example, other unidirectional conducting elements (e.g., transistors) may be used to replace the diode D in the trigger unit 820 shown in FIG12 . The connection relationship of the unidirectional conducting element in the circuit shown in FIG12 is as follows: a first end of the unidirectional conducting element is electrically connected to the clock line, a second end of the unidirectional conducting element is electrically connected to the second end of the first resistor, and the second end of the unidirectional conducting element is unidirectionally conductive to the first end of the unidirectional conducting element.

[0200] For another example, the unidirectional conductive element (diode D) in the trigger unit 820 shown in FIG12 is removed. It should be noted that since the unidirectional conductive element discharges quickly after being turned on, the provision of the unidirectional conductive element can increase the discharge speed of the capacitor C when a low-level signal is generated on the clock line, thereby improving the response speed of the trigger unit 820.

[0201] For another example, the third resistor R3 in the switch unit 830 shown in Figure 12 is removed. It should be noted that when the third resistor R3 in the switch unit 830 is removed, the first end of the transistor T is directly connected to the data interface. At this time, the first end of the transistor T is the first end 830A of the switch unit 830. In addition, in the embodiment of the present application, the function of the third resistor R3 is to limit the current to prevent the data line from burning out. However, when the fixed potential end connected to the second end 830B of the switch unit 830 is higher (not grounded), the current flowing through the data line itself will not be too large, so there is no need to worry about burning out the data line. Therefore, in some application scenarios, removing the third resistor R3 in the switch unit 830 will not affect the operation of the entire circuit.

[0202] It should be noted that the above adjustments to the trigger unit 820 and the switch unit 830 shown in FIG12 are merely exemplary descriptions of the embodiments of the present application. Those skilled in the art may also make other adjustments to the trigger unit 820 and / or the switch unit 830 shown in FIG12 as needed, and the embodiments of the present application do not impose specific limitations thereto.

[0203] It should be noted that some of the contents repeated in the above method embodiment are omitted in the embodiment shown in Figures 8 to 12. For the specific contents of the embodiment shown in Figures 8 to 12, please refer to the description of the above method embodiment. For the sake of brevity, they will not be repeated here.

[0204] Corresponding to the above embodiment, the embodiment of the present application also provides a replaceable accessory.

[0205] Referring to FIG13 , a block diagram of a replaceable accessory is provided for an embodiment of the present application. As shown in FIG13 , the replaceable accessory 1300 includes a slave device. The details of the slave device can be found in the description of the above embodiment and will not be repeated here for the sake of brevity.

[0206] Corresponding to the above embodiment, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, wherein, when the program is executed, the device containing the computer-readable storage medium may be controlled to perform some or all of the steps in the above method embodiment. In a specific implementation, the computer-readable storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0207] Corresponding to the above embodiment, an embodiment of the present application further provides a computer program product, which includes executable instructions. When the executable instructions are executed on a computer, the computer executes some or all of the steps in the above method embodiment.

[0208] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0209] Those skilled in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented using a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0210] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0211] In the several embodiments provided in this application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of this application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0212] The above description is merely a specific embodiment of the present application. Any person skilled in the art may easily conceive of variations or substitutions within the technical scope disclosed in this application, and such variations or substitutions shall be within the scope of protection of this application. The scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. A slave device, the slave device being configured to communicate with a host device via at least a clock line and a data line on a bus, and outputting a high level by the host device when the bus is in an idle state, characterized in that: The slave device is configured as: When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state; When a preset release condition is met, the data line is released, so that the data line returns to a high level state.

2. The slave device according to claim 1, wherein: When a preset release condition is met, releasing the data line so that the data line returns to a high level state includes: When detecting that the clock line switches from a high level state to a low level state, releasing the data line so that the data line returns to a high level state; or, When the low level state of the data line continues for a second period of time, the data line is released so that the data line returns to a high level state.

3. The slave device according to claim 2, wherein: The slave device is further configured to: Parsing the last instruction sent by the host device; When a preset release condition is met, releasing the data line so that the data line returns to a high level state includes: If the last instruction is a data line pull-down instruction, then when a preset release condition is met, the data line is released so that the data line returns to a high level state; If the last instruction is not a data line pull-down instruction, releasing the data line after a preset time delay; The data line pull-down instruction includes the second duration, and the preset time is less than the second duration.

4. The slave device according to claim 3, wherein: If the last instruction is a data line pull-down instruction, then when a preset release condition is met, releasing the data line so that the data line returns to a high level state includes: If the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction matches the address information of the slave device, then when a preset release condition is met, releasing the data line so that the data line returns to a high level state; If the last instruction is a data line pull-down instruction, and the address information in the data line pull-down instruction does not match the address information of the slave device, the data line is released after a preset time delay.

5. The slave device according to claim 1, wherein: The step of pulling the data line down to a low level state after detecting that the clock line is in a high level state for a preset first period of time comprises: The timing starts when a stop signal sent by the host device is received, and after the high level state of the clock line continues for a preset first time period, the data line is pulled down to a low level state.

6. A slave device that communicates with a host device, the slave device comprising a data interface and a clock interface, the data interface being connected to the host device via a data line in a bus, the clock interface being connected to the host device via a clock line in the bus, the clock interface being used to receive a clock signal from the host device, and the data interface being used to send or receive a data signal; when the bus is in an idle state, the clock interface and the data interface receive high-level signals, characterized in that The slave device further includes an electronic module, wherein the electronic module is configured to: When it is detected that the signal received by the clock interface is a high-level signal for a first duration, the data line is pulled down to a low-level state; When it is detected that a preset release condition is met, the data line is released so that the data line returns to a high level state.

7. The slave device according to claim 6, wherein: The electronic module comprises: a control unit configured to connect to the host device at least by using the clock interface through a clock line in the bus and by using the data interface through a data line in the bus; The peripheral circuit is used to pull the data line down to a low level state when it detects that the clock line is in a high level state for a preset first period of time; and release the data line when a preset release condition is met, so that the data line returns to a high level state.

8. The slave device according to claim 7, wherein: The peripheral circuit includes: a trigger unit, wherein a first end of the trigger unit is electrically connected to the clock interface; the trigger unit is configured to output a first control signal at a second end when detecting that the clock line is in a high-level state for a preset first time period; and output a second control signal at a second end when detecting that the clock line switches from a high-level state to a low-level state; A switch unit, wherein a first end of the switch unit is electrically connected to the data interface, and a second end of the switch unit is connected to a reference potential; a control end of the switch unit is electrically connected to the second end of the trigger unit, and the switch unit is configured to turn on the switch unit and pull the data line down to a low level state when the control end of the switch unit receives a first control signal output by the second end of the trigger unit; and to disconnect the switch unit and release the data line, so that the data line returns to a high level state when the control end of the switch unit receives a second control signal output by the second end of the trigger unit.

9. The slave device according to claim 8, wherein: The trigger unit includes: a first resistor, wherein a first end of the first resistor is electrically connected to the clock interface; a capacitor, wherein a first end of the capacitor is electrically connected to the second end of the first resistor, and a second end of the capacitor is connected to a reference potential; The first end of the first resistor is the first end of the trigger unit, and the first end of the capacitor is the second end of the trigger unit.

10. The slave device according to claim 8, wherein: The first end of the control unit is electrically connected to the controlled end of the trigger unit, and the control unit is further configured to control the first end of the control unit to switch from a first state to a second state when the low level state of the data line lasts for a second time period; The trigger unit is also used to, when the first end of the control unit is in the first state, the controlled end of the trigger unit is in an uncontrolled state, and the trigger unit can realize the trigger function of the switch unit; when the first end of the control unit is in the second state, the controlled end of the trigger unit is in a controlled state, and the trigger unit cannot realize the trigger function of the switch unit, so that the switch unit remains in the disconnected state.

11. The slave device according to claim 10, wherein: The trigger unit includes: a first resistor, wherein a first end of the first resistor is electrically connected to the clock interface; a second resistor, wherein a first end of the second resistor is electrically connected to a first end of the control unit; a capacitor, wherein a first end of the capacitor is electrically connected to the second end of the first resistor and the second end of the second resistor, respectively, and a second end of the capacitor is connected to a reference potential; The first end of the first resistor is the first end of the trigger unit, the first end of the capacitor is the second end of the trigger unit, and the first end of the second resistor is the controlled end of the trigger unit.

12. The slave device according to claim 9 or 11, characterized in that: The trigger unit further includes: A unidirectional conducting unit, wherein a first end of the unidirectional conducting element is electrically connected to the clock interface, a second end of the unidirectional conducting element is electrically connected to the second end of the first resistor, and the second end of the unidirectional conducting element is unidirectionally conducting toward the first end of the unidirectional conducting element.

13. The slave device according to claim 9 or 11, characterized in that: The switch unit includes: a transistor, wherein a first terminal of the transistor is electrically connected to the data interface, a second terminal of the transistor is connected to a reference potential, and a control terminal of the transistor is electrically connected to the first terminal of the capacitor; The first end of the transistor is the first end of the switch unit, the second end of the transistor is the second end of the switch unit, and the control end of the transistor is the control end of the switch unit.

14. The slave device according to claim 13, wherein: The switch unit includes: a third resistor, wherein a first end of the third resistor is electrically connected to the data interface, and a second end of the third resistor is electrically connected to the first end of the transistor; Wherein, the first end of the third resistor is the first end of the switch unit.

15. A replaceable accessory, characterized in that: The slave device comprises the slave device according to any one of claims 1 to 14.

16. A communication method, applied to a slave device, wherein the slave device is configured to communicate with a host device via at least a clock line and a data line on a bus, and when the bus is in an idle state, the host device outputs a high level, characterized in that: The method comprises: When it is detected that the clock line is in a high level state for a preset first period of time, the data line is pulled down to a low level state; When a preset release condition is met, the data line is released, so that the data line returns to a high level state.

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