Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component capable of suppressing upward wetting of molten solder and suppressing the occurrence of audible noise.　A multilayer ceramic electronic component 1 comprises: a substantially rectangular parallelepiped laminate 2 having two main surfaces A, two side surfaces B, and two end surfaces C; two external electrodes 3 respectively on the two end surfaces C; and two spacers that are respectively connected to the two external electrodes on a mounting surface, the mounting surface being one of the two main surfaces or one of the two side surfaces and facing a mounting substrate. Each of the two spacers 4 comprises two regions of an inner region 41 and an outer region 42 other than the inner region 41, the inner regions 41 facing each other in the length direction L. When a line V perpendicular to the mounting surface is drawn from the tip Pt of a base electrode layer 30 of the external electrodes 3, the inner region 41 is positioned on the inside relative to the line V in the length direction L. The inner region 41 and the outer region 42 have different porosities.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component such as a multilayer ceramic capacitor.

[0002] Multilayer ceramic electronic components such as multilayer ceramic capacitors are widely used in various electronic devices, such as mobile terminal devices such as mobile phones and personal computers. A multilayer ceramic capacitor comprises a substantially rectangular parallelepiped laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes formed on both opposing ends of the laminate.

[0003] A multilayer ceramic capacitor has an inner layer portion in which dielectric layers and internal electrodes are stacked, and dielectric layers are disposed on the top and bottom of the inner layer portion as outer layers to form a substantially rectangular parallelepiped laminate, and external electrodes are provided on both longitudinal end faces of the laminate to form a capacitor body.

[0004] Furthermore, in order to suppress the occurrence of so-called "squeak noise," a multilayer ceramic capacitor is known that includes a spacer (metal frame) formed on the side of the capacitor body that is mounted on a mounting board so as to cover part of the external electrodes (Patent Document 1).

[0005] U.S. Patent No. 9,799,453

[0006] However, when the solder is heated and melted during mounting, it flows along the surface of the spacer and rises high in the height direction of the multilayer ceramic capacitor, causing expansion and contraction vibrations in the inner layer to propagate to the mounting board, which can make it difficult to suppress the occurrence of squealing.

[0007] An object of the present invention is to provide a multilayer ceramic electronic component, such as a multilayer ceramic capacitor, which can be reliably mounted on a mounting board, and which can suppress wetting-up of molten solder and the generation of squeal.

[0008] The inventor discovered that by dividing two spacers placed on one of the main surfaces or one of the side surfaces of the laminate into two regions in the longitudinal direction, an inner region located on the inside and an outer region located on the outside, and forming the inner and outer regions so that they have different porosities, it is possible to suppress the wetting up of molten solder, and thus completed the present invention.

[0009] That is, the present invention provides a laminate including an inner layer portion in which dielectric layers and internal electrode layers are laminated, the laminate having two main surfaces opposing each other in a lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side surfaces opposing each other in a width direction intersecting the lamination direction and the length direction; two external electrodes connected to the internal electrode layers on each of the two end faces, and covering the end faces and parts of the two main surfaces or parts of the two side surfaces opposing each other; one of the two main surfaces or one of the two side surfaces of the laminate serves as a mounting surface facing a mounting board, and two spacers connected to the external electrodes on the mounting surface side, the external electrodes having a base electrode layer and a plating layer, and the two spacers each having two regions, an inner region opposing each other in the length direction, and an outer region other than the inner region, when a line perpendicular to the mounting surface is drawn from a tip of the base electrode layer covering part of the mounting surface, The inner region is located closer to the center of the laminate in the length direction than a line perpendicular to the mounting surface, and the inner region and the outer region have different porosities.

[0010] According to the present invention, mounting on a mounting board can be performed reliably, and wetting up of molten solder can be suppressed, thereby suppressing the occurrence of squealing.

[0011] 1 is a diagram showing the appearance of a multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II shown in FIG. 1. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III shown in FIG. 1. FIG. 4 is an enlarged cross-sectional view of a portion of a spacer 4 of the multilayer ceramic capacitor 1. FIG. 5 is a flowchart showing a manufacturing method of the multilayer ceramic capacitor 1. FIG. 6 is a diagram illustrating a laminate manufacturing step S1, a base electrode layer forming step S2, and a plating layer forming step S3. FIG. 7 is a cross-sectional view of the multilayer ceramic capacitor 1 on which an insulating material is arranged.

[0012] Hereinafter, a multilayer ceramic capacitor 1 will be described as an embodiment of the multilayer ceramic electronic component of the present invention, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified schematic form to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0013] (Multilayer ceramic capacitor 1) Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to an embodiment taken along line II-II in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to an embodiment taken along line III-III in Fig. 1. Note that Fig. 2 is a cross-section parallel to the length direction L and the stacking direction T, and is also referred to as an LT cross-section. Fig. 3 is a cross-section parallel to the width direction W and the stacking direction T, and is also referred to as a WT cross-section.

[0014] The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a capacitor body 1A including a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2, and a spacer 4 attached to the capacitor body 1A. The laminate 2 also includes an inner layer portion 11 in which dielectric layers 14 and internal electrode layers 15 are laminated.

[0015] In the following description, the terms used to represent the orientation of the multilayer ceramic capacitor 1 are: a length direction L, which is the direction in which a pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1; a stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked; and a width direction W, which is the direction intersecting both the length direction L and the stacking direction T. In the embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.

[0016] (Outer Surfaces of Laminate 2) Of the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T will be referred to as the first main surface A1 and the second main surface A2, a pair of outer surfaces facing each other in the width direction W will be referred to as the first side surface B1 and the second side surface B2, and a pair of outer surfaces facing each other in the length direction L will be referred to as the first end surface C1 and the second end surface C2. Note that when there is no need to particularly distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as the main surface A, when there is no need to particularly distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as the side surface B, and when there is no need to particularly distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as the end surface C.

[0017] The laminate 2 preferably has rounded ridges R1 including corners. The ridges R1 are the portions where two surfaces of the laminate 2, i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C, intersect.

[0018] (Laminate 2) The laminate 2 includes an inner layer portion 11 that forms capacitance, an outer layer portion 12 that is arranged to sandwich the inner layer portion 11 in the stacking direction T, and a side margin portion 16 that is arranged to sandwich the inner layer portion 11 and the outer layer portion 12 in the width direction W.

[0019] (Inner Layer Portion 11) The inner layer portion 11 includes dielectric layers 14 and internal electrode layers 15 stacked along the stacking direction T.

[0020] (Dielectric Layer 14) The dielectric layer 14 is made of a ceramic material, such as BaTiO ３ , SrTiO ３ The dielectric ceramic may be composed mainly of CaTiO.３ and CaZrO ３ By including a large amount of , it is possible to suppress the occurrence of dielectric breakdown in the region between the tip of the first internal electrode layer 15 a described below and the second external electrode 3 b in the length direction L, between the tip of the second internal electrode layer 15 b described below and the first external electrode 3 a in the length direction L, and between the first internal electrode layer 15 a and the second internal electrode layer 15 b.

[0021] (Internal electrode layer 15) The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. In this embodiment, the first internal electrode layers 15a and the second internal electrode layers 15b are alternately arranged. The first internal electrode layer 15a includes a first opposing portion 152a opposing the second internal electrode layer 15b and a first lead portion 151a extending from the first opposing portion 152a toward the first end face C1. An end of the first lead portion 151a is exposed at the first end face C1 and is electrically connected to a first external electrode 3a (described later). The second internal electrode layer 15b includes a second opposing portion 152b opposing the first internal electrode layer 15a and a second lead portion 151b extending from the second opposing portion 152b toward the second end face C2. The end of the second lead portion 151b is electrically connected to a second external electrode 3b (described later). Charge is accumulated in the first opposing portion 152a of the first internal electrode layer 15a and the second opposing portion 152b of the second internal electrode layer 15b.

[0022] The internal electrode layers 15 are preferably formed of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au. Furthermore, by including Sn in the internal electrode layers 15, it is possible to alleviate electric field concentration at the interface between the internal electrode layers 15 and the dielectric layers 14, thereby improving high-temperature load reliability. Note that even if Sn is included in only one of the first internal electrode layers 15a or the second internal electrode layers 15b, the effect of improving high-temperature load reliability can be obtained.

[0023] (Outer Layer Portion 12) The outer layer portion 12 can be formed of the same material as the dielectric layer 14 of the inner layer portion 11. The outer layer portion 12 can also be formed of a DLC film, an insulating resin, or the like.

[0024] (Side margin portion 16) The side margin portion 16 is arranged to sandwich the inner layer portion 11 and the outer layer portion 12 in the width direction W, and includes a first side margin portion 16a that forms a first side surface B1 of the multilayer ceramic capacitor 1, and a second side margin portion 16b that forms a second side surface B2 of the multilayer ceramic capacitor 1. The side margin portion 16 can be formed of the same material as the dielectric layer 14. Segregation of Si at the interface between the side margin portion 16 and the internal electrode layer 15 can improve the flexural strength of the multilayer ceramic capacitor.

[0025] (External electrode 3) The external electrode 3 includes a first external electrode 3a provided on the first end face C1 and a second external electrode 3b provided on the second end face C2. The external electrode 3 covers not only the end face C but also a part of the main face A and the side face B continuing from the end face C.

[0026] As described above, the end of the first lead portion 151a of the first internal electrode layer 15a is exposed at the first end face C1 and is electrically connected to the first external electrode 3a, and the end of the second lead portion 151b of the second internal electrode layer 15b is exposed at the second end face C2 and is electrically connected to the second external electrode 3b.

[0027] The external electrodes 3 include, for example, a base electrode layer 30 and a plating layer 31. However, it is not essential that the external electrodes 3 have such a layered structure. In addition, the external electrodes 3 may include a resin electrode layer to relieve stress applied to the multilayer ceramic capacitor 1.

[0028] The base electrode layer 30 is formed, for example, by applying and baking a conductive paste containing Cu as a main component. The base electrode layer 30 may also contain metal components other than Cu, glass components, and / or ceramic materials. Examples of metal components other than Cu include Mg, Cr, Sr, Al, Na, and Fe. Examples of glass components include oxides of Ba, Sr, Si, Ca, Zn, Al, or B. The metal components may include, as a main component, a component contained in the dielectric layer 14 that forms the inner layer portion 11.

[0029] The base electrode layer can be formed in a two-layer structure. When the base electrode layer has a two-layer structure, the first layer may contain a metal component and a glass component, and the second layer may contain a metal component and a resin. By including a resin in the base electrode layer, the flexural strength can be improved. Note that the second layer does not need to completely cover the first layer, and may cover only a portion of the first layer.

[0030] The plating layer contains, for example, at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The proportion of metal per unit volume of the plating layer is preferably 99% by volume or more. The plating layer preferably does not contain a glass component.

[0031] The plating layer 31 can be formed to have a two-layer structure. The two-layer structure can be formed, for example, by a Ni plating layer disposed on the surface of the base electrode layer 30 and a Sn plating layer disposed on the surface of the Ni plating layer. However, the configuration of the plating layer 31 is not limited to this.

[0032] The plating layer 31 can be formed in a three-layer structure. The three-layer structure can be formed, for example, by sequentially arranging a Sn plating layer, a Ni plating layer, and a Sn plating layer on the surface of the base electrode layer 30, or by sequentially arranging a Cu plating layer, a Ni plating layer, and a Sn plating layer. The Ni plating layer can prevent the base electrode layer from being eroded by solder, and the Sn plating layer can improve mountability.

[0033] (Spacer 4) The spacer 4 includes a pair of first and second spacers 4a and 4b. The first spacer 4a is disposed on the second main surface A2 of the capacitor body 1A, which serves as the mounting surface facing the mounting substrate, on the first end face C1 side in the longitudinal direction L, and the second spacer 4b is disposed on the other end face C2 side. Furthermore, when the mounting surface facing the mounting substrate is the first side surface B1 of the capacitor body 1A, the first spacer 4a is disposed on the first end face C1 side in the longitudinal direction L of the first side surface B1, and the second spacer 4b is disposed on the other end face C2 side.

[0034] The spacer 4 is disposed on the external electrode 3 of the capacitor body 1A and on the surface of the second main surface A2 of the laminate 2 on which no subsequent external electrode 3 is disposed. When the mounting surface facing the mounting board is the first side surface B1 of the capacitor body 1A, the spacer 4 is disposed on the external electrode 3 of the capacitor body 1A and on the surface of the first side surface B1 of the laminate 2 on which no subsequent external electrode 3 is disposed.

[0035] When the mounting surface facing the mounting substrate is the second main surface A2 of the capacitor body 1A, the spacers 4 are preferably arranged so as to protrude in the length direction L of the capacitor body 1A in plan view from the stacking direction T. That is, the first spacers 4a are arranged so as to intersect with a line extending in the stacking direction T from the vertex that is the thickest portion of the first external electrode 3a in the length direction L, and the second spacers 4b are arranged so as to intersect with a line extending in the stacking direction T from the vertex that is the thickest portion of the second external electrode 3b in the length direction L. In this case, it is preferable that the spacers are not arranged so as to protrude by 10 μm or more. Furthermore, when the mounting surface facing the mounting substrate is the first side surface B1 of the capacitor body 1A, the spacers 4 are preferably arranged so as to protrude in the length direction L of the capacitor body 1A in plan view from the width direction W. That is, the first spacer 4a is arranged so as to intersect with a line extending in the width direction T from the vertex, which is the thickest part in the length direction L, of the first external electrode 3a, and the second spacer 4b is arranged so as to intersect with a line extending in the width direction W from the vertex, which is the thickest part in the length direction L of the second external electrode 3b. In this case, it is preferable that the spacers are not arranged so as to protrude by 10 μm or more. By arranging the first spacer 4a and the second spacer 4b in this manner, the area where the spacer 4 and the external electrode 3 are connected can be increased, thereby improving the bonding strength between the spacer 4 and the capacitor body 1A.

[0036] In the embodiment, the external electrode 3 is composed of a base electrode layer 30 and a plating layer 31 covering it, and the spacer 4 is placed on the surface of the plating layer 31. However, the plating layer 31 is not necessarily required, and for example, the spacer 4 may be placed on the surface of the base electrode layer 30.

[0037] The spacer 4 can contain various components such as metal components and resin components, but if it contains a large amount of metal components, for example, the ratio of the volume of the metal components to the surface area increases, thereby reducing the ESR of the multilayer ceramic electronic component. On the other hand, if it contains more resin components than metal powder, the resin components can buffer the vibrations of the multilayer ceramic capacitor, reducing the vibrations transmitted to the mounting board.

[0038] The resin component forming the spacer 4 may be, for example, a phenol resin, an epoxy resin, or the like.

[0039] An example of the structure of the spacer 4 when the spacer 4 is formed using a phenol resin or an epoxy resin is shown in Fig. 4. Fig. 4 is a partially enlarged cross-sectional view of the spacer 4.

[0040] The spacer 4 shown in Fig. 4 contains either Cu or Ni and Sn as metal powder. The Cu and Ni may be coated with Ag. The intermetallic compound formed by adding Sn to either Cu or Ni is less likely to deform due to heat, even when soldering is performed when mounting the multilayer ceramic capacitor 1 on a mounting substrate, and the shape of the spacer 4 can be reliably maintained. In particular, the intermetallic compound formed by adding Sn to an alloy of Cu and Ni is preferred as a component for forming the spacer 4.

[0041] The metal regions MP formed by the metal powder contain a phenolic resin or an epoxy resin. The phenolic resin or the epoxy resin coats the particles of the intermetallic compound and is scattered so as to fill the gaps between the particles. The phenolic resin or the epoxy resin may not completely coat the particles of the intermetallic compound.

[0042] Examples of the phenolic resin include novolac-type phenolic resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, tert-butylphenol novolac resin, and nonylphenol novolac resin, resol-type phenolic resin, and polyoxystyrene such as polyparaoxystyrene. The spacer 4 may contain epoxy resin or rosin in addition to the phenolic resin.

[0043] 4, metal powder MF may be contained in the resin region RP. The metal powder MF inhibits the shrinkage of the resin, and the shrinkage stress caused by the resin can be alleviated.

[0044] 2, the first spacer 4a and the second spacer 4b each include two regions, an inner region 41 and an outer region 42 other than the inner region 41, which are opposed to each other in the length direction L. The inner region 41 and the outer region 42 have different porosities. The inner region 41 and the outer region 42 are defined by the inner and outer regions when a line V perpendicular to the second main surface A2, which is the mounting surface, is drawn from the tip Pt of the base electrode layer 30.

[0045] By adjusting the porosity in the inner region 41 and the outer region 42, it is possible to adjust the amount of solder that wets up along the surface of the spacer 4 when heated during mounting, thereby suppressing the occurrence of squealing caused by the solder wetting up.

[0046] The outer region 42 preferably has a higher porosity than the inner region 41. If the porosity of the outer region 42 is increased, excess molten solder is absorbed into the voids inside the outer region 42 when heated during mounting, thereby suppressing solder wetting. This makes it possible to suppress squealing caused by solder wetting.

[0047] (Measurement of void ratio) The void ratio can be determined by the following method. A cross section of the spacer 4 parallel to the stacking direction T and the length direction L is magnified by a microscope (BX-51) at a total magnification of 50 times, and photographed with a microscope camera (DP22 manufactured by Olympus). The photographed image is binarized to identify voids, and the void ratio can be calculated from the proportion of the area of ​​the voids in the image. If the insulating material 50 described below is applied, the void ratio of the spacer 4 after the insulating material 50 has been applied is measured. The measurement method is not limited to the method described above, and various other methods are possible.

[0048] The porosity of the outer region 42 is preferably 5% or more. If the porosity is less than 5%, the voids are not formed sufficiently, and the amount of solder wetting up cannot be sufficiently suppressed.

[0049] The spacer 4 preferably has a porosity of 20% or less in a region up to 5 μm from the interface with the external electrode 3. This increases the bonding area between the external electrode 3 and the spacer 4, improving the bonding strength between the external electrode 3 and the spacer 4.

[0050] The surface roughness Rzo of the outer region 42 is preferably greater than the surface roughness Rzi of the inner region 41. By increasing the surface roughness Rzo of the outer region 42, excess molten solder can be captured in recesses formed on the surface of the outer region 42 when heated during mounting, thereby effectively suppressing wetting of the solder.

[0051] The surface roughness Rzo of the outer region 42 and the surface roughness Rzi of the inner region 41 can be measured, for example, by using a laser microscope (Keyence Corporation: VK-1000) at a magnification of 20x to observe the surfaces of the outer region 42 and the inner region 41 at positions halfway along the stacking direction T, continuously in the width direction W, from the length direction L. Furthermore, when the mounting surface facing the mounting board is the first side surface B1 of the capacitor body 1A, the surfaces of the outer region 42 and the inner region 41 can be similarly measured at positions halfway along the width direction W, continuously in the stacking direction T, from the length direction L.

[0052] (Manufacturing Method of Multilayer Ceramic Capacitor 1) Fig. 6 is a flowchart illustrating a manufacturing method of the multilayer ceramic capacitor 1. The manufacturing method of the multilayer ceramic capacitor 1 includes a laminate manufacturing step S1, a base electrode layer forming step S2, a plating layer forming step S3, and a spacer arranging step S4. Fig. 7 is a diagram illustrating the laminate manufacturing step S1, the base electrode layer forming step S2, and the plating layer forming step S3.

[0053] (Laminate manufacturing process S1) A ceramic slurry containing ceramic powder, a binder, and a solvent is formed into a sheet on the surface of a carrier film using a die coater, gravure coater, microgravure coater, or the like to prepare a ceramic green sheet 101 for lamination that will become the dielectric layer 14. Next, a conductive paste is printed in strips on the ceramic green sheet 101 for lamination by screen printing, inkjet printing, gravure printing, or the like, and a conductive pattern 102 that will become the internal electrode layer 15 is printed on the surface of the ceramic green sheet 101 for lamination to prepare a material sheet 103.

[0054] 7( a), a plurality of material sheets 103 are stacked so that the conductive patterns 102 face in the same direction and are offset, for example, by half a pitch, in the longitudinal direction between adjacent material sheets 103. Furthermore, outer layer ceramic green sheets 112 that will become the outer layer portions 12 are stacked on both sides of the plurality of stacked material sheets 103.

[0055] The stacked material sheets 103 and the outer layer ceramic green sheets 112 are pressed together by a hydrostatic press or the like to form a mother block 110 shown in FIG. 7(b).

[0056] Next, the mother block 110 is cut along cutting lines X and Y intersecting with cutting line X shown in FIG. 7(b), and fired to produce a plurality of laminates 2 shown in FIG. 7(c).

[0057] (Base electrode layer forming step S2) Subsequently, a conductive paste containing Cu is applied to and baked on the end face C of the laminate 2 to form the base electrode layer 30. The base electrode layer 30 is formed so as to cover not only the end faces C on both sides of the laminate 2, but also the main face A and side face B of the laminate 2, and to cover a part of the end face C side of the main face A. However, the present invention is not limited to this, and the base electrode layer may contain other metals or other components, and two base electrode layers may be provided.

[0058] (Plating layer forming step S3) Next, a plating layer 31 is formed on the surface of the base electrode layer 30 to produce the capacitor body 1A shown in Fig. 7(d) . The plating layer 31 can be composed of a Ni plating layer and a Sn plating layer disposed on the surface of the Ni plating layer, but is not limited to this.

[0059] (Spacer Arranging Step S4) Next, the inner region 41 and the outer region 42 are formed as follows.

[0060] A paste for the inner region is prepared to be used for forming the inner region 41. Examples of the paste for the inner region include the following phenol resin-based and epoxy resin-based pastes.

[0061] An outer region paste is prepared to be used for forming the outer region 42. For example, the outer region paste may be a paste containing a resin component contained in the outer region that contains a larger amount of a resin component with a lower boiling point than the resin component contained in the inner region.

[0062] (Phenol Resin-Based) The paste for the inner region and the paste for the outer region contain metals made of Cu, Ni, Sn, and Ag, a phenol resin, a solvent, and an additive.

[0063] Examples of the phenol resin include novolac-type phenol resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, tert-butylphenol novolac resin, and nonylphenol novolac resin; resol-type phenol resin; and polyoxystyrene such as polyparaoxystyrene.

[0064] The inner region paste and the outer region paste are applied to a first end face C1 side in the length direction L on the second main surface A2 of the capacitor body 1A, which serves as the mounting surface facing the mounting board and on which the first spacers 4a are arranged, and to a second end face C2 side on the other side in the length direction L on which the second spacers 4b are arranged. Furthermore, when the mounting surface of the capacitor body 1A is the first side surface B1, the inner region paste and the outer region paste are applied to a first end face C1 side in the length direction L on which the first spacers 4a are arranged, and to a second end face C2 side on the other side in the length direction L on which the second spacers 4b are arranged, on the first side surface B1 of the capacitor body 1A. The inner region paste and the outer region paste can be applied by screen printing, dispensing, or the like.

[0065] After the inner region paste and the outer region paste are applied, a heating step is performed. When at least a portion of the metal in the paste generates an intermetallic compound to form the metal region MP, some of the phenolic resin is taken into the metal region MP and some is expelled from the metal region MP, while solidifying or curing, thereby forming the inner region 41 of the spacer 4 bonded to the capacitor body 1A.

[0066] (Epoxy Resin-Based) The paste for the inner region and the paste for the outer region contain a metal made of Cu and Ni coated with Sn, Cu coated with Ag, or Cu coated with silver (Ag) instead of Cu, an epoxy resin, and a solvent.

[0067] The epoxy resin is a bisphenol A epoxy resin. The solvent is, for example, diethylene glycol monobutyl ether, diethylene glycol monoethyl ether, or diethylene glycol monomethyl ether. It does not contain a curing agent such as phenol resin or imidazole.

[0068] The epoxy resin-based forming process can be the same as that for the phenolic resin-based forming process described above.

[0069] Alternatively, the paste for the outer region may be applied first, followed by a heat treatment, and then the paste for the inner region may be applied and then a heat treatment may be performed. In this case, the paste for the outer region may have the same resin component as the paste for the inner region.

[0070] Although the embodiment of the present invention has been described above, the present invention is not limited to this and can be embodied in various forms.

[0071] 7 , an insulating material 50 can be disposed between the first spacer 4 a and the second spacer 4 b so as to cover at least a portion of at least one of the first spacer 4 a and the second spacer 4 b and at least a portion of the second main surface A2 or the first side surface B1 of the laminate 2. In addition to this, the insulating material 50 may be disposed so as to fill the gap between the inner region and the second main surface A2 or the first side surface B1 of the laminate 2. By disposing the insulating material 50, it is possible to improve the adhesive strength between the spacer 4 and the external electrode 3 and between the spacer 4 and the laminate 2.

[0072] Figure 7 shows an embodiment in which an insulating material 50 is arranged continuously between the inner region 41 of the first spacer 4a and the inner side surface 41 of the second spacer 4b. In such an embodiment, the insulating material 50 can be shaped so that the length in the width direction W of the central part in the length direction L is shorter than the length in the width direction W of both end parts in the length direction L.

[0073] The insulating material 50 can be arranged continuously between the first spacer 4a and the second spacer 4b, but does not necessarily have to be arranged continuously. For example, the insulating material 50 may be arranged in two parts: one covering a portion of the first spacer 4a and a portion of the second main surface A2 or the first side surface B1 of the laminate 2, and the other covering a portion of the second spacer 4b and a portion of the second main surface A2 or the first side surface B1 of the laminate 2.

[0074] The insulating material 50 can be formed from an insulating resin. The surface of the insulating resin may be coated with an insulating water-repellent agent. By forming the insulating material from an insulating resin, the flexural strength is improved, and by further coating with an insulating water-repellent agent, the moisture resistance is improved. The insulating resin may contain ceramics, glass, etc., or may be formed only from a water-repellent agent.

[0075] The insulating material 50 may be made primarily of epoxy resin, combined with phenolic resin as a curing agent. Other curing agents that can be used include acid anhydride-based, amine-based, and ester-based curing agents. A curing accelerator may also be added to the epoxy resin. The insulating material 50 may also contain, for example, carbon, Co, Al, Cu, N, or Cr. Since the color of the insulating material 50 can be made different from the color of the capacitor body 1A, it is easier to select the orientation when mounting the insulating material 50 on a substrate.

[0076] The insulating material 50 is preferably disposed so as to penetrate into the inside region 41, thereby improving the adhesive strength between the spacer 4, the laminate 2 and the external electrode 3.

[0077] The insulating material 50 may cover the outer surface of the laminate 2 and the outer surface of the external electrode 3, but in this case, the surface of the spacer 4 that connects to the mounting board is not completely covered with the insulating material. Covering the surface with the insulating material 50 reduces the possibility of contact between adjacent electronic components.

[0078] The present invention can be embodied in various forms without departing from the spirit and scope of the present invention.

[0079] <1> A laminate including an inner layer portion in which dielectric layers and internal electrode layers are laminated, the laminate having two main surfaces opposing each other in a lamination direction, two end surfaces opposing each other in a length direction intersecting the lamination direction, and two side surfaces opposing each other in a width direction intersecting the lamination direction and the length direction; two external electrodes connected to the internal electrode layers on each of the two end surfaces and covering the end surfaces and parts of the two main surfaces or parts of the two side surfaces adjacent thereto; one of the two main surfaces or one of the two side surfaces of the laminate serving as a mounting surface facing a mounting board, and two spacers connected to the external electrodes on the mounting surface, the external electrodes having a base electrode layer and a plating layer, and the two spacers each having two regions, an inner region opposing each other in the length direction, and an outer region other than the inner region, when a line perpendicular to the mounting surface is drawn from a tip of the base electrode layer of the external layer electrode covering a part of the mounting surface, The multilayer ceramic electronic component according to <1>, wherein the inner region is located closer to the center of the laminate in the length direction than a line perpendicular to the mounting surface, and the inner region and the outer region have different porosities.<2> The multilayer ceramic electronic component according to <1>, wherein the two end faces comprise a first end face and a second end face, the two external electrodes comprise a first external electrode disposed on the first end face and a second external electrode disposed on the second end face, and the two spacers comprise a first spacer disposed on the first external electrode and a second spacer disposed on the second external electrode, and when viewed from a direction perpendicular to the mounting surface, the first spacer protrudes from the first external electrode.<3> The multilayer ceramic electronic component according to <2>, wherein the second spacer protrudes from the second external electrode.<4> The multilayer ceramic electronic component according to <1>, wherein the two end faces comprise a first end face and a second end face, the two external electrodes comprise a first external electrode arranged on the first end face and a second external electrode arranged on the second end face, the two spacers comprise a first spacer arranged on the first external electrode and a second spacer arranged on the second external electrode, the first spacer intersecting a line drawn from an apex of a maximum thickness portion of the first external electrode where the dimension in the length direction is the longest and perpendicular to the mounting surface. <5> The multilayer ceramic electronic component according to <4>, wherein the second spacer intersecting a line drawn from an apex of a maximum thickness portion of the second external electrode where the dimension in the length direction is the longest and perpendicular to the mounting surface. <6> The multilayer ceramic electronic component according to any of <1> to <5>, wherein the outer region has a higher porosity than the inner region. <7> The multilayer ceramic electronic component according to any one of <1> to <6>, wherein the porosity of the outer region is 5% or more, and the spacer has a porosity of 20% or less in a region up to 5 μm from the interface with the external electrode. <8> The multilayer ceramic electronic component according to any one of <1> to <7>, wherein the surface roughness of the outer region is greater than the surface roughness of the inner region. <9> The multilayer ceramic electronic component according to any one of <1> to <8>, wherein the two spacers contain a metal component and a resin component. <10> The multilayer ceramic electronic component according to <9>, wherein the resin component is a phenolic resin. <11> The multilayer ceramic electronic component according to <1>, wherein the two end faces include a first end face and a second end face; the two external electrodes include a first external electrode arranged on the first end face and a second external electrode arranged on the second end face; the two spacers include a first spacer arranged on the first external electrode and a second spacer arranged on the second external electrode; an insulating material is arranged between the first spacer and the second spacer, and the insulating material is connected to the laminate and an inner region of the first spacer, and to the laminate and an inner region of the second spacer.<12> The multilayer ceramic electronic component according to <11>, wherein the insulating material is disposed so as to penetrate into the interior region.

[0080] A Principal surface A1 First principal surface A2 Second principal surface B Side surface C End surface MF Metal powder MP Metal region P Gap RP Resin region 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 1A Capacitor body 2 Laminate 3 External electrode 3a First external electrode 3b Second external electrode 4 Spacer 4a First spacer 4b Second spacer 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 15 Internal electrode layer 16 Side margin portion 30 Base electrode layer 31 Plating layer 41 Inner region 42 Outer region 50 Insulating material

Claims

1. A laminate including an inner layer portion in which dielectric layers and internal electrode layers are laminated, and having two main surfaces opposing each other in the lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side surfaces opposing each other in a width direction intersecting the lamination direction and the length direction; two external electrodes connected to the internal electrode layers on each of the two end faces, and covering the end face and a portion of the two main surfaces or a portion of the two side surfaces adjacent thereto; one of the two main surfaces or one of the two side surfaces of the laminate serving as a mounting surface facing a mounting board, and two spacers connected to the two external electrodes on the mounting surface, respectively; the external electrodes have a base electrode layer and a plating layer; and the two spacers each have two regions, an inner region opposing each other in the length direction, and an outer region other than the inner region; when a line perpendicular to the mounting surface is drawn from the tip of the base electrode layer covering a portion of the mounting surface, The inner region is located closer to the center of the laminate in the length direction than a line perpendicular to the mounting surface, and the inner region and the outer region have different porosities.

2. The multilayer ceramic electronic component according to claim 1, wherein the two end faces comprise a first end face and a second end face; the two external electrodes comprise a first external electrode arranged on the first end face and a second external electrode arranged on the second end face; the two spacers comprise a first spacer arranged on the first external electrode and a second spacer arranged on the second external electrode; and when viewed from a direction perpendicular to the mounting surface, the first spacer protrudes from the first external electrode.

3. The multilayer ceramic electronic component according to claim 2, wherein the second spacer protrudes beyond the second external electrode.

4. The multilayer ceramic electronic component according to claim 1, wherein the two end faces comprise a first end face and a second end face; the two external electrodes comprise a first external electrode arranged on the first end face and a second external electrode arranged on the second end face; the two spacers comprise a first spacer arranged on the first external electrode and a second spacer arranged on the second external electrode; and the first spacer intersects with a line perpendicular to the mounting surface, drawn from the vertex of the thickest part of the first external electrode, where the dimension in the length direction is greatest.

5. The multilayer ceramic electronic component according to claim 4, wherein the second spacer intersects with a line perpendicular to the mounting surface, drawn from the vertex of the thickest part of the second external electrode where the dimension in the longitudinal direction is the greatest.

6. A multilayer ceramic electronic component according to any one of claims 1 to 5, wherein the outer region has a higher porosity than the inner region.

7. A multilayer ceramic electronic component according to any one of claims 1 to 6, wherein the porosity of the outer region is 5% or more, and the porosity of the spacer is 20% or less in a region extending from the interface with the external electrode to a distance of 5 μm.

8. The multilayer ceramic electronic component according to claim 1, wherein the surface roughness of said outer region is greater than the surface roughness of said inner region.

9. The multilayer ceramic electronic component according to any one of claims 1 to 8, wherein the two spacers contain a metal component and a resin component.

10. The multilayer ceramic electronic component according to claim 9, wherein the resin component is a phenolic resin.

11. The multilayer ceramic electronic component according to claim 1, wherein the two end faces comprise a first end face and a second end face; the two external electrodes comprise a first external electrode disposed on the first end face and a second external electrode disposed on the second end face; the two spacers comprise a first spacer disposed on the first external electrode and a second spacer disposed on the second external electrode; an insulating material is disposed between the first spacer and the second spacer, and the insulating material is connected to the laminate and the inner region of the first spacer, and to the laminate and the inner region of the second spacer.

12. The multilayer ceramic electronic component according to claim 11, wherein the insulating material is disposed so as to penetrate into the interior region.

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