Display device

Abstract

This display device comprises: a first lower connection electrode disposed on the same layer as an anode electrode and distanced therefrom; a first upper connection electrode electrically connected to the first lower connection electrode and disposed on the anode electrode so as to face same; a cathode electrode disposed on the same layer as the first upper connection electrode and distanced therefrom; a first sub-light-emitting element overlapping the anode electrode; and a second sub-light-emitting element overlapping the first lower electrode, wherein the first and second sub-light-emitting elements are electrically connected in series between the anode and cathode electrodes by means of the first lower connection electrode and first upper connection electrode.

Description

display device

[0001] The present invention relates to a display device.

[0002] A display device is a device that displays images by combining light emitted from pixels. When pixel brightness is improved, the display quality of the images displayed on the display device can be improved.

[0003] It should be understood that the description of the background art described above is intended to provide useful background for understanding the technology. However, the description of the background art described above may include ideas, concepts, or insights that were unknown or unrecognized by those skilled in the relevant technical field prior to the effective filing date of the present disclosure.

[0004] An object of the present invention is to provide a display device with improved display quality.

[0005] A display device according to embodiments includes: a pixel circuit layer including a transistor; an anode electrode disposed on the pixel circuit layer and electrically connected to the transistor; a first lower connection electrode, the first lower connection electrode and the anode electrode being disposed on the same layer, the first lower connection electrode being spaced apart from the anode electrode; a first upper connection electrode being electrically connected to the first lower connection electrode and disposed on the anode electrode to face the anode electrode; a cathode electrode, the cathode electrode and the first upper connection electrode being disposed on the same layer, the cathode electrode being spaced apart from the first upper connection electrode; a first sub-light emitting element overlapping the anode electrode; and a second sub-light emitting element overlapping the first lower electrode, wherein the first sub-light emitting element can be electrically connected in series between the second sub-light emitting element and the anode electrode and the cathode electrode through the first lower connection electrode and the first upper connection electrode.

[0006] In one embodiment, the first sub-light emitting element includes a plurality of first sub-light emitting elements, and the plurality of first sub-light emitting elements can be electrically connected in parallel.

[0007] In one embodiment, the second sub-light emitting element comprises a plurality of second sub-light emitting elements, and the plurality of second sub-light emitting elements can be electrically connected in parallel.

[0008] In one embodiment, each of the first sub-light emitting element and the second sub-light emitting element may include a first semiconductor layer having a first polarity; and a second semiconductor layer having a second polarity different from the first polarity and disposed on the first semiconductor layer.

[0009] In one embodiment, the first semiconductor layer of the first sub-light emitting element may be electrically connected to the anode electrode, the second semiconductor layer of the first sub-light emitting element may be electrically connected to the first upper connection electrode, and the first semiconductor layer of the second sub-light emitting element may be electrically connected to the first lower connection electrode.

[0010] In one embodiment, the display device may further include a second upper connecting electrode, the second upper connecting electrode and the first upper connecting electrode being disposed on the same layer, the second upper connecting electrode being spaced apart from the cathode electrode and the first upper connecting electrode and being disposed on the first lower connecting electrode to face the first lower connecting electrode; a second lower connecting electrode, the second lower connecting electrode and the anode electrode being disposed on the same layer, the second lower connecting electrode being spaced apart from the anode electrode and the first lower connecting electrode and being electrically connected to the second upper connecting electrode; and a third sub-light emitting element overlapping the second lower connecting electrode.

[0011] In one embodiment, the second sub-light emitting element may be electrically connected in series with the third sub-light emitting element between the first lower connecting electrode and the cathode electrode through the second lower connecting electrode and the second upper connecting electrode.

[0012] In one embodiment, the third sub-light emitting element comprises a plurality of third sub-light emitting elements, and the plurality of third sub-light emitting elements can be electrically connected in parallel.

[0013] In one embodiment, the display device may further include a third upper connecting electrode, the third upper connecting electrode and the first upper connecting electrode being disposed on the same layer, the third upper connecting electrode being spaced apart from the cathode electrode, the first upper connecting electrode, and the second upper connecting electrode, and being disposed on the second lower connecting electrode to face the second lower connecting electrode; a third lower connecting electrode, the third lower connecting electrode, and the anode electrode being disposed on the same layer, the third lower connecting electrode being spaced apart from the anode electrode, the first lower connecting electrode, and the second lower connecting electrode, and being electrically connected to the third upper connecting electrode; and a fourth sub-light emitting element overlapping the third lower connecting electrode.

[0014] In one embodiment, the third sub-light emitting element can be electrically connected in series between the fourth sub-light emitting element and the second lower connecting electrode and the cathode electrode through the third lower connecting electrode and the third upper connecting electrode.

[0015] A display device according to embodiments of the present invention includes a pixel circuit layer including a transistor; an anode electrode disposed on the pixel circuit layer and electrically connected to the transistor; a first connection electrode spaced apart from the anode electrode, the first connection electrode and the anode electrode being disposed on the same layer; a cathode electrode spaced apart from the anode electrode and the first connection electrode, the cathode electrode and the anode electrode being disposed on the same layer; a first sub-light emitting element electrically connected between the anode electrode and the first connection electrode; and a second sub-light emitting element electrically connected between the first connection electrode and the cathode electrode, wherein the first sub-light emitting element can be electrically connected in series between the second sub-light emitting element and the anode electrode and the cathode electrode through the first connection electrode.

[0016] In one embodiment, the first sub-light emitting element includes a plurality of first sub-light emitting elements, and the plurality of first sub-light emitting elements can be electrically connected in parallel.

[0017] In one embodiment, the second sub-light emitting elements include a plurality of second sub-light emitting elements, and the plurality of second sub-light emitting elements can be electrically connected in parallel.

[0018] In one embodiment, each of the first sub-light emitting element and the second sub-light emitting element may include: a first semiconductor layer having a first polarity; a second semiconductor layer having a second polarity different from the first polarity and disposed on the first semiconductor layer; a first bonding electrode electrically connected to the first semiconductor layer and protruding in a direction toward the pixel circuit layer; and a second bonding electrode electrically connected to the second semiconductor layer and protruding in the direction toward the pixel circuit layer.

[0019] In one embodiment, the first bonding electrode of the first sub-light emitting element may be electrically connected to the anode electrode, the second bonding electrode of the first sub-light emitting element may be electrically connected to the first connection electrode, and the first bonding electrode of the second sub-light emitting element may be electrically connected to the first connection electrode.

[0020] In one embodiment, the display device further includes a second connecting electrode, the second connecting electrode and the anode electrode being disposed on the same layer, the second connecting electrode being spaced apart from the anode electrode, the first connecting electrode, and the cathode electrode; and a third sub-light emitting element electrically connected between the second connecting electrode and the cathode electrode, wherein the second sub-light emitting element and the third sub-light emitting element can be electrically connected in series between the first connecting electrode and the cathode electrode through the second connecting electrode.

[0021] In one embodiment, the third sub-light emitting element includes a plurality of third sub-light emitting elements, and the plurality of third sub-light emitting elements can be electrically connected in parallel.

[0022] A display device according to embodiments of the present invention includes: a pixel circuit layer including a transistor; an anode electrode disposed on the pixel circuit layer and electrically connected to the transistor; a cathode electrode, the cathode electrode and the anode electrode being disposed on the same layer, the cathode electrode being spaced apart from the anode electrode; a first sub-light emitting element and a second sub-light emitting element electrically connected between the anode electrode and the cathode electrode; and a first connecting electrode disposed on the first sub-light emitting element and the second sub-light emitting element, the first connecting electrode electrically connecting the first sub-light emitting element and the second sub-light emitting element, wherein the first sub-light emitting element and the second sub-light emitting element can be electrically connected in series between the anode electrode and the cathode electrode through the first connecting electrode.

[0023] In one embodiment, the first sub-light emitting element includes a plurality of first sub-light emitting elements, and the plurality of first sub-light emitting elements can be electrically connected in parallel.

[0024] In one embodiment, the second sub-light emitting element includes a plurality of second sub-light emitting elements, and the plurality of second sub-light emitting elements can be electrically connected in parallel.

[0025] In one embodiment, each of the first sub-light emitting element and the second sub-light emitting element may include: a first semiconductor layer having a first polarity; a second semiconductor layer having a second polarity different from the first polarity and disposed below the first semiconductor layer; a first bonding electrode electrically connected to the first semiconductor layer and protruding in a direction away from the pixel circuit layer; and a second bonding electrode electrically connected to the second semiconductor layer and protruding in the direction away from the pixel circuit layer.

[0026] In one embodiment, the first bonding electrode of the first sub-light emitting element may be electrically connected to the anode electrode, the second bonding electrode of the first sub-light emitting element may be electrically connected to the first connection electrode, and the first bonding electrode of the second sub-light emitting element may be electrically connected to the first connection electrode.

[0027] In one embodiment, the display device further includes a third sub-light emitting element electrically connected between the first connection electrode and the cathode electrode; and a second connection electrode disposed on the second sub-light emitting element and the third sub-light emitting element, the second connection electrode electrically connecting the second sub-light emitting element and the third sub-light emitting element, wherein the second sub-light emitting element and the third sub-light emitting element can be electrically connected in series to each other through the second connection electrode between the first connection electrode and the cathode electrode.

[0028] In one embodiment, the third sub-light emitting element includes a plurality of third sub-light emitting elements, and the plurality of third sub-light emitting elements can be electrically connected in parallel to each other.

[0029] In one embodiment, the display device may further include a floating electrode disposed between the anode electrode and the cathode electrode.

[0030] In one embodiment, the display device may further include a reflective electrode covering at least a portion of the floating electrode.

[0031] A display device according to embodiments of the present invention may include a first sub-light emitting element and a second sub-light emitting element that are electrically connected in series between an anode electrode and a cathode electrode. In this way, as the first sub-light emitting element and the second sub-light emitting element are electrically connected in series, the brightness of the display device can be further improved.

[0032] The sub-light emitting elements included in the display device according to embodiments of the present invention may be vertical light emitting elements, flip chip type light emitting elements, or lateral chip type light emitting elements. The present invention discloses a novel series connection structure using the various types of light emitting elements described above.

[0033] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present invention.

[0034] FIG. 2 is a block diagram illustrating one embodiment of one of the sub-pixels included in the display device of FIG. 1.

[0035] FIG. 3 is a block diagram illustrating one embodiment of one of the sub-pixels included in the display device of FIG. 1.

[0036] FIG. 4 is a schematic plan view for explaining a display panel constituting the display device of FIG. 1.

[0037] FIG. 5 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 4.

[0038] FIG. 6 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 4.

[0039] FIGS. 7 and 8 are schematic plan views for explaining a first embodiment of one of the pixels included in the display panel of FIG. 3.

[0040] FIGS. 9 and 10 are schematic cross-sectional views illustrating a pixel according to the first embodiment of FIG. 8.

[0041] FIGS. 11 and 12 are schematic plan views illustrating the first and second embodiments of one of the pixels included in the display panel of FIG. 3.

[0042] FIGS. 13 and 14 are schematic cross-sectional views illustrating pixels according to the first and second embodiments of FIG. 12.

[0043] FIGS. 15 and 16 are schematic plan views illustrating embodiments 1-3 of one of the pixels included in the display panel of FIG. 3.

[0044] FIG. 17 is a schematic plan view for explaining a second embodiment of one of the pixels included in the display panel of FIG. 3.

[0045] FIG. 18 and FIG. 19 are schematic cross-sectional views for explaining a pixel according to the second embodiment of FIG. 17.

[0046] FIG. 20 is a schematic plan view for explaining a second embodiment of one of the pixels included in the display panel of FIG. 3.

[0047] Figures 21 to 23 are schematic cross-sectional views for explaining pixels according to the second embodiment of Figure 20.

[0048] FIG. 24 is a schematic plan view for explaining a second-third embodiment of one of the pixels included in the display panel of FIG. 3.

[0049] Figures 25 and 26 are schematic cross-sectional views for explaining pixels according to the second-third embodiment of Figure 24.

[0050] FIG. 27 is a schematic plan view for explaining a third-first embodiment of one of the pixels included in the display panel of FIG. 3.

[0051] FIG. 28 and FIG. 29 are schematic cross-sectional views for explaining a pixel according to the third embodiment of FIG. 27.

[0052] FIG. 30 is a schematic plan view for explaining a third-second embodiment of one of the pixels included in the display panel of FIG. 3.

[0053] Figures 31 to 33 are schematic cross-sectional views for explaining pixels according to the third embodiment of Figure 30.

[0054] FIG. 34 is a schematic plan view for explaining a third embodiment of one of the pixels included in the display panel of FIG. 3.

[0055] Figures 35 and 36 are schematic cross-sectional views for explaining a pixel according to the third embodiment of Figure 34.

[0056] Figure 37 is a block diagram illustrating a display system according to one embodiment.

[0057] Figures 38 to 41 are schematic perspective views illustrating application examples of the display system of Figure 37.

[0058] Hereinafter, embodiments will be described in detail with reference to the attached drawings. It should be noted that the following description will explain parts necessary for understanding the operation of the present invention, and the description of other parts may be omitted to avoid obscuring the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical idea of ​​the present invention in sufficient detail to enable those of ordinary skill in the relevant technical fields to easily implement it.

[0059] Throughout this specification, when a part is said to be "connected" to another part, this includes not only "directly connected" but also "indirectly connected" with other elements intervening. The terminology used herein is for the purpose of describing embodiments and is not intended to limit the present invention.

[0060] Throughout the specification, whenever a part is said to "include" a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise stated.

[0061] In the drawings, the size, thickness, proportion, and dimensions of components may be exaggerated for clarity and ease of explanation. Identical reference numbers may refer to identical components throughout.

[0062] Here, singular expressions may be intended to include plural expressions unless the context clearly indicates otherwise.

[0063] Throughout the specification, the term "and / or" may be meant to include any combination of "and" and "or" for purposes of meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B." "And" and "or" may be used in the sense of a conjunction or a disjunction, and may be understood to be the same as "and / or."

[0064] Throughout the specification, "at least one" may, for purposes of meaning and interpretation, include the meaning of "at least one selected from the group of." For example, "at least one of A and B" may be understood to mean "A, B, or A and B."

[0065] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0066] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features would instead be positioned "above" the other elements or features. Thus, in one embodiment, the term "below" can encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0067] The term "overlapping" or "nesting" can mean that the first object is above, below, or next to the second object, or vice versa. Furthermore, "overlapping" can include layers, stacks, facing, extending, covering, or partially covering, or other appropriate terms understood and recognized by a person skilled in the art.

[0068] The term "confrontation" implies that the first component can directly or indirectly replace the second component. If a third component intervenes between the first and second components, the first and second components are understood to be confronting and indirectly replacing each other.

[0069] When a component is described as being "non-overlapping" or "not overlapping" with another component, this may include the components being spaced apart from each other, offset from each other, adjacent to each other, or any other appropriate terminology that would be understood and recognized by a person skilled in the art.

[0070] The terms "comprises," "comprising," "has," and / or "having" and variations thereof refer to the presence of specified features, integers, steps, operations, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, and / or groups thereof.

[0071] Various embodiments are described with reference to drawings illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the embodiments are not limited thereto.

[0072] As used herein, "about" or "approximately" means within an acceptable range of deviation from the stated value as determined by one of ordinary skill in the art, taking into account the measurement method and any errors associated with the measurement method of the stated value (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0073] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries, for example, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0074] When a specification refers to a component (or region, layer, section, etc.) as being "in," "connected to," or "joined to" another component, it will be understood that it can be directly disposed in, connected to, or joined to the other component referred to above, or that intervening components can be disposed therebetween.

[0075] It will be understood that the terms "connected" or "coupled" may include physical or electrical connections or couplings.

[0076] Embodiments may be described in the accompanying drawings in terms of functional blocks, units, and / or modules.

[0077] A person skilled in the art will understand that such blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

[0078] When blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software.

[0079] Additionally, each block, unit, and / or module may be implemented by dedicated hardware, or a combination of dedicated hardware performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions.

[0080] Each block, unit, and / or module of the embodiments may be physically separated into two or more interacting and individual blocks, units, and / or modules without departing from the scope of the disclosure.

[0081] Additionally, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules without departing from the scope of the disclosure.

[0082] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present invention.

[0083] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0084] The display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) may be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0085] Sub-pixels (SP) can generate light of two or more colors. For example, each sub-pixel (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0086] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. The pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included in the pixel (PXL).

[0087] The gate driver (120) may be connected to the sub-pixels (SP) arranged (or placed) in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) may output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) may include a start signal indicating the start of each frame, a horizontal synchronization signal, or the like within the scope and spirit of the present disclosure.

[0088] The gate driver (120) may be arranged on one side or side surface of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and these drivers may be arranged on one side or side surface of the display panel (DP) and the other side or side surface opposite to the one side. In this way, the gate driver (120) may be arranged on the periphery of the display panel (DP) in various forms according to embodiments.

[0089] The data driver (130) is connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, and the like within the spirit and scope of the present disclosure.

[0090] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn) using the received voltages. When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0091] In embodiments, the gate driver (120) and the data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0092] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) can be configured to generate voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate voltages by receiving an input voltage from outside the display device (DD) and regulating the received voltage.

[0093] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In one embodiment, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0094] The voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). In FIG. 1, the pixel control lines (PXCL) are illustrated as being connected between the voltage generator (140) and the display panel (DP), but embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0095] The controller (150) controls all operations of the display device (DD). The controller (150) receives input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0096] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by arranging the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0097] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0098] FIG. 2 is a block diagram for explaining one embodiment of one of the sub-pixels included in the display device of FIG. 1. In FIG. 2, a sub-pixel (SPij) arranged in an ith row (i is an integer greater than or equal to 1 and less than or equal to m) and a jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of FIG. 1 is illustrated as an example.

[0099] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0100] A light emitting element (LD) may be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) may be connected to one of the power supply lines (PL) of FIG. 1 and may receive a first power supply voltage. The second power supply voltage node (VSSN) may be connected to another of the power supply lines (PL) of FIG. 1 and may receive a second power supply voltage. The first power supply voltage may have a higher level than the second power supply voltage.

[0101] A light emitting element (LD) may be connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power voltage node (VSSN). The light emitting element (LD) may be configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0102] In embodiments, the light-emitting element (LD) may include first to kth sub-light-emitting elements (SLD1 to SLDk) connected between the anode electrode (AE) and the cathode electrode (CE), and in this case, the first to kth sub-light-emitting elements (SLD1 to SLDk) may be connected in series to each other between the anode electrode (AE) and the cathode electrode (CE). In this way, since the light-emitting element (LD) may include a plurality of sub-light-emitting elements (SLD1 to SLDk) connected in series to each other, the luminance of the light-emitting element (LD) may be further improved.

[0103] The sub-pixel circuit (SPC) may be connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0104] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0105] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, and the like within the spirit and scope of the present disclosure.

[0106] FIG. 3 is a block diagram for explaining one embodiment of one of the sub-pixels included in the display device of FIG. 1. In FIG. 3, a sub-pixel (SPij') arranged in an ith row (i is an integer greater than or equal to 1 and less than or equal to m) and a jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of FIG. 1 is illustrated as an example.

[0107] The sub-pixel (SPij') may be substantially the same as the sub-pixel (SPij) described with reference to FIG. 2, except that each of the first to kth sub-light-emitting elements (SLD1 to SLDk) may be composed of multiple light-emitting elements. Therefore, description of overlapping content may be omitted.

[0108] In the sub-pixel (SPij'), each of the first to kth sub-light-emitting elements (SLD1 to SLDk) may include light-emitting elements that are connected in parallel with each other. For example, the first to kth sub-light-emitting elements (SLD1 to SLDk) may each independently include two, three, four, or more light-emitting elements that are connected in parallel with each other. In this case, the first to kth sub-light-emitting elements (SLD1 to SLDk) may be connected in series with each other between the anode electrode (AE) and the cathode electrode (CE), and accordingly, the luminance of the light-emitting element (LD) may be further improved.

[0109] FIG. 4 is a schematic plan view for explaining a display panel constituting the display device of FIG. 1.

[0110] Referring to FIG. 4, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through the display area (DA). The non-display area (NDA) may be positioned around the display area (DA).

[0111] A display panel (DP) may include sub-pixels (SP) arranged in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting (or transverse to) the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on embodiments. The first direction (DR1) may be a column direction, and the second direction (DR2) may be a row direction.

[0112] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). In FIG. 4, the pixel (PXL) is illustrated as including three sub-pixels (SP1, SP2, SP3), but the embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it may be assumed that the pixel (PXL) can include first to third sub-pixels (SP1, SP2, SP3).

[0113] Each of the first to third sub-pixels (SP1, SP2, SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. In the following, for clarity and concise explanation, it is assumed that the first sub-pixel (SP1) can be configured to generate red color light, the second sub-pixel (SP2) can be configured to generate green color light, and the third sub-pixel (SP3) can be configured to generate blue color light.

[0114] Each of the first to third sub-pixels (SP1, SP2, SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate red light, green light, and blue light, respectively.

[0115] As a display panel (DP), a self-luminous display panel can be used, such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements.

[0116] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0117] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0118] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have a closed-loop shape including straight and / or curved edges. For example, the display area (DA) may have shapes within the scope and scope of the present disclosure, such as a polygon, a circle, a semicircle, or an ellipse.

[0119] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In these cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0120] FIG. 5 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 4.

[0121] Referring to FIG. 5, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially stacked on top of the substrate (SUB) in a third direction (DR3) intersecting the first and second directions (DR1, DR2).

[0122] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. In another example, the substrate (SUB) may include a polyimide (PI) substrate. In another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0123] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0124] A pixel circuit layer (PCL) may be disposed on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, and the like within the scope and spirit of the present disclosure.

[0125] Circuit elements of the pixel circuit layer (PCL) can constitute a sub-pixel circuit (SPC) of each of the sub-pixels (SP) of FIG. 4. In other words, the circuit elements of the pixel circuit layer (PCL) can be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0126] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines for driving the display element layer (DPL).

[0127] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0128] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0129] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a given wavelength (or a given color). In some embodiments, the color filter layer may be omitted.

[0130] A window may be provided on the light-functional layer (LFL) to protect the exposed surface (or upper surface) of the display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded or connected to the light-functional layer (LFL) through an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0131] FIG. 6 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 4.

[0132] Referring to FIG. 6, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) may be configured to be substantially the same as (or similar to) the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 5. Therefore, description of overlapping content may be omitted.

[0133] The input sensing layer (ISL) can detect a user's input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting an external object, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0134] FIGS. 7 and 8 are schematic plan views for explaining a first embodiment of one of the pixels included in the display panel of FIG. 3.

[0135] Referring to FIG. 7, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in the second direction (DR2). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0136] First to third anode electrodes (AE1, AE2, AE3) may be respectively disposed in the first to third sub-pixels (SP1, SP2, SP3). The first anode electrode (AE1) may be provided as an anode electrode (AE, see FIG. 3) included in a sub-pixel circuit (SPC, see FIG. 3) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0137] A first lower connection electrode (LCE1) may be disposed in each of the first to third sub-pixels (SP1, SP2, and SP3). The first lower connection electrode (LCE1) may include a first-first lower connection electrode (LCE1a), a first-second lower connection electrode (LCE1b), and a first-third lower connection electrode (LCE1c). The first-first lower connection electrode (LCE1a) may be provided to the first sub-pixel (SP1) and may be spaced apart from the first anode electrode (AE1). The first-second lower connection electrode (LCE1b) may be provided to the second sub-pixel (SP2) and may be spaced apart from the second anode electrode (AE2). The first-third lower connection electrode (LCE1c) may be provided to the third sub-pixel (SP3) and may be spaced apart from the third anode electrode (AE3). In the embodiments, the first to third lower connection electrodes (LCE1a, LCE1b, LCE1c) may be arranged in the same layer as the first to third anode electrodes (AE1, AE2, AE3). In this case, the first to third lower connection electrodes (LCE1a, LCE1b, LCE1c) may be formed through the same forming process as the first to third anode electrodes (AE1, AE2, AE3).

[0138] A first sub light-emitting element (SLD1) may be disposed on each of the first to third anode electrodes (AE1, AE2, AE3). The first sub light-emitting element (SLD1) may include a first-first sub light-emitting element (SLD1a), a first-second sub light-emitting element (SLD1b), and a first-third sub light-emitting element (SLD1c). The first-first sub light-emitting element (SLD1a) may be disposed on the first anode electrode (AE1) so as to overlap with the first anode electrode (AE1). The first-first sub light-emitting element (SLD1a) may be connected to the first anode electrode (AE1). The first-second sub light-emitting element (SLD1b) may be disposed on the second anode electrode (AE2) so as to overlap with the second anode electrode (AE2). The first-second sub light-emitting element (SLD1b) may be connected to the second anode electrode (AE2). The first-third sub-light emitting element (SLD1c) may be positioned on the third anode electrode (AE3) so as to overlap with the third anode electrode (AE3). The first-third sub-light emitting element (SLD1c) may be connected to the third anode electrode (AE3).

[0139] In the embodiments, each of the first to third sub light-emitting elements (SLD1a, SLD1b, SLD1c) may be provided. For example, as illustrated in FIG. 7, two first to third sub light-emitting elements (SLD1a) may be provided on the first anode electrode (AE1), two first to second sub light-emitting elements (SLD1b) may be provided on the second anode electrode (AE2), and two first to third sub light-emitting elements (SLD1c) may be provided on the third anode electrode (AE3). However, the present invention is not limited thereto, and the number of the first to third sub light-emitting elements (SLD1a, SLD1b, SLD1c) disposed on the first to third anode electrodes (AE1, AE2, AE3) may vary depending on the embodiments.

[0140] A second sub light-emitting element (SLD2) may be disposed on each of the first to third lower connection electrodes (LCE1a, LCE1b, LCE1c). The second sub light-emitting element (SLD2) may include a second-first sub light-emitting element (SLD2a), a second-second sub light-emitting element (SLD2b), and a second-third sub light-emitting element (SLD2c). The second-first sub light-emitting element (SLD2a) may be disposed on the first-first lower connection electrode (LCE1a) so as to overlap with the first-first lower connection electrode (LCE1a). The second-first sub light-emitting element (SLD2a) may be connected to the first-first lower connection electrode (LCE1a). The second-second sub light-emitting element (SLD2b) may be disposed on the first-second lower connection electrode (LCE1b) so as to overlap with the first-second lower connection electrode (LCE1b). The second-second sub-light emitting element (SLD2b) may be connected to the first-second lower connection electrode (LCE1b). The second-third sub-light emitting element (SLD2c) may be positioned on the first-third lower connection electrode (LCE1c) so as to overlap with the first-third lower connection electrode (LCE1c). The second-third sub-light emitting element (SLD2c) may be connected to the first-third lower connection electrode (LCE1c).

[0141] In the embodiments, each of the 2-1 to 2-3 sub light-emitting elements (SLD2a, SLD2b, SLD2c) may be provided. For example, as illustrated in FIG. 7, two 2-1 sub light-emitting elements (SLD2a) may be provided on the 1-1 lower connection electrode (LCE1a), two 2-2 sub light-emitting elements (SLD2b) may be provided on the 1-2 lower connection electrode (LCE1b), and two 2-3 sub light-emitting elements (SLD2c) may be provided on the 1-3 lower connection electrode (LCE1c). However, the present invention is not limited thereto, and the number of the 2-1 to 2-3 sub light-emitting elements (SLD2a, SLD2b, SLD2c) arranged on the 1-1 to 1-3 lower connection electrodes (LCE1a, LCE1b, LCE1c) may vary depending on the embodiments.

[0142] The first-first sub-light emitting element (SLD1a) and the second-first sub-light emitting element (SLD2a) may be provided as light emitting elements (LD, see FIG. 3) included in the first sub-pixel (SP1). The first-second sub-light emitting element (SLD1b) and the second-second sub-light emitting element (SLD2b) may be provided as light emitting elements (LD) included in the second sub-pixel (SP2). The first-third sub-light emitting element (SLD1c) and the second-third sub-light emitting element (SLD2c) may be provided as light emitting elements (LD) included in the third sub-pixel (SP3). In this case, the 1-1 sub-light emitting element (SLD1a) and the 2-1 sub-light emitting element (SLD2a) can be viewed as constituting the first light emitting element (LD1) of the 1st sub-pixel (SP1), the 1-2 sub-light emitting element (SLD1b) and the 2-2 sub-light emitting element (SLD2b) can be viewed as constituting the second light emitting element (LD2) of the 2nd sub-pixel (SP2), and the 1-3 sub-light emitting element (SLD1c) and the 2-3 sub-light emitting element (SLD2c) can be viewed as constituting the third light emitting element (LD3) of the 3rd sub-pixel (SP3).

[0143] Each of the first to third light-emitting elements (LD1, LD2, LD3) may be an inorganic light-emitting diode containing an inorganic light-emitting material. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may also be used.

[0144] Referring to FIG. 8, a first upper connection electrode (UCE1) may be disposed on each of the first to third sub-pixels (SP1, SP2, and SP3). The first upper connection electrode (UCE1) may include a first-first upper connection electrode (UCE1a), a first-second upper connection electrode (UCE1b), and a first-third upper connection electrode (UCE1c). The first-first upper connection electrode (UCE1a) may be provided to the first sub-pixel (SP1) and may be disposed on the first anode electrode (AE1) so as to face the first anode electrode (AE1). The first-second upper connection electrode (UCE1b) may be provided to the second sub-pixel (SP2) and may be disposed on the second anode electrode (AE2) so as to face the second anode electrode (AE2). The first-third upper connection electrode (UCE1c) may be provided to the third sub-pixel (SP3) and may be placed on the third anode electrode (AE3) so as to face the third anode electrode (AE3).

[0145] A first-first sub-light emitting element (SLD1a) may be connected between the first anode electrode (AE1) and the first-first upper connection electrode (UCE1a). According to embodiments, when the first-first sub-light emitting elements (SLD1a) are provided, the first-first sub-light emitting elements (SLD1a) may be connected in parallel to each other between the first anode electrode (AE1) and the first-first upper connection electrode (UCE1a).

[0146] A first-second sub-light emitting element (SLD1b) may be connected between the second anode electrode (AE2) and the first-second upper connection electrode (UCE1b). According to embodiments, when the first-second sub-light emitting elements (SLD1b) are provided, the first-second sub-light emitting elements (SLD1b) may be connected in parallel to each other between the second anode electrode (AE2) and the first-second upper connection electrode (UCE1b).

[0147] A first-third sub-light emitting element (SLD1c) may be connected between the third anode electrode (AE3) and the first-third upper connection electrode (UCE1c). According to embodiments, when the first-third sub-light emitting elements (SLD1c) are provided, the first-third sub-light emitting elements (SLD1c) may be connected in parallel to each other between the third anode electrode (AE3) and the first-third upper connection electrode (UCE1c).

[0148] The cathode electrode (CE) may be provided in common to the first to third sub-pixels (SP1, SP2, SP3). For example, the cathode electrode (CE) may be provided as a common electrode. For example, the cathode electrode (CE) may extend in the second direction (DR2) and be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). Although not illustrated, the cathode electrode (CE) may extend not only in the second direction (DR2) but also in the first direction (DR1) and be used as a common electrode for all of the sub-pixels (SP) of FIG. 4. In this way, the cathode electrode (CE) may have various shapes.

[0149] The cathode electrode (CE) may be disposed on the same layer as the first to third upper connection electrodes (UCE1a, UCE1b, UCE1c). For example, the cathode electrode (CE) may be formed through the same forming process as the first to third upper connection electrodes (UCE1a, UCE1b, UCE1c). The cathode electrode (CE) may be disposed on the first to third lower connection electrodes (LCE1a, LCE1b, LCE1c) so as to face the first to third lower connection electrodes (LCE1a, LCE1b, LCE1c).

[0150] A second-first sub-light emitting element (SLD2a) may be connected between the cathode electrode (CE) and the first-first lower connection electrode (LCE1a). According to embodiments, when the second-first sub-light emitting elements (SLD2a) are provided, the second-first sub-light emitting elements (SLD2a) may be connected in parallel to each other between the first-first lower connection electrode (LCE1a) and the cathode electrode (CE).

[0151] A second-second sub-light emitting element (SLD2b) may be connected between the cathode electrode (CE) and the first-second lower connection electrode (LCE1b). According to embodiments, when the second-second sub-light emitting elements (SLD2b) are provided, the second-second sub-light emitting elements (SLD2b) may be connected in parallel to each other between the first-second lower connection electrode (LCE1b) and the cathode electrode (CE).

[0152] A second-third sub-light emitting element (SLD2c) may be connected between the cathode electrode (CE) and the first-third lower connection electrode (LCE1c). According to embodiments, when the second-third sub-light emitting elements (SLD2c) are provided, the second-third sub-light emitting elements (SLD2c) may be connected in parallel to each other between the first-third lower connection electrode (LCE1c) and the cathode electrode (CE).

[0153] The first-first upper connection electrode (UCE1a) may be electrically connected to the first-first lower connection electrode (LCE1a) through the first-first contact hole (CNT1a). In this case, the first-first sub-light-emitting element (SLD1a) and the second-first sub-light-emitting element (SLD2a) may be connected in series to each other through the first-first upper connection electrode (UCE1a) and the first-first lower connection electrode (LCE1a) between the first anode electrode (AE1) and the cathode electrode (CE).

[0154] The first-second upper connection electrode (UCE1b) may be electrically connected to the first-second lower connection electrode (LCE1b) through the first-second contact hole (CNT1b). In this case, the first-second sub-light-emitting element (SLD1b) and the second-second sub-light-emitting element (SLD2b) may be connected in series to each other through the first-second upper connection electrode (UCE1b) and the first-second lower connection electrode (LCE1b) between the second anode electrode (AE2) and the cathode electrode (CE).

[0155] The first-third upper connection electrode (UCE1c) may be electrically connected to the first-third lower connection electrode (LCE1c) through the first-third contact hole (CNT1b). In this case, the first-third sub-light-emitting element (SLD1c) and the second-third sub-light-emitting element (SLD2c) may be connected in series to each other through the first-third upper connection electrode (UCE1c) and the first-third lower connection electrode (LCE1c) between the third anode electrode (AE3) and the cathode electrode (CE).

[0156] FIGS. 9 and 10 are schematic cross-sectional views for explaining a pixel according to the first embodiment of FIG. 8. FIG. 9 is a schematic cross-sectional view taken along line X1-X1' of FIG. 8, and FIG. 10 is a schematic cross-sectional view taken along line Y1-Y1' of FIG. 8.

[0157] Referring to FIGS. 7 to 9, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0158] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0159] As described with reference to FIGS. 2 and 3, the sub-pixel circuit (SPC) of each of the first to third sub-pixels (SP1, SP2, SP3) may include transistors and capacitors. The semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). The conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1.

[0160] A buffer layer (BFL) may be disposed on one surface or plane of a substrate (SUB). The buffer layer (BFL) may serve to prevent diffusion of impurities into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0161] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may include polyimide.

[0162] A transistor (T_SP) may be placed on the buffer layer (BFL). The transistor (T_SP) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). For example, the transistor (T_SP) may be a transistor connected to the first anode electrode (AE1) among the transistors of the sub-pixel circuit (SPC).

[0163] A transistor (T_SP) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0164] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap a gate electrode (GE) of the transistor (T_SP). The channel region may be a semiconductor pattern that is substantially not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. For example, a p-type impurity may be used as the impurity, but embodiments are not limited thereto.

[0165] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0166] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor pattern (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers including inorganic materials. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide. However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0167] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL) to cover the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for forming the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0168] A gate electrode (GE) may be disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0169] The first and second terminals (ET1, ET2) may be disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0170] In the embodiments, the transistor (T_SP) may be formed of a low-temperature polysilicon transistor. However, the embodiments are not limited thereto. For example, the transistor (T_SP) may be formed of an oxide semiconductor transistor. In the embodiments, the sub-pixel circuit (SPC) of the first sub-pixel (SP1) may include transistors of different types. For example, the transistor (T_SP) may be formed of a low-temperature polysilicon transistor, and other transistors included in the sub-pixel circuit (SPC) of the first sub-pixel (SP1) may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the transistor (T_SP) is formed.

[0171] In the embodiments, the transistor (T_SP) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the transistor (T_SP) may be a transistor having a bottom gate structure. The structure of the transistor (T_SP) may be changed in various ways.

[0172] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0173] A first passivation layer (PSV1) may be disposed over the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The first passivation layer (PSV1) may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed underneath (or below) the first passivation layer (PSV1) and may provide a flat upper surface.

[0174] A connection pattern (CP) may be disposed on a first passivation layer (PSV1). The connection pattern (CP) may penetrate the first passivation layer (PSV1) and be connected to a second terminal (ET2) of the transistor (T_SP). The connection pattern (CP) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0175] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0176] A second passivation layer (PSV2) may be disposed on the connection pattern (CP) and the first passivation layer (PSV1). The second passivation layer (PSV2) may protect components disposed beneath the second passivation layer (PSV2) and provide a flat upper surface.

[0177] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0178] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0179] A display element layer (DPL) may be disposed on the second passivation layer (PSV2). The display element layer (DPL) may include a first anode electrode (AE1), a first-first lower connection electrode (LCE1a), a first bank (BNK1), a first light-emitting element (LD1), a first-first upper connection electrode (UCE1a), a cathode electrode (CE), an overcoat layer (OCL), and a capping layer (CPL).

[0180] A first anode electrode (AE1) and a first-first lower connection electrode (LCE1a) may be disposed on a pixel circuit layer (PCL). The first anode electrode (AE1) may be electrically connected to a connection pattern (CP) through a contact hole penetrating a second passivation layer (PSV2). In this way, the first anode electrode (AE1) may be electrically connected to a transistor (T_SP). The first-first lower connection electrode (LCE1a) may be spaced apart from the first anode electrode (AE1).

[0181] A first bank (BNK1) may be disposed on a pixel circuit layer (PCL), a first anode electrode (AE1), and a first-first lower connection electrode (LCE1a). The first bank (BNK1) may have a first opening (OP1) exposing portions of the first anode electrode (AE1) and the first-first lower connection electrode (LCE1a). A first-first sub-light emitting element (SLD1a) may be disposed on the first anode electrode (AE1) exposed by the first opening (OP1) of the first bank (BNK1). A second-first sub-light emitting element (SLD2a) may be disposed on the first-first lower connection electrode (LCE1a) exposed by the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) can be provided as a pixel defining film that defines an area where the first light-emitting element (LD1) is located.

[0182] The first bank (BNK1) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In some embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0183] The first light-emitting element (LD1) may include a light-emitting stack (EST) and a bonding electrode (BDE). The light-emitting stack (EST) may include a first semiconductor layer (11), a second semiconductor layer (12), an active layer (13), and an auxiliary layer (14). The first light-emitting element (LD1) may be implemented as a vertical light-emitting stack in which the bonding electrode (BDE), the first semiconductor layer (11), the active layer (13), the second semiconductor layer (12), and the auxiliary layer (14) are sequentially stacked on top of each other along a third direction (DR3).

[0184] The first semiconductor layer (11) may be configured to provide holes. The first semiconductor layer (11) may have a first polarity. For example, the first semiconductor layer (11) may include at least one p-type semiconductor layer. For example, the first semiconductor layer (11) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the first semiconductor layer (11) is not limited thereto, and various other materials may constitute the first semiconductor layer (11). In one embodiment of the present invention, the first semiconductor layer (11) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0185] The second semiconductor layer (12) is disposed on the first semiconductor layer (11) and may be configured to provide electrons. The second semiconductor layer (12) may have a second polarity different from the first polarity. For example, the second semiconductor layer (12) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (12) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer (12) is not limited thereto, and various other materials may constituting the second semiconductor layer (12). In one embodiment of the present invention, the second semiconductor layer (12) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant). According to an embodiment, the second semiconductor layer (12) may form an n-type semiconductor layer together with the auxiliary layer (14).

[0186] The active layer (13) can provide a region where electrons and holes recombine between the first semiconductor layer (11) and the second semiconductor layer (12). As electrons and holes recombine in the active layer (13), they transition to a lower energy level, and light having a corresponding wavelength can be generated. The active layer (13) can be formed in a single or multiple quantum well structure. When the active layer (13) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer can be repeatedly stacked on top of each other to form the active layer (13). However, the active layer (13) is not limited to the above-described structure.

[0187] The auxiliary layer (14) may include a gallium nitride (GaN) semiconductor material that is substantially undoped with impurities or doped with impurities at a relatively low concentration. The auxiliary layer (14) may form an n-type semiconductor layer together with the second semiconductor layer (12).

[0188] A bonding electrode (BDE) may be disposed under the first semiconductor layer (11). The bonding electrode (BDE) may be electrically connected to the first semiconductor layer (11). In embodiments, the bonding electrode (BDE) of the 1-1 sub-light emitting element (SLD1a) may be electrically connected to the first anode electrode (AE1). The bonding electrode (BDE) of the 2-1 sub-light emitting element (SLD2a) may be electrically connected to the 1-1 lower connection electrode (LCE1a). The bonding electrode (BDE) may include a eutectic metal.

[0189] The first light-emitting element (LD1) may further include an insulating film (15) covering an outer circumferential surface of the vertical light-emitting stack. The insulating film (15) may serve to prevent an electrical short circuit that may occur when the active layer (13) comes into contact with a conductive material other than the first and second semiconductor layers (11, 12). The insulating film (15) may include a transparent insulating material. The insulating film (15) may be configured to expose at least a portion of the bonding electrode (BDE) for electrical connection with the first anode electrode (AE1) or the 1-1 lower connection electrode (LCE1a). The insulating film (15) may be configured to expose an upper surface of the auxiliary layer (14) for electrical connection with the cathode electrode (CE) or the 1-1 upper connection electrode (UCE1a).

[0190] In embodiments, a reflective electrode may be further disposed between the bonding electrode (BDE) and the first semiconductor layer (11). In this case, light emitted from the first light-emitting element (LD1) can be more efficiently output toward the light-functional layer (LFL). The reflective electrode may be composed of a conductive material having a predetermined reflectivity. The conductive material may include an opaque metal. The opaque metal may include, for example, a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy thereof. However, the material of the reflective electrode is not limited thereto.

[0191] An overcoat layer (OCL) may be disposed within the first openings (OP1) in which the first light-emitting element (LD1) is disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1) bonded to the first anode electrode (AE1) and the first-first lower connection electrode (LCE1a) so as not to move. The overcoat layer (OCL) may protect components disposed under the overcoat layer (OCL) from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0192] In embodiments, the overcoat layer (OCL) may not be disposed on the upper surface of the first light-emitting element (LD1). For example, the first light-emitting element (LD1) may protrude into the light-functional layer (LFL). The first light-emitting element (LD1) may be at least partially positioned within the second opening (OP2) of the second bank (BNK2). For example, the height of the upper surface of the first light-emitting element (LD1) from the substrate (SUB) may be higher than the lowermost end of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0193] A first-first upper connection electrode (UCE1a) may be disposed on the first-first sub-light-emitting element (SLD1a). The first-first upper connection electrode (UCE1a) may be disposed to face the first anode electrode (AE1). The first-first upper connection electrode (UCE1a) may cover the upper surface of the first-first sub-light-emitting element (SLD1a). Accordingly, the first-first upper connection electrode (UCE1a) may contact the auxiliary layer (14) of the first-first sub-light-emitting element (SLD1a).

[0194] A cathode electrode (CE) may be placed on the second-first sub-light-emitting element (SLD2a). The cathode electrode (CE) may be placed to face the first-first lower connection electrode (LCE1a). The cathode electrode (CE) may cover the upper surface of the second-first sub-light-emitting element (SLD2a). Accordingly, the cathode electrode (CE) may contact the auxiliary layer (14) of the second-first sub-light-emitting element (SLD2a).

[0195] The cathode electrode (CE) can be electrically connected to a second power supply voltage node (VSSN, see FIG. 2). Accordingly, a second power supply voltage applied to the second power supply voltage node (VSSN) can be transmitted to the second-first sub-light emitting element (SLD2a) through the cathode electrode (CE).

[0196] The first-first upper connection electrode (UCE1a) can be electrically connected to the first-first lower connection electrode (LCE1a). For example, the first-first upper connection electrode (UCE1a) can be in electrical contact with the first-first lower connection electrode (LCE1a) through the first-first contact hole (CNT1a) formed in the first bank (BNK1). Through the first-first upper connection electrode (UCE1a) and the first-first lower connection electrode (LCE1a), the auxiliary layer (14) of the first-first sub-light-emitting element (SLD1a) and the bonding electrode (BDE) of the second-first sub-light-emitting element (SLD2a) can be connected. Accordingly, the first-first sub-light-emitting element (SLD1a) and the second-first sub-light-emitting element (SLD2a) can be connected in series between the cathode electrode (CE) and the first anode electrode (AE1).

[0197] The first-first upper connection electrode (UCE1a) and the cathode electrode (CE) may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In embodiments, the first-first upper connection electrode (UCE1a) and the cathode electrode (CE) may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the materials of the first-first upper connection electrode (UCE1a) and the cathode electrode (CE) are not limited thereto.

[0198] A capping layer (CPL) may be disposed on the first upper connection electrode (UCE1a) and the cathode electrode (CE). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first upper connection electrode (UCE1a), the cathode electrode (CE), and the first light-emitting element (LD1), from external moisture and humidity, etc. within the scope and spirit of the present disclosure. The capping layer (CPL) may include at least one of a metal oxide, such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc. However, the material of the capping layer (CPL) is not limited thereto.

[0199] Above, the pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1) have been described. Each of the second and third sub-pixels (SP2, SP3) of FIGS. 7 and 8 can also be configured similarly to the first sub-pixel (SP1) within a range not otherwise described herein.

[0200] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a third passivation layer (PSV3), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0201] A second bank (BNK2) may be disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have a second opening (OP2) that overlaps the first opening (OP1).

[0202] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In some embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0203] A reflective layer (RFL) may be disposed on side surfaces of the second bank (BNK2) adjacent to the second opening (OP2). The reflective layer (RFL) is configured to reflect incident light, and thus, light emission efficiency may be improved. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0204] A third passivation layer (PSV3) may be disposed on the capping layer (CPL) within the second opening (OP2). The third passivation layer (PSV3) may protect components disposed beneath the third passivation layer (PSV3) and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0205] A first light conversion pattern (CCP1) may be disposed within a second opening (OP2) on the third passivation layer (PSV3). The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. The color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0206] The first sub-pixel (SP1) may be a red sub-pixel. When the first light-emitting element (LD1) emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1) emits red light, the first light conversion pattern (CCP1) may include scattering particles. In this way, the particles included in the first light conversion pattern (CCP1) may be variously changed depending on the color of the light emitted by the first light-emitting element (LD1).

[0207] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may be configured to refract or totally reflect light depending on an incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0208] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) may overlap the first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0209] Referring to FIGS. 7, 8, and 10, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0210] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 9. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1, SP2, SP3) may be provided, respectively. In the display element layer (DPL), first to third light-emitting elements (LD1, LD2, LD3) corresponding to the first to third sub-pixels (SP1, SP2, SP3) may be provided, respectively. The first to third light-emitting elements (LD1, LD2, LD3) may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1) may be connected between a cathode electrode (CE, see FIG. 9) and a transistor (T_SP, see FIG. 9) included in the sub-pixel circuit of the first sub-pixel (SP1). The second light-emitting element (LD2) may be connected between the cathode electrode (CE) and a transistor included in the sub-pixel circuit of the second sub-pixel (SP2). The third light-emitting element (LD3) may be connected between the cathode electrode (CE) and a transistor included in the sub-pixel circuit of the third sub-pixel (SP3). Hereinafter, descriptions of overlapping contents may be omitted.

[0211] A light-functional layer (LFL) may be provided on the display element layer (DPL). The light-functional layer (LFL) is described in the same manner as described with reference to FIG. 9. Hereinafter, description of overlapping content may be omitted.

[0212] The second bank (BNK2) may have second openings (OP2). It may be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the second bank (BNK2). The area overlapping the second bank (BNK2) may correspond to the non-light-emitting area (NEMA). The area overlapping the second openings (OP2) of the second bank (BNK2) may correspond to the light-emitting area (EMA) of the first to third sub-pixels (SP1, SP2, SP3).

[0213] A third passivation layer (PSV3) may be disposed within the second openings (OP2) on the capping layer (CPL). First and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) may be disposed within the second openings (OP2) on the third passivation layer (PSV3).

[0214] In the embodiments, the first to third light-emitting elements (LD1, LD2, LD3) may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light output efficiency. Accordingly, the first to third sub-pixels (SP1, SP2, SP3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0215] In the embodiments, the first to third light-emitting elements (LD1, LD2, LD3) may be configured to emit red, green, and blue light, respectively. In this case, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may each include scattering particles (SCT). In this way, depending on the color of the light emitted from the first to third light-emitting elements (LD1, LD2, LD3), the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed.

[0216] In the embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0217] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first and second light conversion patterns (CCP1, CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3).

[0218] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0219] Each of the first to third color filters (CF1, CF2, CF3) can selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1, CF2, CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, embodiments are not limited thereto, and the first to third color filters (CF1, CF2, CF3) may have a refractive index lower than or equal to that of the low-refractive-index layer (LRL).

[0220] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It can be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0221] In embodiments, the light blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light blocking pattern between the first and second color filters (CF1, CF2) among the light blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, the light blocking pattern between the second and third color filters (CF2, CF3) among the light blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap, and the light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of an adjacent pixel may be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) may extend into the non-emitting area (NEMA) to form the light blocking patterns (LBP).

[0222] FIGS. 11 and 12 are schematic plan views illustrating the first and second embodiments of one of the pixels included in the display panel of FIG. 3.

[0223] Referring to FIG. 11, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in the second direction (DR2). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0224] First to third anode electrodes (AE1, AE2, AE3) may be arranged in the first to third sub-pixels (SP1, SP2, SP3), respectively. The first to third anode electrodes (AE1, AE2, AE3) may be configured in the same manner as described with reference to FIG. 7.

[0225] A first lower connection electrode (LCE1) may be disposed on each of the first to third sub-pixels (SP1, SP2, and SP3). The first lower connection electrode (LCE1) may include a first-first lower connection electrode (LCE1a), a first-second lower connection electrode (LCE1b), and a first-third lower connection electrode (LCE1c). The first-first to first-third lower connection electrodes (LCE1a, LCE1b, and LCE1c) may be configured in the same manner as described with reference to FIG. 7.

[0226] A second lower connection electrode (LCE2) may be disposed in each of the first to third sub-pixels (SP1, SP2, and SP3). The second lower connection electrode (LCE2) may include a second-first lower connection electrode (LCE2a), a second-second lower connection electrode (LCE2b), and a second-third lower connection electrode (LCE2c). The second-first lower connection electrode (LCE2a) may be provided in the first sub-pixel (SP1) and may be spaced apart from the first anode electrode (AE1) and the first-first lower connection electrode (LCE1a). The second-second lower connection electrode (LCE2b) may be provided in the second sub-pixel (SP2) and may be spaced apart from the second anode electrode (AE2) and the first-second lower connection electrode (LCE1b). The 2-3rd lower connection electrode (LCE2c) may be provided to the 3rd sub-pixel (SP3) and may be spaced apart from the 3rd anode electrode (AE3) and the 1-3rd lower connection electrode (LCE1c). In embodiments, the 2-1st to 2-3rd lower connection electrodes (LCE2a, LCE2b, LCE2c) may be arranged in the same layer as the 1st to 3rd anode electrodes (AE1, AE2, AE3) and the 1-1st to 1-3rd lower connection electrodes (LCE1a, LCE1b, LCE1c). In this case, the 2-1 to 2-3 lower connection electrodes (LCE2a, LCE2b, LCE2c) may be formed through the same formation process as the 1-3 anode electrodes (AE1, AE2, AE3) and the 1-1 to 1-3 lower connection electrodes (LCE1a, LCE1b, LCE1c).

[0227] A first sub-light emitting element (SLD1) may be disposed on each of the first to third anode electrodes (AE1, AE2, AE3). The first sub-light emitting element (SLD1) may include a first-first sub-light emitting element (SLD1a), a first-second sub-light emitting element (SLD1b), and a first-third sub-light emitting element (SLD1c). The first-first to first-third sub-light emitting elements (SLD1a, SLD1b, SLD1c) may be configured in the same manner as described with reference to FIG. 7.

[0228] In Fig. 11, each of the first to third sub-light emitting elements (SLD1a, SLD1b, SLD1c) is illustrated as being provided one by one, but the present invention is not limited thereto. For example, as described with reference to Fig. 7, each of the first to third sub-light emitting elements (SLD1a, SLD1b, SLD1c) may be provided.

[0229] A second sub-light emitting element (SLD2) may be disposed on each of the first to third lower connection electrodes (LCE1a, LCE1b, LCE1c). The second sub-light emitting element (SLD2) may include a second-first sub-light emitting element (SLD2a), a second-second sub-light emitting element (SLD2b), and a second-third sub-light emitting element (SLD2c). The second-first to second-third sub-light emitting elements (SLD2a, SLD2b, SLD2c) may be configured in the same manner as described with reference to FIG. 7.

[0230] In Fig. 11, each of the 2-1 to 2-3 sub-light emitting elements (SLD2a, SLD2b, SLD2c) is illustrated as being provided one by one, but the present invention is not limited thereto. For example, as described with reference to Fig. 7, each of the 2-1 to 2-3 sub-light emitting elements (SLD2a, SLD2b, SLD2c) may be provided.

[0231] A third sub light-emitting element (SLD3) may be disposed on each of the 2-1 to 2-3 lower connection electrodes (LCE2a, LCE2b, LCE2c). The third sub light-emitting element (SLD3) may include a 3-1 sub light-emitting element (SLD3a), a 3-2 sub light-emitting element (SLD3b), and a 3-3 sub light-emitting element (SLD3c). The 3-1 sub light-emitting element (SLD3a) may be disposed on the 2-1 lower connection electrode (LCE2a) so as to overlap with the 2-1 lower connection electrode (LCE2a). The 3-1 sub light-emitting element (SLD3a) may be connected to the 2-1 lower connection electrode (LCE2a). The 3-2 sub light-emitting element (SLD3b) may be disposed on the 2-2 lower connection electrode (LCE2b) so as to overlap with the 2-2 lower connection electrode (LCE2b). The third-second sub-light emitting element (SLD3b) may be connected to the second-second lower connection electrode (LCE2b). The third-third sub-light emitting element (SLD3c) may be positioned on the second-third lower connection electrode (LCE2c) so as to overlap with the second-third lower connection electrode (LCE2c). The third-third sub-light emitting element (SLD3c) may be connected to the second-third lower connection electrode (LCE2c).

[0232] In Fig. 11, each of the 3-1 to 3-3 sub light-emitting elements (SLD3a, SLD3b, SLD3c) is illustrated as being provided one by one, but the present invention is not limited thereto. Each of the 3-1 to 3-3 sub light-emitting elements (SLD3a, SLD3b, SLD3c) may be provided. For example, two or more 3-1 sub light-emitting elements (SLD3a) may be provided on the 2-1 lower connection electrode (LCE2a), and in this case, each of the 3-1 sub light-emitting elements (SLD3a) may overlap with the 2-1 lower connection electrode (LCE2a) and may also be connected to the 2-1 lower connection electrode (LCE2a).

[0233] The first-first sub-light emitting element (SLD1a), the second-first sub-light emitting element (SLD2a), and the third-first sub-light emitting element (SLD3a) may be provided as light emitting elements (LD, see FIG. 2) included in the first sub-pixel (SP1). The first-second sub-light emitting element (SLD1b), the second-second sub-light emitting element (SLD2b), and the third-second sub-light emitting element (SLD3b) may be provided as light emitting elements (LD) included in the second sub-pixel (SP2). The first-third sub-light emitting element (SLD1c), the second-third sub-light emitting element (SLD2c), and the third-third sub-light emitting element (SLD3c) may be provided as light emitting elements (LD) included in the third sub-pixel (SP3). In this case, the first-first sub-light emitting element (SLD1a), the second-first sub-light emitting element (SLD2a), and the third-first sub-light emitting element (SLD3a) can be viewed as constituting the first light emitting element (LD1) of the first sub-pixel (SP1), the first-second sub-light emitting element (SLD1b), the second-second sub-light emitting element (SLD2b), and the third-second sub-light emitting element (SLD3b) can be viewed as constituting the second light emitting element (LD2) of the second sub-pixel (SP2), and the first-third sub-light emitting element (SLD1c), the second-third sub-light emitting element (SLD2c), and the third-third sub-light emitting element (SLD3c) can be viewed as constituting the third light emitting element (LD3) of the third sub-pixel (SP3).

[0234] Each of the first to third light-emitting elements (LD1, LD2, LD3) may be an inorganic light-emitting diode containing an inorganic light-emitting material. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may also be used.

[0235] Referring to FIG. 12, a first upper connection electrode (UCE1) may be disposed on each of the first to third sub-pixels (SP1, SP2, and SP3). The first upper connection electrode (UCE1) may include a first-first upper connection electrode (UCE1a), a first-second upper connection electrode (UCE1b), and a first-third upper connection electrode (UCE1c). The first-first to first-third upper connection electrodes (UCE1a, UCE1b, and UCE1c) may be configured in the same manner as described with reference to FIG. 8.

[0236] A first-first sub-light emitting element (SLD1a) may be connected between the first anode electrode (AE1) and the first-first upper connection electrode (UCE1a). According to embodiments, when the first-first sub-light emitting elements (SLD1a) are provided, the first-first sub-light emitting elements (SLD1a) may be connected in parallel to each other between the first anode electrode (AE1) and the first-first upper connection electrode (UCE1a).

[0237] A first-second sub-light emitting element (SLD1b) may be connected between the second anode electrode (AE2) and the first-second upper connection electrode (UCE1b). According to embodiments, when the first-second sub-light emitting elements (SLD1b) are provided, the first-second sub-light emitting elements (SLD1b) may be connected in parallel to each other between the second anode electrode (AE2) and the first-second upper connection electrode (UCE1b).

[0238] A first-third sub-light emitting element (SLD1c) may be connected between the third anode electrode (AE3) and the first-third upper connection electrode (UCE1c). According to embodiments, when the first-third sub-light emitting elements (SLD1c) are provided, the first-third sub-light emitting elements (SLD1c) may be connected in parallel to each other between the third anode electrode (AE3) and the first-third upper connection electrode (UCE1c).

[0239] A second upper connection electrode (UCE2) may be disposed on each of the first to third sub-pixels (SP1, SP2, and SP3). The second upper connection electrode (UCE2) may include a second-first upper connection electrode (UCE2a), a second-second upper connection electrode (UCE2b), and a second-third upper connection electrode (UCE2c). The second-first upper connection electrode (UCE2a) may be provided to the first sub-pixel (SP1), and may be disposed on the first-first lower connection electrode (LCE1a) to face the first-first lower connection electrode (LCE1a). The second-second upper connection electrode (UCE2b) may be provided to the second sub-pixel (SP2), and may be disposed on the first-second lower connection electrode (LCE1b) to face the first-second lower connection electrode (LCE1b). The 2nd-3rd upper connection electrode (UCE2c) may be provided to the 3rd sub-pixel (SP3) and may be placed on the 1st-3rd lower connection electrode (LCE1c) so as to face the 1st-3rd lower connection electrode (LCE1c).

[0240] A second-first sub-light emitting element (SLD2a) may be connected between the first-first lower connection electrode (LCE1a) and the second-first upper connection electrode (UCE2a). According to embodiments, when the second-first sub-light emitting elements (SLD2a) are provided, the second-first sub-light emitting elements (SLD2a) may be connected in parallel between the first-first lower connection electrode (LCE1a) and the second-first upper connection electrode (UCE2a).

[0241] A second-second sub-light emitting element (SLD2b) may be connected between the first-second lower connection electrode (LCE1b) and the second-second upper connection electrode (UCE2b). According to embodiments, when the second-second sub-light emitting elements (SLD2b) are provided, the second-second sub-light emitting elements (SLD2b) may be connected in parallel to each other between the first-second lower connection electrode (LCE1b) and the second-second upper connection electrode (UCE2b).

[0242] A second-third sub-light emitting element (SLD2c) may be connected between the first-third lower connection electrode (LCE1c) and the second-third upper connection electrode (UCE2c). According to embodiments, when the second-third sub-light emitting elements (SLD2c) are provided, the second-third sub-light emitting elements (SLD2c) may be connected in parallel between the first-third lower connection electrode (LCE1c) and the second-third upper connection electrode (UCE2c).

[0243] The cathode electrode (CE) may be provided in common to the first to third sub-pixels (SP1, SP2, SP3). For example, the cathode electrode (CE) may be provided as a common electrode. For example, the cathode electrode (CE) may extend in the second direction (DR2) and be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). Although not illustrated, the cathode electrode (CE) may extend not only in the second direction (DR2) but also in the first direction (DR1) and be used as a common electrode for all of the sub-pixels (SP) of FIG. 4. In this way, the cathode electrode (CE) may have various shapes.

[0244] The cathode electrode (CE) may be disposed on the same layer as the first to third upper connection electrodes (UCE1a, UCE1b, UCE1c) and the second to third upper connection electrodes (UCE2a, UCE2b, UCE2c). For example, the cathode electrode (CE) may be formed through the same forming process as the first to third upper connection electrodes (UCE1a, UCE1b, UCE1c) and the second to third upper connection electrodes (UCE2a, UCE2b, UCE2c). The cathode electrode (CE) may be disposed on the second to third lower connection electrodes (LCE2a, LCE2b, LCE2c) so as to face the second to third lower connection electrodes (LCE2a, LCE2b, LCE2c).

[0245] A third-first sub-light emitting element (SLD3a) may be connected between the cathode electrode (CE) and the second-first lower connection electrode (LCE2a). According to embodiments, when the third-first sub-light emitting elements (SLD3a) are provided, the third-first sub-light emitting elements (SLD3a) may be connected in parallel to each other between the second-first lower connection electrode (LCE2a) and the cathode electrode (CE).

[0246] A third-second sub-light emitting element (SLD3b) may be connected between the cathode electrode (CE) and the second-second lower connection electrode (LCE2b). According to embodiments, when the third-second sub-light emitting elements (SLD3b) are provided, the third-second sub-light emitting elements (SLD3b) may be connected in parallel to each other between the second-second lower connection electrode (LCE2b) and the cathode electrode (CE).

[0247] A third-third sub-light emitting element (SLD3c) may be connected between the cathode electrode (CE) and the second-third lower connection electrode (LCE2c). According to embodiments, when the third-third sub-light emitting elements (SLD3c) are provided, the third-third sub-light emitting elements (SLD3c) may be connected in parallel to each other between the second-third lower connection electrode (LCE2c) and the cathode electrode (CE).

[0248] The first-first upper connection electrode (UCE1a) can be electrically connected to the first-first lower connection electrode (LCE1a) through the first-first contact hole (CNT1a). In this case, the first-first sub-light-emitting element (SLD1a) and the second-first sub-light-emitting element (SLD2a) can be connected in series to each other through the first-first upper connection electrode (UCE1a) and the first-first lower connection electrode (LCE1a) between the first anode electrode (AE1) and the second-first upper connection electrode (UCE2a).

[0249] The 2-1 upper connection electrode (UCE2a) can be electrically connected to the 2-1 lower connection electrode (LCE2a) through the 2-1 contact hole (CNT2a). In this case, the 2-1 sub-light-emitting element (SLD2a) and the 3-1 sub-light-emitting element (SLD3a) can be connected in series to each other through the 2-1 upper connection electrode (UCE2a) and the 2-1 lower connection electrode (LCE2a) between the 1-1 lower connection electrode (LCE1a) and the cathode electrode (CE).

[0250] In this way, the first to third-first sub-light emitting elements (SLD1a, SLD2a, SLD3a) can be connected in series with each other between the first anode electrode (AE1) and the cathode electrode (CE).

[0251] The first-second upper connection electrode (UCE1b) may be electrically connected to the first-second lower connection electrode (LCE1b) through the first-second contact hole (CNT1b). In this case, the first-second sub-light-emitting element (SLD1b) and the second-second sub-light-emitting element (SLD2b) may be connected in series to each other through the first-second upper connection electrode (UCE1b) and the first-second lower connection electrode (LCE1b) between the second anode electrode (AE2) and the second-second upper connection electrode (UCE2b).

[0252] The second-second upper connection electrode (UCE2b) may be electrically connected to the second-second lower connection electrode (LCE2b) through the second-second contact hole (CNT2b). In this case, the second-second sub-light-emitting element (SLD2b) and the third-second sub-light-emitting element (SLD3b) may be connected in series to each other through the second-second upper connection electrode (UCE2b) and the second-second lower connection electrode (LCE2b) between the first-second lower connection electrode (LCE1b) and the cathode electrode (CE).

[0253] In this way, the first to third-second sub-light emitting elements (SLD1b, SLD2b, SLD3b) can be connected in series with each other between the second anode electrode (AE2) and the cathode electrode (CE).

[0254] The first-third upper connection electrode (UCE1c) may be electrically connected to the first-third lower connection electrode (LCE1c) through the first-third contact hole (CNT1c). In this case, the first-third sub-light-emitting element (SLD1c) and the second-third sub-light-emitting element (SLD2c) may be connected in series with each other through the first-third upper connection electrode (UCE1c) and the first-third lower connection electrode (LCE1c) between the third anode electrode (AE3) and the second-third upper connection electrode (UCE2c).

[0255] The 2-3 upper connection electrode (UCE2c) may be electrically connected to the 2-3 lower connection electrode (LCE2c) through the 2-3 contact hole (CNT2c). In this case, the 2-3 sub-light-emitting element (SLD2c) and the 3-3 sub-light-emitting element (SLD3c) may be connected in series to each other through the 2-3 upper connection electrode (UCE2c) and the 2-3 lower connection electrode (LCE2c) between the 1-3 lower connection electrode (LCE1c) and the cathode electrode (CE).

[0256] In this way, the 1st to 3rd sub-light emitting elements (SLD1c, SLD2c, SLD3c) can be connected in series with each other between the third anode electrode (AE3) and the cathode electrode (CE).

[0257] Figures 13 and 14 are schematic cross-sectional views for explaining a pixel according to the first and second embodiments of Figure 12. Figure 13 is a schematic cross-sectional view taken along line X2-X2' of Figure 12, and Figure 14 is a schematic cross-sectional view taken along line Y2-Y2' of Figure 12.

[0258] Referring to FIGS. 11 to 13, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0259] The pixel circuit layer (PCL) can be configured as described with reference to Fig. 9. Therefore, description of overlapping content can be omitted.

[0260] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a first anode electrode (AE1), a first-first lower connection electrode (LCE1a), a second-first lower connection electrode (LCE2a), a first bank (BNK1), a first light-emitting element (LD1), a first-first upper connection electrode (UCE1a), a second-first upper connection electrode (UCE2a), a cathode electrode (CE), an overcoat layer (OCL), and a capping layer (CPL).

[0261] A first anode electrode (AE1), a first-first lower connection electrode (LCE1a), and a second-first lower connection electrode (LCE2a) may be disposed on a pixel circuit layer (PCL). The first anode electrode (AE1) may be electrically connected to a connection pattern (CP) through a contact hole penetrating a second passivation layer (PSV2). In this way, the first anode electrode (AE1) may be electrically connected to a transistor (T_SP). The first-first lower connection electrode (LCE1a) may be spaced apart from the first anode electrode (AE1), and the second-first lower connection electrode (LCE2a) may be spaced apart from the first-first lower connection electrode (LCE1a) and the first anode electrode (AE1).

[0262] A first bank (BNK1) may be disposed on a pixel circuit layer (PCL), a first anode electrode (AE1), a first-first lower connection electrode (LCE1a), and a second-first lower connection electrode (LCE2a). The first bank (BNK1) may have a first opening (OP1) that exposes portions of the first anode electrode (AE1), the first-first lower connection electrode (LCE1a), and the second-first lower connection electrode (LCE2a). A first-first sub-light-emitting element (SLD1a) may be disposed on the first anode electrode (AE1) exposed by the first opening (OP1) of the first bank (BNK1). A second-first sub-light-emitting element (SLD2a) may be disposed on the first-first lower connection electrode (LCE1a) exposed by the first opening (OP1) of the first bank (BNK1). A third-first sub-light emitting element (SLD3a) may be placed on the second-first lower connecting electrode (LCE2a) exposed by the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film defining an area where the first light emitting element (LD1) is positioned.

[0263] The first bank (BNK1) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In some embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0264] The first light-emitting element (LD1) may include a light-emitting stack (EST) and a bonding electrode (BDE). The light-emitting stack (EST) may include a first semiconductor layer (11), a second semiconductor layer (12), an active layer (13), and an auxiliary layer (14). The first light-emitting element (LD1) may be implemented as a vertical light-emitting stack in which the bonding electrode (BDE), the first semiconductor layer (11), the active layer (13), the second semiconductor layer (12), and the auxiliary layer (14) are sequentially stacked along a third direction (DR3).

[0265] The first semiconductor layer (11), the second semiconductor layer (12), the active layer (13), and the auxiliary layer (14) can be configured in the same manner as described with reference to Fig. 9. Therefore, description of overlapping contents is omitted.

[0266] The bonding electrode (BDE) may be disposed under the first semiconductor layer (11) and may be electrically connected to the first semiconductor layer (11). In embodiments, the bonding electrode (BDE) of the 1-1 sub-light emitting element (SLD1a) may be electrically connected to the first anode electrode (AE1), the bonding electrode (BDE) of the 2-1 sub-light emitting element (SLD2a) may be electrically connected to the 1-1 lower connection electrode (LCE1a), and the bonding electrode (BDE) of the 3-1 sub-light emitting element (SLD3a) may be electrically connected to the 2-1 lower connection electrode (LCE2a). The bonding electrode (BDE) may include a eutectic metal.

[0267] The first light-emitting element (LD1) may further include an insulating film (15) covering the outer circumferential surface of the vertical light-emitting stack. The insulating film (15) may serve to prevent an electrical short circuit that may occur when the active layer (13) comes into contact with a conductive material other than the first and second semiconductor layers (11, 12). The insulating film (15) may include a transparent insulating material. The insulating film (15) may be configured to expose at least a portion of the bonding electrode (BDE) for electrical connection with the first anode electrode (AE1), the first-first lower connection electrode (LCE1a), or the second-first lower connection electrode (LCE2a). The insulating film (15) may be configured to expose the upper surface of the auxiliary layer (14) for electrical connection with the cathode electrode (CE), the first-first upper connection electrode (UCE1a), or the second-first upper connection electrode (UCE2a).

[0268] In embodiments, a reflective electrode may be further disposed between the bonding electrode (BDE) and the first semiconductor layer (11). In this case, light emitted from the first light-emitting element (LD1) can be more efficiently output toward the light-functional layer (LFL). The reflective electrode may be composed of a conductive material having a predetermined reflectivity. The conductive material may include an opaque metal. The opaque metal may include, for example, a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy thereof. However, the material of the reflective electrode is not limited thereto.

[0269] An overcoat layer (OCL) may be disposed within the first openings (OP1) in which the first light-emitting element (LD1) is disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1) bonded to the first anode electrode (AE1), the first-first lower connection electrode (LCE1a), and the second-first lower connection electrode (LCE2a) so as not to move. The overcoat layer (OCL) may protect components disposed under the overcoat layer (OCL) from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0270] In embodiments, the overcoat layer (OCL) may not be disposed on the upper surface of the first light-emitting element (LD1). For example, the first light-emitting element (LD1) may protrude into the light-functional layer (LFL). The first light-emitting element (LD1) may be at least partially positioned within the second opening (OP2) of the second bank (BNK2). For example, the height of the upper surface of the first light-emitting element (LD1) from the substrate (SUB) may be higher than the lowermost end of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0271] A first-first upper connection electrode (UCE1a) may be disposed on the first-first sub-light-emitting element (SLD1a). The first-first upper connection electrode (UCE1a) may be disposed to face the first anode electrode (AE1). The first-first upper connection electrode (UCE1a) may cover the upper surface of the first-first sub-light-emitting element (SLD1a). Accordingly, the first-first upper connection electrode (UCE1a) may contact the auxiliary layer (14) of the first-first sub-light-emitting element (SLD1a).

[0272] A second-first upper connection electrode (UCE2a) may be disposed on the second-first sub-light-emitting element (SLD2a). The second-first upper connection electrode (UCE2a) may be disposed to face the first-first lower connection electrode (LCE1a). The second-first upper connection electrode (UCE2a) may cover the upper surface of the second-first sub-light-emitting element (SLD2a). Accordingly, the second-first upper connection electrode (UCE2a) may contact the auxiliary layer (14) of the second-first sub-light-emitting element (SLD2a).

[0273] A cathode electrode (CE) may be placed on the 3-1 sub-light emitting element (SLD3a). The cathode electrode (CE) may be placed to face the 2-1 lower connection electrode (LCE2a). The cathode electrode (CE) may cover the upper surface of the 3-1 sub-light emitting element (SLD3a). Accordingly, the cathode electrode (CE) may contact the auxiliary layer (14) of the 3-1 sub-light emitting element (SLD3a).

[0274] The cathode electrode (CE) can be electrically connected to a second power supply voltage node (VSSN, see FIG. 2). Accordingly, a second power supply voltage applied to the second power supply voltage node (VSSN) can be transmitted to the third-first sub-light emitting element (SLD3a) through the cathode electrode (CE).

[0275] The first-first upper connection electrode (UCE1a) can be electrically connected to the first-first lower connection electrode (LCE1a). For example, the first-first upper connection electrode (UCE1a) can be in electrical contact with the first-first lower connection electrode (LCE1a) through the first-first contact hole (CNT1a) formed in the first bank (BNK1). Through the first-first upper connection electrode (UCE1a) and the first-first lower connection electrode (LCE1a), the auxiliary layer (14) of the first-first sub-light-emitting element (SLD1a) and the bonding electrode (BDE) of the second-first sub-light-emitting element (SLD2a) can be connected. Accordingly, the first-first sub-light-emitting element (SLD1a) and the second-first sub-light-emitting element (SLD2a) can be connected in series between the second-first upper connection electrode (UCE2a) and the first anode electrode (AE1).

[0276] The 2-1 upper connection electrode (UCE2a) can be electrically connected to the 2-1 lower connection electrode (LCE2a). For example, the 2-1 upper connection electrode (UCE2a) can be in electrical contact with the 2-1 lower connection electrode (LCE2a) through the 2-1 contact hole (CNT2a) formed in the 1st bank (BNK1). The auxiliary layer (14) of the 2-1 sub-light-emitting element (SLD2a) and the bonding electrode (BDE) of the 3-1 sub-light-emitting element (SLD3a) can be connected through the 2-1 upper connection electrode (UCE2a) and the 2-1 lower connection electrode (LCE2a). Accordingly, the 2-1 sub-light-emitting element (SLD2a) and the 3-1 sub-light-emitting element (SLD3a) can be connected in series between the 1-1 lower connection electrode (LCE1a) and the cathode electrode (CE).

[0277] The first-first upper connection electrode (UCE1a), the second-first upper connection electrode (UCE2a), and the cathode electrode (CE) may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In embodiments, the first-first upper connection electrode (UCE1a), the second-first upper connection electrode (UCE2a), and the cathode electrode (CE) may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and the like. However, the materials of the first-first upper connection electrode (UCE1a), the second-first upper connection electrode (UCE2a), and the cathode electrode (CE) are not limited thereto.

[0278] A capping layer (CPL) may be disposed on the first-first upper connection electrode (UCE1a), the second-first upper connection electrode (UCE2a), and the cathode electrode (CE). The capping layer (CPL) may be configured in the same manner as described with reference to FIG. 9.

[0279] Above, the pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1) have been described. Each of the second and third sub-pixels (SP2, SP3) of FIGS. 11 and 12 can also be configured similarly to the first sub-pixel (SP1) within a range not otherwise described herein.

[0280] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a third passivation layer (PSV3), a first light conversion pattern (CCP1), a low-refractive layer (LRL), and a color filter layer (CFL). The light functional layer (LFL) may be configured in the same manner as described with reference to FIG. 9. Therefore, description of overlapping content may be omitted.

[0281] Referring to FIGS. 11, 12, and 14, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0282] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 13. The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 9. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1, SP2, SP3) may be provided, respectively. In the display element layer (DPL), first to third light-emitting elements (LD1, LD2, LD3) corresponding to the first to third sub-pixels (SP1, SP2, SP3) may be provided, respectively. The first to third light-emitting elements (LD1, LD2, LD3) may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1) may be connected between a cathode electrode (CE, see FIG. 13) and a transistor (T_SP, see FIG. 13) included in a sub-pixel circuit of the first sub-pixel (SP1). The second light-emitting element (LD2) may be connected between the cathode electrode (CE) and a transistor included in a sub-pixel circuit of the second sub-pixel (SP2). The third light-emitting element (LD3) may be connected between the cathode electrode (CE) and a transistor included in a sub-pixel circuit of the third sub-pixel (SP3). Hereinafter, descriptions of overlapping content may be omitted.

[0283] A light-functional layer (LFL) may be provided on the display element layer (DPL). The light-functional layer (LFL) is described in the same manner as described with reference to FIG. 10. Therefore, description of overlapping content may be omitted.

[0284] FIGS. 15 and 16 are schematic plan views illustrating embodiments 1-3 of one of the pixels included in the display panel of FIG. 3.

[0285] Referring to FIG. 15, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in the second direction (DR2). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0286] First to third anode electrodes (AE1, AE2, AE3) may be arranged in the first to third sub-pixels (SP1, SP2, SP3), respectively. The first to third anode electrodes (AE1, AE2, AE3) may be configured in the same manner as described with reference to FIG. 11.

[0287] A first lower connection electrode (LCE1) may be disposed on each of the first to third sub-pixels (SP1, SP2, SP3). The first lower connection electrode (LCE1) may include a first-first lower connection electrode (LCE1a), a first-second lower connection electrode (LCE1b), and a first-third lower connection electrode (LCE1c). The first-first to first-third lower connection electrodes (LCE1a, LCE1b, LCE1c) may be configured in the same manner as described with reference to FIG. 11.

[0288] A second lower connection electrode (LCE2) may be disposed on each of the first to third sub-pixels (SP1, SP2, and SP3). The second lower connection electrode (LCE2) may include a second-first lower connection electrode (LCE2a), a second-second lower connection electrode (LCE2b), and a second-third lower connection electrode (LCE2c). The second-first to second-third lower connection electrodes (LCE2a, LCE2b, and LCE2c) may be configured in the same manner as described with reference to FIG. 11.

[0289] A third lower connection electrode (LCE3) may be disposed in each of the first to third sub-pixels (SP1, SP2, and SP3). The third lower connection electrode (LCE3) may include a third-first lower connection electrode (LCE3a), a third-second lower connection electrode (LCE3b), and a third-third lower connection electrode (LCE3c). The third-first lower connection electrode (LCE3a) may be provided in the first sub-pixel (SP1), and may be spaced apart from the first anode electrode (AE1), the first-first lower connection electrode (LCE1a), and the second-first lower connection electrode (LCE2a). The third-second lower connection electrode (LCE3b) may be provided in the second sub-pixel (SP2), and may be spaced apart from the second anode electrode (AE2), the first-second lower connection electrode (LCE1b), and the second-second lower connection electrode (LCE2b). The 3-3 lower connection electrode (LCE3c) may be provided to the 3rd sub-pixel (SP3) and may be spaced apart from the 3rd anode electrode (AE3), the 1-3 lower connection electrode (LCE1c), and the 2-3 lower connection electrode (LCE2c).

[0290] In the embodiments, the 3-1 to 3-3 lower connection electrodes (LCE3a, LCE3b, LCE3c) may be arranged in the same layer as the 1-3 anode electrodes (AE1, AE2, AE3), the 1-1 to 1-3 lower connection electrodes (LCE1a, LCE1b, LCE1c), and the 2-1 to 2-3 lower connection electrodes (LCE2a, LCE2b, LCE2c). In this case, the 3-1 to 3-3 lower connection electrodes (LCE3a, LCE3b, LCE3c) may be formed through the same formation process as the 1-3 anode electrodes (AE1, AE2, AE3), the 1-1 to 1-3 lower connection electrodes (LCE1a, LCE1b, LCE1c), and the 2-1 to 2-3 lower connection electrodes (LCE2a, LCE2b, LCE2c).

[0291] A first sub-light emitting element (SLD1) may be disposed on each of the first to third anode electrodes (AE1, AE2, AE3). The first sub-light emitting element (SLD1) may include a first-first sub-light emitting element (SLD1a), a first-second sub-light emitting element (SLD1b), and a first-third sub-light emitting element (SLD1c). The first-first to first-third sub-light emitting elements (SLD1a, SLD1b, SLD1c) may be configured in the same manner as described with reference to FIG. 11.

[0292] In Fig. 15, each of the first to third sub-light emitting elements (SLD1a, SLD1b, SLD1c) is illustrated as being provided one by one, but the present invention is not limited thereto. For example, as described with reference to Fig. 7, each of the first to third sub-light emitting elements (SLD1a, SLD1b, SLD1c) may be provided.

[0293] A second sub-light emitting element (SLD2) may be disposed on each of the first to third lower connection electrodes (LCE1a, LCE1b, LCE1c). The second sub-light emitting element (SLD2) may include a second-first sub-light emitting element (SLD2a), a second-second sub-light emitting element (SLD2b), and a second-third sub-light emitting element (SLD2c). The second-first to second-third sub-light emitting elements (SLD2a, SLD2b, SLD2c) may be configured in the same manner as described with reference to FIG. 11.

[0294] In Fig. 15, each of the 2-1 to 2-3 sub-light emitting elements (SLD2a, SLD2b, SLD2c) is illustrated as being provided one by one, but the present invention is not limited thereto. For example, as described with reference to Fig. 7, each of the 2-1 to 2-3 sub-light emitting elements (SLD2a, SLD2b, SLD2c) may be provided.

[0295] A third sub-light emitting element (SLD3) may be disposed on each of the second-first to second-third lower connection electrodes (LCE2a, LCE2b, LCE2c). The third sub-light emitting element (SLD3) may include a third-first sub-light emitting element (SLD3a), a third-second sub-light emitting element (SLD3b), and a third-third sub-light emitting element (SLD3c). The third-first to third sub-light emitting elements (SLD3a, SLD3b, SLD3c) may be configured in the same manner as described with reference to FIG. 11.

[0296] In Fig. 15, each of the 3-1 to 3-3 sub light-emitting elements (SLD3a, SLD3b, SLD3c) is illustrated as being provided one by one, but the present invention is not limited thereto. Each of the 3-1 to 3-3 sub light-emitting elements (SLD3a, SLD3b, SLD3c) may also be provided. For example, two or more 3-1 sub light-emitting elements (SLD3a) may be provided on the 2-1 lower connection electrode (LCE2a), and in this case, each of the 3-1 sub light-emitting elements (SLD3a) may overlap with the 2-1 lower connection electrode (LCE2a) and may also be connected to the 2-1 lower connection electrode (LCE2a).

[0297] A fourth sub-light emitting element (SLD4) may be disposed on each of the third-first to third-third lower connection electrodes (LCE3a, LCE3b, LCE3c). The fourth sub-light emitting element (SLD4) may include a fourth-first sub-light emitting element (SLD4a), a fourth-second sub-light emitting element (SLD4b), and a fourth-third sub-light emitting element (SLD4c). The fourth-first sub-light emitting element (SLD4a) may be disposed on the third-first lower connection electrode (LCE3a) so as to overlap with the third-first lower connection electrode (LCE3a). The fourth-first sub-light emitting element (SLD4a) may be connected to the third-first lower connection electrode (LCE3a). The fourth-second sub-light emitting element (SLD4b) may be disposed on the third-second lower connection electrode (LCE3b) so as to overlap with the third-second lower connection electrode (LCE3b). The 4-2 sub-light emitting element (SLD4b) may be connected to the 3-2 lower connection electrode (LCE3b). The 4-3 sub-light emitting element (SLD4c) may be positioned on the 3-3 lower connection electrode (LCE3c) so as to overlap with the 3-3 lower connection electrode (LCE3c). The 4-3 sub-light emitting element (SLD4c) may be connected to the 3-3 lower connection electrode (LCE3c).

[0298] In Fig. 15, it is illustrated that each of the 4-1 to 4-3 sub-light emitting elements (SLD4a, SLD4b, SLD4c) is provided one by one, but the present invention is not limited thereto. Each of the 4-1 to 4-3 sub-light emitting elements (SLD4a, SLD4b, SLD4c) may also be provided.

[0299] The first-first sub-light emitting element (SLD1a), the second-first sub-light emitting element (SLD2a), the third-first sub-light emitting element (SLD3a), and the fourth-first sub-light emitting element (SLD4a) may be provided as light emitting elements (LD, see FIG. 2) included in the first sub-pixel (SP1). The first-second sub-light emitting element (SLD1b), the second-second sub-light emitting element (SLD2b), the third-second sub-light emitting element (SLD3b), and the fourth-second sub-light emitting element (SLD4b) may be provided as light emitting elements (LD) included in the second sub-pixel (SP2). The first-third sub-light emitting element (SLD1c), the second-third sub-light emitting element (SLD2c), the third-third sub-light emitting element (SLD3c), and the fourth-third sub-light emitting element (SLD4c) may be provided as light emitting elements (LD) included in the third sub-pixel (SP3). In this case, the first-first sub-light emitting element (SLD1a), the second-first sub-light emitting element (SLD2a), the third-first sub-light emitting element (SLD3a), and the fourth-first sub-light emitting element (SLD4a) can be viewed as constituting the first light emitting element (LD1) of the first sub-pixel (SP1), the first-second sub-light emitting element (SLD1b), the second-second sub-light emitting element (SLD2b), the third-second sub-light emitting element (SLD3b), and the fourth-second sub-light emitting element (SLD4b) can be viewed as constituting the second light emitting element (LD2) of the second sub-pixel (SP2), and the first-third sub-light emitting element (SLD1c), the second-third sub-light emitting element (SLD2c), the third-third sub-light emitting element (SLD3c), and the fourth-third sub-light emitting element (SLD4c) can be viewed as constituting the third light emitting element (LD3) of the third sub-pixel (SP3).

[0300] Each of the first to third light-emitting elements (LD1, LD2, LD3) may be an inorganic light-emitting diode containing an inorganic light-emitting material. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may also be used.

[0301] Referring to FIG. 16, a first upper connection electrode (UCE1) may be disposed on each of the first to third sub-pixels (SP1, SP2, and SP3). The first upper connection electrode (UCE1) may include a first-first upper connection electrode (UCE1a), a first-second upper connection electrode (UCE1b), and a first-third upper connection electrode (UCE1c). The first-first to first-third upper connection electrodes (UCE1a, UCE1b, and UCE1c) may be configured in the same manner as described with reference to FIG. 12.

[0302] A first-first sub-light emitting element (SLD1a) may be connected between the first anode electrode (AE1) and the first-first upper connection electrode (UCE1a). According to embodiments, when the first-first sub-light emitting elements (SLD1a) are provided, the first-first sub-light emitting elements (SLD1a) may be connected in parallel to each other between the first anode electrode (AE1) and the first-first upper connection electrode (UCE1a).

[0303] A first-second sub-light emitting element (SLD1b) may be connected between the second anode electrode (AE2) and the first-second upper connection electrode (UCE1b). According to embodiments, when the first-second sub-light emitting elements (SLD1b) are provided, the first-second sub-light emitting elements (SLD1b) may be connected in parallel to each other between the second anode electrode (AE2) and the first-second upper connection electrode (UCE1b).

[0304] A first-third sub-light emitting element (SLD1c) may be connected between the third anode electrode (AE3) and the first-third upper connection electrode (UCE1c). According to embodiments, when the first-third sub-light emitting elements (SLD1c) are provided, the first-third sub-light emitting elements (SLD1c) may be connected in parallel to each other between the third anode electrode (AE3) and the first-third upper connection electrode (UCE1c).

[0305] A second upper connection electrode (UCE2) may be disposed on each of the first to third sub-pixels (SP1, SP2, and SP3). The second upper connection electrode (UCE2) may include a second-first upper connection electrode (UCE2a), a second-second upper connection electrode (UCE2b), and a second-third upper connection electrode (UCE2c). The second-first to second-third upper connection electrodes (UCE2a, UCE2b, and UCE2c) may be configured in the same manner as described with reference to FIG. 12.

[0306] A second-first sub-light emitting element (SLD2a) may be connected between the first-first lower connection electrode (LCE1a) and the second-first upper connection electrode (UCE2a). According to embodiments, when the second-first sub-light emitting elements (SLD2a) are provided, the second-first sub-light emitting elements (SLD2a) may be connected in parallel between the first-first lower connection electrode (LCE1a) and the second-first upper connection electrode (UCE2a).

[0307] A second-second sub-light emitting element (SLD2b) may be connected between the first-second lower connection electrode (LCE1b) and the second-second upper connection electrode (UCE2b). According to embodiments, when the second-second sub-light emitting elements (SLD2b) are provided, the second-second sub-light emitting elements (SLD2b) may be connected in parallel to each other between the first-second lower connection electrode (LCE1b) and the second-second upper connection electrode (UCE2b).

[0308] A second-third sub-light emitting element (SLD2c) may be connected between the first-third lower connection electrode (LCE1c) and the second-third upper connection electrode (UCE2c). According to embodiments, when the second-third sub-light emitting elements (SLD2c) are provided, the second-third sub-light emitting elements (SLD2c) may be connected in parallel between the first-third lower connection electrode (LCE1c) and the second-third upper connection electrode (UCE2c).

[0309] A third upper connection electrode (UCE3) may be disposed on each of the first to third sub-pixels (SP1, SP2, and SP3). The third upper connection electrode (UCE3) may include a third-first upper connection electrode (UCE3a), a third-second upper connection electrode (UCE3b), and a third-third upper connection electrode (UCE3c). The third-first upper connection electrode (UCE3a) may be provided to the first sub-pixel (SP1), and may be disposed on the second-first lower connection electrode (LCE2a) to face the second-first lower connection electrode (LCE2a). The third-second upper connection electrode (UCE3b) may be provided to the second sub-pixel (SP2), and may be disposed on the second-second lower connection electrode (LCE2b) to face the second-second lower connection electrode (LCE2b). The 3-3 upper connection electrode (UCE3c) may be provided to the 3rd sub-pixel (SP3) and may be placed on the 2-3 lower connection electrode (LCE2c) so as to face the 2-3 lower connection electrode (LCE2c).

[0310] A third-first sub-light emitting element (SLD3a) may be connected between the second-first lower connection electrode (LCE2a) and the third-first upper connection electrode (UCE3a). According to embodiments, when the third-first sub-light emitting elements (SLD3a) are provided, the third-first sub-light emitting elements (SLD3a) may be connected in parallel to each other between the second-first lower connection electrode (LCE2a) and the third-first upper connection electrode (UCE3a).

[0311] A third-second sub-light emitting element (SLD3b) may be connected between the second-second lower connection electrode (LCE2b) and the third-second upper connection electrode (UCE3b). According to embodiments, when the third-second sub-light emitting elements (SLD3b) are provided, the third-second sub-light emitting elements (SLD3b) may be connected in parallel to each other between the second-second lower connection electrode (LCE2b) and the third-second upper connection electrode (UCE3b).

[0312] A third-third sub-light emitting element (SLD3c) may be connected between the second-third lower connection electrode (LCE2c) and the third-third upper connection electrode (UCE3c). According to embodiments, when the third-third sub-light emitting elements (SLD3c) are provided, the third-third sub-light emitting elements (SLD3c) may be connected in parallel between the second-third lower connection electrode (LCE2c) and the third-third upper connection electrode (UCE3c).

[0313] The cathode electrode (CE) may be provided in common to the first to third sub-pixels (SP1, SP2, SP3). For example, the cathode electrode (CE) may be provided as a common electrode. For example, the cathode electrode (CE) may extend in the second direction (DR2) and be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). Although not illustrated, the cathode electrode (CE) may extend not only in the second direction (DR2) but also in the first direction (DR1) and be used as a common electrode for all of the sub-pixels (SP) of FIG. 4. In this way, the cathode electrode (CE) may have various shapes.

[0314] The cathode electrode (CE) may be arranged in the same layer as the first to third upper connection electrodes (UCE1a, UCE1b, UCE1c), the second to third upper connection electrodes (UCE2a, UCE2b, UCE2c), and the third to third upper connection electrodes (UCE3a, UCE3b, UCE3c). The cathode electrode (CE) may be arranged on the third to third lower connection electrodes (LCE3a, LCE3b, LCE3c) so as to face the third to third lower connection electrodes (LCE3a, LCE3b, LCE3c).

[0315] A 4-1 sub-light emitting element (SLD4a) may be connected between the cathode electrode (CE) and the 3-1 lower connection electrode (LCE3a). According to embodiments, when the 4-1 sub-light emitting elements (SLD4a) are provided, the 4-1 sub-light emitting elements (SLD4a) may be connected in parallel to each other between the 3-1 lower connection electrode (LCE3a) and the cathode electrode (CE).

[0316] A 4-2 sub-light emitting element (SLD4b) may be connected between the cathode electrode (CE) and the 3-2 lower connection electrode (LCE3b). According to embodiments, when the 4-2 sub-light emitting elements (SLD4b) are provided, the 4-2 sub-light emitting elements (SLD4b) may be connected in parallel to each other between the 3-2 lower connection electrode (LCE3b) and the cathode electrode (CE).

[0317] A 4-3 sub-light emitting element (SLD4c) may be connected between the cathode electrode (CE) and the 3-3 lower connection electrode (LCE3c). According to embodiments, when the 4-3 sub-light emitting elements (SLD4c) are provided, the 4-3 sub-light emitting elements (SLD4c) may be connected in parallel to each other between the 3-3 lower connection electrode (LCE3c) and the cathode electrode (CE).

[0318] The first-first upper connection electrode (UCE1a) can be electrically connected to the first-first lower connection electrode (LCE1a) through the first-first contact hole (CNT1a). The second-first upper connection electrode (UCE2a) can be electrically connected to the second-first lower connection electrode (LCE2a) through the second-first contact hole (CNT2a). The third-first upper connection electrode (UCE3a) can be electrically connected to the third-first lower connection electrode (LCE3a) through the third-first contact hole (CNT3a). Accordingly, the first-first sub-light-emitting element (SLD1a), the second-first sub-light-emitting element (SLD2a), the third-first sub-light-emitting element (SLD3a), and the fourth-first sub-light-emitting element (SLD4a) can be connected in series with each other between the first anode electrode (AE1) and the cathode electrode (CE).

[0319] The first-second upper connection electrode (UCE1b) can be electrically connected to the first-second lower connection electrode (LCE1b) through the first-second contact hole (CNT1b). The second-second upper connection electrode (UCE2b) can be electrically connected to the second-second lower connection electrode (LCE2b) through the second-second contact hole (CNT2b). The third-second upper connection electrode (UCE3b) can be electrically connected to the third-second lower connection electrode (LCE3b) through the third-second contact hole (CNT3b). Accordingly, the first-second sub-light-emitting element (SLD1b), the second-second sub-light-emitting element (SLD2b), the third-second sub-light-emitting element (SLD3b), and the fourth-second sub-light-emitting element (SLD4b) can be connected in series with each other between the second anode electrode (AE2) and the cathode electrode (CE).

[0320] The first-third upper connection electrode (UCE1c) can be electrically connected to the first-third lower connection electrode (LCE1c) through the first-third contact hole (CNT1c). The second-third upper connection electrode (UCE2c) can be electrically connected to the second-third lower connection electrode (LCE2c) through the second-third contact hole (CNT2c). The third-third upper connection electrode (UCE3c) can be electrically connected to the third-third lower connection electrode (LCE3c) through the third-third contact hole (CNT3c). Accordingly, the first-third sub-light-emitting element (SLD1c), the second-third sub-light-emitting element (SLD2c), the third-third sub-light-emitting element (SLD3c), and the fourth-third sub-light-emitting element (SLD4c) can be connected in series with each other between the third anode electrode (AE3) and the cathode electrode (CE).

[0321] Each of the first to fourth sub light-emitting elements (SLD1, SLD2, SLD3, SLD4) illustrated in FIGS. 15 and 16 may be a vertical light-emitting element including the light-emitting stack (EST) and the bonding electrode (BDE) described with reference to FIGS. 9 and 10. In this case, the first to third sub light-emitting elements (SLD1, SLD2, SLD3) and the first and second lower connection electrodes (LCE1, LCE2) and the first and second upper connection electrodes (UCE1, UCE2) disposed therebetween may be configured in a similar manner to that described with reference to FIG. 13. The third and fourth sub light-emitting elements (SLD3, SLD4) and the third lower connection electrode (LCE3) and the third upper connection electrode (UCE3) disposed therebetween may be configured in a similar manner to that described with reference to FIG. 13.

[0322] FIG. 17 is a schematic plan view for explaining a second embodiment of one of the pixels included in the display panel of FIG. 3.

[0323] Referring to FIG. 17, the pixel (PXL') may include first to third sub-pixels (SP1', SP2', SP3'). The first to third sub-pixels (SP1', SP2', SP3') may be arranged in the second direction (DR2). However, the arrangement of the pixel (PXL') is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1', SP2', SP3') may be arranged in a zigzag pattern.

[0324] First to third anode electrodes (AE1', AE2', AE3') may be respectively disposed in the first to third sub-pixels (SP1', SP2', SP3'). The first anode electrode (AE1') may be provided as an anode electrode (AE, see FIG. 2) connected to a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1'). The second anode electrode (AE2') may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the second sub-pixel (SP2'). The third anode electrode (AE3') may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the third sub-pixel (SP3').

[0325] A first connection electrode (LCE1') may be disposed in each of the first to third sub-pixels (SP1', SP2', and SP3'). The first connection electrode (LCE1') may include a first-first connection electrode (LCE1a'), a first-second connection electrode (LCE1b'), and a first-third connection electrode (LCE1c'). The first-first connection electrode (LCE1a') may be provided to the first sub-pixel (SP1') and may be spaced apart from the first anode electrode (AE1'). The first-second connection electrode (LCE1b') may be provided to the second sub-pixel (SP2') and may be spaced apart from the second anode electrode (AE2'). The first-third connection electrode (LCE1c') may be provided to the third sub-pixel (SP3') and may be spaced apart from the third anode electrode (AE3'). In the embodiments, the first to third connection electrodes (LCE1a', LCE1b', LCE1c') may be arranged in the same layer as the first to third anode electrodes (AE1', AE2', AE3'). In this case, the first to third connection electrodes (LCE1a', LCE1b', LCE1c') may be formed through the same forming process as the first to third anode electrodes (AE1', AE2', AE3').

[0326] The cathode electrode (CE') may be spaced apart from the first to third anode electrodes (AE1', AE2', AE3') and the first to third connection electrodes (LCE1a', LCE1b', LCE1c'). The cathode electrode (CE') may be arranged in the same layer as the first to third anode electrodes (AE1', AE2', AE3'). In embodiments, the cathode electrode (CE') may extend in the first and second directions (DR1, DR2) and may be used as a common electrode for the pixel (PXL') and other pixels adjacent to the pixel (PXL'). In the embodiments, as illustrated in FIG. 17, the first anode electrode (AE1') and the 1-1 connection electrode (LCE1a') may be surrounded by the cathode electrode (CE'), the second anode electrode (AE2') and the 1-2 connection electrode (LCE1b') may be surrounded by the cathode electrode (CE'), and the third anode electrode (AE3') and the 1-3 connection electrode (LCE1c') may be surrounded by the cathode electrode (CE'). In this way, the cathode electrode (CE') may have various shapes.

[0327] First to third light-emitting elements (LD1', LD2', LD3') may be arranged on the first to third anode electrodes (AE1', AE2', AE3'), the first-first to first-third connection electrodes (LCE1a', LCE1b', LCE1c'), and the cathode electrode (CE').

[0328] The first light-emitting element (LD1') may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of the first sub-pixel (SP1'). The first light-emitting element (LD1') may include a 1-1 sub-light-emitting element (SLD1a') and a 2-1 sub-light-emitting element (SLD2a'). The 1-1 sub-light-emitting element (SLD1a') may be electrically connected to the first anode electrode (AE1') and the 1-1 connection electrode (LCE1a'). The 2-1 sub-light-emitting element (SLD2a') may be electrically connected to the 1-1 connection electrode (LCE1a') and the cathode electrode (CE'). Accordingly, the first-first sub-light-emitting element (SLD1a') and the second-first sub-light-emitting element (SLD2a') can be connected in series with each other through the first-first connection electrode (LCE1a') between the first anode electrode (AE1') and the cathode electrode (CE').

[0329] The second light-emitting element (LD2') may be provided as a light-emitting element (LD, see FIG. 2) connected to the sub-pixel circuit (SPC) of the second sub-pixel (SP2'). The second light-emitting element (LD2') may include a first-second sub-light-emitting element (SLD1b') and a second-second sub-light-emitting element (SLD2b'). The first-second sub-light-emitting element (SLD1b') may be electrically connected to the second anode electrode (AE2') and the first-second connection electrode (LCE1b'). The second-second sub-light-emitting element (SLD2b') may be electrically connected to the first-second connection electrode (LCE1b') and the cathode electrode (CE'). Accordingly, the first-second sub-light-emitting element (SLD1b') and the second-second sub-light-emitting element (SLD2b') can be connected in series with each other through the first-second connecting electrode (LCE1b') between the second anode electrode (AE2') and the cathode electrode (CE').

[0330] The third light-emitting element (LD3') may be provided as a light-emitting element (LD, see FIG. 2) connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3'). The third light-emitting element (LD3') may include a 1-3 sub-light-emitting element (SLD1c') and a 2-3 sub-light-emitting element (SLD2c'). The 1-3 sub-light-emitting element (SLD1c') may be electrically connected to the 3rd anode electrode (AE3') and the 1-3 connection electrode (LCE1c'). The 2-3 sub-light-emitting element (SLD2c') may be electrically connected to the 1-3 connection electrode (LCE1c') and the cathode electrode (CE'). Accordingly, the 1-3 sub-light emitting element (SLD1c') and the 2-3 sub-light emitting element (SLD2c') can be connected in series with each other through the 1-3 connecting electrode (LCE1c') between the 3rd anode electrode (AE3') and the cathode electrode (CE').

[0331] The first light-emitting element (LD1'), the second light-emitting element (LD2'), and the third light-emitting element (LD3') may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may also be used.

[0332] Figures 18 and 19 are schematic cross-sectional views for explaining a pixel according to the second embodiment of Figure 17. Figure 18 is a schematic cross-sectional view taken along line X3-X3' of Figure 17, and Figure 19 is a schematic cross-sectional view taken along line Y3-Y3' of Figure 17.

[0333] Referring to FIGS. 17 and 18, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0334] The pixel circuit layer (PCL) is described in the same manner as described with reference to Fig. 9. Therefore, description of overlapping content may be omitted.

[0335] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a first anode electrode (AE1'), a first-first connection electrode (LCE1a'), a cathode electrode (CE'), a first bank (BNK1), first to third reflective electrodes (RFE1, RFE2, RFE3), a first light-emitting element (LD1'), an overcoat layer (OCL), a third passivation layer (PSV3), and a capping layer (CPL).

[0336] A first anode electrode (AE1'), a first-first connection electrode (LCE1a'), and a cathode electrode (CE') may be arranged on a pixel circuit layer (PCL).

[0337] The first anode electrode (AE1') can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second passivation layer (PSV2). In this way, the first anode electrode (AE1') can be electrically connected to the transistor (T_SP).

[0338] The cathode electrode (CE') may be spaced apart from the first anode electrode (AE1') in the first direction (DR1). The cathode electrode (CE') may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE').

[0339] The first-first connecting electrode (LCE1a') may be disposed between the cathode electrode (CE') and the first anode electrode (AE1'). The first-first connecting electrode (LCE1a') may be spaced apart from the cathode electrode (CE') and the first anode electrode (AE1').

[0340] A first bank (BNK1) may be disposed on a first anode electrode (AE1'), a first-first connection electrode (LCE1a'), and a cathode electrode (CE'). The first bank (BNK1) may have a first opening (OP1) exposing portions of the first anode electrode (AE1'), the first-first connection electrode (LCE1a'), and the cathode electrode (CE'). A first light-emitting element (LD1') may be disposed in the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines an area where the first light-emitting element (LD1') is positioned.

[0341] The first bank (BNK1) may be configured to include a light-blocking material, and may prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0342] A first reflective electrode (RFE1) may be disposed on an exposed portion of a first anode electrode (AE1') and a side surface of a first bank (BNK1) adjacent thereto. A second reflective electrode (RFE2) may be disposed on an exposed portion of a cathode electrode (CE') and a side surface of a first bank (BNK1) adjacent thereto. A third reflective electrode (RFE3) may be disposed on an exposed portion of a first-first connection electrode (LCE1a') and a side surface of a first bank (BNK1) adjacent thereto. The first to third reflective electrodes (RFE1, RFE2, RFE3) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1') may be improved. In the embodiments, the first to third reflective electrodes (RFE1, RFE2, RFE3) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0343] The first light-emitting element (LD1') may include a first-first sub-light-emitting element (SLD1a') and a second-first sub-light-emitting element (SLD2a'). Each of the first-first sub-light-emitting element (SLD1a') and the second-first sub-light-emitting element (SLD2a') may include a light-emitting laminate (EST') in which a first semiconductor layer (21), a second semiconductor layer (22), an active layer (23), and an auxiliary layer (24) are sequentially laminated on each other, and first and second bonding electrodes (BDE1, BDE2). Here, the first and second bonding electrodes (BDE1, BDE2) may protrude in a direction toward the pixel circuit layer (PCL), and such a first light-emitting element (LD1') may be referred to as a flip chip type light-emitting element.

[0344] The first semiconductor layer (21) may be configured to provide holes. The first semiconductor layer (21) may have a first polarity. For example, the first semiconductor layer (21) may include at least one p-type semiconductor layer. For example, the first semiconductor layer (21) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the first semiconductor layer (21) is not limited thereto, and various other materials may constituting the first semiconductor layer (21). In one embodiment of the present invention, the first semiconductor layer (21) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0345] The second semiconductor layer (22) is disposed on the first semiconductor layer (21) and may be configured to provide electrons. The second semiconductor layer (22) may have a second polarity different from the first polarity. For example, the second semiconductor layer (22) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (22) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer (22) is not limited thereto, and various other materials may constituting the second semiconductor layer (22). In one embodiment of the present invention, the second semiconductor layer (22) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant). According to an embodiment, the second semiconductor layer (22) may form an n-type semiconductor layer together with the auxiliary layer (24).

[0346] The active layer (23) can provide a region where electrons and holes recombine between the first semiconductor layer (21) and the second semiconductor layer (22). As electrons and holes recombine in the active layer (23), they transition to a lower energy level, and light having a corresponding wavelength can be generated. The active layer (23) can be formed in a single or multiple quantum well structure. When the active layer (23) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer can be repeatedly stacked on top of each other to form the active layer (23). However, the active layer (23) is not limited to the above-described structure.

[0347] The auxiliary layer (24) may include a gallium nitride (GaN) semiconductor material that is substantially undoped with impurities or doped with impurities at a relatively low concentration. The auxiliary layer (24) may form an n-type semiconductor layer together with the second semiconductor layer (22).

[0348] The first bonding electrode (BDE1) may be disposed under the first semiconductor layer (21). The first bonding electrode (BDE1) may be electrically connected to the first semiconductor layer (21). In embodiments, the first bonding electrode (BDE1) of the 1-1 sub-light emitting element (SLD1a') may be electrically connected to the first anode electrode (AE1') by contacting the first reflective electrode (RFE1). The first bonding electrode (BDE1) of the 2-1 sub-light emitting element (SLD2a') may be electrically connected to the 1-1 connection electrode (LCE1a') by contacting the third reflective electrode (RFE3).

[0349] The second bonding electrode (BDE2) may be electrically connected to the second semiconductor layer (22). For example, the second bonding electrode (BDE2) may be in contact with the second semiconductor layer (22) exposed by removing the first semiconductor layer (21) and the active layer (23). In embodiments, the second bonding electrode (BDE2) of the 1-1 sub-light emitting element (SLD1a') may be in contact with the third reflective electrode (RFE3), thereby being electrically connected to the 1-1 connection electrode (LCE1a'). The second bonding electrode (BDE2) of the 2-1 sub-light emitting element (SLD2a') may be in contact with the second reflective electrode (RFE2), thereby being electrically connected to the cathode electrode (CE').

[0350] Accordingly, the first-first sub-light emitting element (SLD1a') and the second-first sub-light emitting element (SLD2a') can be connected in series between the first anode electrode (AE1') and the cathode electrode (CE').

[0351] In embodiments, the first and second bonding electrodes (BDE1, BDE2) may include a eutectic metal.

[0352] The first light-emitting element (LD1') may further include an insulating film (25) covering an outer surface of the light-emitting stack (EST'). The insulating film (25) may serve to prevent an electrical short circuit that may occur when the active layer (23) comes into contact with a conductive material other than the first and second semiconductor layers (21, 22). The insulating film (25) may include a transparent insulating material. The insulating film (25) may be configured to expose at least the lower surfaces of the first and second bonding electrodes (BDE1, BDE2).

[0353] An overcoat layer (OCL) may be disposed within a first opening (OP1) in which first to third reflective electrodes (RFE1, RFE2, RFE3) and a first light-emitting element (LD1') are disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1') bonded to the first to third reflective electrodes (RFE1, RFE2, RFE3) so as not to move. The overcoat layer (OCL) may protect components disposed below the overcoat layer (OCL) from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0354] A third passivation layer (PSV3) may be disposed on the first bank (BNK1) and the overcoat layer (OCL). The third passivation layer (PSV3) may protect components disposed beneath the third passivation layer (PSV3) and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0355] In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface of the first light-emitting element (LD1'). The first light-emitting element (LD1') may protrude into the light-functional layer (LFL). The first light-emitting element (LD1') may be at least partially positioned within the second opening (OP2) of the second bank (BNK2). For example, the height of the upper surface of the first light-emitting element (LD1') from the substrate (SUB) may be higher than the lowermost end of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1') may be provided to the light-functional layer (LFL) at a relatively high rate.

[0356] The capping layer (CPL) may be disposed on the third passivation layer (PSV3). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first light-emitting element (LD1'), from external moisture and humidity, and other things within the spirit and scope of the present disclosure. In embodiments, the capping layer (CPL) may not be disposed on the upper surface of the first light-emitting element (LD1'). In other embodiments, the capping layer (CPL) may entirely cover the first light-emitting element (LD1') and the third passivation layer (PSV3). The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto.

[0357] Above, the pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1') have been described. Each of the second and third sub-pixels (SP2', SP3') of FIG. 17 may also be configured similarly to the first sub-pixel (SP1') within a range not otherwise described herein.

[0358] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0359] A second bank (BNK2) may be disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have a second opening (OP2) that overlaps the first opening (OP1).

[0360] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In some embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0361] A reflective layer (RFL) may be disposed on side surfaces of the second bank (BNK2) adjacent to the second opening (OP2). The reflective layer (RFL) is configured to reflect incident light, and thus, light emission efficiency may be improved. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, embodiments are not limited thereto.

[0362] A fourth passivation layer (PSV4) may be disposed on the capping layer (CPL) within the second opening (OP2). The fourth passivation layer (PSV4) may protect components disposed beneath the fourth passivation layer (PSV4) and provide a flat upper surface. The fourth passivation layer (PSV4) may include the same material as any one of the first to third passivation layers (PSV1, PSV2, PSV3), but embodiments are not limited thereto.

[0363] On the fourth passivation layer (PSV4), a first photo-conversion pattern (CCP1) can be arranged within the second opening (OP2).

[0364] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. The color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0365] The first sub-pixel (SP1') may be a red sub-pixel. When the first light-emitting element (LD1') emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1') emits red light, the first light conversion pattern (CCP1) may include scattering particles. In this way, the particles included in the first light conversion pattern (CCP1) may be variously changed depending on the color of the light emitted from the first light-emitting element (LD1').

[0366] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1) and the first color filter (CF1). The low-refractive-index layer (LRL) may be configured to refract or totally reflect light depending on an incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0367] A color filter layer (CFL) may be disposed on a low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) may overlap a first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. Since the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0368] Referring to FIG. 17 and FIG. 19, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0369] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 18. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1', SP2', SP3') may be provided, respectively. In the display element layer (DPL), first to third light-emitting elements (LD1', LD2', LD3') corresponding to the first to third sub-pixels (SP1', SP2', SP3') may be provided, respectively. The first to third light-emitting elements (LD1', LD2', LD3') may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1') may be connected between a cathode electrode (CE', see FIG. 18) and a transistor (T_SP, see FIG. 18) included in the sub-pixel circuit of the first sub-pixel (SP1'). The second light-emitting element (LD2') may be connected between the cathode electrode (CE') and a transistor included in the sub-pixel circuit of the second sub-pixel (SP2'). The third light-emitting element (LD3') may be connected between the cathode electrode (CE') and a transistor included in the sub-pixel circuit of the third sub-pixel (SP3'). Hereinafter, overlapping descriptions may be omitted.

[0370] A light functional layer (LFL) may be provided on the display element layer (DPL). The light functional layer (LFL) is described in the same manner as described with reference to FIG. 18. Hereinafter, redundant descriptions may be omitted.

[0371] The second bank (BNK2) may have second openings (OP2). It may be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1', SP2', SP3') are defined by the second bank (BNK2). An area overlapping with the second bank (BNK2) may correspond to the non-light-emitting area (NEMA). An area overlapping with the second openings (OP2) of the second bank (BNK2) may correspond to the light-emitting area (EMA) of the first to third sub-pixels (SP1', SP2', SP3').

[0372] A fourth passivation layer (PSV4) may be disposed within the second openings (OP2) on the capping layer (CPL). First and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) may be disposed within the second openings (OP2) on the fourth passivation layer (PSV4).

[0373] In the embodiments, the first to third light-emitting elements (LD1', LD2', LD3') may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light emission efficiency. Accordingly, the first to third sub-pixels (SP1', SP2', SP3') may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0374] In the embodiments, the first to third light-emitting elements (LD1', LD2', LD3') may be configured to emit red, green, and blue light, respectively. In this case, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may each include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the color of the light emitted from the first to third light-emitting elements (LD1', LD2', LD3').

[0375] In the embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0376] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first and second light conversion patterns (CCP1, CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3').

[0377] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0378] Each of the first to third color filters (CF1, CF2, CF3) can selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1') is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2') is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3') is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1, CF2, CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, embodiments are not limited thereto, and the first to third color filters (CF1, CF2, CF3) may have a refractive index lower than or equal to that of the low-refractive-index layer (LRL).

[0379] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It can be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1', SP2', SP3') are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0380] In embodiments, the light blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light blocking pattern between the first and second color filters (CF1, CF2) among the light blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, the light blocking pattern between the second and third color filters (CF2, CF3) among the light blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap, and the light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of an adjacent pixel may be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) may extend into the non-emitting area (NEMA) to form the light blocking patterns (LBP).

[0381] FIG. 20 is a schematic plan view for explaining a second embodiment of one of the pixels included in the display panel of FIG. 3.

[0382] Referring to FIG. 20, except that the first to third sub-light emitting elements (SLD1a', SLD1b', SLD1c') and the second to third sub-light emitting elements (SLD2a', SLD2b', SLD2c') are provided respectively, the pixel (PXL') according to the second embodiment of the present invention may be substantially the same as the pixel (PXL') according to the second embodiment of the present invention described with reference to FIG. 17. Therefore, description of overlapping content may be omitted.

[0383] 1-1 sub light-emitting elements (SLD1a') may be provided. For example, two 1-1 sub light-emitting elements (SLD1a') may be provided, but the present invention is not limited thereto. Three or more 1-1 sub light-emitting elements (SLD1a') may be provided. Each of the 1-1 sub light-emitting elements (SLD1a') may be electrically connected to the first anode electrode (AE1') and the 1-1 connection electrode (LCE1a'). In this case, the 1-1 sub light-emitting elements (SLD1a') may be connected in parallel between the first anode electrode (AE1') and the 1-1 connection electrode (LCE1a').

[0384] Second-first sub-light emitting elements (SLD2a') may be provided. For example, two second-first sub-light emitting elements (SLD2a') may be provided, but the present invention is not limited thereto. Three or more second-first sub-light emitting elements (SLD2a') may be provided. Each of the second-first sub-light emitting elements (SLD2a') may be electrically connected to the first-first connection electrode (LCE1a') and the cathode electrode (CE'). In this case, the second-first sub-light emitting elements (SLD2a') may be connected in parallel between the first-first connection electrode (LCE1a') and the cathode electrode (CE').

[0385] Between the first anode electrode (AE1') and the cathode electrode (CE'), the first-first sub-light emitting elements (SLD1a') and the second-first sub-light emitting elements (SLD2a') can be connected in series with each other through the first-first connecting electrode (LCE1a').

[0386] Likewise, the first-second and first-third sub-light emitting elements (SLD1b', SLD1c') and the second-second and second-third sub-light emitting elements (SLD2b', SLD2c') may also be provided. In this case, the first-second sub-light emitting elements (SLD1b') may be connected in parallel to each other, the first-third sub-light emitting elements (SLD1c') may be connected in parallel to each other, the second-second sub-light emitting elements (SLD2b') may be connected in parallel to each other, and the second-third sub-light emitting elements (SLD2c') may be connected in parallel to each other. The first-second sub-light emitting elements (SLD1b') and the second-second sub-light emitting elements (SLD2b') may be connected in series to each other, and the first-third sub-light emitting elements (SLD1c') and the second-third sub-light emitting elements (SLD2c') may be connected in series to each other.

[0387] Figures 21 to 23 are schematic cross-sectional views for explaining a pixel according to the second embodiment of Figure 20. Figure 21 is a schematic cross-sectional view taken along line X4-X4' of Figure 20, Figure 22 is a schematic cross-sectional view taken along line X5-X5' of Figure 20, and Figure 23 is a schematic cross-sectional view taken along line Y4-Y4' of Figure 20.

[0388] Referring to FIGS. 20 to 23, the first to third sub light-emitting elements (SLD1a', SLD1b', SLD1c') and the second to third sub light-emitting elements (SLD2a', SLD2b', SLD2c') may be provided, respectively. In this case, the first to third sub light-emitting elements (SLD1a', SLD1b', SLD1c') and the second to third sub light-emitting elements (SLD2a', SLD2b', SLD2c') may be light-emitting elements of the flip chip type described with reference to FIG. 18. Hereinafter, descriptions of contents overlapping with those described in FIGS. 18 and 19 may be omitted.

[0389] In the embodiments, the first bonding electrodes (BDE1) of the first-first sub-light emitting elements (SLD1a') may be electrically connected to the first anode electrode (AE1') by contacting the first reflective electrode (RFE1). The second bonding electrodes (BDE2) of the first-first sub-light emitting elements (SLD1a') may be electrically connected to the first-first connection electrode (LCE1a') by contacting the third reflective electrode (RFE3).

[0390] In the embodiments, the first bonding electrodes (BDE1) of the second-first sub-light emitting elements (SLD2a') may be electrically connected to the first-first connection electrode (LCE1a') by contacting the third reflective electrode (RFE3). The second bonding electrodes (BDE2) of the second-first sub-light emitting elements (SLD2a') may be electrically connected to the cathode electrode (CE') by contacting the second reflective electrode (RFE2).

[0391] Accordingly, the first-first sub-light-emitting elements (SLD1a') and the second-first sub-light-emitting elements (SLD2a') can be connected in series with each other between the first anode electrode (AE1') and the cathode electrode (CE'). The first-first sub-light-emitting elements (SLD1a') can be connected in parallel with each other between the first anode electrode (AE1') and the first-first connection electrode (LCE1a'), and the second-first sub-light-emitting elements (SLD2a') can be connected in parallel with each other between the first-first connection electrode (LCE1a') and the cathode electrode (CE').

[0392] Above, the first light-emitting element (LD1') included in the first sub-pixel (SP1') has been described, but the second and third light-emitting elements (LD2', LD3') included in the second and third sub-pixels (SP2', SP3') of FIG. 20 can also be configured similarly to the first light-emitting element (LD1') within a range not described differently herein.

[0393] FIG. 24 is a schematic plan view for explaining a second-third embodiment of one of the pixels included in the display panel of FIG. 3.

[0394] Referring to FIG. 24, the pixel (PXL') may include first to third sub-pixels (SP1', SP2', SP3'). The first to third sub-pixels (SP1', SP2', SP3') may be arranged in the second direction (DR2). However, the arrangement of the pixel (PXL') is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1', SP2', SP3') may be arranged in a zigzag pattern.

[0395] First to third anode electrodes (AE1', AE2', AE3') may be respectively arranged in the first to third sub-pixels (SP1', SP2', SP3'). The first to third anode electrodes (AE1', AE2', AE3') may be configured in the same manner as described with reference to FIG. 17.

[0396] A first connection electrode (LCE1') may be arranged on the first to third sub-pixels (SP1', SP2', SP3'). The first connection electrode (LCE1') may include a first-first connection electrode (LCE1a'), a first-second connection electrode (LCE1b'), and a first-third connection electrode (LCE1c'). The first-first to first-third connection electrodes (LCE1a', LCE1b', LCE1c') may be configured in the same manner as described with reference to FIG. 17.

[0397] A second connection electrode (LCE2') may be arranged in the first to third sub-pixels (SP1', SP2', SP3'). The second connection electrode (LCE2') may include a second-first connection electrode (LCE2a'), a second-second connection electrode (LCE2b'), and a second-third connection electrode (LCE2c'). The second-first connection electrode (LCE2a') may be provided in the first sub-pixel (SP1') and may be spaced apart from the first anode electrode (AE1') and the first-first connection electrode (LCE1a'). The second-second connection electrode (LCE2b') may be provided in the second sub-pixel (SP2') and may be spaced apart from the second anode electrode (AE2') and the first-second connection electrode (LCE1b'). The 2nd-3rd connection electrode (LCE2c') may be provided to the 3rd sub-pixel (SP3') and may be spaced apart from the 3rd anode electrode (AE3') and the 1st-3rd connection electrode (LCE1c'). In embodiments, the 2nd-1st to 2nd-3rd connection electrodes (LCE2a', LCE2b', LCE2c') may be arranged in the same layer as the 1st to 3rd anode electrodes (AE1', AE2', AE3') and the 1st-1st to 1-3rd connection electrodes (LCE1a', LCE1b', LCE1c'). In this case, the 2-1 to 2-3 connection electrodes (LCE2a', LCE2b', LCE2c') may be formed through the same formation process as the 1-3 anode electrodes (AE1', AE2', AE3') and the 1-1 to 1-3 connection electrodes (LCE1a', LCE1b', LCE1c').

[0398] The cathode electrode (CE') may be spaced apart from the first to third anode electrodes (AE1', AE2', AE3'), the first-first to first-third connection electrodes (LCE1a', LCE1b', LCE1c'), and the second-first to second-third connection electrodes (LCE2a', LCE2b', LCE2c'). The cathode electrode (CE') may be arranged in the same layer as the first to third anode electrodes (AE1', AE2', AE3'). In embodiments, the cathode electrode (CE') may extend in the first and second directions (DR1, DR2) and may be used as a common electrode for the pixel (PXL') and other pixels adjacent to the pixel (PXL'). In the embodiments, as illustrated in FIG. 24, the first anode electrode (AE1'), the first-first connection electrode (LCE1a'), and the second-first connection electrode (LCE2a') may be surrounded by the cathode electrode (CE'), the second anode electrode (AE2'), the first-second connection electrode (LCE1b'), and the second-second connection electrode (LCE2b') may be surrounded by the cathode electrode (CE'), and the third anode electrode (AE3'), the first-third connection electrode (LCE1c'), and the second-third connection electrode (LCE2c') may be surrounded by the cathode electrode (CE'). In this way, the cathode electrode (CE') may have various shapes.

[0399] First to third light-emitting elements (LD1', LD2', LD3') may be arranged on the first to third anode electrodes (AE1', AE2', AE3'), the first-first to first-third connection electrodes (LCE1a', LCE1b', LCE1c'), the second-first to second-third connection electrodes (LCE2a', LCE2b', LCE2c'), and the cathode electrode (CE').

[0400] The first light-emitting element (LD1') may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of the first sub-pixel (SP1'). The first light-emitting element (LD1') may include a 1-1 sub-light-emitting element (SLD1a'), a 2-1 sub-light-emitting element (SLD2a'), and a 3-1 sub-light-emitting element (SLD3a'). The 1-1 sub-light-emitting element (SLD1a') may be electrically connected to the first anode electrode (AE1') and the 1-1 connection electrode (LCE1a'). The 2-1 sub-light-emitting element (SLD2a') may be electrically connected to the 1-1 connection electrode (LCE1a') and the 2-1 connection electrode (LCE2a'). The 3-1 sub-light emitting element (SLD3a') can be electrically connected to the 2-1 connecting electrode (LCE2a') and the cathode electrode (CE'). Accordingly, the 1-1 sub-light emitting element (SLD1a'), the 2-1 sub-light emitting element (SLD2a'), and the 3-1 sub-light emitting element (SLD3a') can be connected in series to each other through the 1-1 connecting electrode (LCE1a') and the 2-1 connecting electrode (LCE2a') between the first anode electrode (AE1') and the cathode electrode (CE').

[0401] The second light-emitting element (LD2') may be provided as a light-emitting element (LD, see FIG. 2) connected to the sub-pixel circuit (SPC) of the second sub-pixel (SP2'). The second light-emitting element (LD2') may include a first-second sub-light-emitting element (SLD1b'), a second-second sub-light-emitting element (SLD2b'), and a third-second sub-light-emitting element (SLD3b'). The first-second sub-light-emitting element (SLD1b') may be electrically connected to the second anode electrode (AE2') and the first-second connection electrode (LCE1b'). The second-second sub-light-emitting element (SLD2b') may be electrically connected to the first-second connection electrode (LCE1b') and the second-second connection electrode (LCE2b'). The third-second sub-light-emitting element (SLD3b') can be electrically connected to the second-second connection electrode (LCE2b') and the cathode electrode (CE'). Accordingly, the first-second sub-light-emitting element (SLD1b'), the second-second sub-light-emitting element (SLD2b'), and the third-second sub-light-emitting element (SLD3b') can be connected in series to each other through the first-second connection electrode (LCE1b') and the second-second connection electrode (LCE2b') between the second anode electrode (AE2') and the cathode electrode (CE').

[0402] The third light-emitting element (LD3') may be provided as a light-emitting element (LD, see FIG. 2) connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3'). The third light-emitting element (LD3') may include a 1-3 sub-light-emitting element (SLD1c'), a 2-3 sub-light-emitting element (SLD2c'), and a 3-3 sub-light-emitting element (SLD3c'). The 1-3 sub-light-emitting element (SLD1c') may be electrically connected to the 3rd anode electrode (AE3') and the 1-3 connection electrode (LCE1c'). The 2-3 sub-light-emitting element (SLD2c') may be electrically connected to the 1-3 connection electrode (LCE1c') and the 2-3 connection electrode (LCE2c'). The 3-3 sub-light emitting element (SLD3c') can be electrically connected to the 2-3 connecting electrode (LCE2c') and the cathode electrode (CE'). Accordingly, the 1-3 sub-light emitting element (SLD1c'), the 2-3 sub-light emitting element (SLD2c'), and the 3-3 sub-light emitting element (SLD3c') can be connected in series to each other through the 1-3 connecting electrode (LCE1c') and the 2-3 connecting electrode (LCE2c') between the 3rd anode electrode (AE3') and the cathode electrode (CE').

[0403] The first light-emitting element (LD1'), the second light-emitting element (LD2'), and the third light-emitting element (LD3') may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may also be used.

[0404] Figures 25 and 26 are schematic cross-sectional views for explaining a pixel according to the second-third embodiment of Figure 24. Figure 25 is a schematic cross-sectional view taken along line X6-X6' of Figure 24, and Figure 26 is a schematic cross-sectional view taken along line Y5-Y5' of Figure 24.

[0405] Referring to FIGS. 24 and 25, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0406] The pixel circuit layer (PCL) is described in the same manner as described with reference to Fig. 18. Therefore, description of overlapping content may be omitted.

[0407] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a first anode electrode (AE1'), a first-first connection electrode (LCE1a'), a second-first connection electrode (LCE2a'), a cathode electrode (CE'), a first bank (BNK1), first to fourth reflective electrodes (RFE1, RFE2, RFE3, RFE4), a first light-emitting element (LD1'), an overcoat layer (OCL), a third passivation layer (PSV3), and a capping layer (CPL).

[0408] A first anode electrode (AE1'), a first-first connection electrode (LCE1a'), a second-first connection electrode (LCE2a'), and a cathode electrode (CE') may be arranged on a pixel circuit layer (PCL).

[0409] The first anode electrode (AE1') can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second passivation layer (PSV2). In this way, the first anode electrode (AE1') can be electrically connected to the transistor (T_SP).

[0410] The cathode electrode (CE') may be spaced apart from the first anode electrode (AE1') in the first direction (DR1). The cathode electrode (CE') may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE').

[0411] The first-first connecting electrode (LCE1a') may be disposed between the cathode electrode (CE') and the first anode electrode (AE1'). The first-first connecting electrode (LCE1a') may be spaced apart from the cathode electrode (CE') and the first anode electrode (AE1').

[0412] The second-first connecting electrode (LCE2a') may be positioned between the first-first connecting electrode (LCE1a') and the cathode electrode (CE'). The second-first connecting electrode (LCE2a') may be spaced apart from the cathode electrode (CE'), the first-first connecting electrode (LCE1a'), and the first anode electrode (AE1').

[0413] A first bank (BNK1) may be disposed on a first anode electrode (AE1'), a first-first connection electrode (LCE1a'), a second-first connection electrode (LCE2a'), and a cathode electrode (CE'). The first bank (BNK1) may have a first opening (OP1) that exposes portions of the first anode electrode (AE1'), the first-first connection electrode (LCE1a'), the second-first connection electrode (LCE2a'), and the cathode electrode (CE'). A first light-emitting element (LD1') may be disposed in the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines an area where the first light-emitting element (LD1') is positioned.

[0414] The first bank (BNK1) may be configured to include a light-blocking material, and may prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0415] A first reflective electrode (RFE1) may be disposed on an exposed portion of a first anode electrode (AE1') and a side surface of a first bank (BNK1) adjacent thereto. A second reflective electrode (RFE2) may be disposed on an exposed portion of a cathode electrode (CE') and a side surface of a first bank (BNK1) adjacent thereto. A third reflective electrode (RFE3) may be disposed on an exposed portion of a first-first connection electrode (LCE1a') and a side surface of a first bank (BNK1) adjacent thereto. A fourth reflective electrode (RFE4) may be disposed on an exposed portion of a second-first connection electrode (LCE2a') and a side surface of a first bank (BNK1) adjacent thereto. The first to fourth reflective electrodes (RFE1, RFE2, RFE3, RFE4) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1') can be improved. In embodiments, the first to fourth reflective electrodes (RFE1, RFE2, RFE3, RFE4) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0416] The first light-emitting element (LD1') may include a first-first sub-light-emitting element (SLD1a'), a second-first sub-light-emitting element (SLD2a'), and a third-first sub-light-emitting element (SLD3a'). Each of the first-first sub-light-emitting element (SLD1a'), the second-first sub-light-emitting element (SLD2a'), and the third-first sub-light-emitting element (SLD3a') may include a light-emitting laminate (EST') in which a first semiconductor layer (21), a second semiconductor layer (22), an active layer (23), and an auxiliary layer (24) are sequentially laminated on each other, and first and second bonding electrodes (BDE1, BDE2). Here, the first and second bonding electrodes (BDE1, BDE2) may protrude in a direction toward the pixel circuit layer (PCL), and such a first light-emitting element (LD1') may be referred to as a flip chip type light-emitting element. Here, the description with reference to Fig. 17 can be substantially applied to a flip chip type light-emitting element. Therefore, description of overlapping content can be omitted.

[0417] In the embodiments, the first bonding electrode (BDE1) of the 1-1 sub-light emitting element (SLD1a') may be electrically connected to the first anode electrode (AE1') by contacting the first reflective electrode (RFE1). The second bonding electrode (BDE2) of the 1-1 sub-light emitting element (SLD1a') may be electrically connected to the 1-1 connection electrode (LCE1a') by contacting the third reflective electrode (RFE3).

[0418] In the embodiments, the first bonding electrode (BDE1) of the 2-1 sub-light emitting element (SLD2a') may be electrically connected to the 1-1 connection electrode (LCE1a') by contacting the third reflective electrode (RFE3). The second bonding electrode (BDE2) of the 2-1 sub-light emitting element (SLD2a') may be electrically connected to the 2-1 connection electrode (LCE2a') by contacting the fourth reflective electrode (RFE3).

[0419] In the embodiments, the first bonding electrode (BDE1) of the 3-1 sub-light emitting element (SLD3a') may be electrically connected to the 2-1 connection electrode (LCE2a') by contacting the 4th reflective electrode (RFE4). The second bonding electrode (BDE2) of the 3-1 sub-light emitting element (SLD3a') may be electrically connected to the cathode electrode (CE') by contacting the 2nd reflective electrode (RFE2).

[0420] Accordingly, between the first anode electrode (AE1') and the cathode electrode (CE'), the first-first sub-light emitting element (SLD1a'), the second-first sub-light emitting element (SLD2a'), and the third-first sub-light emitting element (SLD3a') can be connected in series with each other.

[0421] In embodiments, the first and second bonding electrodes (BDE1, BDE2) may include a eutectic metal.

[0422] The first light-emitting element (LD1') may further include an insulating film (25) covering an outer surface of the light-emitting stack (EST'). The insulating film (25) may serve to prevent an electrical short circuit that may occur when the active layer (23) comes into contact with a conductive material other than the first and second semiconductor layers (21, 22). The insulating film (25) may include a transparent insulating material. The insulating film (25) may be configured to expose at least the lower surfaces of the first and second bonding electrodes (BDE1, BDE2).

[0423] An overcoat layer (OCL) may be disposed within a first opening (OP1) in which the first to third reflective electrodes (RFE1, RFE2, RFE3) and the first light-emitting element (LD1') are disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1') bonded to the first to fourth reflective electrodes (RFE1, RFE2, RFE3, RFE4) so ​​as not to move. The overcoat layer (OCL) may protect components disposed below the overcoat layer (OCL) from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0424] A third passivation layer (PSV3) may be disposed on the first bank (BNK1) and the overcoat layer (OCL). The third passivation layer (PSV3) may protect components disposed beneath the third passivation layer (PSV3) and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0425] In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface of the first light-emitting element (LD1'). The first light-emitting element (LD1') may protrude into the light-functional layer (LFL). The first light-emitting element (LD1') may be at least partially positioned within the second opening (OP2) of the second bank (BNK2). For example, the height of the upper surface of the first light-emitting element (LD1') from the substrate (SUB) may be higher than the lowermost end of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1') may be provided to the light-functional layer (LFL) at a relatively high rate.

[0426] The capping layer (CPL) may be disposed on the third passivation layer (PSV3). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first light-emitting element (LD1'), from external moisture and humidity, and other things within the spirit and scope of the present disclosure. In embodiments, the capping layer (CPL) may not be disposed on the upper surface of the first light-emitting element (LD1'). In other embodiments, the capping layer (CPL) may entirely cover the first light-emitting element (LD1') and the third passivation layer (PSV3). The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto.

[0427] Above, the pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1') have been described. Each of the second and third sub-pixels (SP2', SP3') of FIG. 24 may also be configured similarly to the first sub-pixel (SP1') to the extent not otherwise described herein.

[0428] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive layer (LRL), and a color filter layer (CFL). The light functional layer (LFL) may be described in the same manner as described with reference to FIG. 17. Therefore, description of overlapping content may be omitted.

[0429] Referring to FIG. 24 and FIG. 26, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0430] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 25. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1', SP2', SP3') may be provided, respectively. In the display element layer (DPL), first to third light-emitting elements (LD1', LD2', LD3') corresponding to the first to third sub-pixels (SP1', SP2', SP3') may be provided, respectively. The first to third light-emitting elements (LD1', LD2', LD3') may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1') may be connected between a cathode electrode (CE', see FIG. 25) and a transistor (T_SP, see FIG. 25) included in the sub-pixel circuit of the first sub-pixel (SP1'). The second light-emitting element (LD2') may be connected between the cathode electrode (CE') and a transistor included in the sub-pixel circuit of the second sub-pixel (SP2'). The third light-emitting element (LD3') may be connected between the cathode electrode (CE') and a transistor included in the sub-pixel circuit of the third sub-pixel (SP3'). Hereinafter, overlapping descriptions may be omitted.

[0431] A light-functional layer (LFL) may be provided on the display element layer (DPL). The light-functional layer (LFL) is described in the same manner as described with reference to FIG. 19. Therefore, description of overlapping content may be omitted.

[0432] FIG. 27 is a schematic plan view for explaining a third-first embodiment of one of the pixels included in the display panel of FIG. 3.

[0433] Referring to FIG. 27, the pixel (PXL") may include first to third sub-pixels (SP1", SP2", SP3"). The first to third sub-pixels (SP1", SP2", SP3") may be arranged in the second direction (DR2). However, the arrangement of the pixel (PXL") is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1", SP2", SP3") may be arranged in a zigzag pattern.

[0434] First to third anode electrodes (AE1", AE2", AE3") may be respectively disposed in the first to third sub-pixels (SP1", SP2", SP3"). The first anode electrode (AE1") may be provided as an anode electrode (AE, see FIG. 2) of a sub-pixel circuit (SPC, see FIG. 2) included in the first sub-pixel (SP1"). The second anode electrode (AE2") may be provided as an anode electrode (AE) of a sub-pixel circuit (SPC) included in the second sub-pixel (SP2"). The third anode electrode (AE3") may be provided as an anode electrode (AE) of a sub-pixel circuit (SPC) included in the third sub-pixel (SP3").

[0435] The cathode electrode (CE") may be spaced apart from the first to third anode electrodes (AE1", AE2", AE3"). The cathode electrode (CE") may be disposed in the same layer as the first to third anode electrodes (AE1", AE2", AE3"). The cathode electrode (CE") may be spaced apart from the first to third anode electrodes (AE1", AE2", AE3") in a first direction (DR1). In embodiments, the cathode electrode (CE") may extend in a second direction (DR2) and be used as a common electrode for the pixel (PXL") and other pixels adjacent to the pixel (PXL"). Although not shown, the cathode electrode (CE") may extend in the first direction (DR1) as well as the second direction (DR2) and be used as a common electrode for all of the sub-pixels (SP) of FIG. 4. In this way, the cathode electrode (CE") can have various shapes.

[0436] In embodiments, a floating electrode (FTE") may be further disposed between the first to third anode electrodes (AE1", AE2", AE3") and the cathode electrode (CE"). The floating electrode (FTE") may be spaced apart from the first to third anode electrodes (AE1", AE2", AE3") and the cathode electrode (CE"). The floating electrode (FTE") may be disposed in the same layer as the first to third anode electrodes (AE1", AE2", AE3").

[0437] According to embodiments, the floating electrode (FTE") may function as a repair wire by being connected to any one of the first to third anode electrodes (AE1", AE2", AE3").

[0438] According to embodiments, the floating electrode (FTE") may be connected to the cathode electrode (CE") and may function as an auxiliary wire to lower the resistance of the cathode electrode (CE").

[0439] According to embodiments, floating electrodes (FTE") may be provided. For example, first and second floating electrodes extending in the second direction (DR2) and arranged in the first direction (DR1) may be disposed between the first to third anode electrodes (AE1", AE2", AE3") and the cathode electrode (CE"). In this case, one of the first and second floating electrodes may be connected to one of the first to third anode electrodes (AE1", AE2", AE3"), thereby functioning as a repair wire, and the other of the first and second floating electrodes may be connected to the cathode electrode (CE"), thereby functioning as an auxiliary wire for lowering the resistance of the cathode electrode (CE").

[0440] According to embodiments, the floating electrode (FTE") may be omitted, in which case the cathode electrode (CE") may be extended and disposed in the area where the floating electrode (FTE") is disposed as shown in FIG. 27. Accordingly, the resistance of the cathode electrode (CE") may be reduced.

[0441] First to third light-emitting elements (LD1", LD2", LD3") may be disposed on first to third anode electrodes (AE1", AE2", AE3"), cathode electrodes (CE"), and floating electrodes (FTE").

[0442] The first light-emitting element (LD1") may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of the first sub-pixel (SP1"). The first light-emitting element (LD1") may include a 1-1 sub-light-emitting element (SLD1a") and a 2-1 sub-light-emitting element (SLD2a"). The 1-1 sub-light-emitting element (SLD1a") may be electrically connected to a first anode electrode (AE1") and a 1-1 connection electrode (UCE1a") described below. The second-first sub-light-emitting element (SLD2a") can be electrically connected to the first-first connection electrode (UCE1a") and the cathode electrode (CE"). Accordingly, the first-first sub-light-emitting element (SLD1a") and the second-first sub-light-emitting element (SLD2a") can be connected in series with each other through the first-first connection electrode (UCE1a") between the first anode electrode (AE1") and the cathode electrode (CE").

[0443] The second light-emitting element (LD2") may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of the second sub-pixel (SP2"). The second light-emitting element (LD2") may include a first-second sub-light-emitting element (SLD1b") and a second-second sub-light-emitting element (SLD2b"). The first-second sub-light-emitting element (SLD1b") may be electrically connected to a second anode electrode (AE2") and a first-second connection electrode (UCE1b") described below. The second-second sub-light-emitting element (SLD2b") can be electrically connected to the first-second connection electrode (UCE1b") and the cathode electrode (CE"). Accordingly, the first-second sub-light-emitting element (SLD1b") and the second-second sub-light-emitting element (SLD2b") can be connected in series with each other through the first-second connection electrode (UCE1b") between the second anode electrode (AE2") and the cathode electrode (CE").

[0444] The third light-emitting element (LD3") may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of a third sub-pixel (SP3"). The third light-emitting element (LD3") may include a 1-3 sub-light-emitting element (SLD1c") and a 2-3 sub-light-emitting element (SLD2c"). The 1-3 sub-light-emitting element (SLD1c") may be electrically connected to a third anode electrode (AE3") and a 1-3 connection electrode (UCE1c") described below. The 2-3 sub-light emitting element (SLD2c") can be electrically connected to the 1-3 connecting electrode (UCE1c") and the cathode electrode (CE"). Accordingly, the 1-3 sub-light emitting element (SLD1c") and the 2-3 sub-light emitting element (SLD2c") can be connected in series with each other through the 1-3 connecting electrode (UCE1c") between the 3rd anode electrode (AE3") and the cathode electrode (CE").

[0445] The first light-emitting element (LD1"), the second light-emitting element (LD2"), and the third light-emitting element (LD3") may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0446] A first transparent electrode (ITO1), a second transparent electrode (ITO2), and a first connection electrode (UCE1") can be placed on the first light-emitting element (LD1"), the second light-emitting element (LD2"), and the third light-emitting element (LD3").

[0447] The first transparent electrode (ITO1) may be disposed in each of the first to third sub-pixels (SP1", SP2", and SP3"). In the first sub-pixel (SP1"), the first anode electrode (AE1") and the first-first sub-light emitting element (SLD1a") may be electrically connected to each other through the first transparent electrode (ITO1). In the second sub-pixel (SP2"), the second anode electrode (AE2") and the first-second sub-light emitting element (SLD1b") may be electrically connected to each other through the first transparent electrode (ITO1). In the third sub-pixel (SP3"), the third anode electrode (AE3") and the first-third sub-light emitting element (SLD1c") may be electrically connected to each other through the first transparent electrode (ITO1).

[0448] The second transparent electrode (ITO2) may be disposed in each of the first to third sub-pixels (SP1", SP2", and SP3"). In the first sub-pixel (SP1"), the cathode electrode (CE") and the second-first sub-light emitting element (SLD2a") may be electrically connected to each other through the second transparent electrode (ITO2). In the second sub-pixel (SP2"), the cathode electrode (CE") and the second-second sub-light emitting element (SLD2b") may be electrically connected to each other through the second transparent electrode (ITO2). In the third sub-pixel (SP3"), the cathode electrode (CE") and the second-third sub-light emitting element (SLD2c") may be electrically connected to each other through the second transparent electrode (ITO1).

[0449] The first connection electrode (UCE1") may be spaced apart from the first and second transparent electrodes (ITO1, ITO2). In embodiments, the first connection electrode (UCE1") may be disposed on the same layer as the first and second transparent electrodes (ITO1, ITO2). The first connection electrode (UCE1") may include a first-first connection electrode (UCE1a"), a first-second connection electrode (UCE1b"), and a first-third connection electrode (UCE1c").

[0450] The first-first connection electrode (UCE1a") may be provided to the first sub-pixel (SP1"). The first-first connection electrode (UCE1a") may be electrically connected to the first-first sub-light-emitting element (SLD1a") and the second-first sub-light-emitting element (SLD2a").

[0451] The first-second connection electrode (UCE1b") may be provided to the second sub-pixel (SP2"). The first-second connection electrode (UCE1b") may be electrically connected to the first-second sub-light-emitting element (SLD1b") and the second-second sub-light-emitting element (SLD2b").

[0452] The first-third connection electrode (UCE1c") may be provided to the third sub-pixel (SP3"). The first-third connection electrode (UCE1c") may be electrically connected to the first-third sub-light-emitting element (SLD1c") and the second-third sub-light-emitting element (SLD2c").

[0453] Figures 28 and 29 are schematic cross-sectional views for explaining a pixel according to the third embodiment of Figure 27. Figure 28 is a schematic cross-sectional view taken along line X7-X7' of Figure 27, and Figure 29 is a schematic cross-sectional view taken along line Y6-Y6' of Figure 27.

[0454] Referring to FIGS. 27 and 28, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0455] The pixel circuit layer (PCL) can be configured as described with reference to Fig. 9. Therefore, description of overlapping content can be omitted.

[0456] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a first anode electrode (AE1"), a floating electrode (FTE"), a cathode electrode (CE"), a first bank (BNK1), first to third reflective electrodes (RFE1, RFE2, RFE3), an overcoat layer (OCL), a first light-emitting element (LD1"), a third passivation layer (PSV3), first and second transparent electrodes (ITO1, ITO2), a first-first connection electrode (UCE1a"), and a capping layer (CPL).

[0457] A first anode electrode (AE1"), a floating electrode (FTE"), and a cathode electrode (CE") may be disposed on the pixel circuit layer (PCL).

[0458] The first anode electrode (AE1") can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second passivation layer (PSV2). In this way, the first anode electrode (AE1") can be electrically connected to the transistor (T_SP).

[0459] The cathode electrode (CE") may be spaced apart from the first anode electrode (AE1") in the first direction (DR1). The cathode electrode (CE") may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE").

[0460] A floating electrode (FTE") may be disposed between the first anode electrode (AE1") and the cathode electrode (CE"). The floating electrode (FTE") may be spaced apart from the first anode electrode (AE1") and the cathode electrode (CE").

[0461] A first bank (BNK1) may be disposed on a first anode electrode (AE1"), a floating electrode (FTE"), and a cathode electrode (CE"). The first bank (BNK1) may have a first opening (OP1) exposing portions of the first anode electrode (AE1"), the floating electrode (FTE"), and the cathode electrode (CE"). A first light-emitting element (LD1") may be disposed in the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines an area where the first light-emitting element (LD1") is positioned.

[0462] The first bank (BNK1) may be configured to include a light-blocking material, and may prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0463] A first reflective electrode (RFE1) may be disposed on an exposed portion of a first anode electrode (AE1") and a side surface of a first bank (BNK1) adjacent thereto. A second reflective electrode (RFE2) may be disposed on an exposed portion of a cathode electrode (CE") and a side surface of a first bank (BNK1) adjacent thereto. A third reflective electrode (RFE3) may be disposed on an exposed portion of a floating electrode (FTE") and a side surface of a first bank (BNK1) adjacent thereto. The first to third reflective electrodes (RFE1, RFE2, RFE3) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1") may be improved. In the embodiments, the first to third reflective electrodes (RFE1, RFE2, RFE3) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0464] An overcoat layer (OCL) may be disposed within the first opening (OP1) of the first bank (BNK1) on the first to third reflective electrodes (RFE1, RFE2, RFE3) and the second passivation layer (PSV2). A first light-emitting element (LD1") may be disposed on the overcoat layer (OCL). The first light-emitting element (LD1") may be partially buried in the overcoat layer (OCL).

[0465] The overcoat layer (OCL) can fix the first light-emitting element (LD1") so that it does not move. The overcoat layer (OCL) can protect components disposed under the overcoat layer (OCL) from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) can include epoxy, but embodiments are not limited thereto.

[0466] The first light-emitting element (LD1") may include a first-first sub-light-emitting element (SLD1a") and a second-first sub-light-emitting element (SLD2a"). Each of the first-first sub-light-emitting element (SLD1a") and the second-first sub-light-emitting element (SLD2a") may include a light-emitting stack (EST") in which an auxiliary layer (34), a second semiconductor layer (32), an active layer (33), and a first semiconductor layer (31) are sequentially laminated on each other, and first and second bonding electrodes (BDE1, BDE2). Here, the first and second bonding electrodes (BDE1, BDE2) may protrude in a direction away from the pixel circuit layer (PCL), and such a first light-emitting element (LD1") may be referred to as a lateral chip type light-emitting element.

[0467] The first semiconductor layer (31) may be configured to provide holes. The first semiconductor layer (31) may have a first polarity. For example, the first semiconductor layer (31) may include at least one p-type semiconductor layer. For example, the first semiconductor layer (31) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the first semiconductor layer (31) is not limited thereto, and various other materials may constitute the first semiconductor layer (31). In one embodiment of the present invention, the first semiconductor layer (31) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0468] The second semiconductor layer (32) is disposed under the first semiconductor layer (31) and may be configured to provide electrons. The second semiconductor layer (32) may have a second polarity different from the first polarity. For example, the second semiconductor layer (32) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (32) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer (32) is not limited thereto, and various other materials may constituting the second semiconductor layer (32). In one embodiment of the present invention, the second semiconductor layer (32) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant). According to an embodiment, the second semiconductor layer (32) may form an n-type semiconductor layer together with the auxiliary layer (34).

[0469] The active layer (33) can provide a region where electrons and holes recombine between the first semiconductor layer (31) and the second semiconductor layer (32). As electrons and holes recombine in the active layer (33), they transition to a lower energy level, and light having a corresponding wavelength can be generated. The active layer (33) can be formed in a single or multiple quantum well structure. When the active layer (33) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer can be repeatedly stacked on top of each other to form the active layer (23). However, the active layer (33) is not limited to the above-described structure.

[0470] The auxiliary layer (34) may include a gallium nitride (GaN) semiconductor material that is substantially undoped with impurities or doped with impurities at a relatively low concentration. The auxiliary layer (34) may form an n-type semiconductor layer together with the second semiconductor layer (32).

[0471] A first bonding electrode (BDE1) may be disposed on a first semiconductor layer (31). The first bonding electrode (BDE1) may be electrically connected to the first semiconductor layer (31). A second bonding electrode (BDE2) may be electrically connected to the second semiconductor layer (32). For example, the second bonding electrode (BDE2) may contact the second semiconductor layer (32) exposed by removing the first semiconductor layer (31) and the active layer (33). In embodiments, the first and second bonding electrodes (BDE1, BDE2) may include a eutectic metal.

[0472] The first light-emitting element (LD1") may further include an insulating film (35) covering an outer surface of the light-emitting stack (EST"). The insulating film (35) may serve to prevent an electrical short circuit that may occur when the active layer (33) comes into contact with a conductive material other than the first and second semiconductor layers (31, 32). The insulating film (35) may include a transparent insulating material. The insulating film (35) may be configured to expose at least the upper surfaces of the first and second bonding electrodes (BDE1, BDE2).

[0473] A third passivation layer (PSV3) may be disposed on the first to third reflective electrodes (RFE1, RFE2, RFE3), the first light-emitting element (LD1"), and the overcoat layer (OCL). The third passivation layer (PS3) may protect components disposed under the third passivation layer (PSV3) and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as any one of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0474] The third passivation layer (PSV3) may have second to seventh openings (OP2, OP3, OP4, OP5, OP6, OP7). The second opening (OP2) may expose a portion of the first reflective electrode (RFE1). The third opening (OP3) may expose a top surface of the first bonding electrode (BDE1) of the 1-1 sub-light emitting element (SLD1a"). The fourth opening (OP4) may expose a top surface of the second bonding electrode (BDE2) of the 1-1 sub-light emitting element (SLD1a"). The fifth opening (OP5) may expose a top surface of the first bonding electrode (BDE1) of the 2-1 sub-light emitting element (SLD2a"). The sixth opening (OP6) may expose a top surface of the second bonding electrode (BDE2) of the 2-1 sub-light emitting element (SLD2a"). The seventh opening (OP7) can expose a portion of the second reflective electrode (RFE2).

[0475] A first transparent electrode (ITO1), a second transparent electrode (ITO2), and a first-first connection electrode (UCE1a") may be disposed on the third passivation layer (PSV3).

[0476] The first transparent electrode (ITO1) can electrically connect the first reflective electrode (RFE1) exposed by the second opening (OP2) to the first bonding electrode (BDE1) of the first-first sub-light-emitting element (SLD1a") exposed by the third opening (OP3). Accordingly, the first bonding electrode (BDE1) of the first-first sub-light-emitting element (SLD1a") can be electrically connected to the first anode electrode (AE1") through the first transparent electrode (ITO1) and the first reflective electrode (RFE1).

[0477] The second transparent electrode (ITO2) can electrically connect the second reflective electrode (RFE2) exposed by the seventh opening (OP7) to the second bonding electrode (BDE2) of the second-first sub-light-emitting element (SLD2a") exposed by the sixth opening (OP6). Accordingly, the second bonding electrode (BDE2) of the second-first sub-light-emitting element (SLD2a") can be electrically connected to the cathode electrode (CE") through the second transparent electrode (ITO2) and the second reflective electrode (RFE2).

[0478] The first-first connection electrode (UCE1a") can electrically connect the second bonding electrode (BDE2) of the first-first sub-light-emitting element (SLD1a") exposed by the fourth opening (OP4) to the first bonding electrode (BDE1) of the second-first sub-light-emitting element (SLD2a") exposed by the fifth opening (OP5). Accordingly, the second bonding electrode (BDE2) of the first-first sub-light-emitting element (SLD1a") can be electrically connected to the first bonding electrode (BDE1) of the second-first sub-light-emitting element (SLD2a") via the first-first connection electrode (UCE1a").

[0479] In this way, the first-first sub-light-emitting element (SLD1a") and the second-first sub-light-emitting element (SLD2a") can be connected in series with each other through the first-first connection electrode (UCE1a") between the first anode electrode (AE1") and the cathode electrode (CE").

[0480] In the embodiments, the first transparent electrode (ITO1), the second transparent electrode (ITO2), and the 1-1 connection electrode (UCE1a") may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In the embodiments, the first transparent electrode (ITO1), the second transparent electrode (ITO2), and the 1-1 connection electrode (UCE1a") may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the materials of the first transparent electrode (ITO1), the second transparent electrode (ITO2), and the 1-1 connection electrode (UCE1a") are not limited thereto.

[0481] A capping layer (CPL) may be disposed on the third passivation layer (PSV3). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first and second transparent electrodes (ITO1, ITO2), the first-first connection electrode (UCE1a"), the first light-emitting element (LD1"), etc., from external moisture and humidity, etc. within the scope and spirit of the present disclosure. The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto.

[0482] Above, the pixel circuit layer (PCL) and the display element layer (DPL) of the first sub-pixel (SP1") have been described. Each of the second and third sub-pixels (SP2", SP3") of FIG. 27 can also be configured similarly to the first sub-pixel (SP1"), unless otherwise described herein.

[0483] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0484] A second bank (BNK2) may be positioned on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have an eighth opening (OP8) that overlaps the first opening (OP1).

[0485] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In some embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0486] A reflective layer (RFL) may be disposed on the side surfaces of the second bank (BNK2) adjacent to the eighth opening (OP8). The reflective layer (RFL) is configured to reflect incident light, and thus, light emission efficiency may be improved. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0487] A fourth passivation layer (PSV4) may be disposed on the capping layer (CPL) within the eighth opening (OP8). The fourth passivation layer (PSV4) may protect components disposed beneath the fourth passivation layer (PSV4) and provide a flat upper surface. The fourth passivation layer (PSV4) may include the same material as any one of the first to third passivation layers (PSV1, PSV2, PSV3), but embodiments are not limited thereto.

[0488] On the fourth passivation layer (PSV4), a first light conversion pattern (CCP1) can be arranged within the eighth opening (OP8).

[0489] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. The color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0490] The first sub-pixel (SP1") may be a red sub-pixel. When the first light-emitting element (LD1") emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1") emits red light, the first light conversion pattern (CCP1) may include scattering particles. In this way, the particles included in the first light conversion pattern (CCP1) may be variously changed depending on the color of the light emitted from the first light-emitting element (LD1").

[0491] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1) and the first color filter (CF1). The low-refractive-index layer (LRL) may be configured to refract or totally reflect light depending on an incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0492] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) may overlap the first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1") is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0493] Referring to FIGS. 27 and 29, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0494] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 28. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1", SP2", SP3") may be provided, respectively. In the display element layer (DPL), first to third light-emitting elements (LD1", LD2", LD3") corresponding to the first to third sub-pixels (SP1", SP2", SP3") may be provided, respectively. The first to third light-emitting elements (LD1", LD2", LD3") may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1") may be connected between the cathode electrode (CE"), see FIG. 28) and a transistor (T_SP, see FIG. 28) included in the sub-pixel circuit of the first sub-pixel (SP1"). The second light-emitting element (LD2") may be connected between the cathode electrode (CE") and a transistor included in the sub-pixel circuit of the second sub-pixel (SP2"). The third light-emitting element (LD3") may be connected between the cathode electrode (CE") and a transistor included in the sub-pixel circuit of the third sub-pixel (SP3"). Hereinafter, overlapping descriptions may be omitted.

[0495] A light functional layer (LFL) may be provided on the display element layer (DPL). The light functional layer (LFL) is described in the same manner as described with reference to FIG. 28. Hereinafter, redundant descriptions may be omitted.

[0496] The second bank (BNK2) may have eight openings (OP8). It may be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1", SP2", SP3") are defined by the second bank (BNK2). An area overlapping the second bank (BNK2) may correspond to the non-light-emitting area (NEMA). An area overlapping the eight openings (OP8) of the second bank (BNK2) may correspond to the light-emitting area (EMA) of the first to third sub-pixels (SP1", SP2", SP3").

[0497] A fourth passivation layer (PSV4) may be disposed within the eighth openings (OP8) on the capping layer (CPL). First and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) may be disposed within the eighth openings (OP8) on the fourth passivation layer (PSV4).

[0498] In the embodiments, the first to third light-emitting elements (LD1", LD2", LD3") may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light emission efficiency. Accordingly, the first to third sub-pixels (SP1", SP2", SP3") may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0499] In the embodiments, the first to third light-emitting elements (LD1", LD2", LD3") may be configured to emit red, green, and blue light, respectively. In this case, each of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the first to third light-emitting elements (LD1", LD2", LD3").

[0500] In the embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0501] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first and second light conversion patterns (CCP1, CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3").

[0502] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0503] Each of the first to third color filters (CF1, CF2, CF3) can selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1") is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2") is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3") is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1, CF2, CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, embodiments are not limited thereto, and the first to third color filters (CF1, CF2, CF3) may have a refractive index lower than or equal to that of the low-refractive-index layer (LRL).

[0504] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1", SP2", SP3") are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0505] In embodiments, the light blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light blocking pattern between the first and second color filters (CF1, CF2) among the light blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, the light blocking pattern between the second and third color filters (CF2, CF3) among the light blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap, and the light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of an adjacent pixel may be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) may extend into the non-emitting area (NEMA) to form the light blocking patterns (LBP).

[0506] FIG. 30 is a schematic plan view for explaining a third-second embodiment of one of the pixels included in the display panel of FIG. 3.

[0507] Referring to FIG. 30, except that the first to third sub-light emitting elements (SLD1a", SLD1b", SLD1c") and the second to third sub-light emitting elements (SLD2a", SLD2b", SLD2c") are provided, the pixel (PXL") according to the third embodiment of the present invention may be substantially the same as the pixel (PXL") according to the third embodiment of the present invention described with reference to FIG. 27. Therefore, description of overlapping content may be omitted.

[0508] 1-1 sub light-emitting elements (SLD1a") may be provided. For example, two 1-1 sub light-emitting elements (SLD1a") may be provided, but the present invention is not limited thereto. Three or more 1-1 sub light-emitting elements (SLD1a") may be provided. Each of the 1-1 sub light-emitting elements (SLD1a") may be electrically connected to the first anode electrode (AE1") and the 1-1 connection electrode (UCE1a"). In this case, the 1-1 sub light-emitting elements (SLD1a") may be connected in parallel with each other between the first anode electrode (AE1") and the 1-1 connection electrode (UCE1a").

[0509] 2-1 sub light-emitting elements (SLD2a") may be provided. For example, two 2-1 sub light-emitting elements (SLD2a") may be provided, but the present invention is not limited thereto. Three or more 2-1 sub light-emitting elements (SLD2a") may be provided. Each of the 2-1 sub light-emitting elements (SLD2a") may be electrically connected to the 1-1 connection electrode (UCE1a") and the cathode electrode (CE"). In this case, the 2-1 sub light-emitting elements (SLD2a") may be connected in parallel to each other between the 1-1 connection electrode (UCE1a") and the cathode electrode (CE").

[0510] Between the first anode electrode (AE1") and the cathode electrode (CE"), the first-first sub-light-emitting elements (SLD1a") and the second-first sub-light-emitting elements (SLD2a") can be connected in series to each other through the first-first connecting electrode (UCE1a").

[0511] Likewise, first-second and first-third sub-light emitting elements (SLD1b", SLD1c") and second-second and second-third sub-light emitting elements (SLD2b", SLD2c") may also be provided. In this case, the first-second sub-light emitting elements (SLD1b") may be connected in parallel to each other, the first-third sub-light emitting elements (SLD1c") may be connected in parallel to each other, the second-second sub-light emitting elements (SLD2b") may be connected in parallel to each other, and the second-third sub-light emitting elements (SLD2c") may be connected in parallel to each other. The first-second sub-light emitting elements (SLD1b") and the second-second sub-light emitting elements (SLD2b") may be connected in series to each other, and the first-third sub-light emitting elements (SLD1c") and the second-third sub-light emitting elements (SLD2c") may be connected in series to each other.

[0512] Figures 31 to 33 are schematic cross-sectional views for explaining a pixel according to the third embodiment of Figure 30. Figure 31 is a schematic cross-sectional view taken along line X8-X8' of Figure 30, Figure 32 is a schematic cross-sectional view taken along line X9-X9' of Figure 30, and Figure 33 is a schematic cross-sectional view taken along line Y7-Y7' of Figure 30.

[0513] Referring to FIGS. 30 to 33, the first to third sub-light emitting elements (SLD1a", SLD1b", SLD1c") and the second to third sub-light emitting elements (SLD2a", SLD2b", SLD2c") may be provided, respectively. In this case, the first to third sub-light emitting elements (SLD1a", SLD1b", SLD1c") and the second to third sub-light emitting elements (SLD2a", SLD2b", SLD2c") may be light emitting elements of the lateral chip type described with reference to FIG. 28. Hereinafter, descriptions of contents overlapping with those described in FIGS. 28 and 29 may be omitted.

[0514] In the embodiments, the first bonding electrodes (BDE1) of the first-first sub-light-emitting elements (SLD1a") may be electrically connected to the first anode electrode (AE1") through the first transparent electrodes (ITO1) and the first reflective electrode (RFE1). The second bonding electrodes (BDE2) of the second-first sub-light-emitting elements (SLD2a") may be electrically connected to the cathode electrode (CE") through the second transparent electrodes (ITO2) and the second reflective electrode (RFE2).

[0515] In the embodiments, the second bonding electrodes (BDE2) of the first-first sub-light emitting elements (SLD1a") may be electrically connected to the first bonding electrodes (BDE1) of the second-first sub-light emitting elements (SLD2a") via the first-first connection electrode (UCE1a").

[0516] Accordingly, the first-first sub-light-emitting elements (SLD1a") and the second-first sub-light-emitting elements (SLD2a") can be connected in series with each other between the first anode electrode (AE1") and the cathode electrode (CE"). The first-first sub-light-emitting elements (SLD1a") can be connected in parallel with each other between the first anode electrode (AE1") and the first-first connection electrode (UCE1a"), and the second-first sub-light-emitting elements (SLD2a") can be connected in parallel with each other between the first-first connection electrode (UCE1a") and the cathode electrode (CE").

[0517] Above, the first light-emitting element (LD1") included in the first sub-pixel (SP1") has been described, but the second and third light-emitting elements (LD2", LD3") included in the second and third sub-pixels (SP2", SP3") of FIG. 30 may also be configured similarly to the first light-emitting element (LD1") within a range not described differently herein.

[0518] FIG. 34 is a schematic plan view for explaining a third embodiment of one of the pixels included in the display panel of FIG. 3.

[0519] Referring to FIG. 34, the pixel (PXL") may include first to third sub-pixels (SP1", SP2", SP3"). The first to third sub-pixels (SP1", SP2", SP3") may be arranged in the second direction (DR2). However, the arrangement of the pixel (PXL") is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1", SP2", SP3") may be arranged in a zigzag pattern.

[0520] First to third sub-pixels (SP1", SP2", SP3") and first to third anode electrodes (AE1", AE2", AE3") may be respectively arranged. The first to third anode electrodes (AE1", AE2", AE3") may be configured in the same manner as described with reference to FIG. 27.

[0521] The cathode electrode (CE") may be spaced apart from the first to third anode electrodes (AE1", AE2", AE3"). The cathode electrode (CE") may be configured as described with reference to FIG. 27.

[0522] In embodiments, a floating electrode (FTE") may be further disposed between the first to third anode electrodes (AE1", AE2", AE3") and the cathode electrode (CE"). The floating electrode (FTE") may be configured as described with reference to FIG. 27.

[0523] First to third light-emitting elements (LD1", LD2", LD3") may be disposed on first to third anode electrodes (AE1", AE2", AE3"), cathode electrodes (CE"), and floating electrodes (FTE").

[0524] The first light-emitting element (LD1") may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of the first sub-pixel (SP1"). The first light-emitting element (LD1") may include a first-first sub-light-emitting element (SLD1a"), a second-first sub-light-emitting element (SLD2a"), and a third-first sub-light-emitting element (SLD3a"). The first-first sub-light-emitting element (SLD1a") may be electrically connected to the first anode electrode (AE1") and the first-first connection electrode (UCE1a"). The second-first sub-light-emitting element (SLD2a") may be electrically connected to the first-first connection electrode (UCE1a") and the second-first connection electrode (UCE2a"). The third-first sub-light-emitting element (SLD3a") can be electrically connected to the second-first connection electrode (UCE2a") and the cathode electrode (CE"). Accordingly, the first-first sub-light-emitting element (SLD1a"), the second-first sub-light-emitting element (SLD2a"), and the third-first sub-light-emitting element (SLD3a") can be connected in series with each other through the first-first connection electrode (UCE1a") and the second-first connection electrode (UCE2a") between the first anode electrode (AE1") and the cathode electrode (CE").

[0525] The second light-emitting element (LD2") may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of the second sub-pixel (SP2"). The second light-emitting element (LD2") may include a first-second sub-light-emitting element (SLD1b"), a second-second sub-light-emitting element (SLD2b"), and a third-second sub-light-emitting element (SLD3b"). The first-second sub-light-emitting element (SLD1b") may be electrically connected to the second anode electrode (AE2") and the first-second connection electrode (UCE1b"). The second-second sub-light-emitting element (SLD2b") may be electrically connected to the first-second connection electrode (UCE1b") and the second-second connection electrode (UCE2b"). The 3-2 sub-light emitting element (SLD3b") can be electrically connected to the 2-2 connection electrode (UCE2b") and the cathode electrode (CE"). Accordingly, the 1-2 sub-light emitting element (SLD1b"), the 2-2 sub-light emitting element (SLD2b"), and the 3-2 sub-light emitting element (SLD3b") can be connected in series to each other through the 1-2 connection electrode (UCE1b") and the 2-2 connection electrode (UCE2b") between the 2nd anode electrode (AE2") and the cathode electrode (CE").

[0526] The third light-emitting element (LD3") may be provided as a light-emitting element (LD, see FIG. 2) connected to a sub-pixel circuit (SPC) of a third sub-pixel (SP3"). The third light-emitting element (LD3") may include a 1-3 sub-light-emitting element (SLD1c"), a 2-3 sub-light-emitting element (SLD2c"), and a 3-3 sub-light-emitting element (SLD3c"). The 1-3 sub-light-emitting element (SLD1c") may be electrically connected to the 3rd anode electrode (AE3") and the 1-3 connection electrode (UCE1c"). The 2-3 sub-light-emitting element (SLD2c") may be electrically connected to the 1-3 connection electrode (UCE1c") and the 2-3 connection electrode (UCE2c"). The 3-3 sub-light emitting element (SLD3c") can be electrically connected to the 2-3 connecting electrode (UCE2c") and the cathode electrode (CE"). Accordingly, the 1-3 sub-light emitting element (SLD1c"), the 2-3 sub-light emitting element (SLD2c"), and the 3-3 sub-light emitting element (SLD3c") can be connected in series to each other through the 1-3 connecting electrode (UCE1c") and the 2-3 connecting electrode (UCE2c") between the 3rd anode electrode (AE3") and the cathode electrode (CE").

[0527] The first light-emitting element (LD1"), the second light-emitting element (LD2"), and the third light-emitting element (LD3") may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0528] A first transparent electrode (ITO1), a second transparent electrode (ITO2), a first connection electrode (UCE1"), and a second connection electrode (UCE2") can be arranged on the first light-emitting element (LD1"), the second light-emitting element (LD2"), and the third light-emitting element (LD3").

[0529] The first transparent electrode (ITO1) may be disposed in each of the first to third sub-pixels (SP1", SP2", and SP3"). In the first sub-pixel (SP1"), the first anode electrode (AE1") and the first-first sub-light emitting element (SLD1a") may be electrically connected to each other through the first transparent electrode (ITO1). In the second sub-pixel (SP2"), the second anode electrode (AE2") and the first-second sub-light emitting element (SLD1b") may be electrically connected to each other through the first transparent electrode (ITO1). In the third sub-pixel (SP3"), the third anode electrode (AE3") and the first-third sub-light emitting element (SLD1c") may be electrically connected to each other through the first transparent electrode (ITO1).

[0530] The second transparent electrode (ITO2) may be disposed in each of the first to third sub-pixels (SP1", SP2", and SP3"). In the first sub-pixel (SP1"), the cathode electrode (CE") and the 3-1 sub-light emitting element (SLD3a") may be electrically connected to each other through the second transparent electrode (ITO2). In the second sub-pixel (SP2"), the cathode electrode (CE") and the 3-2 sub-light emitting element (SLD3b") may be electrically connected to each other through the second transparent electrode (ITO2). In the third sub-pixel (SP3"), the cathode electrode (CE") and the 3-3 sub-light emitting element (SLD3c") may be electrically connected to each other through the second transparent electrode (ITO1).

[0531] The first connection electrode (UCE1") may be spaced apart from the first and second transparent electrodes (ITO1, ITO2). In embodiments, the first connection electrode (UCE1") may be disposed on the same layer as the first and second transparent electrodes (ITO1, ITO2). The first connection electrode (UCE1") may include a first-first connection electrode (UCE1a"), a first-second connection electrode (UCE1b"), and a first-third connection electrode (UCE1c").

[0532] The first-first connection electrode (UCE1a") may be provided to the first sub-pixel (SP1"). The first-first connection electrode (UCE1a") may be electrically connected to the first-first sub-light-emitting element (SLD1a") and the second-first sub-light-emitting element (SLD2a").

[0533] The first-second connection electrode (UCE1b") may be provided to the second sub-pixel (SP2"). The first-second connection electrode (UCE1b") may be electrically connected to the first-second sub-light-emitting element (SLD1b") and the second-second sub-light-emitting element (SLD2b").

[0534] The first-third connection electrode (UCE1c") may be provided to the third sub-pixel (SP3"). The first-third connection electrode (UCE1c") may be electrically connected to the first-third sub-light-emitting element (SLD1c") and the second-third sub-light-emitting element (SLD2c").

[0535] The second connection electrode (UCE2") may be spaced apart from the first and second transparent electrodes (ITO1, ITO2), and the first connection electrode (UCE1"). In embodiments, the second connection electrode (UCE2") may be disposed on the same layer as the first and second transparent electrodes (ITO1, ITO2). The second connection electrode (UCE2") may include a second-first connection electrode (UCE2a"), a second-second connection electrode (UCE2b"), and a second-third connection electrode (UCE2c").

[0536] The second-first connection electrode (UCE2a") may be provided to the first sub-pixel (SP1"). The second-first connection electrode (UCE2a") may be electrically connected to the second-first sub-light-emitting element (SLD2a") and the third-first sub-light-emitting element (SLD3a").

[0537] The second-second connection electrode (UCE2b") may be provided to the second sub-pixel (SP2"). The second-second connection electrode (UCE2b") may be electrically connected to the second-second sub-light-emitting element (SLD2b") and the third-second sub-light-emitting element (SLD3b").

[0538] The 2-3 connection electrode (UCE2c") may be provided to the 3rd sub-pixel (SP3"). The 2-3 connection electrode (UCE2c") may be electrically connected to the 2-3 sub-light-emitting element (SLD2c") and the 3-3 sub-light-emitting element (SLD3c").

[0539] Figures 35 and 36 are schematic cross-sectional views for explaining a pixel according to the third embodiment of Figure 34. Figure 35 is a schematic cross-sectional view taken along line X10-X10' of Figure 34, and Figure 36 is a schematic cross-sectional view taken along line Y8-Y8' of Figure 34.

[0540] Referring to FIGS. 34 and 35, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0541] The pixel circuit layer (PCL) can be configured as described with reference to Fig. 28. Therefore, description of overlapping content can be omitted.

[0542] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include a first anode electrode (AE1"), a floating electrode (FTE"), a cathode electrode (CE"), a first bank (BNK1), first to third reflective electrodes (RFE1, RFE2, RFE3), an overcoat layer (OCL), a first light-emitting element (LD1"), a third passivation layer (PSV3), first and second transparent electrodes (ITO1, ITO2), a first-first connection electrode (UCE1a"), a second-first connection electrode (UCE2a"), and a capping layer (CPL).

[0543] The first anode electrode (AE1") can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second passivation layer (PSV2). In this way, the first anode electrode (AE1") can be electrically connected to the transistor (T_SP).

[0544] The cathode electrode (CE") may be spaced apart from the first anode electrode (AE1") in the first direction (DR1). The cathode electrode (CE") may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE").

[0545] A floating electrode (FTE") may be disposed between the first anode electrode (AE1") and the cathode electrode (CE"). The floating electrode (FTE") may be spaced apart from the first anode electrode (AE1") and the cathode electrode (CE").

[0546] A first bank (BNK1) may be disposed on a first anode electrode (AE1"), a floating electrode (FTE"), and a cathode electrode (CE"). The first bank (BNK1) may have a first opening (OP1) exposing portions of the first anode electrode (AE1"), the floating electrode (FTE"), and the cathode electrode (CE"). A first light-emitting element (LD1") may be disposed in the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines an area where the first light-emitting element (LD1") is positioned.

[0547] The first bank (BNK1) may be configured to include a light-blocking material, and may prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0548] A first reflective electrode (RFE1) may be disposed on an exposed portion of a first anode electrode (AE1") and a side surface of a first bank (BNK1) adjacent thereto. A second reflective electrode (RFE2) may be disposed on an exposed portion of a cathode electrode (CE") and a side surface of a first bank (BNK1) adjacent thereto. A third reflective electrode (RFE3) may be disposed on an exposed portion of a floating electrode (FTE") and a side surface of a first bank (BNK1) adjacent thereto. The first to third reflective electrodes (RFE1, RFE2, RFE3) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1") may be improved. In the embodiments, the first to third reflective electrodes (RFE1, RFE2, RFE3) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0549] An overcoat layer (OCL) may be disposed within the first opening (OP1) of the first bank (BNK1) on the first to third reflective electrodes (RFE1, RFE2, RFE3) and the second passivation layer (PSV2). A first light-emitting element (LD1") may be disposed on the overcoat layer (OCL). The first light-emitting element (LD1") may be partially buried in the overcoat layer (OCL).

[0550] The overcoat layer (OCL) can fix the first light-emitting element (LD1") so that it does not move. The overcoat layer (OCL) can protect components disposed under the overcoat layer (OCL) from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) can include epoxy, but embodiments are not limited thereto.

[0551] The first light-emitting element (LD1") may include a first-first sub-light-emitting element (SLD1a"), a second-first sub-light-emitting element (SLD2a"), and a third-first sub-light-emitting element (SLD3a"). Each of the first-first sub-light-emitting element (SLD1a"), the second-first sub-light-emitting element (SLD2a"), and the third-first sub-light-emitting element (SLD3a") may include a light-emitting stack (EST") in which an auxiliary layer (34), a second semiconductor layer (32), an active layer (33), and a first semiconductor layer (31) are sequentially stacked, and first and second bonding electrodes (BDE1, BDE2). Here, the first and second bonding electrodes (BDE1, BDE2) may protrude in a direction away from the pixel circuit layer (PCL), and this first light-emitting element (LD1") may be referred to as a light-emitting element of a lateral chip type. Here, the description with reference to FIG. 28 may be substantially identically applied to the light-emitting element of the lateral chip type. Therefore, description of overlapping content may be omitted.

[0552] A third passivation layer (PSV3) may be disposed on the first to third reflective electrodes (RFE1, RFE2, RFE3), the first light-emitting element (LD1"), and the overcoat layer (OCL). The third passivation layer (PS3) may protect components disposed under the third passivation layer (PSV3) and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as any one of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0553] The third passivation layer (PSV3) may have second to ninth openings (OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9). The second opening (OP2) may expose a portion of the first reflective electrode (RFE1). The third opening (OP3) may expose a top surface of the first bonding electrode (BDE1) of the first-first sub-light-emitting element (SLD1a"). The fourth opening (OP4) may expose a top surface of the second bonding electrode (BDE2) of the first-first sub-light-emitting element (SLD1a"). The fifth opening (OP5) can expose the upper surface of the first bonding electrode (BDE1) of the 2-1 sub light-emitting element (SLD2a"). The sixth opening (OP6) can expose the upper surface of the second bonding electrode (BDE2) of the 2-1 sub light-emitting element (SLD2a"). The seventh opening (OP7) can expose the upper surface of the first bonding electrode (BDE1) of the 3-1 sub light-emitting element (SLD3a"). The eighth opening (OP8) can expose the upper surface of the second bonding electrode (BDE2) of the 3-1 light-emitting element (SLD3a"). The ninth opening (OP9) can expose a part of the second reflective electrode (RFE2).

[0554] A first transparent electrode (ITO1), a second transparent electrode (ITO2), a first-first connection electrode (UCE1a"), and a second-first connection electrode (UCE2a") can be arranged on the third passivation layer (PSV3).

[0555] The first transparent electrode (ITO1) can electrically connect the first reflective electrode (RFE1) exposed by the second opening (OP2) to the first bonding electrode (BDE1) of the first-first sub-light-emitting element (SLD1a") exposed by the third opening (OP3). Accordingly, the first bonding electrode (BDE1) of the first-first sub-light-emitting element (SLD1a") can be electrically connected to the first anode electrode (AE1") through the first transparent electrode (ITO1) and the first reflective electrode (RFE1).

[0556] The second transparent electrode (ITO2) can electrically connect the second reflective electrode (RFE2) exposed by the ninth opening (OP9) to the second bonding electrode (BDE2) of the 3-1 sub-light emitting element (SLD3a") exposed by the eighth opening (OP8). Accordingly, the second bonding electrode (BDE2) of the 3-1 sub-light emitting element (SLD3a") can be electrically connected to the cathode electrode (CE") through the second transparent electrode (ITO2) and the second reflective electrode (RFE2).

[0557] The first-first connection electrode (UCE1a") can electrically connect the second bonding electrode (BDE2) of the first-first sub-light-emitting element (SLD1a") exposed by the fourth opening (OP4) to the first bonding electrode (BDE1) of the second-first sub-light-emitting element (SLD2a") exposed by the fifth opening (OP5). Accordingly, the second bonding electrode (BDE2) of the first-first sub-light-emitting element (SLD1a") can be electrically connected to the first bonding electrode (BDE1) of the second-first sub-light-emitting element (SLD2a") via the first-first connection electrode (UCE1a").

[0558] The second-first connection electrode (UCE2a") can electrically connect the second bonding electrode (BDE2) of the second-first sub-light-emitting element (SLD2a") exposed by the sixth opening (OP6) to the first bonding electrode (BDE1) of the third-first sub-light-emitting element (SLD3a") exposed by the seventh opening (OP7). Accordingly, the second bonding electrode (BDE2) of the second-first sub-light-emitting element (SLD2a") can be electrically connected to the first bonding electrode (BDE1) of the third-first sub-light-emitting element (SLD3a") via the second-first connection electrode (UCE2a").

[0559] In this way, between the first anode electrode (AE1") and the cathode electrode (CE"), the first-first sub-light-emitting element (SLD1a"), the second-first sub-light-emitting element (SLD2a"), and the third-first sub-light-emitting element (SLD3a") can be connected in series to each other through the first-first connection electrode (UCE1a") and the second-first connection electrode (UCE2a").

[0560] In the embodiments, the first transparent electrode (ITO1), the second transparent electrode (ITO2), the first-first connection electrode (UCE1a"), and the second-first connection electrode (UCE2a") may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In the embodiments, the first transparent electrode (ITO1), the second transparent electrode (ITO2), the first-first connection electrode (UCE1a"), and the second-first connection electrode (UCE2a") may include at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and the like. However, the materials of the first transparent electrode (ITO1), the second transparent electrode (ITO2), the first-first connection electrode (UCE1a"), and the second-first connection electrode (UCE2a") are not limited thereto.

[0561] A capping layer (CPL) may be disposed on the third passivation layer (PSV3). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first and second transparent electrodes (ITO1, ITO2), the first-first connection electrode (UCE1a"), the second-first connection electrode (UCE2a"), the first light-emitting element (LD1"), etc., from external moisture and humidity, etc. within the scope and spirit of the present disclosure. The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto.

[0562] Above, the pixel circuit layer (PCL) and the display element layer (DPL) of the first sub-pixel (SP1") have been described. Each of the second and third sub-pixels (SP2", SP3") of FIG. 34 can also be configured similarly to the first sub-pixel (SP1"), unless otherwise described herein.

[0563] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive layer (LRL), and a color filter layer (CFL). The light functional layer (LFL) is described in the same manner as described with reference to FIG. 28. Therefore, redundant descriptions may be omitted.

[0564] Referring to FIG. 34 and FIG. 36, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0565] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 35. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1", SP2", SP3") may be provided, respectively. In the display element layer (DPL), first to third light-emitting elements (LD1", LD2", LD3") corresponding to the first to third sub-pixels (SP1", SP2", SP3") may be provided, respectively. The first to third light-emitting elements (LD1", LD2", LD3") may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1") may be connected between the cathode electrode (CE"), see FIG. 35) and a transistor (T_SP, see FIG. 35) included in the sub-pixel circuit of the first sub-pixel (SP1"). The second light-emitting element (LD2") may be connected between the cathode electrode (CE") and a transistor included in the sub-pixel circuit of the second sub-pixel (SP2"). The third light-emitting element (LD3") may be connected between the cathode electrode (CE") and a transistor included in the sub-pixel circuit of the third sub-pixel (SP3"). Hereinafter, overlapping descriptions may be omitted.

[0566] A light function layer (LFL) may be provided on the display element layer (DPL). The light function layer (LFL) is described in the same manner as described with reference to Fig. 29. Therefore, redundant description is omitted.

[0567] Figure 37 is a block diagram illustrating a display system according to one embodiment.

[0568] Referring to FIG. 37, the display system (1000) may include a processor (1100) and a display device (1200).

[0569] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), and the like, all within the scope and spirit of the present disclosure. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0570] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0571] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0572] Figures 38 to 41 are schematic perspective views illustrating application examples of the display system of Figure 37.

[0573] Referring to FIG. 38, the display system (1000) of FIG. 37 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0574] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0575] Referring to FIG. 39, the display system (1000) of FIG. 37 may be applied to an automotive display system (3000). Here, the automotive display system (3000) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0576] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0577] Referring to FIG. 40, the display system (1000) of FIG. 37 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0578] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0579] The frame (4100) may include a battery, a touch pad, a microphone, a camera, etc. The frame (4100) may include a projector that outputs light, a processor that controls light signals, etc.

[0580] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or other materials within the scope and spirit of the present disclosure.

[0581] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0582] Referring to FIG. 41, the display system (1000) of FIG. 37 can be applied to a head-mounted display device (5000).

[0583] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0584] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in a form within the spirit and scope of the present disclosure, such as a glasses frame form or a helmet form.

[0585] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0586] Although the present invention has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. A pixel circuit layer including a transistor; An anode electrode disposed on the pixel circuit layer and electrically connected to the transistor; A first lower connecting electrode, wherein the first lower connecting electrode and the anode electrode are arranged in the same layer, and the first lower connecting electrode is spaced apart from the anode electrode; A first upper connecting electrode electrically connected to the first lower connecting electrode and positioned above the anode electrode so as to face the anode electrode; A cathode electrode, wherein the cathode electrode and the first upper connecting electrode are arranged in the same layer, and the cathode electrode is spaced apart from the first upper connecting electrode; a first sub-light emitting element overlapping the anode electrode; and including a second sub-light emitting element overlapping the first lower electrode, A display device, wherein the first sub-light emitting element is electrically connected in series with the second sub-light emitting element between the anode electrode and the cathode electrode through the first lower connecting electrode and the first upper connecting electrode.

2. In paragraph 1, The first sub-light emitting element includes a plurality of first sub-light emitting elements, A display device in which the plurality of first sub-light emitting elements are electrically connected in parallel.

3. In paragraph 1, The second sub-light emitting element includes a plurality of second sub-light emitting elements, A display device in which the plurality of second sub-light emitting elements are electrically connected in parallel.

4. In paragraph 1, Each of the first sub-light emitting element and the second sub-light emitting element, a first semiconductor layer having a first polarity; and A display device comprising a second semiconductor layer having a second polarity different from the first polarity and disposed on the first semiconductor layer.

5. In paragraph 4, The first semiconductor layer of the first sub-light emitting element is electrically connected to the anode electrode, The second semiconductor layer of the first sub-light emitting element is electrically connected to the first upper connecting electrode, A display device, wherein the first semiconductor layer of the second sub-light emitting element is electrically connected to the first lower connecting electrode.

6. In paragraph 1, A second upper connecting electrode, wherein the second upper connecting electrode and the first upper connecting electrode are disposed on the same layer, the second upper connecting electrode is spaced apart from the cathode electrode and the first upper connecting electrode, and is disposed on the first lower connecting electrode so as to face the first lower connecting electrode; A second lower connecting electrode, wherein the second lower connecting electrode and the anode electrode are arranged in the same layer, the second lower connecting electrode is spaced apart from the anode electrode and the first lower connecting electrode and is electrically connected to the second upper connecting electrode; and A display device further comprising a third sub-light emitting element overlapping the second lower connecting electrode.

7. In paragraph 6, A display device wherein the second sub-light emitting element is electrically connected in series with the third sub-light emitting element through the second lower connecting electrode and the second upper connecting electrode between the first lower connecting electrode and the cathode electrode.

8. In paragraph 7, The third sub-light emitting element includes a plurality of third sub-light emitting elements, A display device in which the plurality of third sub-light emitting elements are electrically connected in parallel.

9. In paragraph 6, A third upper connecting electrode, wherein the third upper connecting electrode and the first upper connecting electrode are disposed on the same layer, the third upper connecting electrode is spaced apart from the cathode electrode, the first upper connecting electrode, and the second upper connecting electrode, and is disposed on the second lower connecting electrode so as to face the second lower connecting electrode; A third lower connecting electrode, wherein the third lower connecting electrode and the anode electrode are arranged in the same layer, the third lower connecting electrode is spaced apart from the anode electrode, the first lower connecting electrode, and the second lower connecting electrode, and is electrically connected to the third upper connecting electrode; and A display device further comprising a fourth sub-light emitting element overlapping the third lower connecting electrode.

10. In paragraph 9, A display device wherein the third sub-light emitting element is electrically connected in series with the fourth sub-light emitting element through the third lower connecting electrode and the third upper connecting electrode between the second lower connecting electrode and the cathode electrode.

11. Pixel circuit layer including a transistor; An anode electrode disposed on the pixel circuit layer and electrically connected to the transistor; A first connecting electrode spaced apart from the anode electrode, wherein the first connecting electrode and the anode electrode are arranged in the same layer; A cathode electrode spaced apart from the anode electrode and the first connecting electrode, wherein the cathode electrode and the anode electrode are arranged in the same layer; a first sub-light emitting element electrically connected between the anode electrode and the first connecting electrode; and A second sub-light emitting element electrically connected between the first connecting electrode and the cathode electrode is included, A display device, wherein the first sub-light emitting element is electrically connected in series with the second sub-light emitting element through the first connection electrode between the anode electrode and the cathode electrode.

12. In paragraph 11, The above first sub-light emitting element includes a plurality of first sub-light emitting elements, A display device in which the plurality of first sub-light emitting elements are electrically connected in parallel.

13. In paragraph 11, The above second sub-light emitting elements include a plurality of second sub-light emitting elements, A display device in which the plurality of second sub-light emitting elements are electrically connected in parallel.

14. In paragraph 11, Each of the first sub-light emitting element and the second sub-light emitting element, A first semiconductor layer having a first polarity; A second semiconductor layer having a second polarity different from the first polarity and disposed on the first semiconductor layer; A first bonding electrode electrically connected to the first semiconductor layer and protruding in a direction toward the pixel circuit layer; and A display device comprising a second bonding electrode electrically connected to the second semiconductor layer and protruding in the direction toward the pixel circuit layer.

15. In paragraph 14, The first bonding electrode of the first sub-light emitting element is electrically connected to the anode electrode, The second bonding electrode of the first sub-light emitting element is electrically connected to the first connection electrode, A display device, wherein the first bonding electrode of the second sub-light emitting element is electrically connected to the first connection electrode.

16. In paragraph 11, A second connecting electrode, wherein the second connecting electrode and the anode electrode are arranged in the same layer, the second connecting electrode is spaced apart from the anode electrode, the first connecting electrode, and the cathode electrode; and Further comprising a third sub-light emitting element electrically connected between the second connecting electrode and the cathode electrode, A display device wherein the second sub-light emitting element and the third sub-light emitting element are electrically connected in series through the second connection electrode between the first connection electrode and the cathode electrode.

17. In paragraph 16, The third sub-light emitting element includes a plurality of third sub-light emitting elements, A display device in which the plurality of third sub-light emitting elements are electrically connected in parallel.

18. Pixel circuit layer including a transistor; An anode electrode disposed on the pixel circuit layer and electrically connected to the transistor; A cathode electrode, wherein the cathode electrode and the anode electrode are arranged in the same layer, and the cathode electrode is spaced apart from the anode electrode; A first sub-light emitting element and a second sub-light emitting element electrically connected between the anode electrode and the cathode electrode; and A first connecting electrode disposed on the first sub-light emitting element and the second sub-light emitting element, the first connecting electrode electrically connecting the first sub-light emitting element and the second sub-light emitting element, A display device, wherein the first sub-light emitting element and the second sub-light emitting element are electrically connected in series through the first connection electrode between the anode electrode and the cathode electrode.

19. In paragraph 18, The above first sub-light emitting element includes a plurality of first sub-light emitting elements, A display device in which the plurality of first sub-light emitting elements are electrically connected in parallel.

20. In paragraph 18, The second sub-light emitting element includes a plurality of second sub-light emitting elements, A display device in which the plurality of second sub-light emitting elements are electrically connected in parallel.

21. In paragraph 11, Each of the first sub-light emitting element and the second sub-light emitting element, A first semiconductor layer having a first polarity; A second semiconductor layer having a second polarity different from the first polarity and disposed below the first semiconductor layer; A first bonding electrode electrically connected to the first semiconductor layer and protruding in a direction away from the pixel circuit layer; and A display device comprising a second bonding electrode electrically connected to the second semiconductor layer and protruding in the direction away from the pixel circuit layer.

22. In paragraph 21, The first bonding electrode of the first sub-light emitting element is electrically connected to the anode electrode, The second bonding electrode of the first sub-light emitting element is electrically connected to the first connection electrode, A display device, wherein the first bonding electrode of the second sub-light emitting element is electrically connected to the first connection electrode.

23. In paragraph 18, a third sub-light emitting element electrically connected between the first connecting electrode and the cathode electrode; and A second connecting electrode disposed on the second sub-light emitting element and the third sub-light emitting element, the second connecting electrode electrically connecting the second sub-light emitting element and the third sub-light emitting element, further comprising: A display device wherein the second sub-light emitting element and the third sub-light emitting element are electrically connected in series to each other through the second connection electrode between the first connection electrode and the cathode electrode.

24. In paragraph 23, The third sub-light emitting element includes a plurality of third sub-light emitting elements, A display device in which the plurality of third sub-light emitting elements are electrically connected in parallel with each other.

25. In paragraph 18, A display device further comprising a floating electrode disposed between the anode electrode and the cathode electrode.

26. In paragraph 25, A display device further comprising a reflective electrode covering at least a portion of the floating electrode.

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