Display device and manufacturing method therefor

Abstract

The display device according to the present invention comprises: a substrate; a pixel circuit layer located on the substrate; and a display element layer located on the pixel circuit layer, wherein the display element layer comprises: a first bank comprising a first opening; a first light emitting element disposed in the first opening and comprising a first bonding electrode and a second bonding electrode, wherein the first bonding electrode is electrically connected to one electrode of a first transistor located in the pixel circuit layer; a second bank located on the first bank and comprising a second opening that at least partially overlaps the first opening in the vertical direction; and a second light emitting element located in the second opening and comprising a third bonding electrode and a fourth bonding electrode, wherein the third bonding electrode is electrically connected to the second bonding electrode.

Description

Display device and manufacturing method thereof

[0001] The present invention relates to a display device and a method for manufacturing the same.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting display devices (OLEDs) is increasing.

[0003] Depending on the display device's usage environment, users may experience difficulty viewing images. For example, when using the display device outdoors, users may experience difficulty viewing images due to relatively strong external light.

[0004] The technical challenge to be solved is to provide a display device capable of exhibiting high brightness based on the same current and a method for manufacturing the same.

[0005] A display device according to one embodiment of the present invention comprises: a substrate; a pixel circuit layer positioned on the substrate; and a display element layer positioned on the pixel circuit layer, wherein the display element layer comprises: a first bank including a first opening; a first light-emitting element positioned within the first opening, including a first bonding electrode and a second bonding electrode, wherein the first bonding electrode is electrically connected to a first electrode of a first transistor positioned within the pixel circuit layer; a second bank positioned on the first bank, including a second opening at least partially overlapping the first opening in a vertical direction; and a second light-emitting element positioned within the second opening, including a third bonding electrode and a fourth bonding electrode, wherein the third bonding electrode is electrically connected to the second bonding electrode.

[0006] The display element layer may further include: a first anode electrode positioned below the first bank and electrically connected to one electrode of the first transistor; and a first reflective electrode positioned on the first anode electrode and the first bank and connecting the first bonding electrode and the first anode electrode.

[0007] The display element layer may further include: a first cathode electrode positioned below the first bank; and a second reflective electrode positioned on the first cathode electrode and the first bank, and connecting the second bonding electrode and the first cathode electrode.

[0008] The above display element layer may further include a second anode electrode connecting the second reflective electrode and the third bonding electrode.

[0009] The display element layer may further include: a common electrode commonly connected to a plurality of sub-pixel circuits; and a second cathode electrode electrically connecting the fourth bonding electrode and the common electrode.

[0010] The above display element layer may further include a common connection electrode positioned on the first bank and the common electrode and connected to the second cathode electrode.

[0011] The above common connection electrode may be spaced apart from the first reflective electrode.

[0012] The above common connection electrode can be commonly connected to the plurality of sub-pixel circuits.

[0013] The second cathode electrode may be commonly connected to the plurality of sub-pixel circuits.

[0014] The first light-emitting element may include an n-type semiconductor layer and a p-type semiconductor layer, the first bonding electrode may be connected to the p-type semiconductor layer of the first light-emitting element, and the second bonding electrode may be connected to the n-type semiconductor layer of the first light-emitting element.

[0015] The second light-emitting element may include an n-type semiconductor layer and a p-type semiconductor layer, the third bonding electrode may be connected to the p-type semiconductor layer of the second light-emitting element, and the fourth bonding electrode may be connected to the n-type semiconductor layer of the second light-emitting element.

[0016] A method for manufacturing a display device according to one embodiment of the present invention comprises the steps of: preparing a substrate; forming a pixel circuit layer on the substrate; and forming a display element layer on the pixel circuit layer, wherein the step of forming the display element layer comprises: forming a first bank including a first opening; positioning a first light-emitting element within the first opening; forming a second bank including a second opening on the first bank, the second opening at least partially overlapping the first opening in a vertical direction; and positioning a second light-emitting element within the second opening, wherein the first light-emitting element and the second light-emitting element are connected in series.

[0017] The step of forming the display element layer further includes: a step of forming a first contact hole in a first insulating layer of the pixel circuit layer; and a step of forming a first anode electrode, a first cathode electrode, and a common electrode on the first insulating layer, wherein the first anode electrode can overlap the first contact hole.

[0018] The step of forming the display element layer may further include the step of forming a first reflective electrode positioned on the first bank and the first anode electrode, a second reflective electrode positioned on the first bank and the first cathode electrode, and a common connection electrode positioned on the first bank and the common electrode.

[0019] The step of positioning the first light-emitting element may include: positioning the first bonding electrode of the first light-emitting element on the first reflective electrode, and positioning the second bonding electrode of the first light-emitting element on the second reflective electrode.

[0020] The step of forming the display element layer may further include: a step of forming a second insulating layer on the first light-emitting element; and a step of forming a second contact hole exposing the second reflective electrode and a third contact hole exposing the common connection electrode in the second insulating layer.

[0021] The step of forming the display element layer further includes the step of forming a second anode electrode and a second cathode electrode on the second insulating layer, wherein the second anode electrode overlaps the second contact hole, and the second cathode electrode overlaps the third contact hole.

[0022] The step of positioning the second light-emitting element may include: positioning the third bonding electrode of the second light-emitting element on the second anode electrode, and positioning the fourth bonding electrode of the second light-emitting element on the second cathode electrode.

[0023] The above second cathode electrode can be commonly connected to a plurality of sub-pixel circuits.

[0024] The upper common electrode can be commonly connected to the plurality of sub-pixel circuits.

[0025] The display device and its manufacturing method according to the present invention can exhibit high brightness based on the same current.

[0026] Figure 1 is a block diagram showing an embodiment of a display device.

[0027] FIG. 2 is a block diagram showing an embodiment of one of the sub-pixels of FIG. 1.

[0028] FIG. 3 is a plan view showing an embodiment of the display panel of FIG. 1.

[0029] FIG. 4 is a cross-sectional view showing an embodiment of the display panel of FIG. 3.

[0030] FIG. 5 is a cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0031] Fig. 6 is a cross-sectional view showing an embodiment of a sub-pixel.

[0032] FIGS. 7 to 13 are drawings for explaining a method of manufacturing a pixel including the sub-pixel of FIG. 6.

[0033] Fig. 14 is a cross-sectional view taken along line II-II' of Figs. 7 to 13.

[0034] Figures 15 to 21 are drawings showing other embodiments of the arrangement structure of light-emitting elements.

[0035] Figure 22 is a block diagram showing an embodiment of a display system.

[0036] Figures 23 to 26 are perspective views showing application examples of the display system of Figure 22.

[0037] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the following description only describes portions necessary for understanding the operation of the present invention, and that explanations of other portions will be omitted to avoid obscuring the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to provide a detailed explanation of the technical concepts of the present invention to a person skilled in the art to which the present invention pertains, to a degree that allows the technical concepts of the present invention to be easily implemented.

[0038] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element in between. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the present invention. Throughout the specification, when a part is said to "comprise" a certain element, this does not exclude other elements unless specifically stated to the contrary, but rather means that other elements can be included. "At least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes any combination of one or more of the configurations.

[0039] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0040] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features are now positioned "above" the other elements or features. Thus, in one embodiment, the term "below" may encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other orientations), and the spatially relative terms used herein are to be interpreted accordingly.

[0041] Various embodiments are described with reference to drawings illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0042] Figure 1 is a block diagram showing an embodiment of a display device.

[0043] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0044] The display panel (DP) includes sub-pixels (SP). The sub-pixels (SP) can be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) can be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0045] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0046] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. In this way, the pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included therein.

[0047] The gate driver (120) is connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0048] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and the other side of the display panel (DP) opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0049] The data driver (130) is connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, etc.

[0050] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0051] In embodiments, the gate driver (120) and data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0052] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) is configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from the outside of the display device (DD) and regulating the received voltage.

[0053] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In other embodiments, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0054] In addition, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). Although FIG. 1 illustrates that the pixel control lines (PXCL) are connected between the voltage generator (140) and the display panel (DP), embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the sub-pixels (SP) through the gate driver (120) and the pixel control lines (PXCL).

[0055] The controller (150) controls all operations of the display device (DD). The controller (150) receives input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0056] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by aligning the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0057] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0058] Fig. 2 is a block diagram showing an embodiment of one of the sub-pixels of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in an ith row (i is an integer greater than or equal to 1 and less than or equal to m) and a jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is exemplarily illustrated.

[0059] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC), a first light-emitting element (LD11), and a second light-emitting element (LD12).

[0060] A first light-emitting element (LD11) and a second light-emitting element (LD12) may be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first light-emitting element (LD11) and the second light-emitting element (LD12) may be connected in series. The first power supply voltage node (VDDN) is connected to one of the power supply lines (PL) of FIG. 1 and receives a first power supply voltage. The second power supply voltage node (VSSN) is connected to another of the power supply lines (PL) of FIG. 1 and receives a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0061] The first light-emitting element (LD11) is connected between the first anode electrode (AE11) and the first cathode electrode (CE11). The second light-emitting element (LD12) is connected between the second anode electrode (AE12) and the second cathode electrode (CE2). The first cathode electrode (CE11) and the second anode electrode (AE12) may be electrically the same node. The first anode electrode (AE11) may be connected to the first power voltage node (VDDN) through the sub-pixel circuit (SPC). For example, the first anode electrode (AE11) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The second cathode electrode (CE2) may be connected to the second power voltage node (VSSN). The first light-emitting element (LD11) and the second light-emitting element (LD12) are configured to emit light according to a current flowing from the first anode electrode (AE11) to the second cathode electrode (CE2).

[0062] The sub-pixel circuit (SPC) may be connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) controls the first light-emitting element (LD11) and the second light-emitting element (LD12) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the first light-emitting element (LD11) and the second light-emitting element (LD12) in response to pixel control signals received through the pixel control lines (PXCL).

[0063] For these operations, the sub-pixel circuit (SPC) may include circuit elements, such as transistors and at least one capacitor.

[0064] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, and the like.

[0065] FIG. 3 is a plan view showing an embodiment of the display panel of FIG. 1.

[0066] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) displays an image through the display area (DA). The non-display area (NDA) is arranged around the display area (DA).

[0067] A display panel (DP) includes sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0068] Among a plurality of sub-pixels (SP), two or more sub-pixels can constitute one pixel (PXL). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1 to SP3), but embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1 to SP3).

[0069] Each of the first to third sub-pixels (SP1 to SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for the sake of clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) generates blue color light.

[0070] Each of the first to third sub-pixels (SP1 to SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate red light, green light, and blue light, respectively.

[0071] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0072] Components for controlling sub-pixels (SP) may be placed in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be placed in the non-display area (NDA).

[0073] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0074] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have a closed loop shape including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, circle, semicircle, or ellipse.

[0075] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0076] FIG. 4 is a cross-sectional view showing an embodiment of the display panel of FIG. 3.

[0077] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0078] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As yet another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0079] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0080] A pixel circuit layer (PCL) is arranged on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns arranged between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0081] The circuit elements of the pixel circuit layer (PCL) may include a sub-pixel circuit (SPC, see FIG. 2) of each of the sub-pixels (SP) of FIG. 3. In other words, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0082] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0083] A display element layer (DPL) is arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0084] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0085] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or color). In embodiments, the color filter layer may be omitted.

[0086] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0087] FIG. 5 is a cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0088] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) are configured similarly to the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4, respectively. Hereinafter, redundant descriptions are omitted.

[0089] An input sensing layer (ISL) can detect user input on the upper surface (or display surface) of a display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting external objects, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0090] Fig. 6 is a cross-sectional view showing an embodiment of a sub-pixel.

[0091] Referring to FIG. 6, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0092] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0093] As described with reference to FIG. 2, each of the first to third sub-pixels (SP1 to SP3) may include a sub-pixel circuit (SPC, see FIG. 2) including transistors and one or more capacitors. The semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). In addition, the conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1.

[0094] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0095] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may include polyimide.

[0096] A first transistor (T_SP1) may be placed on the buffer layer (BFL). The first transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). For example, the first transistor (T_SP1) may be understood as a transistor connected to the first anode electrode (AE11) among the transistors of the sub-pixel circuit (SPC).

[0097] A first transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a drain electrode, and the second terminal (ET2) may be a source electrode.

[0098] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the first transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. For example, a p-type impurity or an n-type impurity may be used as the impurity, but the embodiments are not limited thereto.

[0099] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0100] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor pattern (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers including an inorganic material. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0101] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL) to cover the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for forming the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0102] A gate electrode (GE) is disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0103] The first and second terminals (ET1, ET2) are disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) can include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0104] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), the embodiments are not limited thereto. In the embodiments, the first terminal (ET1) may be a first contact region adjacent to one side of the channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the light emitting element (LD) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0105] In embodiments, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, the embodiments are not limited thereto. For example, the first transistor (T_SP1) may also be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit (SPC) of the first sub-pixel (SP1) may include transistors of different types. For example, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and the other transistors of the first sub-pixel (SP1) may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the first transistor (T_SP1) is formed.

[0106] In the embodiments, the first transistor (T_SP1) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the first transistor (T_SP1) may be a transistor having a bottom gate structure. In addition, the structure of the first transistor (T_SP1) may be changed in various ways.

[0107] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0108] A first passivation layer (PSV1) may be disposed on the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed thereunder and may provide a flat upper surface.

[0109] A connection pattern (CP1) may be arranged on a first passivation layer (PSV1). The connection pattern (CP1) may penetrate the first passivation layer (PSV1) and be connected to a first terminal (ET1) of a transistor (T_SP1). The connection pattern (CP1) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0110] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0111] A second passivation layer (PSV2) is disposed on the connection pattern (CP1) and the first passivation layer (PSV1). The second passivation layer (PSV2) protects components disposed thereunder and can provide a flat upper surface.

[0112] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0113] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0114] A display element layer (DPL) may be disposed on the second passivation layer (PSV2). The display element layer (DPL) may include a first anode electrode (AE11), a first cathode electrode (CE11), a common electrode (VSSE), a first bank (BNK1), first and second reflective electrodes (RFE11, RFE12), a common connection electrode (VSSCE), a first light-emitting element (LD11), a first overcoat layer (OCL1), a third passivation layer (PSV3), a second anode electrode (AE12), a second cathode electrode (CE2), a first capping layer (CPL1), a second bank (BNK2), third and fourth reflective electrodes (RFE13, RFE14), a second overcoat layer (OCL2), a fourth passivation layer (PSV4), and a second capping layer (CPL2).

[0115] On the pixel circuit layer (PCL), a first anode electrode (AE11), a first cathode electrode (CE11), and a common electrode (VSSE) are arranged.

[0116] The first anode electrode (AE11) may be connected to the connection electrode (CP1) through a contact hole (PSV2H) penetrating the second passivation layer (PSV2). The first anode electrode (AE11) may be positioned to overlap the contact hole (PSV2H). The first anode electrode (AE11) may be electrically connected to the first terminal (ET1) of the first transistor (T_SP1). In an embodiment where the first passivation layer (PSV1) is unnecessary, the first anode electrode (AE11) may be directly connected to the first terminal (ET1) of the first transistor (T_SP1).

[0117] The first cathode electrode (CE11) may be spaced apart from the first anode electrode (AE11) in the second direction (DR2). The first cathode electrode (CE11) may be connected to a corresponding sub-pixel circuit (SPC).

[0118] The common electrode (VSSE) may be spaced apart from the first anode electrode (AE11) in the opposite direction of the second direction (DR2). The common electrode (VSSE) may be commonly connected to a plurality of sub-pixel circuits (SPC). The common electrode (VSSE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the common electrode (VSSE).

[0119] A first bank (BNK1) may be disposed on a first anode electrode (AE11), a first cathode electrode (CE11), and a common electrode (VSSE). The first bank (BNK1) may have a first opening (OP1) exposing a portion of the first anode electrode (AE11) and a portion of the first cathode electrode (CE11). In addition, the first bank (BNK1) may further have an opening exposing a portion of the common electrode (VSSE). A first light-emitting element (LD11) may be disposed within the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines an area in which the first light-emitting element (LD11) is positioned.

[0120] The first bank (BNK1) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0121] A first reflective electrode (RFE11) may be disposed on an exposed portion of the first anode electrode (AE11) and a side surface of the first bank (BNK1) adjacent thereto. The first reflective electrode (RFE11) may be positioned on the first anode electrode (AE11) and the first bank (BNK1) and may connect the first bonding electrode (BDE1) and the first anode electrode (AE11). A second reflective electrode (RFE12) may be disposed on an exposed portion of the first cathode electrode (CE11) and a side surface of the first bank (BNK1) adjacent thereto. The second reflective electrode (RFE12) may be positioned on the first cathode electrode (CE11) and the first bank (BNK1) and may connect the second bonding electrode (BDE2) and the first cathode electrode (CE11). A common connection electrode (VSSCE) is positioned on the first bank (BNK1) and the common electrode (VSSE), and may be connected to a second cathode electrode (CE2). The common connection electrode (VSSCE) may be commonly connected to a plurality of sub-pixel circuits.

[0122] The first and second reflective electrodes (RFE1, RFE2) and the common connection electrode (VSSCE) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD11) may be improved. In embodiments, the first and second reflective electrodes (RFE11, RFE12) and the common connection electrode (VSSCE) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0123] The first light-emitting element (LD11) is electrically connected to the first anode electrode (AE11) via the first reflective electrode (RFE11). The first light-emitting element (LD11) is electrically connected to the first cathode electrode (CE11) via the second reflective electrode (RFE12). The first light-emitting element (LD11) can be bonded to the first and second reflective electrodes (RFE11, RFE12).

[0124] The first light-emitting element (LD11) may include a first semiconductor layer (11), an active layer (12), a second semiconductor layer (13), and an auxiliary layer (15). The first light-emitting element (LD11) includes a light-emitting laminate in which the auxiliary layer (15), the first semiconductor layer (11), the active layer (12), and the second semiconductor layer (13) are sequentially laminated.

[0125] The first light-emitting element (LD11) includes first and second bonding electrodes (BDE1, BDE2) facing in the same direction (for example, in a direction opposite to the third direction (DR3)). The first bonding electrode (BDE1) may be connected to the second semiconductor layer (13). The second bonding electrode (BDE2) may be connected to the first semiconductor layer (11) exposed by etching the second semiconductor layer (13) and the active layer (12). The first light-emitting element (LD11) may be a flip chip type light-emitting element.

[0126] The first semiconductor layer (11) is configured to provide electrons to the active layer (12). The first semiconductor layer (11) may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer (11) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer (11) is not limited thereto, and various other materials may also constitute the first semiconductor layer (11). In one embodiment of the present invention, the first semiconductor layer (11) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). According to an embodiment, the first semiconductor layer (11) may form an n-type semiconductor layer together with the auxiliary layer (15).

[0127] The active layer (12) is disposed on the first semiconductor layer (11) and may be a region where electrons and holes recombine. As electrons and holes recombine in the active layer (12), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The active layer (12) may be formed in a single or multiple quantum well structure. When the active layer (12) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer may be repeatedly stacked to form the active layer (12). However, embodiments of the active layer (12) are not limited thereto.

[0128] The second semiconductor layer (13) is disposed on the active layer (12) and provides holes to the active layer (12). The second semiconductor layer (13) may include a semiconductor layer of a different type from the first semiconductor layer (11). For example, the second semiconductor layer (13) may include at least one p-type semiconductor layer. For example, the second semiconductor layer (13) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the second semiconductor layer (13) is not limited thereto, and various other materials may constituting the second semiconductor layer (13). In one embodiment of the present invention, the second semiconductor layer (13) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0129] The auxiliary layer (15) may include a gallium nitride (GaN) semiconductor material that is not doped with impurities, and may form an n-type semiconductor layer together with the first semiconductor layer (11).

[0130] The first bonding electrode (BDE1) may be electrically connected to the second semiconductor layer (13). The second bonding electrode (BDE2) may be electrically connected to the first semiconductor layer (11). The first and second bonding electrodes (BDE1, BDE2) may include a eutectic metal.

[0131] The first light-emitting element (LD1) may further include an insulating film (16) covering an outer surface of the light-emitting stack. The insulating film (16) may prevent an electrical short circuit that may occur when the active layer (12) comes into contact with a conductive material other than the first and second semiconductor layers (11, 13). The insulating film (16) may include a transparent insulating material. The insulating film (16) is configured to expose the lower surfaces of the first and second bonding electrodes (BDE1, BDE2).

[0132] The lower surface of the first bonding electrode (BDE1) contacts the first reflective electrode (RFE11). Accordingly, the first bonding electrode (BDE1) is electrically connected to the first anode electrode (AE11) through the first reflective electrode (RFE11). That is, the first bonding electrode (BDE1) can be electrically connected to the first terminal (ET1) of the first transistor (T_SP1) located in the pixel circuit layer (PCL). The lower surface of the second bonding electrode (BDE2) contacts the second reflective electrode (RFE12). Accordingly, the second bonding electrode (BDE2) is electrically connected to the first cathode electrode (CE11) through the second reflective electrode (RFE12).

[0133] A first overcoat layer (OCL1) may be disposed within a first opening (OP1) in which first and second reflective electrodes (RFE11, RFE12) and a first light-emitting element (LD11) are disposed. The first overcoat layer (OCL1) may fix the first light-emitting element (LD11) bonded to the first and second reflective electrodes (RFE11, RFE12) so as not to move. In addition, the first overcoat layer (OCL1) may protect components disposed thereunder from foreign substances such as dust and moisture. For example, the first overcoat layer (OCL1) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the first overcoat layer (OCL1) may include epoxy, but embodiments are not limited thereto.

[0134] A third passivation layer (PSV3) may be disposed on the first bank (BNK1), the first overcoat layer (OCL1), and the first light-emitting element (LD11). The third passivation layer (PSV3) may protect components disposed thereunder and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0135] Contact holes (PSV3H1, PSVH2) may be formed in the third passivation layer (PSV3). The contact hole (PSV3H1) may expose the second reflective electrode (RFE12). The contact hole (PSV3H2) may expose the common connection electrode (VSSCE).

[0136] A second anode electrode (AE12) and a second cathode electrode (CE2) may be disposed on a third passivation layer (PSV3). The second anode electrode (AE12) may be disposed to overlap a contact hole (PSV3H1) and may contact a second reflective electrode (RFE12). The second cathode electrode (CE2) may be disposed to overlap a contact hole (PSV3H2) and may contact a common connection electrode (VSSCE). The second cathode electrode (CE2) may be commonly connected to a plurality of sub-pixel circuits. For example, the second anode electrode (AE12) and the second cathode electrode (CE2) may be formed of a transparent conductor such as ITO, IZO, ZnO, or ITZO. In another embodiment, the second anode electrode (AE12) and the second cathode electrode (CE2) may be formed of an opaque conductor. For example, the second anode electrode (AE12) and the second cathode electrode (CE2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0137] The first capping layer (CPL1) is disposed on the third passivation layer (PSV3), the second anode electrode (AE12), and the second cathode electrode (CE2). The first capping layer (CPL1) can protect components under the first capping layer (CPL1) from external moisture and humidity. The first capping layer (CPL1) can include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the first capping layer (CPL1) is not limited thereto.

[0138] A second bank (BNK2) is disposed on the first capping layer (CPL1). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have a second opening (OP2) that at least partially overlaps the first opening (OP1).

[0139] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. The second bank (BNK2) may be configured with the same or similar material as the first bank (BNK1).

[0140] A third reflective electrode (RFE13) may be disposed on the exposed portion of the first capping layer (CPL1) through the second opening (OP2) and on the side surface of the second bank (BNK2) adjacent thereto. A fourth reflective electrode (RFE14) may be disposed on the exposed portion of the first capping layer (CPL1) through the second opening (OP2) and on the side surface of the second bank (BNK2) adjacent thereto. The third and fourth reflective electrodes (RFE13, RFE14) may be formed of the same or similar material as the first and second reflective electrodes (RFE11, RFE12). Accordingly, the light emission efficiency of the second light-emitting element (LD12) may be improved.

[0141] The third and fourth reflective electrodes (RFE13, RFE14) may not cover the second anode electrode (AE12) and the second cathode electrode (CE2) exposed to the second opening (OP2). In another embodiment, the third and fourth reflective electrodes (RFE13, RFE14) may only minimally cover the second anode electrode (AE12) and the second cathode electrode (CE2) exposed to the second opening (OP2). Therefore, it is possible to minimize blocking of light emitted from the first light-emitting diode (LD11) by the third and fourth reflective electrodes (RFE13, RFE14).

[0142] The second light-emitting element (LD12) may be positioned within the second opening (OP2). The second light-emitting element (LD12) may have the same or similar configuration as the first light-emitting element (LD11). For example, the third bonding electrode (BDE3) of the second light-emitting element (LD12) may correspond to the first bonding electrode (BDE1) of the first light-emitting element (LD11). In addition, the fourth bonding electrode (BDE4) of the second light-emitting element (LD12) may correspond to the second bonding electrode (BDE2) of the first light-emitting element (LD11). In the description of the second light-emitting element (LD12), any description that overlaps with the description of the first light-emitting element (LD11) will be omitted.

[0143] The third bonding electrode (BDE3) of the second light-emitting element (LD12) may be connected to the second anode electrode (AE12). The third bonding electrode (BDE3) may be electrically connected to the second bonding electrode (BDE2). For example, the third bonding electrode (BDE3) may be connected to the second bonding electrode (BDE2) via the second anode electrode (AE12) and the second reflective electrode (REF12).

[0144] The fourth bonding electrode (BDE4) of the second light-emitting element (LD12) may be connected to the second cathode electrode (CE2). The fourth bonding electrode (BDE4) may be electrically connected to the common electrode (VSSE). For example, the fourth bonding electrode (BDE4) may be connected to the common electrode (VSSE) via the second cathode electrode (CE2) and the common connection electrode (VSSCE).

[0145] A second overcoat layer (OCL2) may be disposed within the second opening (OP2) in which the third and fourth reflective electrodes (RFE13, RFE14) and the second light-emitting element (LD12) are disposed. The second overcoat layer (OCL2) may fix the second light-emitting element (LD12) bonded to the second anode electrode (AE12) and the second cathode electrode (CE2) so as not to move. In addition, the second overcoat layer (OCL2) may protect components disposed thereunder from foreign substances such as dust and moisture. For example, the second overcoat layer (OCL2) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the second overcoat layer (OCL2) may include epoxy, but embodiments are not limited thereto.

[0146] A fourth passivation layer (PSV4) may be disposed on the second bank (BNK2), the second overcoat layer (OCL2), and the second light-emitting element (LD12). The fourth passivation layer (PSV4) may protect components disposed thereunder and provide a flat upper surface. The fourth passivation layer (PSV4) may include the same material as any one of the first to third passivation layers (PSV1, PSV2, PSV3), but embodiments are not limited thereto.

[0147] In some embodiments, contact holes or trenches may be formed in the fourth passivation layer (PSV4). The contact holes or trenches may expose portions of the second bank (BNK2). In such cases, the light-blocking materials of the third bank (BNK3) that fill the contact holes or trenches may more effectively prevent light mixing between adjacent sub-pixels.

[0148] In embodiments, the fourth passivation layer (PSV4) may not be disposed on the upper portion of the second light-emitting element (LD12). The upper portion of the second light-emitting element (LD12) may protrude into the light-functional layer (LFL). The second light-emitting element (LD12) may be at least partially positioned within the third opening (OP3) of the third bank (BNK3). For example, the height of the upper portion of the second light-emitting element (LD12) from the substrate (SUB) may be higher than the lowermost portion of the reflective layer (RFL). Accordingly, light emitted from the second light-emitting element (LD12) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0149] The second capping layer (CPL2) is disposed on the fourth passivation layer (PSV4). The second capping layer (CPL2) can protect components under the second capping layer (CPL2) from external moisture and humidity. In embodiments, the second capping layer (CPL2) may not be disposed on the second light-emitting element (LD12). In other embodiments, the second capping layer (CPL2) may entirely cover the second light-emitting element (LD12) and the fourth passivation layer (PSV4). The second capping layer (CPL2) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the second capping layer (CPL2) is not limited thereto.

[0150] The pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1) have been described above. Each of the second and third sub-pixels (SP2, SP3) described below can also be configured similarly to the first sub-pixel (SP1), unless otherwise described herein (see FIGS. 7 to 14).

[0151] A light functional layer (LFL) is disposed on the second capping layer (CPL2). The light functional layer (LFL) may include a third bank (BNK3), a reflective layer (RFL), a fifth passivation layer (PSV5), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0152] A third bank (BNK3) is disposed on the second capping layer (CPL2). The third bank (BNK3) may overlap the second bank (BNK2). The third bank (BNK3) may have a third opening (OP3) that at least partially overlaps the second opening (OP2).

[0153] The third bank (BNK3) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the third bank (BNK3) may include an organic material. For example, the third bank (BNK3) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0154] A reflective layer (RFL) may be disposed on side surfaces of the third bank (BNK3) adjacent to the third opening (OP3). The reflective layer (RFL) is configured to reflect incident light, thereby improving light emission efficiency. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto. According to an embodiment, the reflective layer (RFL) may also cover the second capping layer (CPL2) exposed through the third opening (OP3).

[0155] A fifth passivation layer (PSV5) is disposed within a third opening (OP3) on the second capping layer (CPL2) or the reflective layer (RFL). The fifth passivation layer (PSV5) protects components disposed thereunder and can provide a flat upper surface. The fifth passivation layer (PSV5) may include the same material as any one of the first to fourth passivation layers (PSV1 to PSV4), but embodiments are not limited thereto.

[0156] On the fifth passivation layer (PSV5), a first light conversion pattern (CCP1) may be arranged within the third opening (OP3). In some embodiments, the fifth passivation layer (PSV5) may not cover the second light-emitting element (LD12). Accordingly, the light emission efficiency of the second light-emitting element (LD12) may be increased. In some embodiments, the height of the upper portion of the fifth passivation layer (PSV5) may be the same as the height of the upper portion of the second light-emitting element (LD12).

[0157] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. Additionally, the color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0158] The first sub-pixel (SP1) may be a red sub-pixel. When the first light-emitting element (LD1) emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1) emits red light, the first light conversion pattern (CCP1) may include scattering particles. In this way, the particles included in the first light-conversion pattern (CCP1) may be variously changed depending on the first light-emitting element (LD1).

[0159] A low-refractive-index layer (LRL) may be disposed on the third bank (BNK3), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1) and the first color filter (CF1). The low-refractive-index layer (LRL) is configured to refract or totally reflect light depending on the incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0160] A color filter layer (CFL) may be disposed on a low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) overlaps the first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0161] According to the present embodiment, two light-emitting elements (LD11, LD12) can be connected in series to one sub-pixel circuit (SPC). Accordingly, the display device (DD) can exhibit high brightness based on the same current. That is, a relatively low current may be required to exhibit the same brightness. This can bring about the additional effect of reducing power consumption and heat generation. In addition, when a PWM circuit is applied to the sub-pixel circuit (SPC), the duty ratio can be increased, which can be advantageous for low-grayscale expression.

[0162] In addition, the light-emitting elements (LD11, LD12) connected in series can be stacked in a vertical direction (e.g., in the third direction (DR3)) to save space on a plane. Accordingly, a display area (DA) can be configured with a high resolution while minimizing dead space.

[0163] Although this embodiment uses two stacked and serially connected light emitting elements (LD11, LD12) as an example, in other embodiments the display device (DD) may include three or more stacked and serially connected light emitting elements.

[0164] FIGS. 7 to 13 are drawings for explaining a method of manufacturing a pixel including the sub-pixel of FIG. 6.

[0165] Referring to FIGS. 7 to 13, a pixel (PXL) may include first to third sub-pixels (SP1 to SP3). FIG. 6 is a cross-sectional view taken along line II' crossing the first sub-pixel (SP1).

[0166] The first to third sub-pixels (SP1 to SP3) may be arranged in the first direction (DR1). However, the arrangement of the pixels (PXL) is not limited thereto and may vary depending on the embodiments. For example, the first to third sub-pixels (SP1 to SP3) may be arranged in a zigzag pattern.

[0167] Referring to FIG. 7, contact holes (PSV2H, ...) can be formed in the second passivation layer (PSV2) of the pixel circuit layer (PCL). Thereafter, first anode electrodes (AE11, AE21, AE31), first cathode electrodes (CE11, CE21, CE31), and a common electrode (VSSE) can be formed on the second passivation layer (PSV2).

[0168] The first anode electrodes (AE11, AE21, AE31) may be positioned to overlap with the corresponding contact holes (PSV2H, ...). Accordingly, the first anode electrode (AE11) may be connected to the sub-pixel circuit (SPC) of the first sub-pixel (SP1). Similarly, the first anode electrode (AE21) may be connected to the sub-pixel circuit (SPC) of the second sub-pixel (SP2). The first anode electrode (AE31) may be connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0169] The first cathode electrodes (CE11, CE21, CE31) may be positioned in a second direction (DR2) from the corresponding first anode electrodes (AE11, AE21, AE31). The common electrode (VSSE) may be positioned in an opposite direction in the second direction (DR2) from the first anode electrodes (AE11, AE21, AE31).

[0170] Referring to FIG. 8, a first bank (BNK1) including first openings (OP1, ...) may be formed. The first openings (OP1, ...) may be formed one by one for each sub-pixel (SP1 to SP3). The first openings (OP1, ...) may expose a portion of the corresponding first cathode electrodes (CE11, CE21, CE31) and a portion of the corresponding first anode electrodes (AE11, AE21, AE31). The first bank (BNK1) may further include openings exposing a portion of the common electrode (VSSE).

[0171] Referring to FIG. 9, first reflective electrodes (RFE11, RFE21, RFE31), second reflective electrodes (RFE12, RFE22, RFE32), and a common connection electrode (VSSCE) may be formed. The first reflective electrodes (RFE11, RFE21, RFE31) may be positioned on the first bank (BNK1) and corresponding first anode electrodes (AE11, AE21, AE31). The second reflective electrodes (RFE12, RFE22, RFE32) may be positioned on the first bank (BNK1) and corresponding first cathode electrodes (CE11, CE21, CE31). The common connection electrode (VSSCE) may be positioned on the first bank (BNK1) and the common electrode (VSSE).

[0172] Referring to FIG. 10, the first light-emitting elements (LD11, LD21, LD31) can be positioned within the corresponding first openings (OP1, ...). For example, the first bonding electrode (BDE1) of the first light-emitting element (LD11) of the first sub-pixel (SP1) can be positioned on the first reflective electrode (RFE11), and the second bonding electrode (BDE2) of the first light-emitting element (LD11) can be positioned on the second reflective electrode (RFE12). The first light-emitting element (LD21) of the second sub-pixel (SP2) and the first light-emitting element (LD31) of the third sub-pixel (SP3) can also be positioned in the same manner.

[0173] The first light-emitting elements (LD11, LD21, LD31) may be inorganic light-emitting diodes containing inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0174] Referring to Fig. 11, a third passivation layer (PSV3) can be formed on the first light-emitting elements (LD11, LD21, LD31). In addition, contact holes (PSV3H1, ...) exposing the second reflective electrodes (RFE12, RFE22, RFE32) and contact holes (PSV3H2, ...) exposing the common connection electrode (VSSCE) can be formed in the third passivation layer (PSV3).

[0175] Next, second anode electrodes (AE12, AE22, AE32) and a second cathode electrode (CE2) can be formed on the third passivation layer (PSV3). The second anode electrodes (AE12, AE22, AE32) can be positioned to overlap with the contact holes (PSV3H1, ...). The second cathode electrode (CE2) can be positioned to overlap with the contact holes (PSV3H2, ...).

[0176] Referring to FIG. 12, a first capping layer (CPL1) may be formed, and a second bank (BNK2) may be formed on the first capping layer (CPL1). The second bank (BNK2) may include second openings (OP2, ...). The second openings (OP2, ...) may be formed one for each sub-pixel (SP1 to SP3). The second openings (OP2, ...) may expose a portion of the corresponding second anode electrodes (AE12, AE22, AE32) and a portion of the second cathode electrode (CE2).

[0177] Referring to FIG. 13, third reflective electrodes (RFE13, ...) and fourth reflective electrodes (RFE14, ...) can be formed on the second bank (BNK2).

[0178] Thereafter, the second light-emitting elements (LD12, LD22, LD32) can be positioned in the second openings (OP2, ...) of the second bank (BNK2). For example, the third bonding electrode (BDE3) of the second light-emitting element (LD12) of the first sub-pixel (SP1) can be positioned on the second anode electrode (AE12), and the fourth bonding electrode (BDE4) of the second light-emitting element (LD12) can be positioned on the second cathode electrode (CE2). The second light-emitting element (LD22) of the second sub-pixel (SP2) and the second light-emitting element (LD32) of the third sub-pixel (SP3) can also be positioned in the same manner.

[0179] Accordingly, the first light-emitting elements (LD11, LD21, LD31) and the corresponding second light-emitting elements (LD12, LD22, LD32) can be connected in series. The second light-emitting elements (LD12, LD22, LD32) can be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes can be used.

[0180] Fig. 14 is a cross-sectional view taken along line II-II' of Figs. 7 to 13.

[0181] Referring to Fig. 14, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) may be sequentially provided on a substrate (SUB). In describing Fig. 14, description of content overlapping with Fig. 6 will be omitted.

[0182] The third bank (BNK3) has third openings (OP3, ...). It can be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1 to SP3) are defined by the third bank (BNK3). The overlapping area of ​​the third bank (BNK3) may correspond to the non-light-emitting area (NEMA). The overlapping area of ​​the third openings (OP3, ...) of the third bank (BNK3) may correspond to the light-emitting area (EMA) of the first to third sub-pixels (SP1 to SP3).

[0183] On the fifth passivation layer (PSV5), first and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) may be arranged in third openings (OP3, ...). In embodiments, the first light emitting elements (LD11, LD21, LD31) and the second light emitting elements (LD12, LD22, LD32) may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light emission efficiency. Accordingly, the first to third sub-pixels (SP1 to SP3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0184] In embodiments, the light emitting elements (LD11, LD12) of the first sub-pixel (SP1) may be configured to emit red light. At this time, the light emitting elements (LD21, LD22) of the second sub-pixel (SP2) may be configured to emit green light. The light emitting elements (LD31, LD32) of the third sub-pixel (SP3) may be configured to emit blue light. In this case, each of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the light emitting elements.

[0185] In embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0186] A low-refractive-index layer (LRL) may be disposed on the third bank (BNK3), the reflective layer (RFL), the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3).

[0187] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1 to CF3) and light blocking patterns (LBP).

[0188] Each of the first to third color filters (CF1 to CF3) can selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1 to CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, embodiments are not limited thereto, and the first to third color filters (CF1 to CF3) may have a refractive index lower than or equal to that of the low-refractive-index layer (LRL).

[0189] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1 to CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1 to SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0190] In embodiments, the light blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1 to CF3) overlap. For example, each of the light blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1 to CF3). As another example, the light blocking pattern between the first and second color filters (CF1, CF2) among the light blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light blocking pattern between the second and third color filters (CF2, CF3) among the light blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1 to CF3) can extend into the non-emission area (NEMA) to form light blocking patterns (LBP).

[0191] Figures 15 to 21 are drawings showing other embodiments of the arrangement structure of light-emitting elements.

[0192] Referring to FIGS. 15 to 21, the first light-emitting element (LD1) may include a first bonding electrode (BDE1p) connected to a p-type semiconductor layer and a second bonding electrode (BDE1n) connected to an n-type semiconductor layer. The second light-emitting element (LD2) may include a third bonding electrode (BDE2p) connected to the p-type semiconductor layer and a fourth bonding electrode (BDE2n) connected to the n-type semiconductor layer. The second light-emitting element (LD2) may be positioned in the third direction (DR3) of the first light-emitting element (LD1). That is, the second light-emitting element (LD2) may be stacked on the first light-emitting element (LD1).

[0193] Referring to FIG. 15, unlike the case of FIG. 6, an embodiment is illustrated in which the first bonding electrode (BDE1p) is positioned in the second direction (DR2) from the second bonding electrode (BDE1n). At this time, the third bonding electrode (BDE2p) may be positioned in the opposite direction of the second direction (DR2) from the fourth bonding electrode (BDE2n). The current path (LDC) indicates the direction in which current flows, and it can be confirmed that the first light-emitting element (LD1) and the second light-emitting element (LD2) are connected in series.

[0194] Referring to Fig. 16, the second light-emitting element (LD2) may be arranged in a flipped manner relative to Fig. 15. Referring to Fig. 17, the first light-emitting element (LD1) may be arranged in a flipped manner relative to Fig. 15. Referring to Fig. 18, the first light-emitting element (LD1) and the second light-emitting element (LD2) may be arranged in a flipped manner relative to Fig. 15.

[0195] Referring to FIG. 19, a part of the first light-emitting element (LD1) and a part of the second light-emitting element (LD2) may overlap with respect to the third direction (DR3). For example, the second bonding electrode (BDE1n) of the first light-emitting element (LD1) and the fourth bonding electrode (BDE2n) of the second light-emitting element (LD2) may overlap. At this time, referring to FIG. 20, in the planar direction (the first direction (DR1) and the second direction (DR2)), the second light-emitting element (LD2) may be tilted with respect to the first light-emitting element (LD1). For example, a virtual line connecting the first bonding electrode (BDE1p) and the second bonding electrode (BDE1n) of the first light-emitting element (LD1) and a virtual line connecting the third bonding electrode (BDE2p) and the fourth bonding electrode (BDE2n) of the second light-emitting element (LD2) may not be parallel. According to this embodiment, it can be helpful to secure free space between elements.

[0196] Referring to Fig. 21, the first light-emitting element (LD1) and the second light-emitting element (LD2) may be connected in parallel. In this case, even if a defect occurs in either the first light-emitting element (LD1) or the second light-emitting element (LD2), the corresponding sub-pixel can display an image with the remaining normal light-emitting element.

[0197] Figure 22 is a block diagram showing an embodiment of a display system.

[0198] Referring to FIG. 22, the display system (1000) may include a processor (1100) and a display device (1200).

[0199] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0200] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0201] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0202] Figures 23 to 26 are perspective views showing application examples of the display system of Figure 22.

[0203] Referring to FIG. 23, the display system (1000) of FIG. 22 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0204] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0205] Referring to FIG. 24, the display system (1000) of FIG. 22 may be applied to an automotive display system (3000). Here, the automotive display system (3000) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0206] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display provided in a vehicle.

[0207] Referring to FIG. 25, the display system (1000) of FIG. 22 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0208] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0209] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0210] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0211] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0212] Referring to FIG. 26, the display system (1000) of FIG. 22 can be applied to a head-mounted display device (5000).

[0213] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0214] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0215] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0216] The drawings and detailed description of the invention described so far are merely illustrative of the present invention and are used solely for the purpose of explaining the present invention and are not intended to limit the scope of the invention as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments are possible. Accordingly, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. Substrate; a pixel circuit layer positioned on the substrate; and including a display element layer positioned on the pixel circuit layer, The above display element layer: A first bank including a first opening; A first light-emitting element positioned within the first opening, comprising a first bonding electrode and a second bonding electrode, wherein the first bonding electrode is electrically connected to a first electrode of a first transistor positioned in the pixel circuit layer; a second bank positioned on the first bank and including a second opening at least partially overlapping the first opening in a vertical direction; and A second light emitting element positioned within the second opening, comprising a third bonding electrode and a fourth bonding electrode, wherein the third bonding electrode is electrically connected to the second bonding electrode. Display device.

2. In paragraph 1, The above display element layer: a first anode electrode located at the lower portion of the first bank and electrically connected to the first electrode of the first transistor; and Further comprising a first reflective electrode positioned on the first anode electrode and the first bank, and connecting the first bonding electrode and the first anode electrode. Display device.

3. In paragraph 2, The above display element layer: a first cathode electrode positioned below the first bank; and Further comprising a second reflective electrode positioned on the first cathode electrode and the first bank, and connecting the second bonding electrode and the first cathode electrode. Display device.

4. In paragraph 3, The above display element layer: Further comprising a second anode electrode connecting the second reflective electrode and the third bonding electrode, Display device.

5. In paragraph 4, The above display element layer: a common electrode commonly connected to a plurality of sub-pixel circuits; and Further comprising a second cathode electrode electrically connecting the fourth bonding electrode and the common electrode; Display device.

6. In paragraph 5, The above display element layer: Further comprising a common connection electrode positioned on the first bank and the common electrode and connected to the second cathode electrode, Display device.

7. In paragraph 6, The above common connection electrode is spaced apart from the first reflective electrode, Display device.

8. In paragraph 6, The above common connection electrode is commonly connected to the plurality of sub-pixel circuits, Display device.

9. In paragraph 5, The second cathode electrode is commonly connected to the plurality of sub-pixel circuits, Display device.

10. In paragraph 1, The above first light-emitting element includes an n-type semiconductor layer and a p-type semiconductor layer, The above first bonding electrode is connected to the p-type semiconductor layer of the first light-emitting element, The second bonding electrode is connected to the n-type semiconductor layer of the first light-emitting element. Display device.

11. In paragraph 10, The above second light-emitting element includes an n-type semiconductor layer and a p-type semiconductor layer, The third bonding electrode is connected to the p-type semiconductor layer of the second light-emitting element, The fourth bonding electrode is connected to the n-type semiconductor layer of the second light-emitting element. Display device.

12. Step for preparing the substrate; A step of forming a pixel circuit layer on the substrate; and A step of forming a display element layer on the pixel circuit layer is included, The steps of forming the above display element layer are: A step of forming a first bank including a first opening; A step of positioning a first light-emitting element inside the first opening; A step of forming a second bank on the first bank, the second bank including a second opening that at least partially overlaps the first opening in a vertical direction; and comprising a step of positioning a second light-emitting element inside the second opening; The first light-emitting element and the second light-emitting element are connected in series, Method for manufacturing a display device.

13. In paragraph 12, The steps of forming the above display element layer are: A step of forming a first contact hole in the first insulating layer of the pixel circuit layer; and Further comprising a step of forming a first anode electrode, a first cathode electrode, and a common electrode on the first insulating layer, The first anode electrode overlaps the first contact hole, Method for manufacturing a display device.

14. In paragraph 13, The steps of forming the above display element layer are: Further comprising the step of forming a first reflective electrode positioned on the first bank and the first anode electrode, a second reflective electrode positioned on the first bank and the first cathode electrode, and a common connection electrode positioned on the first bank and the common electrode. Method for manufacturing a display device.

15. In paragraph 14, The step of positioning the first light-emitting element is: A step of positioning the first bonding electrode of the first light-emitting element on the first reflective electrode and positioning the second bonding electrode of the first light-emitting element on the second reflective electrode, Method for manufacturing a display device.

16. In paragraph 15, The steps of forming the above display element layer are: A step of forming a second insulating layer on the first light-emitting element; and Further comprising a step of forming a second contact hole exposing the second reflective electrode and a third contact hole exposing the common connection electrode in the second insulating layer. Method for manufacturing a display device.

17. In paragraph 16, The steps of forming the above display element layer are: Further comprising a step of forming a second anode electrode and a second cathode electrode on the second insulating layer, The second anode electrode overlaps the second contact hole, The second cathode electrode overlaps with the third contact hole, Method for manufacturing a display device.

18. In paragraph 17, The step of positioning the second light-emitting element is: A step of positioning the third bonding electrode of the second light-emitting element on the second anode electrode and positioning the fourth bonding electrode of the second light-emitting element on the second cathode electrode, Method for manufacturing a display device.

19. In paragraph 17, The second cathode electrode is commonly connected to a plurality of sub-pixel circuits, Method for manufacturing a display device.

20. In paragraph 19, The upper common electrode is commonly connected to the plurality of sub-pixel circuits. Method for manufacturing a display device.

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