Multi-coil system for etching uniformity control

Abstract

A plasma process system is provided, including: a chamber having an enclosed plasma processing region and an interior region that surrounds the enclosed plasma processing region; an upper magnetic coil disposed in the interior region, the upper magnetic coil being annularly shaped and oriented along a first horizontal plane above the enclosed plasma processing region; a lower magnetic coil disposed in the interior region, the lower magnetic coil being annularly shaped and oriented along a second horizontal plane below the enclosed plasma processing region; wherein the upper and lower magnetic coils are configured such that a height of the wafer during processing is at an approximate midpoint between the first horizontal plane and the second horizontal plane; a first DC power supply that applies a first DC current to the upper magnetic coil; a second DC power supply that applies a second DC current to the lower magnetic coil.

Description

Multi-coil System for Etching Uniformity ControlBACKGROUND OF THE INVENTION

[0001] Plasma etching processes are often used in the manufacture of semiconductor devices on semiconductor wafers. In the plasma etching process, a semiconductor wafer that includes semiconductor devices under manufacture is exposed to a plasma generated within a plasma processing volume. The plasma interacts with material(s) on the semiconductor wafer so as to remove material(s) from the semiconductor wafer and / or modify material(s) to enable their subsequent removal from the semiconductor wafer. The plasma can be generated using specific reactant gases that will cause constituents of the plasma to interact with the material(s) to be removed / modified from the semiconductor wafer, without significantly interacting with other materials on the wafer that are not to be removed / modified. The plasma is generated by using radiofrequency signals to energize the specific reactant gases. These radiofrequency signals are transmitted through the plasma processing volume that contains the reactant gases, with the semiconductor wafer held in exposure to the plasma processing volume. The transmission paths of the radiofrequency signals through the plasma processing volume can affect how the plasma is generated within the plasma processing volume. For example, the reactant gases may be energized to a greater extent in regions of the plasma processing volume where larger amounts of radiofrequency signal power is transmitted, thereby causing spatial non-uniformities in the plasma characteristics throughout the plasma processing volume. The spatial non-uniformities in plasma characteristics can manifest as spatial non-uniformity in ion density, ion energy, and / or reactive constituent density, among other plasma characteristics. The spatial non-uniformities in plasma characteristics can correspondingly cause spatial non-uniformities in plasma processing results on the semiconductor wafer. Therefore, the manner in which radiofrequency signals are transmitted through the plasma processing volume can have an effect on the uniformity of plasma processing results on the semiconductor wafer. It is within this context that the present disclosure arises.SUMMARY OF TH E INVENTION

[0002] Broadly speaking, embodiments of the present disclosure provide methods and systems for plasma uniformity control using a multi-coil system.

[0003] In some implementations, a plasma process system is provided, including the following: a chamber having an enclosed plasma processing region in which a plasma is generated for processing a wafer, the chamber further having an interior region that surrounds the enclosedplasma processing region; an upper magnetic coil disposed in the interior region and outside of the enclosed plasma processing region, the upper magnetic coil being annularly shaped and oriented along a first horizontal plane at a height above the enclosed plasma processing region; a lower magnetic coil disposed in the interior region and outside of the enclosed plasma processing region, the lower magnetic coil being annularly shaped and oriented along a second horizontal plane at a height below the enclosed plasma processing region; wherein the upper and lower magnetic coils are configured such that a height of the wafer during processing is at an approximate midpoint between the first horizontal plane and the second horizontal plane; a first DC power supply that applies a first DC current to the upper magnetic coil; a second DC power supply that applies a second DC current to the lower magnetic coil.

[0004] In some implementations, the first and second DC power supplies are configured such that the application of the first and second DC currents causes the upper and lower magnetic coils, respectively, to produce magnetic fields having opposite polarity.

[0005] In some implementations, the opposite polarity causes axial components of the magnetic fields to at least partially cancel along the wafer.

[0006] In some implementations, the upper magnetic coil and the lower magnetic coil have substantially the same diameter and are substantially vertically aligned.

[0007] In some implementations, the upper magnetic coil and the lower magnetic coil are aligned with a C-shroud in the chamber.

[0008] In some implementations, the upper magnetic coil is disposed substantially directly above the C-shroud.

[0009] In some implementations, the upper magnetic coil and the lower magnetic coil are substantially aligned with an outer wall of the C-shroud.

[0010] In some implementations, the upper magnetic coil and the lower magnetic coil are substantially aligned with an interior portion of the C-shroud.

[0011] In some implementations, the upper magnetic coil or the lower magnetic coil includes windings of copper wire.

[0012] In some implementations, the copper wire has a teflon coating.

[0013] In some implementations, the upper magnetic coil or the lower magnetic coil is at least partially enclosed in an anodized aluminum sheath.

[0014] In some implementations, the lower magnetic coil is suspended by a plurality of brackets.

[0015] In some implementations, the interior region is under vacuum during processing in order to exhaust process gases from the plasma processing region.

[0016] In some implementations, a plasma process system is provided, including the following: a chamber having an enclosed plasma processing region in which a plasma is generated for processing a wafer, the chamber further having an interior region that surrounds the enclosed plasma processing region; an upper magnetic coil disposed in the interior region and outside of the enclosed plasma processing region, the upper magnetic coil being annularly shaped and oriented along a first horizontal plane at a height above the enclosed plasma processing region; a lower magnetic coil disposed in the interior region and outside of the enclosed plasma processing region, the lower magnetic coil being annularly shaped and oriented along a second horizontal plane at a height below the enclosed plasma processing region; wherein the upper and lower magnetic coils are configured such that an approximate midpoint horizontal plane between the first horizontal plane and the second horizontal plane intersects a bulk region of the plasma; a first DC power supply that applies a first DC current to the upper magnetic coil; a second DC power supply that applies a second DC current to the lower magnetic coil.BRIEF DESCRIPTION OF DRAWI NGS

[0017] FIG. 1 shows a vertical cross-section view through a plasma processing system 100 for use in semiconductor chip manufacturing, in accordance with some embodiments.

[0018] FIG. 2 illustrates a cutaway view of a portion of a process chamber / reactor having a multicoil setup for etch uniformity control, in accordance with implementations of the disclosure.

[0019] FIG. 3 conceptually illustrates magnetic fields produced by a multi-coil system in a plasma process chamber, in accordance with the implementation of FIG. 2.

[0020] FIG. 4 illustrates a cutaway view of a portion of a process chamber having a multi-coil setup for etch uniformity control, in accordance with implementations of the disclosure.

[0021] FIG. 5 is a chart conceptually illustrating etch rate uniformity correction that is made possible with different power configurations in a two-coil system, in accordance with implementations of the disclosure.

[0022] FIG. 6 conceptually illustrates a multi-coil system with coils perpendicular to the wafer plane for addressing azimuthal non-uniformity, in accordance with implementations of the disclosure.

[0023] FIG. 7 illustrates several conceptual cross-section views showing various magnetic field topologies, including azimuthally asymmetric topologies, which can be created using perpendicularly oriented magnetic coils, in accordance with the implementation of FIG. 6.

[0024] FIG. 8 is a conceptual schematic diagram of a system for controlling power to multiple magnetic coils, in accordance with implementations of the disclosure.

[0025] FIG. 9 shows an example schematic of the control system 120 of FIG. 1, in accordance with some embodiments.DETAILED DESCRI PTION OF TH E I NVENTION

[0026] In the following description, numerous specific details are set forth in order to provide an understanding of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present disclosure.

[0027] In plasma etching systems for semiconductor wafer fabrication, spatial variation of etching results across the semiconductor wafer can be characterized by radial etch uniformity and azimuthal etch uniformity. Radial etch uniformity can be characterized by the variation in etch rate or tilt as a function of radial position on the semiconductor wafer. And, azimuthal etch uniformity can be characterized by the variation in etch rate or tilt as a function of azimuthal position on the semiconductor wafer. In some plasma processing systems, such as in the system described herein, the semiconductor wafer is positioned on an electrode from which radiofrequency signals emanate to generate a plasma within a plasma generation region overlying the semiconductor wafer, with the plasma having characteristics controlled to cause a prescribed etching process to occur on the semiconductor wafer.

[0028] In capacitive coupled plasma (CCP) systems, there is a tendency to exhibit center plasma non-uniformity due to standing waves and localized accumulation of positive and negative ions. This results in radial non-uniformity of etch rate. For example, many CCP tools may exhibit dramatic increases in etch rate towards the center of the wafer.

[0029] Furthermore, there is tool-to-tool variation with respect to etch non-uniformity. Some tools may exhibit significant spikes in etch rate at the center, whereas other tools may not. Often this is correlated to the presence or absence of magnetic fields, as the flux from chamber parts, which may vary in configuration from tool to tool, differs. Further, the local environment or specific location of a given tool, and surrounding hardware, may affect the local magnetic fields which are present, and which in turn affect etch non-uniformity.

[0030] In view of the foregoing problems in existing CCP systems, implementations of the disclosure provide multi-coil systems for the application of tunable B-fields to improve plasma / etch uniformity across the wafer.

[0031] FIG. 1 shows a vertical cross-section view through a plasma processing system 100 for use in semiconductor chip manufacturing, in accordance with some embodiments. The system 100includes a chamber 101 formed by walls 101A, a top member 101B, and a bottom member 101C. The walls 101A, top member 101B, and bottom member 101C collectively form an interior region 103 within the chamber 101. The bottom member 101C includes an exhaust port 105 through which exhaust gases from plasma processing operations are directed. In some embodiments, during operation, a suction force is applied at the exhaust port 105, such as by a turbo pump or other vacuum device, to draw process exhaust gases out of the interior region 103 of the chamber 101. In some embodiments, the chamber 101 is formed of aluminum. However, in various embodiments, the chamber 101 can be formed of essentially any material that provides sufficient mechanical strength, acceptable thermal performance, and is chemically compatible with the other materials to which it interfaces and to which it is exposed during plasma processing operations within the chamber 101, such as stainless steel, among others. At least one wall 101A of the chamber 101 includes a door 107 through which a semiconductor wafer W is transferred into and out of the chamber 101. In some embodiments, the door 107 is configured as a slit-valve door.

[0032] In some embodiments, the semiconductor wafer W is a semiconductor wafer undergoing a fabrication procedure. For ease of discussion, the semiconductor wafer W is referred to as wafer W hereafter. However, it should be understood that in various embodiments, the wafer W can be essentially any type of substrate that is subjected to a plasma-based fabrication process. For example, in some embodiments, the wafer W as referred to herein can be a substrate formed of silicon, sapphire, GaN, GaAs or SiC, or other substrate materials, and can include glass panels / substrates, metal foils, metal sheets, polymer materials, or the like. Also, in various embodiments, the wafer W as referred to herein may vary in form, shape, and / or size. For example, in some embodiments, the wafer W referred to herein may correspond to a circular-shaped semiconductor wafer on which integrated circuit devices are manufactured. In various embodiments, the circular-shaped wafer W can have a diameter of 200 mm (millimeters), 300 mm, 450 mm, or of another size. Also, in some embodiments, the wafer W referred to herein may correspond to a non-circular substrate, such as a rectangular substrate for a flat panel display, or the like, among other shapes.

[0033] The plasma processing system 100 includes an electrode 109 positioned on a facilities plate 111. In some embodiments, the electrode 109 and the facilities plate 111 are formed of aluminum. However, in other embodiments, the electrode 109 and the facilities plate 111 can be formed of another electrically conductive material that has sufficient mechanical strength and that has compatible thermal and chemical performance characteristics. A ceramic layer 110 is formed on a top surface of the electrode 109. The ceramic layer 110 is configured to receive and support thewafer W during performance of plasma processing operations on the wafer W. In some embodiments, the top surface of the electrode 190 that is located radially outside of the ceramic layer 110 and the peripheral side surfaces of the electrode 109 are covered with a spray coat of ceramic.

[0034] The ceramic layer 110 includes an arrangement of one or more clamp electrodes 112 for generating an electrostatic force to hold the wafer W to the top surface of the ceramic layer 110. In some embodiments, the ceramic layer 110 includes an arrangement of two clamp electrodes 112 that operate in a bipolar manner to provide a clamping force to the wafer W. The clamp electrodes 112 are connected to a direct current (DC) supply 117 that generates a controlled clamping voltage to hold the wafer W against the top surface of the ceramic layer 110. Electrical wires 119A, 119B are connected between the DC supply 117 and the facilities plate 111. Electrical wires / conductors are routed through the facilities plate 111 and the electrode 109 to electrically connect the wires 119A, 119B to the clamp electrodes 112. The DC supply 117 is connected to a control system 120 through one or more signal conductors 121.

[0035] The electrode 109 also includes an arrangement of temperature control fluid channels 123 through which a temperature control fluid is flowed to control a temperature of the electrode 109 and in turn control a temperature of the wafer W. The temperature control fluid channels 123 are plumbed (fluidly connected) to ports on the facilities plate 111. Temperature control fluid supply and return lines are connected to these ports on the facilities plate 111 and to a temperature control fluid circulation system 125, as indicated by arrow 126. The temperature control fluid circulation system 125 includes a temperature control fluid supply, a temperature control fluid pump, and a heat exchanger, among other devices, to provide a controlled flow of temperature control fluid through the electrode 109 in order to obtain and maintain a prescribed wafer W temperature. The temperature control fluid circulation system 125 is connected to the control system 120 through one or more signal conductors 127. In various embodiments, various types of temperature control fluid can be used, such as water or a refrigerant liquid / gas. Also, in some embodiments, the temperature control fluid channels 123 are configured to enable spatially varying control of the temperature of the wafer W, such as in two dimensions (x and y) across the wafer W.

[0036] The ceramic layer 110 also includes an arrangement of backside gas supply ports (not shown) that are fluidly connected to corresponding backside gas supply channels within the electrode 109. The backside gas supply channels within the electrode 109 are routed through the electrode 109 to the interface between the electrode 109 and the facilities plate 111. One or more backside gas supply line(s) are connected to ports on the facilities plate 111 and to a backside gassupply system 129, as indicated by arrow 130. The facilities plate 111 is configured to supply the backside gas(es) from the one or more backside gas supply line(s) to the backside gas supply channels within the electrode 109. The backside gas supply system 129 includes a backside gas supply, a mass flow controller, and a flow control valve, among other devices, to provide a controlled flow of backside gas through the arrangement of backside gas supply ports in the ceramic layer 110. In some embodiments, the backside gas supply system 129 also includes one or more components for controlling a temperature of the backside gas. In some embodiments, the backside gas is helium. Also, in some embodiments, the backside gas supply system 129 can be used to supply clean dry air (CDA) to the arrangement of backside gas supply ports in the ceramic layer 110. The backside gas supply system 129 is connected to the control system 120 through one or more signal conductors 131.

[0037] Three lift pins 132 extend through the facilities plate 111, the electrode 109, and the ceramic layer 110 to provide for vertical movement of the wafer W relative to the top surface of the ceramic layer 110. In some embodiments, vertical movement of the lift pins 132 is controlled by a respective electromechanical and / or pneumatic lifting device 133 connected to the facilities plate 111. The three lifting devices 133 are connected to the control system 120 through one or more signal conductors 134. In some embodiments, the three lift pins 132 are positioned to have a substantially equal azimuthal spacing about a vertical centerline of the electrode 109 / ceramic layer 110 that extends perpendicular to the top surface of the ceramic layer 110. It should be understood that the lift pins 132 are raised to receive the wafer W into the chamber 101 and to remove the wafer W from the chamber 101. Also, the lift pins 132 are lowered to allow the wafer W to rest on the top surface of the ceramic layer 110 during processing of the wafer W.

[0038] Also, in various embodiments, one or more of the electrode 109, the facilities plate 111, the ceramic layer 110, the clamp electrodes 112, the lift pins 132, or essentially any other component associated therewith can be equipped to include one or more sensors, such as sensors for temperature measurement, electrical voltage measurement, and electrical current measurement, among others. Any sensor disposed within the electrode 109, the facilities plate 111, the ceramic layer 110, the clamp electrodes 112, the lift pins 132, or essentially any other component associated therewith is connected to the control system 120 by way of electrical wire, optical fiber, or through a wireless connection.

[0039] The facilities plate 111 is set within an opening of a ceramic support 113, and is supported by the ceramic support 113. The ceramic support 113 is positioned on a supporting surface 114 of a cantilever arm assembly 115. In some embodiments, the ceramic support 113 has a substantiallyannular shape, such that the ceramic support 113 substantially circumscribes the outer radial perimeter of the facilities plate 111, while also providing a supporting surface 116 upon which a bottom outer peripheral surface of the facilities plate 111 rests. The cantilever arm assembly 115 extends through the wall 101A of the chamber 101. In some embodiments, a sealing mechanism 135 is provided within the wall 101A of the chamber 101 where the cantilever arm assembly 115 is located to provide for sealing of the interior region 103 of the chamber 101, while also enabling the cantilever arm assembly 115 to move upward and downward in the z-direction in a controlled manner.

[0040] The cantilever arm assembly 115 has an open region 118 through which various devices, wires, cables, and tubing is routed to support operations of the system 100. The open region 118 within the cantilever arm assembly is exposed to ambient atmospheric conditions outside of the chamber 101, e.g. air composition, temperature, pressure, and relative humidity. Also, a radiofrequency signal supply rod 137 is positioned inside of the cantilever arm assembly 115. More specifically, the radiofrequency signal supply rod 137 is positioned inside of an electrically conductive tube 139, such that the radiofrequency signal supply rod 137 is spaced apart from the inner wall of the tube 139. The sizes of the radiofrequency signal supply rod 137 and the tube 139 may vary. The region inside of the tube 139 between the inner wall of the tube 139 and the radiofrequency signal supply rod 137 is occupied by air along the full length of the tube 139.

[0041] In some embodiments, the radiofrequency signal supply rod 137 is substantially centered within the tube 139, such that a substantially uniform radial thickness of air exists between the radiofrequency signal supply rod 137 and the inner wall of the tube 139, along the length of tube 139. However, in some embodiments, the radiofrequency signal supply rod 137 is not centered within the tube 139, but the air gap within the tube 139 exists at all locations between the radiofrequency signal supply rod 137 and the inner wall of the tube 139, along the length of the tube 139. A delivery end of the radiofrequency signal supply rod 137 is electrically and physically connected to a lower end of a radiofrequency signal supply shaft 141. In some embodiments, the delivery end of the radiofrequency signal supply rod 137 is bolted to a lower end of a radiofrequency signal supply shaft 141. An upper end of the radiofrequency signal supply shaft 141 is electrically and physically connected to the bottom of the facilities plate 111. In some embodiments, the upper end of the radiofrequency signal supply shaft 141 is bolted to the bottom of the facilities plate 111. In some embodiments, both the radiofrequency signal supply rod 137 and the radiofrequency signal supply shaft 141 are formed of copper. In some embodiments, the radiofrequency signal supply rod 137 is formed of copper, or aluminum, or anodized aluminum. Insome embodiments, the radiofrequency signal supply shaft 141 is formed of copper, or aluminum, or anodized aluminum. In other embodiments, the radiofrequency signal supply rod 137 and / or the radiofrequency signal supply shaft 141 is formed of another electrically conductive material that provides for transmission of radiofrequency electrical signals. In some embodiments, the radiofrequency signal supply rod 137 and / or the radiofrequency signal supply shaft 141 is coated with an electrically conductive material (such as silver or another electrically conductive material) that provides for transmission of radiofrequency electrical signals. Also, in some embodiments, the radiofrequency signal supply rod 137 is a solid rod. However, in other embodiments, the radiofrequency signal supply rod 137 is a tube. Also, it should be understood that a region 140 surrounding the connection between the radiofrequency signal supply rod 137 and the radiofrequency signal supply shaft 141 is occupied by air.

[0042] A supply end of the radiofrequency signal supply rod 137 is connected electrically and physically to an impedance matching system 143. The impedance matching system 143 is connected to a first radiofrequency signal generator 147 and a second radiofrequency signal generator 149. The impedance matching system 143 is also connected to the control system 120 through one or more signal conductors 144. The first radiofrequency signal generator 147 is also connected to the control system 120 through one or more signal conductors 148. The second radiofrequency signal generator 149 is also connected to the control system 120 through one or more signal conductors 150. The impedance matching system 143 includes an arrangement of inductors and capacitors sized and connected to provide for impedance matching so that radiofrequency power can be transmitted along the radiofrequency signal supply rod 137, along the radiofrequency signal supply shaft 141, through the facilities plate 111, through the electrode 109, and into a plasma processing region 182 above the ceramic layer 110. In some embodiments, the first radiofrequency signal generator 147 is a high frequency radiofrequency signal generator, and the second radiofrequency signal generator 149 is a low frequency radiofrequency signal generator. In some embodiments, the first radiofrequency signal generator 147 generates radiofrequency signals within a range extending from about 50 MegaHertz (MHz) to about 70 MHz, or within a range extending from about 54 MHz to about 63 MHz, or at about 60 MHz. In some embodiments, the first radiofrequency signal generator 147 supplies radiofrequency power within a range extending from about 5 kiloWatts (kW) to about 25 kW, or within a range extending from about 10 kW to about 20 kW, or within a range extending from about 15 kW to about 20 kW, or of about 10 kW, or of about 16 kW. In some embodiments, the second radiofrequency signal generator 149 generates radiofrequency signals within a range extending from about 50 kiloHertz (kHz) to about500 kHz, or within a range extending from about 330 kHz to about 440 kHz, or at about 400 kHz. In some embodiments, the second radiofrequency signal generator 149 supplies radiofrequency power within a range extending from about 15 kW to about 100 kW, or within a range extending from about 30 kW to about 50 kW, or of about 34 kW, or of about 50 kW. In an example embodiment, the first radiofrequency signal generator 147 is set to generate radiofrequency signals having a frequency of about 60 MHz, and the second radiofrequency signal generator 149 is set to generate radiofrequency signals having a frequency of about 400 kHz.

[0043] A coupling ring 161 is configured and positioned to extend around the outer radial perimeter of the electrode 109. In some embodiments, the coupling ring 161 is formed of a ceramic material. A quartz ring 163 is configured and positioned to extend around the outer radial perimeters of both the coupling ring 161 and the ceramic support 113. In some embodiments, the coupling ring 161 and the quartz ring 163 are configured to have substantially aligned top surfaces when the quartz ring 163 is positioned around both the coupling ring 161 and the ceramic support 113. Also, in some embodiments, the substantially aligned top surfaces of the coupling ring 161 and the quartz ring 163 are substantially aligned with a top surface of the electrode 109, said top surface being present outside of the radial perimeter of the ceramic layer 110. Also, in some embodiments, a cover ring 165 is configured and positioned to extend around the outer radial perimeter of the top surface of the quartz ring 163. In some embodiments, the cover ring 165 is formed of quartz. In some embodiments, the cover ring 165 is configured to extend vertically above the top surface of the quartz ring 163. In this manner, the cover ring 165 provides a peripheral boundary within which an edge ring 167 is positioned.

[0044] The edge ring 167 is configured to facilitate extension of the plasma sheath radially outward beyond the peripheral edge of the wafer W to provide improvement in process results near the periphery of the wafer W. In various embodiments, the edge ring 167 is formed of a conductive material, such as crystalline silicon, polycrystalline silicon (polysilicon), boron doped single crystalline silicon, aluminum oxide, quartz, aluminum nitride, silicon nitride, silicon carbide, or a silicon carbide layer on top of an aluminum oxide layer, or an alloy of silicon, or a combination thereof, among other materials. It should be understood that the edge ring 167 is formed as an annular-shaped structure, e.g. as a ring-shaped structure. The edge ring 167 can perform many functions, including shielding components underlying the edge ring 167 from being damaged by ions of a plasma 180 formed within a plasma processing region 182. Also, the edge ring 167 improves uniformity of the plasma 180 at and along the outer peripheral region of the wafer W.

[0045] A fixed outer support flange 169 is attached to the cantilever arm assembly 115. The fixed outer support flange 169 is configured to extend around an outer vertical side surface of the ceramic support 113, and around an outer vertical side surface of the quartz ring 163, and around a lower outer vertical side surface of the cover ring 165. The fixed outer support flange 169 has an annular shape that circumscribes the assembly of the ceramic support 113, the quartz ring 163, and the cover ring 165. The fixed outer support flange 169 has an L-shaped vertical cross-section that includes a vertical portion and a horizontal portion. The vertical portion of the L-shaped crosssection of the fixed outer support flange 169 has an inner vertical surface that is positioned against the outer vertical side surface of the ceramic support 113, and against the outer vertical side surface of the quartz ring 163, and against the lower outer vertical side surface of the cover ring 165. In some embodiments, the vertical portion of the L-shaped cross-section of the fixed outer support flange 169 extends over an entirety of the outer vertical side surface of the ceramic support 113, and over an entirety of the outer vertical side surface of the quartz ring 163, and over the lower outer vertical side surface of the cover ring 165. In some embodiments, the cover ring 165 extends radially outward above a top surface of the vertical portion of the L-shaped crosssection of the fixed outer support flange 169. And, in some embodiments, an upper outer vertical side surface of the cover ring 165 (located above the top surface of the vertical portion of the L- shaped cross-section of the fixed outer support flange 169) is substantially vertically aligned with an outer vertical surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169. The horizontal portion of the L-shaped cross-section of the fixed outer support flange 169 is positioned on and fastened to the supporting surface 114 of a cantilever arm assembly 115. The fixed outer support flange 169 is formed of an electrically conductive material. In some embodiments, the fixed outer support flange 169 is formed of aluminum or anodized aluminum. However, in other embodiments, the fixed outer support flange 169 can be formed of another electrically conductive material, such as copper or stainless steel. In some embodiments, the horizontal portion of the L-shaped cross-section of the fixed outer support flange 169 is bolted to the supporting surface 114 of a cantilever arm assembly 115.

[0046] An articulating outer support flange 171 is configured and positioned to extend around the outer vertical surface 169D of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169, and to extend around the upper outer vertical side surface of the cover ring 165. The articulating outer support flange 171 has an annular shape that circumscribes both the vertical portion of the L-shaped vertical cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the cover ring 165. The articulating outer support flange 171 hasan L-shaped vertical cross-section that includes a vertical portion and a horizontal portion. The vertical portion of the L-shaped cross-section of the articulating outer support flange 171 has an inner vertical surface that is positioned proximate to and spaced apart from both the outer vertical side surface of the vertical portion of the L-shaped cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the cover ring 165. In this manner, the articulating outer support flange 171 is moveable in the vertical direction (z-direction) along both the vertical portion of the L-shaped vertical cross-section of the fixed outer support flange 169 and the upper outer vertical side surface of the cover ring 165. The articulating outer support flange 171 is formed of an electrically conductive material. In some embodiments, the articulating outer support flange 171 is formed of aluminum or anodized aluminum. However, in other embodiments, the articulating outer support flange 171 can be formed of another electrically conductive material, such as copper or stainless steel.

[0047] A number of electrically conductive straps 173 are connected between the articulating outer support flange 171 and the fixed outer support flange 169, around the outer radial perimeters of both the articulating outer support flange 171 and the fixed outer support flange 169. In the example embodiment, the electrically conductive straps 173 are shown to have an "outward" configuration, in that the electrically conductive straps 173 bend outward away from the fixed outer support flange 169. In some embodiments, the electrically conductive straps 173 are formed of stainless steel. However, in other embodiments, the electrically conductive straps 173 can be formed of another electrically conductive material, such as aluminum or copper, among others.

[0048] In some embodiments, forty-eight (48) electrically conductive straps 173 are distributed in a substantially equally spaced manner around the outer radial perimeters of the articulating outer support flange 171 and the fixed outer support flange 169. It should be understood, however, that the number of electrically conductive straps 173 can vary in different embodiments. In some embodiments, the number of electrically conductive straps 173 is within a range extending from about 24 to about 80, or within a range extending from about 36 to about 60, or within a range extending from about 40 to about 56. In some embodiments, the number of electrically conductive straps 173 is less than 24. In some embodiments, the number of electrically conductive straps 173 is greater than 80. Because the number of electrically conductive straps 173 has an effect on the ground return paths for the radiofrequency signals around the perimeter of the plasma processing region 182, the number of electrically conductive straps 173 can have an effect on the uniformity of process results across the wafer W. Also, the size of the electrically conductive straps 173 can vary in different embodiments.

[0049] In some embodiments, the electrically conductive straps 173 are connected to the fixed outer support flange 169 by a clamping force applied by securing a clamp ring 175 to a top surface of the horizontal portion of the L-shaped cross-section of the fixed outer support flange 169. In some embodiments, the clamp ring 175 is bolted to the fixed outer support flange 169. In some embodiments, the bolts that secure the clamp ring 175 to the fixed outer support flange 169 are positioned at locations between the electrically conductive straps 173. However, in some embodiments, one or more bolts that secure the clamp ring 175 to the fixed outer support flange 169 can be positioned to extend through electrically conductive straps 173. In some embodiments, the clamp ring 175 is formed of a same material as the fixed outer support flange 169. However, in other embodiments, the clamp ring 175 and the fixed outer support flange 169 can be formed of different materials.

[0050] In some embodiments, the electrically conductive straps 173 are connected to the articulating outer support flange 171 by a clamping force applied by securing a clamp ring 177 to a bottom surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange 171. Alternatively, in some embodiments, the first end portion of each of the plurality of electrically conductive straps 173 is connected to the upper surface of the horizontal portion of the articulating outer support flange 171 by the clamp ring 177. In some embodiments, the clamp ring 177 is bolted to the articulating outer support flange 171. In some embodiments, the bolts that secure the clamp ring 177 to the articulating outer support flange 171 are positioned at locations between the electrically conductive straps 173. However, in some embodiments, one or more bolts that secure the clamp ring 177 to the articulating outer support flange 171 can be positioned to extend through electrically conductive straps 173. In some embodiments, the clamp ring 177 is formed of a same material as the articulating outer support flange 171. However, in other embodiments, the clamp ring 177 and the articulating outer support flange 171 can be formed of different materials.

[0051] A set of support rods 201 are positioned around the cantilever arm assembly 115 to extend vertically through the horizontal portion 169B of the L-shaped cross-section of the fixed outer support flange 169. The upper end of the support rods 201 are configured to engage with the bottom surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange 171. In some embodiments, a lower end of each of the support rods 201 is engaged with a resistance mechanism 203. The resistance mechanism 203 is configured to provide an upward force to the corresponding support rod 201 that will resist downward movement of the support rod 201, while allowing some downward movement of the support rod 201. In someembodiments, the resistance mechanism 203 includes a spring to provide the upward force to the corresponding support rod 201. In some embodiments, the resistance mechanism 203 includes a material, e.g. spring and / or rubber, that has a sufficient spring constant to provide the upward force to the corresponding support rod 201. It should be understood that as the articulating outer support flange 171 moves downward to engage the set of support rods 201, the set of support rods 201 and corresponding resistance mechanisms 203 provide an upward force to the articulating outer support flange 171. In some embodiments, the set of support rods 201 includes three support rods 201 and corresponding resistance mechanisms 203. In some embodiments, the support rods 201 are positioned to have a substantially equal azimuthal spacing relative to a vertical centerline of the electrode 109. However, in other embodiments, the support rods 201 are positioned to have a non-equal azimuthal spacing relative to a vertical centerline of the electrode 109. Also, in some embodiments, more than three support rods 201 and corresponding resistance mechanisms 203 are provided to support the articulating outer support flange 171.

[0052] With continued reference back FIG. 1, the plasma processing system 100 further includes a C-shroud member 185 positioned above the electrode 109. The C-shroud member 185 is configured to interface with the articulating outer support flange 171. Specifically, a seal 179 is disposed on the top surface of the horizontal portion of the L-shaped cross-section of the articulating outer support flange 171, such that the seal 179 is engaged by the C-shroud member 185 when the articulating outer support flange 171 is moved upward toward the C-shroud member 185. In some embodiments, the seal 179 is electrically conductive to assist with establishing electrical conduction between the C-shroud member 185 and the articulating outer support flange 171. In some embodiments, the C-shroud member 185 is formed of polysilicon. However, in other embodiments, the C-shroud member 185 is formed of another type of electrically conductive material that is chemically compatible with the processes to be formed in the plasma processing region 182, and that has sufficient mechanical strength.

[0053] The C-shroud is configured to extend around the plasma processing region 182 and provide a radial extension of the plasma processing region 182 volume into the region defined within the C- shroud member 185. The C-shroud member 185 includes a lower wall 185A, an outer vertical wall 185B, and an upper wall 185C. In some embodiments, the outer vertical wall 185B and the upper wall 185C of the C-shroud member 185 are solid, non-perforated members, and the lower wall 185A of the C-shroud member 185 includes a number of vents 186 through which process gases flow from within the plasma processing region 182. In some embodiments, a throttle member 196 is disposed below the vents 186 of the C-shroud member 185 to control a flow of process gasthrough the vents 186. More specifically, in some embodiments, the throttle member 196 is configured to move up and down vertically in the z-direction relative to the C-shroud member 185 to control the flow of process gas through the vents 186. In some embodiments, the throttle member 196 is configured to engage with and / or enter the vents 186.

[0054] The upper wall 185C of the C-shroud member 185 is configured to support an upper electrode 187A / 187B. In some embodiments, the upper electrode 187A / 187B includes an inner upper electrode 187A and an outer upper electrode 187B. Alternatively, in some embodiments, the inner upper electrode 187A is present and the outer upper electrode 187B is not present, with the inner upper electrode 187A extending radially to cover the location that would be occupied by the outer upper electrode 187B. In some embodiments, the inner upper electrode 187A is formed of single crystal silicon and the outer upper electrode 187B is formed of polysilicon. However, in other embodiments, the inner upper electrode 187A and the outer upper electrode 187B can be formed of other materials that are structurally, chemically, electrically, and mechanically compatible with the processes to be performed within the plasma processing region 182. The inner upper electrode 187A includes a number of throughports 197 defined as holes extending through an entire vertical thickness of the inner upper electrode 187A. The throughports 197 are distributed across the inner upper electrode 187A, relative to the x-y plane, to provide for flow of process gas(es) from a plenum region 188 above the upper electrode 187A / 187B to the plasma processing region 182 below the upper electrode 187A / 187B.

[0055] It should be understood that the distribution of throughports 197 across the inner upper electrode 187A can be configured in different ways for different embodiments. For example, a total number of throughports 197 within the inner upper electrode 187A and / or a spatial distribution of throughports 197 within the inner upper electrode 187A can vary between different embodiments. Also, a diameter of the throughports 197 can vary between different embodiments. In general, it is of interest to reduce the diameter of the throughports 197 to a size small enough to prevent intrusion of the plasma 180 into the throughports 197 from the plasma processing region 182. In some embodiments, as the diameter of the throughports 197 is reduced, the total number of throughports 197 within the inner upper electrode 187A is increased to maintain a prescribed overall flowrate of process gas(es) from the process gas plenum region 188 through the inner upper electrode 187A to the plasma processing region 182. Also, in some embodiments, the upper electrode 187A / 187B is electrically connected to a reference ground potential. However, in other embodiments, the inner upper electrode 187A and / or the outer upper electrode 187B is / areelectrically connected to either a respective direct current (DC) electrical supply or a respective radiofrequency power supply by way of a corresponding impedance matching circuit.

[0056] The plenum region 188 is defined by an upper member 189. One or more gas supply ports 192 are formed through the chamber 101 and the upper member 189 to be in fluid communication with the plenum region 188. The one or more gas supply ports 192 are fluidly connected (plumbed) to a process gas supply system 191. The process gas supply system 191 includes one or process gas supplies, one or more mass flow controller(s), one or more flow control valve(s), among other devices, to provide controlled flow of one or more process gas(es) through the one or more gas supply ports 192 to the plenum region 188, as indicated by arrow 193. In some embodiments, the process gas supply system 191 also includes one or more components for controlling a temperature of the process gas(es). The process gas supply system 191 is connected to the control system 120 through one or more signal conductors 194.

[0057] A processing gap (gl) is defined as the vertical (z-direction) distance as measured between the top surface of the ceramic layer 110 and the bottom surface of the inner upper electrode 187A. The size of the processing gap (gl) can be adjusted by moving the cantilever arm assembly 115 in the vertical direction (z-direction). As the cantilever arm assembly 115 moves upward, the articulating outer support flange 171 eventually engages the lower wall 185A of the C-shroud member 185, at which point the articulating outer support flange 171 moves along the fixed outer support flange 169 as the cantilever arm assembly 115 continues to move upward until the set of support rods 201 engage the articulating outer support flange 171 and the prescribed processing gap (gl) size is achieved. Then, to reverse this movement for removal of the wafer W from the chamber, the cantilever arm assembly 115 is moved downward until the articulating outer support flange 171 moves away from the lower wall 185A of the C-shroud member 185. It should be understood that FIG. 1 shows the system 100 in a closed configuration with the wafer W position on the ceramic layer 110 for plasma processing.

[0058] During plasma processing operations within the plasma processing system 100, the one or more process gas(es) are supplied to the plasma processing region 182 by way of the process gas supply system 191, plenum region 188, and throughports 197 within the inner upper electrode 187A. Also, radiofrequency signals are transmitted into the plasma processing region 182, by way of the first and second radiofrequency signal generators 147, 149, the impedance matching system 143, the radiofrequency signal supply rod 137, the radiofrequency signal supply shaft 141, the facilities plate 111, the electrode 109, and through the ceramic layer 110. The radiofrequency signals transform the process gas(es) into the plasma 180 within the plasma processing region 182.Ions and / or reactive constituents of the plasma interact with one or more materials on the wafer W to cause a change in composition and / or shape of particular material(s) present on the wafer W. The exhaust gases from the plasma processing region 182 flow through the vents 186 in the C- shroud member 185 and through the interior region 103 within the chamber 101 to the exhaust port 105 under the influence of a suction force applied at the exhaust port 105, as indicated by arrows 195.

[0059] In various embodiments, the electrode 109 can be configured to have different diameters. However, in some embodiments, to increase the surface of the electrode 109 upon which the edge ring 167 rests, the diameter of the electrode 109 is extended. In some embodiments, an electrically conductive gel 226 is disposed between a bottom of the edge ring 167 and the top of the electrode 109 and / or between the bottom of the edge ring 167 and the top of the coupling ring 161. In these embodiments, the increased diameter of the electrode 109 provides more surface area upon which the conductive gel is disposed between the edge ring 167 and the electrode 109.

[0060] It should be understood that the combination of the articulating outer support flange 171, the electrically conductive straps 173, and the fixed outer support flange 169 are electrically at a reference ground potential, and collectively form a ground return path for radiofrequency signals transmitted from the electrode 109 through the ceramic layer 110 into the plasma processing region 182. The azimuthal uniformity of this ground return path around the perimeter of the electrode 109 can have an effect on uniformity of process results on the wafer W. For example, in some embodiments, the uniformity of etch rate across the wafer W can be affected by the azimuthal uniformity of the ground return path around the perimeter of the electrode 109. To this end, it should be understood that the number, configuration, and arrangement of the electrically conductive straps 173 around the perimeter of the electrode 109 can affect the uniformity of process results across the wafer W.

[0061] With reference back to FIG. 1, a Tunable Edge Sheath (TES) system is implemented to include a TES electrode 225 disposed (embedded) within the coupling ring 161. The TES system also includes a number of TES radiofrequency signal supply pins 223 in physical and electrical connection with the TES electrode 225. Each TES radiofrequency signal supply pin 223 extends through a corresponding insulator feedthrough member 231 configured to electrically separate the TES radiofrequency signal supply pin 223 from surrounding structures, such as from the ceramic support 113 and the cantilever arm assembly 115 structure. In some embodiments, o-rings 1 1 and 229 are disposed to ensure that the region inside of the insulator feedthrough member 231 is not exposed to any materials / gases present within the plasma processing region 182. In someembodiments, the TES radiofrequency signal supply pins 223 are formed of copper, or aluminum, or anodized aluminum, among others.

[0062] The TES radiofrequency signal supply pins 223 extend into the open region 118 inside of the cantilever arm assembly 115, where each of the TES radiofrequency signal supply pins 223 is electrically connected to a TES radiofrequency signal supply conductor 219 through a corresponding TES radiofrequency signal filter 221. In some embodiments, three TES radiofrequency signal supply pins 223 are positioned to physically and electrically connect with the TES electrode 225 at substantially equally spaced azimuthal locations about the centerline of the electrode 109. It should be understood, however, that other embodiments can have more than three TES radiofrequency signal supply pins 223 in physical and electrical connection with the TES electrode 225. Also, some embodiments can have either one or two TES radiofrequency signal supply pins 223 in physical and electrical connection with the TES electrode 225. Each TES radiofrequency signal supply pin 223 is electrically connected to a corresponding TES radiofrequency signal filter 221, with each TES radiofrequency signal filter 221 electrically connected to the TES radiofrequency signal supply conductor 219. In some embodiments, each TES radiofrequency signal filter 221 is configured as an inductor. For example, in some embodiments, each TES radiofrequency signal filter 221 is configured as a coiled conductor, such as a metal coil wrapped around a dielectric core structure. In various embodiments, the metal coil can be formed of solid copper rod, copper tubing, aluminum rod, or aluminum tubing, among others. Also, in some embodiments, each TES radiofrequency signal filter 221 can be configured as a combination of inductive and capacitive structures. In the interest of improving plasma processing result uniformity across the wafer W, each of the TES radiofrequency signal filters 221 has a substantially same configuration.

[0063] In some embodiments, the TES radiofrequency signal supply conductor 219 is formed as a ring-shaped (annular-shaped) structure, so as to extend around the open region 118 inside of the cantilever arm assembly 115 to enable physical and electrical connection of the azimuthally distributed TES radiofrequency signal filters 221 with the TES radiofrequency signal supply conductor 219. In some embodiments, the TES radiofrequency signal supply conductor 219 is formed as a solid (non-tubular) structure. Alternatively, in some embodiments, the TES radiofrequency signal supply conductor 219 is formed as a tubular structure. In some embodiments, the TES radiofrequency signal supply conductor 219 is formed of copper, or aluminum, or anodized aluminum, among others.

[0064] The TES radiofrequency signal supply conductor 219 is electrically connected to a TES radiofrequency supply cable 217. Also, a capacitor 218 is connected between the TESradiofrequency signal supply conductor 219 and a reference ground potential, such as the structure of the cantilever arm assembly 115. More specifically, the capacitor 218 has a first terminal electrically connected to both the TES radiofrequency supply cable 217 and the TES radiofrequency signal supply conductor 219, and the capacitor 218 has a second terminal electrically connected to the reference ground potential. In some embodiments, the capacitor 218 is a variable capacitor. In some embodiments, the capacitor 218 is a fixed capacitor. In some embodiments, the capacitor 218 is set to have a capacitance within a range extending from about 10 picoFarads to about 100 picoFarads. The TES radiofrequency supply cable 217 is connected to a TES impedance matching system 211. The TES impedance matching system 211 is connected to a TES radiofrequency signal generator 213. Radiofrequency signals generated by the TES radiofrequency signal generator 213 are transmitted through the TES impedance matching system 211 to the TES radiofrequency supply cable 217, then to the TES radiofrequency signal supply conductor 219, then through the TES radiofrequency signal filters 221 to the respective TES radiofrequency signal supply pins 223, and to the TES electrode 225 within the coupling ring 161. In some embodiments, the TES radiofrequency signal generator 213 is configured and operated to generate radiofrequency signals within a frequency range extending from about 50 kiloHertz to about 27 MHz. In some embodiments, the TES radiofrequency signal generator 213 supplies radiofrequency power within a range extending from about 50 Watts to about 10 kiloWatts. The TES radiofrequency signal generator 213 is also connected to the control system 120 through one or more signal conductors 215.

[0065] The TES impedance matching system 211 includes an arrangement of inductors and capacitors sized and connected to provide for impedance matching so that radiofrequency power can be transmitted from the TES radiofrequency signal generator 213 along the TES radiofrequency supply cable 217, along the TES radiofrequency signal supply conductor 219, through the TES radiofrequency signal filters 221, through the respective TES radiofrequency signal supply pins 223, to the TES electrode 225 within the coupling ring 161, and into the plasma processing region 182 above the edge ring 167. The TES impedance matching system 211 is also connected to the control system 120 through one or more signal conductors 214.

[0066] By transmitting radiofrequency signals / power through the TES electrode 225 disposed (embedded) within the coupling ring 161, the TES system is capable of controlling characteristics of the plasma 180 near the peripheral edge of the wafer W. For example, in some embodiments, the TES system is operated to control the plasma 180 sheath properties near the edge ring 167, such as by controlling a shape of the plasma 180 sheath and / or by controlling a size (either increase in sheath thickness or decrease in sheath thickness). Also, in some embodiments, by controlling theshape of the plasma 180 sheath near the edge ring 167, it is possible to control various properties of the bulk plasma 180 over the wafer W. Also, in some embodiments, the TES system is operated to control a density of the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is operated to either increase or decrease the density of the plasma 180 near the edge ring 167. Also, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring 167, which in turn controls / influences movement of ions and other charged constituents within the plasma 180 near the edge ring 167. For example, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring 167 to attract more ions from the plasma 180 toward the edge of the wafer W. And, in some embodiments, the TES system is operated to control a bias voltage present on the edge ring 167 to repel ions from the plasma 180 away from the edge of the wafer W. It should be understood that the TES system can be operated to perform a variety of different functions, such as those mentioned above, among others, either separately or in combination.

[0067] In some embodiments, the coupling ring 161 is formed of a dielectric material, such as quartz, or ceramic, or alumina (AI2O3), or a polymer, among others.

[0068] A bottom surface of the edge ring 167 has a portion that is coupled to the upper surface of the coupling ring 161 through a layer of thermally and electrically conductive gel to thermally sink the coupling ring 161 to the edge ring 167. Also, the bottom surface of the edge ring 167 has another portion that is coupled to an upper surface of the electrode 109 through a layer of thermally and electrically conductive gel. Examples of the thermally and electrically conductive gel include polyimide, polyketone, polyetherketone, polyether sulfone, polyethylene terephthalate, fluoroethylene propylene copolymers, cellulose, triacetates, and silicone, among others. In some embodiments, the thermally and electrically conductive gel is formed as a double-sided tape. In some embodiments, the edge ring 167 has an inner diameter sized to be proximate to the outer diameter of the ceramic layer 110.

[0069] In various embodiments, the TES electrode 225 is formed of an electrically conductive material, such as platinum, steel, aluminum, or copper, among others. During operation, capacitive coupling occurs between the TES electrode 225 and the edge ring 167, such that the edge ring 167 is electrically powered to influence processing of the wafer W near the outer perimeter of the wafer W.

[0070] In order to address etch non-uniformity, at present, a single coil system can be used to generate magnetic fields for uniformity improvement. While some improvement is possible, thesingle coil setup demonstrates a lack of field topology tunability, resulting in relatively inflexible etch correction that can only be tuned by varying the polarity and magnitude of the coil.

[0071] However, implementations of the present disclosure provide multi-coil systems that enable a magnetic field with significantly improved tunable topology. This enables improved etching uniformity by impacting the plasma density distribution in the reactor. With the usage of a multicoil system, field topology can be greatly tuned and tailored to a specific correction to improve etch uniformity.

[0072] The coils can also be placed inside the vacuum reactor creating a more confined field around the wafer and plasma region. Coils parallel or perpendicular to the wafer plane can address specific non-uniformity challenges including radial versus azimuthal etching non-uniformities. The synergetic usage of multiple coils greatly increases the tunability of the magnetic field topology generated around the wafer plane and in the bulk of the plasma. Furthermore, by bringing the coils closer to the wafer plane, inside the reactor, the field intensity can be significantly increased, and less field distortion is present. Independent current control in the coils, which can be parallel and / or perpendicular to the wafer plane, can ultimately provide a tunable magnetic field topology that provides superior zonal non-uniformity control.

[0073] FIG. 2 illustrates a cutaway view of a portion of a process chamber / reactor having a multicoil setup for etch uniformity control, in accordance with implementations of the disclosure.

[0074] In the illustrated implementation, the multi-coil system includes two magnetic coils, an upper magnetic coil 240 and a lower magnetic coil 242. Each of the upper and lower magnetic coils is substantially ring-shaped or annularly shaped. The upper / lower magnetic coils are oriented along horizontal planes which are parallel to the wafer's planar surface, and also axially aligned with the wafer.

[0075] Each of the upper and lower magnetic coils consists of a number of turns / windings of a conductive wire, such as a copper wire. In some implementations, the conductive wire is coated with a non-reactive coating to protect the conductive material. For example, in some implementations, the conductive wire is coated with Teflon or another non-reactive coating that is resistive to the environment of the interior region of the chamber during processing. In some implementations, the conductive wire is specifically a Teflon-coated copper wire.

[0076] In some implementations, the conductive wire has a thickness in the range of about 12 to 16 AWG. In some implementations, the upper or lower magnetic coil consists of approximately 30 to 100 number of turns of conductive wire.

[0077] In some implementations, the upper or lower magnetic coil has a substantially rectangular cross-section, as shown in the illustrated implementation. In other implementations, the upper or lower magnetic coil may have other cross-sectional shapes, such as circular, oval, triangular, hexagonal, etc. In some implementations, the upper or lower magnetic coil has a cross-sectional width in the range of about 1 to 5 cm, and a cross-sectional height in the range of about 1 to 5 cm.

[0078] In some implementations, the upper or lower magnetic coil, being annularly shaped as discussed, extends from an inner diameter to an outer diameter. In some implementations, the inner diameter is in the range of about 50 to 60 cm. In some implementations, the outer diameter (or overall diameter) is in the range of about 51 to 65 cm. Thus, in some implementations, the radial width / thickness of the upper or lower magnetic coil is in the range of about 1 to 5 cm. Furthermore, in some implementations, the upper or lower magnetic coil has a vertical thickness in the range of about 1 to 5 cm.

[0079] In some implementations, the upper and lower magnetic coils are substantially the same or substantially similar in construction and dimensions. In other implementations, the upper and lower magnetic coils may differ in terms of their construction and dimensions.

[0080] In the illustrated implementation, the upper and lower magnetic coils are substantially the same in construction and dimensions, and as such, are vertically aligned with each other, such that the windings of the upper magnetic coil are vertically disposed over the windings of the lower magnetic coil.

[0081] In the illustrated implementation, the upper magnetic coil is positioned substantially directly above, or on top of, the C-shroud 185. Whereas the lower magnetic coil is positioned below the C-shroud 185, and below the throttle member 196. In some implementations, the upper and lower magnetic coils are substantially aligned with the outer vertical wall 185B of the C-shroud 185. It will be appreciated that as exhaust gases from the plasma processing region 182 flow through the C-shroud as previously described, then it may be desirable to position the lower magnetic coil 242 toward the periphery of the interior region 103 of the chamber 101 so as not to block the flow of exhaust gases from the chamber.

[0082] In some implementations, the lower magnetic coil is supported by a plurality of brackets 244 that support and position the lower magnetic coil at a predefined height. In some implementations, at least three brackets are provided, and circumferentially spaced at equivalent intervals around and / or below the C-shroud. In some implementations, the brackets 244 are height adjustable in order to enable adjustments in the height or tilt of the lower magnetic coil 242. For example, in some implementations, the adjustable brackets can facilitate leveling of the lowermagnetic coil, or setting the height of the lower magnetic coil to different heights for different processes or recipes. In some implementations, the adjustable brackets can facilitate setting the lower magnetic coil to have an intentional tilt to generate a magnetic field that addresses an azimuthal non-uniformity.

[0083] In some implementations, the magnetic coils are covered with a protective sheath, which can be formed from a resistive and corrosion resistant material such as anodized aluminum. In the illustrated implementation, the protective sheath for the upper magnetic coil 240 is defined by an upper sheath assembly consisting of an upper sheath portion 246 and a lower sheath portion 248. In the illustrated implementation, the protective sheath for the lower magnetic coil 242 is defined by a lower sheath assembly consisting of an upper sheath portion 252 and a lower sheath portion 250. It will be appreciated that the upper and lower magnetic coils are disposed outside of the plasma processing region 182 but still within the interior region 103 of the chamber 101, and as such, may still be exposed to radicals and ions which are exhausted from the C-shroud into the interior region 103 as they are being pumped out of the chamber 101. Therefore, the provision of protective sheaths for the magnetic coils helps to protect the magnetic coils against being damaged by such exposure.

[0084] FIG. 3 conceptually illustrates magnetic fields produced by a multi-coil system in a plasma process chamber, in accordance with the implementation of FIG. 2.

[0085] In the illustrated implementation, the upper magnetic coil 240 and the lower magnetic coil 242 are shown in their relative positioning, axially aligned at different vertical heights. In some implementations, the heights of the upper and lower magnetic coils are configured so that the wafer is disposed at a height approximately halfway between the heights of the upper and lower magnetic coils. That is, the center plane between the upper and lower magnetic coils is approximately aligned with the wafer plane. For example, with reference to the illustrated implementation, if the upper magnetic coil 240 is oriented along a horizontal plane Hl at a first height, and the lower magnetic coil 242 is oriented along a horizontal plane H2 at a second height, then the wafer plane 300 is approximately at the midpoint, or approximately equidistant, between the horizontal planes Hl and H2, at a height that is approximately halfway between the first and second heights. The wafer plane can be defined by the top surface of the wafer in some implementations. In some implementations, the wafer plane is at a height that is within about -40 to 40 mm of the midpoint between the horizontal planes along which the upper and lower magnetic coils are oriented.

[0086] In the illustrated implementation, the various arrows conceptually show magnetic field vectors when the upper and lower magnetic coils are powered with DC current at opposite polarities. The resulting magnetic field demonstrates a predominant radial component along the wafer plane 300 (and near the plasma sheath), while the magnetic field in the bulk plasma demonstrates a more significant axial component in addition to the radial component. This field topology is made possible by the configuration of the upper and lower magnetic coils. Along the wafer plane, the radial components of the fields generated by the upper and lower magnetic coils sum together and reinforce each other, whereas the axial components mostly cancel each other. The overall field is mostly radial along the wafer plane, which is more effective for addressing radial tilt non-uniformity in an etch process than would be possible with a single coil system.

[0087] FIG. 4 illustrates a cutaway view of a portion of a process chamber having a multi-coil setup for etch uniformity control, in accordance with implementations of the disclosure.

[0088] In the illustrated implementation, an upper magnetic coil 400 and a lower magnetic coil 402 are provided. The upper magnetic coil 400 is positioned directly over a radially inner portion of the C-shroud 185, and more specifically over the upper wall 185C of the C-shroud. Whereas the lower magnetic coil 402 is positioned beneath the radially inner portion of the C-shroud 185. The positioning of the upper and lower magnetic coils is configured so that the midpoint between the coils, identified by the plane 404 in the illustrated implementation, is aligned with the bulk plasma during plasma processing.

[0089] In some implementations as shown in the illustrated implementation, the lower magnetic coil 402 is positioned adjacent to an outer flange 408 that abuts, from below, the inner portion of the lower wall 185A of the C-shroud 185.

[0090] In some implementations, the upper magnetic coil 400 is at least partially covered and protected by a sheath 406, which can be constructed of anodized aluminum in some implementations. In some implementations, the lower magnetic coil 402 is at least partially covered and protected by a sheath 410, which can be constructed of anodized aluminum in some implementations.

[0091] By positioning the lower magnetic coils 400 and 402 as shown, aligned with a radially inner portion of the C-shroud 185, then the coils are vertically aligned with each other, and the lower magnetic coil 402 is positioned towards the inside of the exhaust flow pathway, so as not to block the flow of exhaust gas from the plasma processing region 182.

[0092] It will be appreciated that the upper and lower magnetic coils 400 / 402 can be constructed in a similar fashion as the coils described at FIG. 2. In some implementations, the radial width of theupper or lower magnetic coil 400 / 402 is in the range of about 1 to 5 cm. In some implementations, the vertical thickness of the upper or lower magnetic coil 400 / 402 is in the range of about 1 to 5 cm. In some implementations, the upper or lower magnetic coil 400 / 402 has an inner diameter in the range of about 40 to 50 cm, or an outer diameter (or overall diameter) in the range of about 41 to 55 cm.

[0093] FIG. 5 is a chart conceptually illustrating etch rate uniformity correction that is made possible with different power configurations in a two-coil system, in accordance with implementations of the disclosure.

[0094] Along the upper row are conceptual cross-section views showing the magnetic field topologies produced by various DC current combinations applied to the upper and lower magnetic coils in accordance with the implementation of FIG. 4. Along the bottom row are corresponding graphs showing thermal oxide etch rate uniformity correction resulting from such magnetic field topologies. As can be seen, a wide variety of field topologies and resulting etch rate corrections are possible.

[0095] For example, in the conceptual cross-section 500, a ratio of DC current applied to the upper coil versus the lower coil is about -2.3, so that the current applied to the upper coil is significantly greater than that applied to the lower coil. The resulting B-field topology is conceptually shown by the arrows, such that along the approximate midpoint plane between the coils (in the bulk plasma in this implementation), the B-field is strongly axially downward over the center region over the wafer, and directed radially outward at an angle of about -43 degrees from horizontal over the edge region of the wafer. This produces an etch rate correction effect that is shown by the graph 502, wherein etch rate is significantly depressed in the center region of the wafer, but increased towards the edge region of the wafer.

[0096] As can be seen from the additional conceptual cross-sections and corresponding etch rate correction graphs, a variety of B field topologies can be generated by applying various DC current combinations, with resulting etch rate corrections that can be applied to address various etch nonuniformity profiles. Notably, with the use of two coils, it becomes possible to control the angles of the magnetic field, as well as its strength. This provides a significant advantage in tunability over single-coil systems in which it is not possible to change the angles of the magnetic field, only its strength.

[0097] FIG. 6 conceptually illustrates a multi-coil system with coils perpendicular to the wafer plane for addressing azimuthal non-uniformity, in accordance with implementations of the disclosure.

[0098] In the illustrated implementation, an underside view of an upper portion of the chamber is shown, showing the C-shroud 185. More specifically, a plurality of coils 600 are positioned around the C-shroud 185 at regular intervals, with the coils being oriented perpendicular to the wafer plane. More specifically, the coils are axially aligned in parallel with a radial direction from the center of the wafer outward, so that the axis of a given coil orthogonally intersects a center axis of the wafer. It will be appreciated that in some implementations, the axis of a coil may be substantially aligned with the bulk plasma during processing. In some implementations, the axis of a coil may be aligned with (or near) the top surface of the wafer or the plasma sheath.

[0099] In the illustrated implementation, there are eight coils 600 distributed evenly around the C- shroud. However, in other implementations, there may be more or fewer coils.

[0100] FIG. 7 illustrates several conceptual cross-section views showing various magnetic field topologies, including azimuthally asymmetric topologies, which can be created using perpendicularly oriented magnetic coils, in accordance with the implementation of FIG. 6.

[0101] In the illustrated concept 700, the various magnetic coils 600 are disposed around the C- shroud 185 as shown, and oriented and / or supplied with DC current so as to have the same radial polarity. In this configuration as shown, the B field is symmetric and directed radially inward toward the center.

[0102] In the illustrated concept 702, the radial polarities of the various coils 600 are the same, but flipped by comparison with the concept 700, thereby yielding a B field topology that is directed radially outward.

[0103] In the illustrated concept 704, three coils are flipped in polarity as compared to the concept 700, producing a B field gradient as shown, that is asymmetric and directed towards one side of the C-shroud.

[0104] In the illustrated concept 706, the coils are configured to have alternating polarity as shown. This results in a B field topology having steep gradients between the coils.

[0105] As can be seen, with the individually controllable coils 600, it is possible to operate various DC current configurations with various polarities, providing various symmetric and asymmetric gradients to address various types of non-uniformity, including azimuthal non-uniformity.

[0106] FIG. 8 is a conceptual schematic diagram of a system for controlling power to multiple magnetic coils, in accordance with implementations of the disclosure.

[0107] In the illustrated implementation, the control system 120 is operatively connected to, and controls the operation of, several DC power supplies 800, 802, 804, and 806. The DC power supplies respectively apply a DC current to magnetic coils 808, 810, 812, and 814. The control system 120can control the magnitude / strength of the DC current (e.g. Amperage) and the polarity (e.g. positive or negative; or, counterclockwise or clockwise) of the DC current supplied by a given one of the DC power supplies.

[0108] In some implementations, the magnetic coils 808, 810, 812, and 814 can be any of the magnetic coils described in accordance with the various implementations of the disclosure. Though four magnetic coils and four corresponding DC power supplies are shown, it will be appreciated that there can be additional magnetic coils and DC power supplies in other implementations.

[0109] In some implementations, a user interface is provided to enable an operator to adjust the parameters of the DC power supplies, such as by providing settings for adjustment of the DC current magnitude, and its polarity, for any given DC power supply.

[0110] As has been discussed, in some implementations, application of a B-field during plasma processing can be used to reduce plasma non-uniformity, and thereby reduce etch non-uniformity.

[0111] It will be appreciated that any of the methods described in the present disclosure can be implemented to run automatically by the control system 120.

[0112] FIG. 9 shows an example schematic of the control system 120 of FIG. 1, in accordance with some embodiments. In some embodiments, the control system 120 is configured as a process controller for controlling the semiconductor fabrication process performed in plasma processing system 100. In various embodiments, the control system 120 includes a processor 901, a storage hardware unit (HU) 903 (e.g. memory), an input HU 905, an output HU 907, an input / output (I / O) interface 909, an I / O interface 911, a network interface controller (NIC) 913, and a data communication bus 915. The processor 901, the storage HU 903, the input HU 905, the output HU 907, the I / O interface 909, the I / O interface 911, and the NIC 913 are in data communication with each other by way of the data communication bus 915. The input HU 905 is configured to receive data communication from a number of external devices. Examples of the input HU 905 include a data acquisition system, a data acquisition card, etc. The output HU 907 is configured to transmit data to a number of external devices. An examples of the output HU 907 is a device controller. Examples of the NIC 913 include a network interface card, a network adapter, etc. Each of the I / O interfaces 909 and 911 is defined to provide compatibility between different hardware units coupled to the I / O interface. For example, the I / O interface 909 can be defined to convert a signal received from the input HU 905 into a form, amplitude, and / or speed compatible with the data communication bus 915. Also, the I / O interface 907 can be defined to convert a signal received from the data communication bus 915 into a form, amplitude, and / or speed compatible with the output HU 907. Although various operations are described herein as being performed by the 1processor 901 of the control system 120, it should be understood that in some embodiments various operations can be performed by multiple processors of the control system 120 and / or by multiple processors of multiple computing systems in data communication with the control system 120.

[0113] In some embodiments, the control system 120 is employed to control devices in various wafer fabrication systems based in-part on sensed values. For example, the control system 120 may control one or more of valves 917, filter heaters 919, wafer support structure heaters 921, pumps 923, and other devices 925 based on the sensed values and other control parameters. The valves 917 can include valves associated with control of the backside gas supply system 129, the process gas supply system 191, and the temperature control fluid circulation system 125. The control system 120 receives the sensed values from, for example, pressure manometers 927, flow meters 929, temperature sensors 931, and / or other sensors 933, e.g. voltage sensors, current sensors, etc. The control system 120 may also be employed to control process conditions within the plasma processing system 100 during performance of plasma processing operations on the wafer W. For example, the control system 120 can control the type and amounts of process gas(es) supplied from the process gas supply system 191 to the plasma processing region 182. Also, the control system 120 can control operation of the first radiofrequency signal generator 147, the second radiofrequency signal generator 149, the impedance matching system 143, the TES radiofrequency signal generator 213, and the TES impedance matching system 211. Also, the control system 120 can control operation of the DC supply 117 for the clamping electrode(s) 112. The control system 120 can also control operation of the lifting devices 133 for the lift pins 132 and operation of the door 107. The control system 120 also controls operation of the backside gas supply system 129 and the temperature control fluid circulation system 125. The control system 120 also control vertical movement of the cantilever arm assembly 115. The control system 120 also controls operation of the throttle member 196 and the pump that controls suction at the exhaust port 105. The control system 120 also controls operation of the hold-down control mechanisms 913 of the hold-down rods 911 of the TES system 1000. The control system 120 also receives input from the temperature probe of the TES system 1000. It should be understood that the control system 120 is equipped to provide for programmed and / or manual control any function within the plasma processing system 100.

[0114] In some embodiments, the control system 120 is configured to execute computer programs including sets of instructions for controlling process timing, process gas delivery system temperature, and pressure differentials, valve positions, mixture of process gases, process gas flowrate, backside cooling gas flow rate, chamber pressure, chamber temperature, wafer support structure temperature (wafer temperature), RF power levels, RF frequencies, RF pulsing, impedance matching system 143 settings, cantilever arm assembly position, bias power, and other parameters of a particular process. Other computer programs stored on memory devices associated with the control system 120 may be employed in some embodiments. In some embodiments, there is a user interface associated with the control system 120. The user interface include a display 935 (e.g. a display screen and / or graphical software displays of the apparatus and / or process conditions), and user input devices 937 such as pointing devices, keyboards, touch screens, microphones, etc.

[0115] Software for directing operation of the control system 120 may be designed or configured in many different ways. Computer programs for directing operation of the control system 120 to execute various wafer fabrication processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran or others. Compiled object code or script is executed by the processor 901 to perform the tasks identified in the program. The control system 120 can be programmed to control various process control parameters related to process conditions such as, for example, filter pressure differentials, process gas composition and flow rates, backside cooling gas composition and flow rates, temperature, pressure, plasma conditions, such as RF power levels and RF frequencies, bias voltage, cooling gas / fluid pressure, and chamber wall temperature, among others. Examples of sensors that may be monitored during the wafer fabrication process include, but are not limited to, mass flow control modules, pressure sensors, such as the pressure manometers 927 and the temperature sensors 931. Appropriately programmed feedback and control algorithms may be used with data from these sensors to control / adjust one or more process control parameters to maintain desired process conditions.

[0116] In some implementations, the control system 120 is part of a broader fabrication control system. Such fabrication control systems can include semiconductor processing equipment, including a processing tools, chambers, and / or platforms for wafer processing, and / or specific processing components, such as a wafer pedestal, a gas flow system, etc. These fabrication control systems may be integrated with electronics for controlling their operation before, during, and after processing of the wafer. The control system 120 may control various components or subparts of the fabrication control system. The control system 120, depending on the wafer processing requirements, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, the delivery of backside cooling gases, temperature settings (e.g. heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF)generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0117] Broadly speaking, the control system 120 may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable wafer processing operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g. software). Program instructions may be instructions communicated to the control system 120 in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on the wafer W within system 100. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0118] The control system 120, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the plasma processing system 100, or otherwise networked to the system 100, or a combination thereof. For example, the control system 120 may be in the "cloud" of all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system 100 to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to the system 100 over a network, which may include a local network or the Internet.

[0119] The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system 100 from the remote computer. In some examples, the control system 120 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed within the plasma processing system 100. Thus as described above, the control system 120 may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controlsdescribed herein. An example of a distributed controller for such purposes would be one or more integrated circuits on the plasma processing system 100 in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process performed on the plasma processing system 100.

[0120] Without limitation, example systems that the control system 120 can interface with may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers. As noted above, depending on the process step or steps to be performed by the tool, the control system 120 might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0121] Embodiments described herein may also be implemented in conjunction with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. Embodiments described herein can also be implemented in conjunction with distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network. It should be understood that the embodiments described herein, particularly those associated with the control system 120, can employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus may be specially constructed for a special purpose computer. When defined as a special purpose computer, the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose. In some embodiments, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache,or obtained over a network. When data is obtained over a network, the data may be processed by other computers on the network, e.g. a cloud of computing resources.

[0122] Various embodiments described herein can be implemented through process control instructions instantiated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit that can store data, which can be thereafter be read by a computer system. Examples of the non-transitory computer-readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes, and other optical and non-optical data storage hardware units. The non-transitory computer- readable medium can include computer-readable tangible medium distributed over a network- coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

[0123] Although the foregoing disclosure includes some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. For example, it should be understood that one or more features from any embodiment disclosed herein may be combined with one or more features of any other embodiment disclosed herein. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and what is claimed is not to be limited to the details given herein, but may be modified within the scope and equivalents of the described embodiments.

Claims

Claims1. A plasma process system, comprising: a chamber having an enclosed plasma processing region in which a plasma is generated for processing a wafer, the chamber further having an interior region that surrounds the enclosed plasma processing region; an upper magnetic coil disposed in the interior region and outside of the enclosed plasma processing region, the upper magnetic coil being annularly shaped and oriented along a first horizontal plane at a height above the enclosed plasma processing region; a lower magnetic coil disposed in the interior region and outside of the enclosed plasma processing region, the lower magnetic coil being annularly shaped and oriented along a second horizontal plane at a height below the enclosed plasma processing region; wherein the upper and lower magnetic coils are configured such that a height of the wafer during processing is at an approximate midpoint between the first horizontal plane and the second horizontal plane; a first DC power supply that applies a first DC current to the upper magnetic coil; a second DC power supply that applies a second DC current to the lower magnetic coil.

2. The plasma process system of claim 1, wherein the first and second DC power supplies are configured such that the application of the first and second DC currents causes the upper and lower magnetic coils, respectively, to produce magnetic fields having opposite polarity.

3. The plasma process system of claim 2, wherein the opposite polarity causes axial components of the magnetic fields to at least partially cancel along the wafer.

4. The plasma process system of claim 1, wherein the upper magnetic coil and the lower magnetic coil have substantially the same diameter and are substantially vertically aligned.

5. The plasma process system of claim 1, wherein the upper magnetic coil and the lower magnetic coil are aligned with a C-shroud in the chamber.

6. The plasma process system of claim 5, wherein the upper magnetic coil is disposed substantially directly above the C-shroud.

7. The plasma process system of claim 6, wherein the upper magnetic coil and the lower magnetic coil are substantially aligned with an outer wall of the C-shroud.

8. The plasma process system of claim 6, wherein the upper magnetic coil and the lower magnetic coil are substantially aligned with an interior portion of the C-shroud.

9. The plasma process system of claim 1, wherein the upper magnetic coil or the lower magnetic coil includes windings of copper wire.

10. The plasma process system of claim 9, wherein the copper wire has a teflon coating.

11. The plasma process system of claim 1, wherein the upper magnetic coil or the lower magnetic coil is at least partially enclosed in an anodized aluminum sheath.

12. The plasma process system of claim 1, wherein the lower magnetic coil is suspended by a plurality of brackets.

13. The plasma process system of claim 1, wherein the interior region is under vacuum during processing in order to exhaust process gases from the plasma processing region.

14. A plasma process system, comprising: a chamber having an enclosed plasma processing region in which a plasma is generated for processing a wafer, the chamber further having an interior region that surrounds the enclosed plasma processing region; an upper magnetic coil disposed in the interior region and outside of the enclosed plasma processing region, the upper magnetic coil being annularly shaped and oriented along a first horizontal plane at a height above the enclosed plasma processing region; a lower magnetic coil disposed in the interior region and outside of the enclosed plasma processing region, the lower magnetic coil being annularly shaped and oriented along a second horizontal plane at a height below the enclosed plasma processing region; wherein the upper and lower magnetic coils are configured such that an approximate midpoint horizontal plane between the first horizontal plane and the second horizontal plane intersects a bulk region of the plasma; a first DC power supply that applies a first DC current to the upper magnetic coil; a second DC power supply that applies a second DC current to the lower magnetic coil.

15. The plasma process system of claim 1, wherein the first and second DC power supplies are configured such that the application of the first and second DC currents causes the upper and lower magnetic coils, respectively, to produce axial magnetic fields having opposite polarity.

16. The plasma process system of claim 1, wherein the upper magnetic coil and the lower magnetic coil have substantially the same diameter and are substantially vertically aligned.

17. The plasma process system of claim 1, wherein the upper magnetic coil and the lower magnetic coil are aligned with a C-shroud in the chamber.

18. The plasma process system of claim 17, wherein the upper magnetic coil is disposed substantially directly above the C-shroud.

19. The plasma process system of claim 18, wherein the upper magnetic coil and the lower magnetic coil are substantially aligned with an outer wall of the C-shroud.

20. The plasma process system of claim 18, wherein the upper magnetic coil and the lower magnetic coil are substantially aligned with an interior portion of the C-shroud.

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