Gate integration in complementary field effect transistor (CFET) devices

Abstract

A semiconductor structure includes a bottom field effect transistor (FET) module and a top FET module stacked on the bottom FET module in a first direction, a split metal gate in a first circuit region, the split metal gate comprising a first bottom metal gate, a first top metal gate, and a split-gate dielectric layer between the first bottom metal gate and the first top metal gate, and a common metal gate in a second circuit region, the common metal gate comprising a second bottom metal gate and a second top metal gate, wherein the second top metal gate is electrically connected to the second bottom metal gate.

Description

GATE INTEGRATION IN COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) DEVICESBACKGROUNDField

[0001] Embodiments described herein generally relate to semiconductor device fabrication, and more particularly, to split gate and common gate integration in complementary field effect transistor (CFET) devices.Description of the Related Art

[0002] To continue scaling beyond the physical limit of planar metal oxide semiconductor field effect transistor (MOSFET), three-dimensional FinFET, stacked nanosheet gate-all-around FET (GAA FETs), and complementary FET (CFET) have been proposed. In a CFET architecture, n-type devices and p-type devices are stacked on top of each other vertically, and a power distribution network is designed to be implemented at the bottom of the device, which helps in optimizing routing of interconnect.

[0003] In a common gate configuration, gate terminals of a p-channel MOS (p- MOS) transistor and an n-channel MOS (n-MOS) transistor are connected to a common input signal, and thus tied together to receive the same voltage. The common gate configuration is often used in the CFET devices for certain applications, which allows for a simpler design and better control over the device characteristics.

[0004] In a split gate configuration, gate terminals of a p-MOS transistor and an n- channel MOS (n-MOS) transistor are separate and have independent input signals, which allows for independent control over the operation of each transistor. The split gate configuration provides more flexibility and allows for different voltage levels and switching behaviors for the p-MOS and the n-MOS transistors.

[0005] The choice between the common gate and the split gate configurations depends on the specific requirements of the CFET application, such as power consumption, noise immunity, and design complexity.

[0006] Thus, a process integration that enables both the common gateconfiguration and the split gate configuration within one integrated circuit design is needed.SUMMARY

[0007] Embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a bottom field effect transistor (FET) module and a top FET module stacked on the bottom FET module in a first direction, a split metal gate in a first circuit region, the split metal gate comprising a first bottom metal gate, a first top metal gate, and a split-gate dielectric layer between the first bottom metal gate and the first top metal gate, and a common metal gate in a second circuit region, the common metal gate comprising a second bottom metal gate and a second top metal gate, wherein the second top metal gate is electrically connected to the second bottom metal gate.

[0008] Embodiments of the present disclosure provide a method of forming a complementary field-effect transistor (CFET). The method includes depositing a bottom work function metal layer within contact trenches extending through a bottom FET module and a top FET module stacked on the bottom FET module in a first direction, filling the contact trenches with contact metal fill material, removing portions of the bottom work function metal layer and the contact metal fill material in the top FET module, depositing a protection layer within the contact trenches, removing the protection layer from the contact trenches in a first circuit region and leaving the protection layer within the contact trenches in a second circuit region, selectively depositing a split-gate dielectric layer on exposed surfaces of the contact metal fill material within the contact trenches in the first circuit region, removing the protection layer, and depositing a top work function metal layer within the contact trenches and filling the contact trenches with the contact metal fill material.

[0009] Embodiments of the present disclosure provide a method of forming a complementary field-effect transistor (CFET). The method includes depositing a bottom work function metal layer within contact trenches extending through a bottom FET module and a top FET module stacked on the bottom FET module in a first direction, filling the contact trenches with contact metal fill material, removing portions of the bottom work function metal layer and the contact metal fill material in the top FET module, depositing a protection layer within the contact trenches, removing theprotection layer from the contact trenches in a first circuit region and leave the protection layer within the contact trenches in a second circuit region, removing the protection layer, and depositing a top work function metal layer within the contact trenches and fill the contact trenches with the contact metal fill material.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope of the disclosure, as the disclosure may admit to other equally effective embodiments.

[0011] Figure 1 is a schematic top view of a multi-chamber processing system, according to one or more embodiments of the present disclosure.

[0012] Figure 2 is an isometric view of a portion of a semiconductor structure that may form a complementary field-effect transistor (CFET), according to one or more embodiments of the present disclosure.

[0013] Figure 3 depicts a process flow diagram of a method of forming cell transistors in a semiconductor structure according to one embodiment.

[0014] Figures 4A, 4B, 4C, 4D, 4E, 4F, and 4G are isometric views of a portion of a semiconductor structure corresponding to various states of the method of Figure 3.

[0015] Figure 5 depicts a process flow diagram of a method 500 of forming cell transistors in a semiconductor structure according to one embodiment.

[0016] Figures 6A, 6B, 6C, 6D, 6E, 6F, and 6G are isometric views of a portion of the semiconductor structure corresponding to various states of the method of Figure 5.

[0017] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. In the figures and thefollowing description, an orthogonal coordinate system including an X-axis, a Y-axis, and a Z-axis is used. The directions represented by the arrows in the drawings are assumed to be positive directions for convenience. It is contemplated that elements disclosed in some embodiments may be beneficially utilized on other implementations without specific recitation.DETAILED DESCRIPTION

[0018] The embodiments described herein provide a process integration method that forms common metal gates and split metal gates in one integrated circuit design in CFET devices.

[0019] Figure 1 is a schematic top view of a multi-chamber processing system 100, according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 can be processed in and transferred between the various chambers without exposing the substrates to an ambient environment exterior to the processing system 100 (e.g., an atmospheric ambient environment such as may be present in a fab). For example, the substrates can be processed in and transferred between the various chambers maintained at a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment among various processes performed on the substrates in the processing system 100. Accordingly, the processing system 100 may provide for an integrated solution for some processing of substrates.

[0020] Examples of a processing system that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer® or Centura® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California.

[0021] In the illustrated example of Figure 1 , the factory interface 102 includes a docking station 132 and factory interface robots 134 to facilitate transfer of substrates. The docking station 132 is adapted to accept one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includesa blade 138 disposed on one end of the respective factory interface robot 134 adapted to transfer the substrates from the factory interface 102 to the load lock chambers 104, 106.

[0022] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, slit valve openings with slit valves for passing substrates therethrough by the transfer robots 112, 114 and for providing a seal between respective chambers to prevent a gas from passing between the respective chambers. Generally, any port is open for transferring a substrate therethrough. Otherwise, the port is closed.

[0023] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically illustrated). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo-pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, a factory interface robot 134 transfers a substrate from a FOUR 136 through a port 140 or 142 to a load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and holding chambers 116, 118 with an interior low pressure or vacuum environment (which may include an inert gas). Hence, the pumping down of the load lock chamber 104 or 106 facilitates passing the substrate between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0024] With the substrate in the load lock chamber 104 or 106 that has been pumped down, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 through the port 144 or 146. The transfer robot112 is then capable of transferring the substrate to and / or between any of the processing chambers 120, 122 through the respective ports 152, 154 for processing and the holding chambers 116, 118 through the respective ports 148, 150 for holding to await further transfer. Similarly, the transfer robot 114 is capable of accessing the substrate in the holding chamber 116 or 118 through the port 156 or 158 and is capable of transferring the substrate to and / or between any of the processing chambers 124, 126, 128, 130 through the respective ports 160, 162, 164, 166 for processing and the holding chambers 116, 118 through the respective ports 156, 158 for holding to await further transfer. The transfer and holding of the substrate within and among the various chambers can be in the low pressure or vacuum environment provided by the gas and pressure control system.

[0025] The processing chambers 120, 122, 124, 126, 128, 130 can be any appropriate chamber for processing a substrate. In some examples, the processing chamber 120 can be capable of performing etch processes, the processing chamber 122 can be capable of performing cleaning processes, the processing chamber 124 can be capable of performing selective removal processes, the processing chamber 126 can be capable of performing chemical vapor deposition (CVD) deposition processes, and the processing chambers 128, 130 can be capable of performing respective epitaxial growth processes.

[0026] A system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 168 may control the operation of the processing system 100 using a direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data collection and feedback from the respective chambers to coordinate performance of the processing system 100.

[0027] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174. The CPU 170 may be one of any form of a general purpose processor that can be used in an industrial setting. The memory 172, or non-transitory computer-readable medium, is accessible by the CPU 170 and may be one or more of memory such as random access memory (RAM), read onlymemory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 174 are coupled to the CPU 170 and may comprise cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction code stored in the memory 172 (or in memory of a particular processing chamber) as, for example, a software routine. When the computer instruction code is executed by the CPU 170, the CPU 170 controls the chambers to perform processes in accordance with the various methods.

[0028] Other processing systems can be in other configurations. For example, more or fewer processing chambers may be coupled to a transfer apparatus. In the illustrated example, the transfer apparatus includes the transfer chambers 108, 110 and the holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

[0029] Figure 2 is an isometric view of a portion of a semiconductor structure 200 that may form a complementary field-effect transistor (CFET), according to one or more embodiments of the present disclosure.

[0030] The semiconductor structure 200 shown in Figure 2 includes a bottom field effect transistor (FET) module TRB, and a top FET module TRTstacked on the bottom FET module TRBin the Z direction. In one example, the bottom FET module TRBincludes p-channel transistors (not shown in Figure 2) embedded within an inter-layer dielectric (ILD) 202 , and the top FET module TRTincludes n-channel transistors (not shown in Figure 2) embedded within the ILD 202. The semiconductor structures 200 may include more than one circuit regions, circuit A, circuit B, and circuit C. In one example, in the circuit A, each transistor in the bottom FET module TRBincludes a bottom metal gate and a pair of source / drain (S / D) regions provided on opposite sides of the bottom metal gate, and each transistor in the top FET module TRTincludes a top metal gate and a pair of S / D regions provided on opposite sides of the top metal gate. A stack of a bottom metal gate and a top metal gate is a split metal gate. In the circuit B and the circuit C, each transistor in the bottom FET module TRBincludes acommon metal gate extending in the bottom FET module TRBand the top FET module TRTand a pair of source / drain (S / D) regions provided on opposite sides of the common metal gate, and each transistor in the top FET module TRTincludes the same common metal gate and a pair of S / D regions provided on opposite sides of the common metal gate. A common metal gate extends in the bottom FET module TRBand the top FET module TRT.

[0031] The ILD 202 may be formed of silicon oxide (SiC>2), silicon oxynitride (SiON), aluminum oxide (AI2O3), or any combination thereof. The ILD 202 is protected by an ILD protection layer 204 formed of SiN, SiCN, SiC, SiOCN, SiCO, or metal oxide (e.g., AI2O2, TiN, WOx, WC) and formed above STI 206. The STIs 206 may be formed of silicon oxide (SiO2) and protected by an STI protection layer 208 formed of SiN, SiCN, SiCON, SiC, SiCO above a substrate 210. The ILD protection layer 204 may be covered by a high-k dielectric layer 212 formed of high-k dielectric material, such as hafnium oxide (HfO2).

[0032] The semiconductor structure 200 further includes a contact etch stop layer (CESL) 214 between the bottom FET module TRBand the top FET module TRT.

[0033] The term “substrate” as used herein refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. The substrate may be a silicon based material or any suitable insulating materials or conductive materials as needed. The substrate may include a material such as crystalline silicon (e.g., Si<100> or Si<111 >), silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0034] Figure 3 depicts a process flow diagram of a method 300 of forming a semiconductor structure 400 that may be the semiconductor structure 200 forming a portion of a complementary field-effect transistor (CFET), according to one or more embodiments of the present disclosure. Figures 4A, 4B, 4C, 4D, 4E, 4F, and 4G are isometric views of a portion of the semiconductor structure 400 corresponding to various states of the method 300. In Figures 4A, 4B, 4C, 4D, 4E, 4F, and 4G, a cutout of the semiconductor structure 400 along the YZ plane including the line A-A shown in Figure 4A, and a cut-out of the semiconductor structure 400 along the ZX planeincluding the line B-B are shown in Figure 4A. It should be understood that Figures 4A, 4B, 4C, 4D, 4E, 4F, and 4G illustrate only partial schematic views of the semiconductor structure 400, and the semiconductor structure 400 may contain any number of transistor sections and additional materials having aspects as illustrated in the figures. It should also be noted that although the method illustrated in Figure 3 is described sequentially, other process sequences that include one or more operations that have been omitted and / or added, and / or has been rearranged in another desirable order, fall within the scope of the embodiments of the disclosure provided herein.

[0035] As shown in Figure 4A, the semiconductor structure 400 includes a bottom field effect transistor (FET) module TRB, and a top FET module TRTstacked on the bottom FET module TRBin the Z direction. In one example, p-channel transistors are to be formed and embedded within an inter-layer dielectric (ILD) 202 in the bottom FET module TRB, and n-channel transistors are to be formed and embedded within the ILD 202 in the top FET module TRT. The semiconductor structures 400 may include more than one circuit regions, circuit A, circuit B, and circuit C. In the method 300 described herein, split metal gates are formed in the circuit A.

[0036] The semiconductor structure 400 further includes silicon channel layers 402 extending in the X direction. The silicon channel layers 402 in the FET module TRBand the silicon channel layers 402 in the top FET module TRTare isolated by middle dielectric isolation (MDI) 216, formed of dielectric material, such as SiN, SiC>2, SiCN, SiCO, SiCON.

[0037] The ILD 202 may be formed of silicon oxide (SiC>2), silicon oxynitride (SiON), aluminum oxide (AI2O3), or any combination thereof. The ILD 202 is protected by an ILD protection layer 204 formed of SiN, SiCN, SiC, SiOCN, SiCO, or metal oxide (e.g., AI2O2, TiN, WOx, WC) and formed above shallow trench isolations (STIs) 206. The STIs 206 may be formed of silicon oxide (SiO2) and protected by an STI protection layer 208 formed of SiN, SiC, SiCN, SiCON, SiCO above a substrate 210. The MDI 216 may be formed dielectric material, such as SiN, SiO2, SiCN, SiCO, SiCON. The semiconductor structure 400 further includes a contact etch stop layer (CESL) 214 between the bottom FET module TRBand the top FET module TRT.

[0038] The method 300 begins with block 302, in which a bottom metal gap-fillprocess is performed to deposit a bottom work function metal layer 404 within contact trenches 406 extending through the top FET module TRTand the bottom FET module TRB, and fill the contact trenches 406 with contact metal fill material 408, as shown in Figure 4A.

[0039] The bottom work function metal layer 404 may be formed of WN, TiN, AIN, or MoN. The contact metal fill material 408 may be tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), conductive oxides or nitrides thereof, or any combination thereof.

[0040] The bottom metal gap-fill process may include any appropriate deposition process, such as such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0041] In block 304, a bottom metal recess process is performed to remove portions of the bottom work function metal layer 404 and the contact metal fill material 408 in the top FET module TRTabove the MDI 216, as shown in Figure 4B. The remaining metal contact fill material 408 forms bottom metal gates 202B.

[0042] The bottom metal recess process may include any appropriate wet etch process performed in a processing chamber, such as the processing chamber 120 shown in Figure 1 , and any appropriate deposition process, such as such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0043] In block 306, a protection material gap-fill process is performed to deposit a protection layer 410 within the contact trenches 406, as shown in Figure 4C.

[0044] The protection layer 410 may be formed of any gap-fill patterning material, such as carbon.

[0045] The protection material gap-fill process may include any appropriate gap-fill process, such as a chemical vapor deposition (CVD) process, flowable CVD (FCVD) process, or a spin-on process performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0046] In block 308, a protection layer bottom open etch process is performed to remove the protection layer 410 from the contact trenches 406 in the circuit A and leave the protection layer 410 within the contact trenches 406 in the circuit B and the circuit C, as shown in Figure 4D. The contact trenches 406 in the circuit B and the circuit C remain covered by the protection layer 410.

[0047] The protection layer bottom open etch process may include any anisotropic etch process, such as a reactive ion etching (RIE) performed in a processing chamber, such as the processing chamber 120 shown in Figure 1 . In a circuit design where the circuit A has enough isotropic etch margin to the circuit B and the circuit C, the protection layer bottom open etch process may include isotropic etch process, performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0048] In block 310, a bottom-up split gate dielectric deposition process is performed to selectively deposit a split-gate dielectric layer 412 on exposed surface of the bottom metal gates 208B within the contact trenches 406 in the circuit A, as shown in Figure 4E. The split-gate dielectric layer 412 is not deposited on the bottom metal gates 208B in the circuit B and the circuit C due to the protection layer 410 thereon.

[0049] The split-gate dielectric layer 412 may be silicon oxide (SiO ), silicon nitride (Si3N4), silicon carbide (SiC), silicon carbon nitride (SiCN), or silicon carbon oxynitride (SiCON).

[0050] The bottom-up split gate dielectric deposition process may each include a directional selective fill (DSF) process, such as such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0051] In block 312, a protection layer removal process is performed to remove the protection layer 410, as shown in Figure 4F.

[0052] The protection layer removal process may include any isotropic etch process, such as wet etching or radical etching, or any anisotropic etch process, such as a reactive ion etching (RIE), performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0053] In block 314, a top metal gap-fill process is performed to deposit a top workfunction metal layer 414 within the contact trenches 406 and fill the contact trenches 406 with the contact metal fill material 408, as shown in Figure 4F.

[0054] The top work function metal layer 414 may be formed of Ti Al or TiAIC. The bottom work function metal layer 404 covering the bottom metal gate 202B and the top work function metal layer 414 covering the top metal gate 202T may have different work functions to match the electrical characteristics of the bottom FET module TRBand the top FET module TRT. The contact metal fill material 408 in the top FET module TRTforms top metal gates 202T.

[0055] In the circuit A, the bottom metal gate 202B and the top metal gate 202T, electrically isolated from each other by the split-gate dielectric layer 412, together form a split metal gate. In the circuit B and the circuit C, the bottom metal gate 202B and the top metal gate 202T, electrically connected to each other (not electrically isolated from each other by a split-gate dielectric layer 412), together form a common metal gate.

[0056] The top metal gap-fill process may include any appropriate deposition process, such as such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0057] In some embodiments, the bottom-up split gate dielectric deposition process in block 310 is skipped and the top metal gap-fill process in block 314 is performed to deposit a top work function metal layer 414 within the contact trenches 406 and fill the contact trenches 406 with the contact metal fill material 408, as shown in Figure 4G.

[0058] The contact metal fill material 408 in the top FET module TRTforms top metal gates 202T. Since the split-gate dielectric layer 412 is not formed between the bottom metal gate 202B and the top metal gate 202T, the bottom metal gate 202B and the top metal gate 202T together form a common metal gate.

[0059] In comparison, a split metal gate may be formed in the circuit A and common gates may be formed in the circuit B and the circuit C without the use of the protection layer 410, in which the split-gate dielectric layer 412 is deposited on exposed surfaces of the bottom metal gate 202B in the circuit A, the circuit B, and the circuit C. To form common gates in the circuit B and the circuit C, the split-gate dielectric layer 412 needsto be removed by a patterning process, such as extreme ultraviolet (EUV) lithography, limited by an overlay tolerance. Furthermore, the high-k dielectric layer 212 may be exposed and damaged during the removal of the split-gate dielectric layer 412 in the circuit B and the circuit C.

[0060] Figure 5 depicts a process flow diagram of a method 500 of forming a semiconductor structure 600 that may be the semiconductor structure 400 forming a portion of a complementary field-effect transistor (CFET), after the semiconductor structure 400 shown in Figure 4B is formed, according to one or more embodiments of the present disclosure. The method 500 includes blocks 302-308 and alternative steps to blocks 310 and 312 of the method 300 (including forming a split-gate dielectric layer 412 on exposed surface of the bottom metal gates 208B within the contact trenches 406 in the circuit A). Figures 6A, 6B, 6C, 6D, 6E, 6F, and 6G are isometric views of a portion of the semiconductor structure 600 corresponding to various states of the method 500. In 6A, 6B, 6C, 6D, 6E, 6F, and 6G, a cut-out of the semiconductor structure 600 along the YZ plane including the line A-A shown in Figure 4A, and a cutout of the semiconductor structure 600 along the ZX plane including the line B-B are shown in Figure 4A. It should be understood that Figures 6A, 6B, 6C, 6D, 6E, 6F, and 6G illustrate only partial schematic views of the semiconductor structure 600, and the semiconductor structure 600 may contain any number of transistor sections and additional materials having aspects as illustrated in the figures. It should also be noted that although the method illustrated in Figure 5 is described sequentially, other process sequences that include one or more operations that have been omitted and / or added, and / or has been rearranged in another desirable order, fall within the scope of the embodiments of the disclosure provided herein.

[0061] The method 500 begins with block 502, in which a bottom-up split gate dielectric deposition process is performed, to the semiconductor structure 400 shown in Figure 4B, to selectively deposit a split-gate dielectric layer 412 on exposed surface of the bottom metal gates 208B within the contact trenches 406 and on the high-k dielectric layer 212, as shown in Figure 6A.

[0062] The split-gate dielectric layer 412 may be silicon oxide (SiO ), silicon nitride (Si3N4), silicon carbide (SiC), silicon carbon nitride (SiCN), or silicon carbon oxynitride (SiCON).

[0063] The bottom-up split gate dielectric deposition process may each include a directional selective fill (DSF) process, such as such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0064] In block 504, a bottom-up protection deposition process is performed to selectively deposit a bottom protection layer 602 on exposed surface of the split-gate dielectric layer 412, as shown in Figure 6B.

[0065] The bottom protection layer 602 may be carbon or silicon oxide (SiO ).

[0066] The bottom-up protection deposition process may each include a directional selective fill (DSF) process, such as such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0067] In block 506, a top dielectric layer removal process is performed to remove the split-gate dielectric layer 412 on the high-k dielectric layer 212, as shown in Figure 6C. The split-gate dielectric layer 412 on the bottom metal gates 208B within the contact trenches 406 remain due to the bottom protection layer 602.

[0068] The top dielectric layer removal process may include a wet etch process using hydrofluoric acid (dHF) to remove silicon oxide (SiO ) or using phosphoric acid (H3PO4) to remove silicon nitride (Si3N4), or any appropriate dry radical etching process.

[0069] In block 508, a protection layer removal process is performed to remove the bottom protection layer 602, as shown in Figure 6D.

[0070] The protection layer removal process may include any isotropic etch process, such as wet etching or radical etching, or any anisotropic etch process, such as a reactive ion etching (RIE), performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0071] In block 510, a protection material gap-fill process is performed to deposit a protection layer 410 within the contact trenches 406, as shown in Figure 6E.

[0072] The protection layer 410 may be formed of any gap-fill patterning material, such as carbon.

[0073] The protection material gap-fill process may include any appropriate gap-fill process, such as a chemical vapor deposition (CVD) process, flowable CVD (FCVD) process, or a spin-on process performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0074] In block 512, a protection layer open process is performed to remove the protection layer 410 from the circuit B and the circuit C, as shown in Figure 6F.

[0075] The protection layer open process may include any anisotropic etch process, such as a reactive ion etching (RIE) performed in a processing chamber, such as the processing chamber 120 shown in Figure 1. In a circuit design where the circuit A has enough isotropic etch margin to the circuit B and the circuit C, the protection layer bottom open etch process may include isotropic etch process, performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0076] In block 514, a split gate dielectric removal process to remove the split-gate dielectric layer 412 on the bottom metal gates 208B in the circuit B and the circuit C.

[0077] The split gate dielectric removal process may include a wet etch process using hydrofluoric acid (dHF) to remove silicon oxide (SiO ) or using phosphoric acid (H3PO4) to remove silicon nitride (Si3N4), or any appropriate dry radical etching process.

[0078] In block 516, a protection layer removal process is performed to remove the protection layer 410, as shown in Figure 6G.

[0079] The protection layer removal process may include any isotropic etch process, such as wet etching or radical etching, or any anisotropic etch process, such as a reactive ion etching (RIE), performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0080] In block 518, a top metal gap-fill process is performed to deposit a top work function metal layer 414 within the contact trenches 406 and fill the contact trenches 406 with the contact metal fill material 408, to arrive the semiconductor structure 400 shown in Figure 4F.

[0081] The top work function metal layer 414 may be formed of Ti Al or TiAIC. The bottom work function metal layer 404 covering the bottom metal gate 202B and thetop work function metal layer 414 covering the top metal gate 202T may have different work functions to match the electrical characteristics of the bottom FET module TRBand the top FET module TRT. The contact metal fill material 408 in the top FET module TRTforms top metal gates 202T.

[0082] In the circuit A, the bottom metal gate 202B and the top metal gate 202T, electrically isolated from each other by the split-gate dielectric layer 412, together form a split metal gate. In the circuit B and the circuit C, the bottom metal gate 202B and the top metal gate 202T, electrically connected to each other (not electrically isolated from each other by a split-gate dielectric layer 412), together form a common metal gate.

[0083] The top metal gap-fill process may include any appropriate deposition process, such as such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.

[0084] In some embodiments, the bottom-up split gate dielectric deposition process in block 310 is skipped and the top metal gap-fill process in block 314 is performed to deposit a top work function metal layer 414 within the contact trenches 406 and fill the contact trenches 406 with the contact metal fill material 408, as shown in Figure 4G.

[0085] The contact metal fill material 408 in the top FET module TRTforms top metal gates 202T. Since the split-gate dielectric layer 412 is not formed between the bottom metal gate 202B and the top metal gate 202T, the bottom metal gate 202B and the top metal gate 202T together form a common metal gate.

[0086] In comparison, a split metal gate may be formed in the circuit A and common gates may be formed in the circuit B and the circuit C without the use of the protection layer 410, in which the split-gate dielectric layer 412 is deposited on exposed surfaces of the bottom metal gate 202B in the circuit A, the circuit B, and the circuit C. To form common gates in the circuit B and the circuit C, the split-gate dielectric layer 412 needs to be removed by a patterning process, such as extreme ultraviolet (EUV) lithography, limited by an overlay tolerance. Furthermore, the high-k dielectric layer 212 may be exposed and damaged during the removal of the split-gate dielectric layer 412 in the circuit B and the circuit C.

[0087] In block 508, a protection layer bottom open etch process is performed to remove the protection layer 410 from the contact trenches 406 in the circuit A and leave the protection layer 410 within the contact trenches 406 in the circuit B and the circuit C, as shown in Figure 6D. The contact trenches 406 in the circuit B and the circuit C remain covered by the protection layer 410.

[0088] The protection layer bottom open etch process may include any anisotropic etch process, such as a reactive ion etching (RIE) performed in a processing chamber, such as the processing chamber 120 shown in Figure 1 . In a circuit design where the circuit A has enough isotropic etch margin to the circuit B and the circuit C, the protection layer bottom open etch process may include isotropic etch process, performed in a processing chamber, such as the processing chamber 120 shown in Figure 1.

[0089] The embodiments described herein provide a process integration method that forms common metal gates and split metal gates in one integrated circuit design in CFET devices.

[0090] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:1 . A semiconductor structure , comprising: a bottom field effect transistor (FET) module and a top FET module stacked on the bottom FET module in a first direction; a split metal gate in a first circuit region, the split metal gate comprising a first bottom metal gate, a first top metal gate, and a split-gate dielectric layer between the first bottom metal gate and the first top metal gate; and a common metal gate in a second circuit region, the common metal gate comprising a second bottom metal gate and a second top metal gate, wherein the second top metal gate is electrically connected to the second bottom metal gate.

2. The semiconductor structure of claim 1 , wherein the first bottom metal gate, and the second bottom metal gate each comprise tungsten (W), ruthenium (Ru), or molybdenum (Mo), and are covered by a bottom work function metal layer.

3. The semiconductor structure of claim 2, wherein the bottom work function metal layer comprises WN, TiN, AIN, or MoN.

4. The semiconductor structure of claim 1 , wherein the first top metal gate and the second top metal gate each comprise tungsten (W), ruthenium (Ru), or molybdenum (Mo), and are covered by a top work function metal layer.

5. The semiconductor structure of claim 4, wherein the top work function metal layer comprises TiAl or TiAIC.

6. The semiconductor structure of claim 1 , wherein the split-gate dielectric layer comprises silicon oxide (SiC>2), silicon nitride (SisN4), silicon carbide (SiC), silicon carbon nitride (SiCN), or silicon carbon oxynitride (SiCON).

7. The semiconductor structure of claim 1 , further comprising: a plurality of bottom silicon channel layers extending through the first bottom metal gate; a plurality of top silicon channel layers extending through the first top metalgate; and a middle dielectric isolation (MDI) isolating the plurality of bottom silicon channel layers and the plurality of top silicon channel layers.

8. A method of forming a complementary field-effect transistor (CFET), comprising: depositing a bottom work function metal layer within contact trenches extending through a bottom FET module and a top FET module stacked on the bottom FET module in a first direction; filling the contact trenches with contact metal fill material; removing portions of the bottom work function metal layer and the contact metal fill material in the top FET module; depositing a protection layer within the contact trenches; removing the protection layer from the contact trenches in a first circuit region and leaving the protection layer within the contact trenches in a second circuit region; selectively depositing a split-gate dielectric layer on exposed surfaces of the contact metal fill material within the contact trenches in the first circuit region; removing the protection layer; and depositing a top work function metal layer within the contact trenches and filling the contact trenches with the contact metal fill material.

9. The method of claim 8, wherein the contact metal fill material comprises tungsten (W), ruthenium (Ru), or molybdenum (Mo).

10. The method of claim 8, wherein the bottom work function metal layer comprises WN, TiN, AIN, or MoN.11 . The method of claim 10, wherein the top work function metal layer comprises TiAl or TiAIC.

12. The method of claim 8, wherein the protection layer comprises carbon.

13. The method of claim 8, wherein the depositing of the protection layer comprisesa chemical vapor deposition (CVD) process, flowable CVD (FCVD) process, or a spin- on process.

14. The method of claim 8, wherein the split-gate dielectric layer comprises silicon oxide (SiC>2), silicon nitride (Si3N4), silicon carbide (SiC), silicon carbon nitride (SiCN), or silicon carbon oxynitride (SiCON).

15. The method of claim 8, wherein the selectively depositing of the split-gate dielectric layer comprises a directional selective fill (DSF) process.

16. A method of forming a complementary field-effect transistor (CFET), comprising: depositing a bottom work function metal layer within contact trenches extending through a bottom FET module and a top FET module stacked on the bottom FET module in a first direction; filling the contact trenches with contact metal fill material; removing portions of the bottom work function metal layer and the contact metal fill material in the top FET module; depositing a protection layer within the contact trenches; removing the protection layer from the contact trenches in a first circuit region and leave the protection layer within the contact trenches in a second circuit region; removing the protection layer; and depositing a top work function metal layer within the contact trenches and fill the contact trenches with the contact metal fill material.

17. The method of claim 16, wherein the contact metal fill material comprises tungsten (W), ruthenium (Ru), or molybdenum (Mo).

18. The method of claim 16, wherein the bottom work function metal layer comprises WN, TiN, AIN, or MoN.

19. The method of claim 18, wherein the top work function metal layer comprises TiAl or TiAIC.

20. The method of claim 16, wherein the protection layer comprises carbon.

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