Shift register unit and driving method therefor, light-emission control circuit, and display apparatus

Abstract

Provided are a shift register unit and a driving method therefor, a light-emission control circuit, and a display apparatus, relating to the technical field of display. The shift register unit comprises a preceding-stage decoding circuit and at least two subsequent-stage driving circuits. The preceding-stage decoding circuit is capable of controlling the potential of a control node on the basis of a gating signal provided by at least one gating terminal and a clock signal provided by a clock terminal. Each of the subsequent-stage driving circuits is capable of outputting a first power supply signal or a second power supply signal to a subsequent-stage output terminal on the basis of the potential of the control node. Hence, partitioned gating can be achieved by flexibly configuring gating signals, so that various subsequent-stage driving circuits in different shift register units can flexibly output light-emission control signals to multiple rows of pixels, thereby driving the multiple rows of pixels to emit light. That is, the shift register unit can flexibly refresh pixels on the basis of display-frame partitioning.

Description

Shift register unit and driving method thereof, light emitting control circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a shift register unit and driving method thereof, a light emitting control circuit and a display device. BACKGROUND

[0002] The gate driving circuit and the light emitting control circuit can also be arranged on the display panel by using a gate driver on array (GOA) technology, so as to facilitate the narrow frame design.

[0003] In the related art, the light emitting control circuit generally includes a plurality of GOA units connected in cascade, and the plurality of GOA units are connected in one-to-one correspondence with a plurality of rows of pixels on the display panel, and are used to transmit light emitting control signals to the plurality of rows of pixels row by row, so as to light up the pixels row by row, that is, to realize row-by-row scanning and refreshing, so that the display panel can display a picture.

[0004] However, the driving mode of the light emitting control circuit in the related art is single, and cannot flexibly refresh different regions on the display panel according to the display picture.

[0005] SUMMARY

[0006] A shift register unit and driving method thereof, a light emitting control circuit and a display device are provided. The technical solutions are as follows:

[0007] In one aspect, a shift register unit is provided, which includes a front-stage decoding circuit and at least two back-stage driving circuits.

[0008] The front-stage decoding circuit includes a pre-charge circuit connected with at least two gate control terminals, a first clock terminal, a second clock terminal and a control node, and used to control the on-off of the first clock terminal and the control node in response to a gate signal provided by each of the gate control terminals, a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal; and each of the back-stage driving circuits includes:

[0009] an input circuit connected with the control node, a control clock terminal, an input clock terminal and a back-stage pull-up node, and used to control the on-off of the input clock terminal and the back-stage pull-up node in response to the potential of the control node, a control clock signal provided by the control clock terminal and an input clock signal provided by the input clock terminal.

[0010] A post-stage pull-down control circuit is connected with the control node, the control clock end, the post-stage pull-up node, the first power supply end and the post-stage pull-down node respectively, and is configured to control the on-off of the control clock end and the post-stage pull-down node in response to the potential of the control node, and control the on-off of the first power supply end and the post-stage pull-down node in response to the potential of the post-stage pull-up node.

[0011] A post-stage pull-down circuit is connected with the post-stage pull-down node, the first power supply end and the post-stage output end respectively, and is configured to control the on-off of the first power supply end and the post-stage output end in response to the potential of the post-stage pull-down node.

[0012] A post-stage output circuit is connected with the post-stage pull-up node, the second power supply end and the post-stage output end respectively, and is configured to control the on-off of the second power supply end and the post-stage output end in response to the potential of the post-stage pull-up node, so as to output a light-emitting control signal through the post-stage output end.

[0013] Optionally, the post-stage pull-down control circuit comprises:

[0014] A first pull-down control sub-circuit is connected with the control node, the control clock end and the post-stage pull-down node respectively, and is configured to control the on-off of the control clock end and the post-stage pull-down node in response to the potential of the control node.

[0015] A second pull-down control sub-circuit is connected with the post-stage pull-up node, the first power supply end and the post-stage pull-down node respectively, and is configured to control the on-off of the first power supply end and the post-stage pull-down node in response to the potential of the post-stage pull-up node.

[0016] Optionally, the first pull-down control sub-circuit comprises a first transistor.

[0017] The gate of the first transistor is connected with the control node, the first pole of the first transistor is connected with the control clock end, and the second pole of the first transistor is connected with the post-stage pull-down node.

[0018] Optionally, the second pull-down control sub-circuit comprises a second transistor.

[0019] The gate of the second transistor is connected with the post-stage pull-up node, the first pole of the second transistor is connected with the first power supply end, and the second pole of the second transistor is connected with the post-stage pull-down node.

[0020] Optionally, the post-stage driving circuit further comprises:

[0021] A first holding circuit is connected between the first pull-down control sub-circuit and the back-stage pull-down node, and is also connected with the control clock end, and is configured to control the first pull-down control sub-circuit and the back-stage pull-down node in response to the control clock signal.

[0022] Optionally, the first holding circuit comprises a third transistor.

[0023] The gate of the third transistor is connected with the control clock end, the first pole of the third transistor is connected with the first pull-down control sub-circuit, and the second pole of the third transistor is connected with the back-stage pull-down node.

[0024] Optionally, the back-stage driving circuit further comprises:

[0025] A second holding circuit is connected with the first power supply end and the back-stage pull-down node respectively, and is configured to maintain the potential of the back-stage pull-down node based on the first power supply signal provided by the first power supply end.

[0026] Optionally, the second holding circuit comprises a first capacitor.

[0027] One end of the first capacitor is connected with the first power supply end, and the other end of the first capacitor is connected with the back-stage pull-down node.

[0028] Optionally, the back-stage driving circuit further comprises:

[0029] A back-stage isolation circuit is connected between the back-stage pull-up node and the back-stage output circuit, and is also connected with the second power supply end, and is configured to control the back-stage pull-up node and the back-stage output circuit to be conductive in response to the second power supply signal.

[0030] Optionally, the back-stage isolation circuit comprises a fourth transistor.

[0031] The gate of the fourth transistor is connected with the second power supply end, the first pole of the fourth transistor is connected with the back-stage pull-up node, and the second pole of the fourth transistor is connected with the back-stage output circuit.

[0032] Optionally, the back-stage pull-down circuit comprises a fifth transistor.

[0033] The gate of the fifth transistor is connected with the back-stage pull-down node, the first pole of the fifth transistor is connected with the first power supply end, and the second pole of the fifth transistor is connected with the back-stage output end.

[0034] Optionally, the fifth transistor comprises a first sub-transistor and a second sub-transistor connected in series.

[0035] The gate of the first sub-transistor and the gate of the second sub-transistor are connected with the post-stage pull-down node, the first pole of the first sub-transistor is connected with the first power supply end, the second pole of the first sub-transistor is connected with the first pole of the second sub-transistor, and the second pole of the second sub-transistor is connected with the post-stage output end; the post-stage driving circuit further comprises:

[0036] An anti-creeping circuit is connected with the post-stage output end, the second power supply end and the series connection node of the first sub-transistor and the second sub-transistor respectively, and is used for controlling the on-off of the second power supply end and the series connection node in response to the potential of the post-stage output end.

[0037] Optionally, the anti-creeping circuit comprises a sixth transistor.

[0038] The gate of the sixth transistor is connected with the post-stage output end, the first pole of the sixth transistor is connected with the second power supply end, and the second pole of the sixth transistor is connected with the series connection node.

[0039] Optionally, the input circuit comprises a seventh transistor, an eighth transistor and a ninth transistor.

[0040] The gate and the first pole of the seventh transistor are connected with the input clock end, and the second pole of the seventh transistor is connected with the post-stage pull-up node.

[0041] The gate of the eighth transistor is connected with the control node, the first pole of the eighth transistor is connected with the second pole of the ninth transistor, and the second pole of the eighth transistor is connected with the post-stage pull-up node.

[0042] The gate of the ninth transistor is connected with the control clock end, and the first pole of the ninth transistor is connected with the input clock end.

[0043] Optionally, the post-stage output circuit comprises a tenth transistor and a second capacitor.

[0044] The gate of the tenth transistor is connected with the post-stage pull-up node, the first pole of the tenth transistor is connected with the second power supply end, and the second pole of the tenth transistor is connected with the post-stage output end.

[0045] One end of the second capacitor is connected with the post-stage pull-up node, and the other end of the second capacitor is connected with the post-stage output end.

[0046] Optionally, the pre-charge circuit is further connected with the second power supply end and is used for storing the potential of the control node based on the second power supply signal; the pre-stage decoding circuit further comprises:

[0047] A charging circuit is connected with the control node, the second clock terminal, the third clock terminal, the second power supply terminal and the front-stage pull-up node respectively, and is configured to control the on-off of the second power supply terminal and the front-stage pull-up node in response to the potential of the control node and the third clock signal provided by the third clock terminal, and control the on-off of the third clock terminal and the front-stage pull-up node in response to the second clock signal;

[0048] A reset circuit is connected with the reset terminal, the first power supply terminal, the control node and the front-stage pull-up node respectively, and is configured to control the on-off of the first power supply terminal and the control node in response to the reset signal provided by the reset terminal, and control the on-off of the first power supply terminal and the front-stage pull-up node;

[0049] At least two front-stage output circuits are connected with the front-stage pull-up node, one-to-one corresponding at least two output clock terminals and one-to-one corresponding at least two front-stage output terminals respectively, and each front-stage output circuit is configured to control the on-off of the corresponding one output clock terminal and one front-stage output terminal in response to the potential of the front-stage pull-up node;

[0050] A front-stage pull-down control circuit is connected with the control node, the second clock terminal, the third clock terminal, the first power supply terminal, the second power supply terminal, the front-stage pull-up node and a front-stage pull-down node respectively, and is configured to control the on-off of the second clock terminal and the front-stage pull-down node in response to the potential of the control node and the third clock signal, control the on-off of the second power supply terminal and the front-stage pull-down node in response to the second clock signal, control the on-off of the second clock terminal and the front-stage pull-down node in response to the potential of the front-stage pull-up node, and store the potential of the front-stage pull-down node based on the first power supply signal;

[0051] A front-stage pull-down circuit is connected with the front-stage pull-down node, the first power supply terminal, the front-stage pull-up node and the at least two front-stage output terminals respectively, and is configured to control the on-off of the first power supply terminal and the front-stage pull-up node in response to the potential of the front-stage pull-down node, and control the on-off of the first power supply terminal and each front-stage output terminal, so as to output a gate drive signal through the front-stage output terminal.

[0052] Optionally, the front-stage decoding circuit further comprises:

[0053] A first front-stage isolation circuit is connected between the control node and the front-stage pull-down control circuit, and is further connected with the second power supply terminal, and is configured to control the conduction of the control node and the front-stage pull-down control circuit in response to the second power supply signal;

[0054] A second pre-stage isolation circuit is connected between the pre-stage pull-up node and the at least two pre-stage output circuits, and is also connected with the second power supply terminal, and is configured to control the pre-stage pull-up node and the at least two pre-stage output circuits to be conductive in response to the second power supply signal.

[0055] In another aspect, a driving method of a shift register unit is provided for driving the shift register unit according to any one of the preceding aspects; the method comprises:

[0056] In a first stage, in the pre-stage decoding circuit, a pre-charge circuit controls the first clock terminal and the control node to be conductive in response to a gate signal provided by each of the at least two gate terminals, a first clock signal provided by the first clock terminal, and a second clock signal provided by the second clock terminal.

[0057] In a second stage, in each of the post-stage driving circuits, a post-stage input circuit controls the input clock terminal and the post-stage pull-up node to be conductive in response to a potential of the control node, a control clock signal provided by the control clock terminal, and an input clock signal provided by the input clock terminal, a post-stage pull-down control circuit controls the control clock terminal and the post-stage pull-down node to be conductive in response to the potential of the control node, and a post-stage pull-down circuit controls the first power supply terminal and the post-stage output terminal to be conductive in response to a potential of the post-stage pull-down node.

[0058] In a third stage, in each of the post-stage driving circuits, the post-stage input circuit controls the input clock terminal and the post-stage pull-up node to be conductive in response to the input clock signal, the post-stage pull-down control circuit controls the control clock terminal and the post-stage pull-down node to be conductive in response to the potential of the control node and the potential of the post-stage pull-up node, and the post-stage output circuit controls the second power supply terminal and the post-stage output terminal to be conductive in response to the potential of the post-stage pull-up node.

[0059] In yet another aspect, a light emitting control circuit is provided, comprising: a plurality of groups of shift register units, each group of the shift register units comprising: at least two shift register units according to any one of the preceding aspects;

[0060] Each group of the shift register units shares the first clock terminal, the second clock terminal, the control clock terminal, the input clock terminal, and the gate terminals, and each group of the shift register units is configured to receive different gate signals provided by the at least two gate terminals.

[0061] In still another aspect, a display device is provided, comprising: a display panel, and a light emitting control circuit according to the yet another aspect described above;

[0062] The display panel includes a plurality of pixels, and the light-emitting control circuit is connected with the plurality of pixels and is configured to transmit a light-emitting control signal to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0064] FIG. 1 is a structural schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0065] FIG. 2 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0066] FIG. 3 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0067] FIG. 4 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0068] FIG. 5 is a circuit structural schematic diagram of a post-stage driving circuit according to an embodiment of the present disclosure;

[0069] FIG. 6 is a circuit structural schematic diagram of another post-stage driving circuit according to an embodiment of the present disclosure;

[0070] FIG. 7 is a circuit structural schematic diagram of another post-stage driving circuit according to an embodiment of the present disclosure;

[0071] FIG. 8 is a circuit structural schematic diagram of another post-stage driving circuit according to an embodiment of the present disclosure;

[0072] FIG. 9 is a structural schematic diagram of a pre-stage decoding circuit according to an embodiment of the present disclosure;

[0073] FIG. 10 is a structural schematic diagram of another pre-stage decoding circuit according to an embodiment of the present disclosure;

[0074] FIG. 11 is a circuit structural schematic diagram of a pre-stage decoding circuit according to an embodiment of the present disclosure;

[0075] FIG. 12 is a structural schematic diagram of another shift register unit according to an embodiment of the present disclosure;

[0076] FIG. 13 is a circuit structural schematic diagram of a shift register unit according to an embodiment of the present disclosure;

[0077] FIG. 14 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure;

[0078] FIG. 15 is a structural diagram of a light emitting control circuit according to an embodiment of the present disclosure;

[0079] FIG. 16 is a timing diagram of a shift register unit according to an embodiment of the present disclosure;

[0080] FIG. 17 is a timing diagram of a gate signal according to an embodiment of the present disclosure;

[0081] FIG. 18 is a structural diagram of a display device according to an embodiment of the present disclosure;

[0082] FIG. 19 is a structural diagram of a pixel according to an embodiment of the present disclosure;

[0083] FIG. 20 is a timing diagram of a pixel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] For the purpose of the present disclosure, the technical solutions and advantages will be more apparent, the embodiments of the present disclosure will be described in further detail below with reference to the drawings.

[0085] It should be noted that the transistors used in all embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchangeable, and the source is referred to as the first pole and the drain is referred to as the second pole, or the drain is referred to as the first pole and the source is referred to as the second pole. According to the form in the drawings, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain. In addition, the switching transistor used in the embodiments of the present disclosure can include any one of a P-type transistor and an N-type transistor or a combination thereof. Among them, the P-type transistor is turned on when the gate is low voltage, and is turned off when the gate is high voltage, and the N-type transistor is turned on when the gate is high voltage, and is turned off when the gate is low voltage. In addition, the plurality of signals in each embodiment correspond to a first potential and a second potential, and the first potential and the second potential only represent that the potential of the signal has two different states, and do not represent that the first potential or the second potential has a specific value.

[0086] High-end display has strict requirements on image quality, especially game professional display, which usually needs high refresh rate. In order to better compatible low power consumption and high refresh rate, the partition high refresh technology (also can be called frame rate conversion technology) is generally used, which separately uses high refresh rate for dynamic picture. This technology requires that each GOA unit in the gate drive circuit and each GOA unit in the light emitting control circuit can work flexibly and has random gating capability. In addition, with the increase of resolution, and the popularity of virtual reality (VR) display, augmented reality (AR) and three-dimensional (3-dimension, 3D) display applications, in order to reduce the amount of frame transmission data, the gate drive circuit and the light emitting control circuit also need to have random gating capability.

[0087] However, each GOA unit in the common gate drive circuit can provide a gate drive signal to each row of pixels in the display row by row, so that each row of pixels is turned on row by row, and cannot be adjusted in real time according to the picture to be displayed, which cannot meet the current display requirements. Or in some implementation ways, it is also considered to partition the multiple rows of pixels, and the multiple GOA units included in the gate drive circuit are also partitioned and designed accordingly, so that the high refresh rate of a partition can be locally controlled. However, after partitioning the gate drive circuit, the GOA units of each partition are no longer cascaded, so it is necessary to separately set an opening signal end STU for the GOA units of each partition to drive the GOA units in the partition to work, and in some embodiments, it is also necessary to separately set a dummy GOA for the GOA units of each partition. In this way, not only the hardware complexity and cost are increased, but also the number of partitions is limited. And the light emitting control circuit cannot be partitioned and worked at present, and does not have random gating capability.

[0088] Based on this, the embodiment of the disclosure provides a decoder type GOA unit, which can make the light emitting control circuit have random gating capability when applied to the light emitting control circuit, and is especially suitable for the display which needs partition high refresh. FIG. 1 is a structural schematic diagram of a shift register unit provided by the embodiment of the disclosure. As shown in FIG. 1, the shift register unit includes a front-stage decoding circuit 10 and at least two rear-stage drive circuits 00.

[0089] As shown in FIG. 2, the front-stage decoding circuit 10 includes a pre-charge circuit 11.

[0090] The pre-charge circuit 11 is connected with at least two gate terminals D0...Dm, a first clock terminal CLK1, a second clock terminal CLK2 and a control node P, and is configured to control the on-off of the first clock terminal CLK1 and the control node P in response to a gate signal provided by each of the at least two gate terminals D0...Dm, a first clock signal provided by the first clock terminal CLK1 and a second clock signal provided by the second clock terminal CLK2. m is an integer greater than 1. For example, m can be 7, 9 or other.

[0091] In an example, the potential of the first clock signal and the potential of the second clock signal are generally opposite in the same period. Thus, assuming that the potential of the gate signal provided by any gate terminal is a first potential, the pre-charge circuit 11 can control the first clock terminal CLK1 and the control node P to be conductive when the potential of the first clock signal is the first potential and the potential of the second clock signal is a second potential, so that the first clock terminal CLK1 transmits the first clock signal of the first potential to the control node P; and can control the first clock terminal CLK1 and the control node P to be conductive when the potential of the second clock signal is the first potential and the potential of the first clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal of the second potential to the control node P. Assuming that the potential of the gate signal provided by each gate terminal is the second potential, the pre-charge circuit 11 can control the first clock terminal CLK1 and the control node P to be conductive when the potential of the first clock signal is the first potential and the potential of the second clock signal is the second potential, so that the first clock terminal CLK1 transmits the first clock signal to the control node P; and can control the first clock terminal CLK1 and the control node P to be disconnected when the potential of the second clock signal is the first potential and the potential of the first clock signal is the second potential.

[0092] That is, the current shift register unit can be gated or not gated by controlling the potential of the gate signal provided by each of the at least two gate terminals D0...Dm. If the current shift register unit is gated, it can normally output a signal, and if the current shift register unit is not gated, it will not output a signal, so as to achieve the purpose of controlling the refresh frequency.

[0093] Optionally, the frequency of the gate signal provided by each of the gate terminals D0 to Dm can be sequentially reduced, that is, the pulse of the gate signal provided by each of the gate terminals can be sequentially reduced.

[0094] Optionally, in the embodiments of the present disclosure, the first potential can be a valid potential, and the second potential can be an invalid potential. For a P-type transistor in the circuit, the first potential can be a low potential relative to the second potential. For an N-type transistor in the circuit, the first potential can be a high potential relative to the second potential.

[0095] With reference back to FIG. 2, it can be seen that each back-stage driving circuit 00 comprises an input circuit 01, a back-stage pull-down control circuit 02, a back-stage pull-down circuit 03, and a back-stage output circuit 04.

[0096] The input circuit 01 is connected with the control node P, the control clock terminal CLKE, the input clock terminal CLKP and the back-stage pull-up node Q_em respectively, and is configured to control the on-off of the input clock terminal CLKP and the back-stage pull-up node Q_em in response to the potential of the control node P, the control clock signal provided by the control clock terminal CLKE and the input clock signal provided by the input clock terminal CLKP.

[0097] For example, the input circuit 01 can control the input clock terminal CLKP and the back-stage pull-up node Q_em to be connected when the potential of the control node P is the first potential and the potential of the control clock signal is the first potential, or control the input clock terminal CLKP and the back-stage pull-up node Q_em to be connected when the potential of the input clock signal is the first potential, so that the input clock terminal CLKP transmits the input clock signal to the back-stage pull-up node Q_em; and can control the input clock terminal CLKP and the back-stage pull-up node Q_em to be disconnected when the potential of the control node P is the second potential and / or the potential of the control clock signal is the second potential, or control the input clock terminal CLKP and the back-stage pull-up node Q_em to be disconnected when the potential of the input clock signal is the second potential.

[0098] The back-stage pull-down control circuit 02 is connected with the control node P, the control clock terminal CLKE, the back-stage pull-up node Q_em, the first power supply terminal VGH and the back-stage pull-down node QB_em respectively, and is configured to control the on-off of the control clock terminal CLKE and the back-stage pull-down node QB_em in response to the potential of the control node P, and control the on-off of the first power supply terminal VGH and the back-stage pull-down node QB_em in response to the potential of the back-stage pull-up node Q_em.

[0099] For example, the pull-down control circuit 02 can control the control clock terminal CLKE to be connected to the pull-down node QB_em when the potential of the control node P is the first potential, so that the control clock terminal CLKE transmits the control clock signal to the pull-down node QB_em; and can control the control clock terminal CLKE to be disconnected from the pull-down node QB_em when the potential of the control node P is the second potential. Similarly, the pull-down control circuit 02 can control the first power terminal VGH to be connected to the pull-down node QB_em when the potential of the pull-up node Q_em is the first potential, so that the first power terminal VGH transmits the first power signal to the pull-down node QB_em; and can control the first power terminal VGH to be disconnected from the pull-down node QB_em when the potential of the pull-up node Q_em is the second potential. The potential of the first power signal can be a high potential.

[0100] The pull-down circuit 03 is connected to the pull-down node QB_em, the first power terminal VGH and the output terminal EM respectively, and is configured to control the first power terminal VGH and the output terminal EM in response to the potential of the pull-down node QB_em.

[0101] For example, the pull-down circuit 03 can control the first power terminal VGH to be connected to the output terminal EM when the potential of the pull-down node QB_em is the first potential, so that the first power terminal VGH transmits the first power signal to the output terminal EM; and can control the first power terminal VGH to be disconnected from the output terminal EM when the potential of the pull-down node QB_em is the second potential.

[0102] The output circuit 04 is connected to the pull-up node Q_em, the second power terminal VGL and the output terminal EM respectively, and is configured to control the second power terminal VGL and the output terminal EM in response to the potential of the pull-up node Q_em, so as to output the light control signal through the output terminal EM. Thus, the pull-down driving circuit 00 is also a shift register unit included in the light control circuit.

[0103] For example, the output circuit 04 can control the second power terminal VGL to be connected to the output terminal EM when the potential of the pull-up node Q_em is the first potential, so that the second power terminal VGL transmits the second power signal to the output terminal EM; and can control the second power terminal VGL to be disconnected from the output terminal EM when the potential of the pull-up node Q_em is the second potential. The potential of the second power signal can be a low potential.

[0104] 1 , the pre-stage decoding circuit 10 and at least two post-stage driving circuits 00 can be connected to the same control node P. The pre-stage decoding circuit 10 can control the potential of the control node P based on a strobe signal and a clock signal. The at least two post-stage driving circuits 00 can each output a light emission control signal through a post-stage output terminal EM based on the potential of the control node P.

[0105] It will be understood that, referring to FIG. 1 , at least two subsequent driver circuits 00 can be connected to at least two output terminals EM1 ... EMn in a one-to-one correspondence, and these at least two output terminals EM1 ... EMn can be connected to multiple rows of pixels in a one-to-one correspondence. Furthermore, each subsequent driver circuit 00 can be connected to a different control clock terminal CLKE and a different output clock terminal CLKP, so that light emission control signals are output row by row to the multiple rows of pixels. Here, n can be an integer greater than 1. For example, n can be 2, 4, or other values.

[0106] In summary, an embodiment of the present disclosure provides a shift register unit. The shift register unit includes: a front-stage decoding circuit and at least two rear-stage driving circuits. The front-stage decoding circuit is capable of controlling the potential of a control node based on a gating signal provided by at least one gating terminal and a clock signal provided by a clock terminal. In each rear-stage driving circuit, the input circuit and the rear-stage pull-down control circuit are capable of controlling the potential of the rear-stage pull-up node and the potential of the rear-stage pull-down node respectively based on the potential of the control node, so that the rear-stage pull-down circuit outputs a first power signal to the rear-stage output terminal based on the potential of the rear-stage pull-down node, and the rear-stage output circuit outputs a second power signal to the rear-stage output terminal based on the potential of the rear-stage pull-up node. In this way, partition gating can be achieved by flexibly setting the gating signal, so that each rear-stage driving circuit in different shift register units flexibly outputs a light-emitting control signal to multiple rows of pixels to drive multiple rows of pixels to emit light. That is, the shift register unit provided by the embodiment of the present disclosure can flexibly refresh pixels according to the partitioning of the display screen.

[0107] Alternatively, FIG3 is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG3 , the subsequent pull-down control circuit 02 may include: a first pull-down control sub-circuit 021 and a second pull-down control sub-circuit 022 .

[0108] Among them, the first pull-down control sub-circuit 021 can be connected to the control node P, the control clock terminal CLKE and the subsequent pull-down node QB_em respectively, and can be used to control the connection and disconnection of the control clock terminal CLKE and the subsequent pull-down node QB_em in response to the potential of the control node P.

[0109] For example, the first pull-down control sub-circuit 021 can control the control clock terminal CLKE to be connected with the pull-down node QB_em when the potential of the control node P is the first potential, and can control the control clock terminal CLKE to be disconnected from the pull-down node QB_em when the potential of the control node P is the second potential.

[0110] The second pull-down control sub-circuit 022 can be connected with the pull-up node Q_em, the first power supply terminal VGH and the pull-down node QB_em respectively, and can be used to control the first power supply terminal VGH to be connected with the pull-down node QB_em in response to the potential of the pull-up node Q_em.

[0111] For example, the second pull-down control sub-circuit 022 can control the first power supply terminal VGH to be connected with the pull-down node QB_em when the potential of the pull-up node Q_em is the first potential, and can control the first power supply terminal VGH to be disconnected from the pull-down node QB_em when the potential of the pull-up node Q_em is the second potential.

[0112] Optionally, based on FIG. 3, FIG. 4 shows another structure diagram of a shift register unit provided by the embodiment of the present disclosure. As shown in FIG. 4, the post-stage driving circuit 00 can further include a first holding circuit 05.

[0113] The first holding circuit 05 can be connected between the first pull-down control sub-circuit 021 and the pull-down node QB_em, and can be further connected with the control clock terminal CLKE, and can be used to control the first pull-down control sub-circuit 021 to be connected with the pull-down node QB_em in response to the control clock signal.

[0114] For example, the first holding circuit 05 can control the first pull-down control sub-circuit 021 to be connected with the pull-down node QB_em when the potential of the control clock signal is the first potential, and can control the first pull-down control sub-circuit 021 to be disconnected from the pull-down node QB_em when the potential of the control clock signal is the second potential.

[0115] That is, the first pull-down control sub-circuit 021 can be indirectly connected with the pull-down node QB_em through the first holding circuit 05. In this way, when the potential of the control clock signal is the second potential (for example, high potential), the first holding circuit 05 can reliably control the first pull-down control sub-circuit 021 to be disconnected from the pull-down node QB_em, so as to avoid the control clock signal from leaking to the pull-down node QB_em through the first pull-down control sub-circuit 021, that is, the potential of the pull-down node QB_em can be better maintained.

[0116] Optionally, referring to Fig. 4 again, it can also be seen that the post-stage driving circuit 00 can further comprise a second holding circuit 06.

[0117] The second holding circuit 06 can be connected with the first power supply end VGH and the post-stage pull-down node QB_em respectively, and can be used to hold the potential of the post-stage pull-down node QB_em based on the first power supply signal provided by the first power supply end VGH. In this way, the potential of the post-stage pull-down node QB_em can be further maintained better.

[0118] Optionally, referring to Fig. 3 and Fig. 4 again, it can also be seen that the post-stage driving circuit 00 can further comprise a post-stage isolation circuit 07.

[0119] The post-stage isolation circuit 07 can be connected between the post-stage pull-up node Q_em and the post-stage output circuit 04, and can also be connected with the second power supply end VGL, and can be used to control the post-stage pull-up node Q_em and the post-stage output circuit 04 to be turned on in response to the second power supply signal.

[0120] It can be understood that by setting the post-stage isolation circuit 07, the post-stage output circuit 04 can be prevented from being misoperated due to the leakage of the pull-up node Q_em, that is, the working reliability of the post-stage output circuit 04 can be ensured to be better.

[0121] Optionally, based on Fig. 3, Fig. 5 shows a circuit structure schematic diagram of a shift register unit. Based on Fig. 4, Fig. 6 shows another circuit structure schematic diagram of a shift register unit. Referring to Fig. 5 and Fig. 6, it can be seen that the first pull-down control sub-circuit 021 can comprise a first transistor T1.

[0122] The gate of the first transistor T1 can be connected with the control node P, the first pole of the first transistor T1 can be connected with the control clock end CLKE, and the second pole of the first transistor T1 can be connected with the post-stage pull-down node QB_em.

[0123] Optionally, referring to Fig. 5 and Fig. 6 again, it can be seen that the second pull-down control sub-circuit 022 can comprise a second transistor T2.

[0124] The gate of the second transistor T2 can be connected with the post-stage pull-up node Q_em, the first pole of the second transistor T2 can be connected with the first power supply end VGH, and the second pole of the second transistor T2 can be connected with the post-stage pull-down node QB_em.

[0125] Optionally, referring to Fig. 6 again, it can be seen that the first holding circuit 05 can comprise a third transistor T3.

[0126] The gate of the third transistor T3 can be connected with the control clock end CLKE, the first pole of the third transistor T3 can be connected with the first pull-down control sub-circuit 021, and the second pole of the third transistor T3 can be connected with the rear-stage pull-down node QB_em. It can be understood that the first pole of the third transistor T3 can be connected with the second pole of the first transistor T1 included in the first pull-down control sub-circuit 021.

[0127] Optionally, with continuous reference to FIG. 6, it can be seen that the second holding circuit 06 can include a first capacitor C1.

[0128] One end of the first capacitor C1 can be connected with the first power supply end VGH, and the other end of the first capacitor C1 can be connected with the rear-stage pull-down node QB_em. That is, the first capacitor C1 can be connected in series between the first power supply end VGH and the rear-stage pull-down node QB_em.

[0129] Optionally, with continuous reference to FIG. 5 and FIG. 6, it can be seen that the rear-stage isolation circuit 07 can include a fourth transistor T4.

[0130] The gate of the fourth transistor T4 can be connected with the second power supply end VGL, the first pole of the fourth transistor T4 can be connected with the rear-stage pull-up node Q_em, and the second pole of the fourth transistor T4 can be connected with the rear-stage output circuit 04.

[0131] Optionally, with continuous reference to FIG. 5 and FIG. 6, it can be seen that the rear-stage pull-down circuit 03 can include a fifth transistor T5.

[0132] The gate of the fifth transistor T5 can be connected with the rear-stage pull-down node QB_em, the first pole of the fifth transistor T5 can be connected with the first power supply end VGH, and the second pole of the fifth transistor T5 can be connected with the rear-stage output end EM.

[0133] Optionally, based on FIG. 6, FIG. 7 shows another circuit structure schematic diagram of a shift register unit. As shown in FIG. 7, the fifth transistor T5 can include a first sub-transistor T51 and a second sub-transistor T52 connected in series.

[0134] The gate of the first sub-transistor T51 and the gate of the second sub-transistor T52 can be connected with the rear-stage pull-down node QB_em, the first pole of the first sub-transistor T51 can be connected with the first power supply end VGH, the second pole of the first sub-transistor T51 can be connected with the first pole of the second sub-transistor T52, and the second pole of the second sub-transistor T52 can be connected with the rear-stage output end EM. On this basis, the rear-stage driving circuit 00 can further include an anti-leakage circuit 08.

[0135] The leakage prevention circuit 08 can be connected with the output end EM, the second power supply end VGL and the series connection node S of the first sub-transistor T51 and the second sub-transistor T52 respectively, and can be used to control the connection between the second power supply end VGL and the series connection node S in response to the potential of the output end EM.

[0136] For example, the leakage prevention circuit 08 can control the second power supply end VGL to be connected with the series connection node S when the potential of the output end EM is the first potential, so that the second power supply end VGL transmits the second power supply signal to the series connection node S; and can control the second power supply end VGL to be disconnected with the series connection node S when the potential of the output end EM is the second potential.

[0137] It can be understood that when the potential of the pull-down node QB_em is the first potential (e.g. low potential), the pull-down circuit 03 can control the first power supply end VGH to be connected with the output end EM, so that the first power supply end VGH transmits the first power supply signal with high potential to the output end EM. Further, the leakage prevention circuit 08 can control the second power supply end VGL to be disconnected with the series connection node S. When the potential of the pull-up node Q_em is the first potential (e.g. low potential), the pull-up circuit 04 can control the second power supply end VGL to be connected with the output end EM, so that the second power supply end VGL transmits the first power supply signal with low potential to the output end EM. Further, the leakage prevention circuit 08 can control the second power supply end VGL to be connected with the series connection node S. In this way, the leakage current of the pull-down circuit 03 can be reduced.

[0138] Optionally, based on FIG. 7, FIG. 8 shows another circuit structure schematic diagram of a shift register unit. As shown in FIG. 8, the leakage prevention circuit 08 can include a sixth transistor T6.

[0139] The gate of the sixth transistor T6 can be connected with the output end EM, the first pole of the sixth transistor T6 can be connected with the second power supply end VGL, and the second pole of the sixth transistor T6 can be connected with the series connection node S.

[0140] Optionally, it can also be seen from FIGS. 5 to 8 that the input circuit 01 can include a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9.

[0141] The gate and the first pole of the seventh transistor T7 can be connected with the input clock end CLKP, and the second pole of the seventh transistor T7 can be connected with the pull-up node Q_em.

[0142] The gate of the eighth transistor T8 can be connected with the control node P, the first pole of the eighth transistor T8 can be connected with the second pole of the ninth transistor T9, and the second pole of the eighth transistor T8 can be connected with the pull-up node Q_em.

[0143] The gate of the ninth transistor T9 can be connected with the control clock end CLKE, and the first pole of the ninth transistor T9 can be connected with the input clock end CLKP.

[0144] Optionally, with continuous reference to FIGS. 5 to 8, it can also be seen that the post-stage output circuit 04 can include a tenth transistor T10 and a second capacitor C2.

[0145] The gate of the tenth transistor T10 can be connected with the post-stage pull-up node Q_em, the first pole of the tenth transistor T10 can be connected with the second power end VGL, and the second pole of the tenth transistor T10 can be connected with the post-stage output end EM.

[0146] One end of the second capacitor C2 can be connected with the post-stage pull-up node Q_em, and the other end of the second capacitor C2 can be connected with the post-stage output end EM. That is, the second capacitor C2 can be connected in series between the post-stage pull-up node Q_em and the post-stage output end EM.

[0147] Optionally, FIG. 9 is a structural schematic diagram of a pre-stage decoding circuit provided by an embodiment of the present disclosure. As shown in FIG. 9, the pre-charge circuit 11 can also be connected with the second power end VGL and can be used to store the potential of the control node based on the second power signal. Moreover, the pre-stage decoding circuit 10 can further include a charging circuit 12, a reset circuit 13, at least two pre-stage output circuits 14, a pre-stage pull-down control circuit 15, and a pre-stage pull-down circuit 16.

[0148] The charging circuit 12 can be connected with the control node P, the second clock end CLK2, the third clock end CLK3, the second power end VGL and the pre-stage pull-up node Q respectively, and can be used to control the on-off of the second power end VGL and the pre-stage pull-up node Q in response to the potential of the control node P and the third clock signal provided by the third clock end CLK3, and can be used to control the on-off of the third clock end CLK3 and the pre-stage pull-up node Q in response to the second clock signal.

[0149] For example, the charging circuit 12 can control the second power supply end VGL to be connected to the front-stage pull-up node Q when the potential of the control node P is the first potential and the potential of the third clock signal is the first potential, so that the second power supply end VGL transmits the second power supply signal to the front-stage pull-up node Q; and can control the second power supply end VGL to be disconnected from the front-stage pull-up node Q when the potential of the control node P is the second potential and / or the potential of the third clock signal is the second potential. Similarly, the charging circuit 12 can control the third clock end CLK3 to be connected to the front-stage pull-up node Q when the potential of the second clock signal is the first potential, so that the third clock end CLK3 transmits the third clock signal to the front-stage pull-up node Q; and can control the third clock end CLK3 to be disconnected from the front-stage pull-up node Q when the potential of the second clock signal is the second potential.

[0150] The reset circuit 13 can be connected to the reset end TRS, the first power supply end VGH, the control node P and the front-stage pull-up node Q respectively, and can be used to control the connection and disconnection of the first power supply end VGH and the control node P, and the connection and disconnection of the first power supply end VGH and the front-stage pull-up node Q in response to a reset signal provided by the reset end TRS.

[0151] For example, the reset circuit 13 can control the first power supply end VGH to be connected to the control node P and the front-stage pull-up node Q when the potential of the reset signal is the first potential, so that the first power supply end VGH transmits the first power supply signal to the control node P and the front-stage pull-up node Q; and can control the first power supply end VGH to be disconnected from the control node P and the front-stage pull-up node Q when the potential of the reset signal is the second potential.

[0152] The at least two front-stage output circuits 14 can be connected to the front-stage pull-up node Q, one-to-one corresponding at least two output clock ends CLKS1…CLKSn and one-to-one corresponding at least two front-stage output ends Scout1…Scoutn respectively, and each front-stage output circuit 14 can be used to control the connection and disconnection of a corresponding one of the output clock ends and a corresponding one of the front-stage output ends in response to the potential of the front-stage pull-up node Q.

[0153] For example, each front-stage output circuit 14 can control a corresponding one of the output clock ends and a corresponding one of the front-stage output ends to be connected when the potential of the front-stage pull-up node Q is the first potential, so that the output clock end transmits the output clock signal to the front-stage output end; and can control a corresponding one of the output clock ends and a corresponding one of the front-stage output ends to be disconnected when the potential of the front-stage pull-up node Q is the second potential. The front-stage output end can be connected to a pixel in a display panel through a gate line and be used to output a gate driving signal to the pixel.

[0154] The pre-stage pull-down control circuit 15 can be connected with the control node P, the second clock terminal CLK2, the third clock terminal CLK3, the first power terminal VGH, the second power terminal VGL, the pre-stage pull-up node Q and the pre-stage pull-down node QB respectively, and can be configured to control the connection between the second clock terminal CLK2 and the pre-stage pull-down node QB in response to the potential of the control node P and the third clock signal, control the connection between the second power terminal VGL and the pre-stage pull-down node QB in response to the second clock signal, control the connection between the second clock terminal CLK2 and the pre-stage pull-down node QB in response to the potential of the pre-stage pull-up node, and store the potential of the pre-stage pull-down node QB based on the first power signal.

[0155] For example, the pre-stage pull-down control circuit 15 can control the second clock terminal CLK2 to be connected to the pre-stage pull-down node QB when the potential of the control node P is the first potential and the potential of the third clock signal is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the pre-stage pull-down node QB; and can control the second clock terminal CLK2 to be disconnected from the pre-stage pull-down node QB when the potential of the control node P and / or the potential of the third clock signal is the second potential. Similarly, the pull-down control circuit 15 can control the second power terminal VGL to be connected to the pre-stage pull-down node QB when the potential of the second clock signal is the first potential, so that the second power terminal VGL transmits the second power signal to the pre-stage pull-down node QB; and can control the second power terminal VGL to be disconnected from the pre-stage pull-down node QB when the potential of the second clock signal is the second potential. Similarly, the pull-down control circuit 15 can control the second clock terminal CLK2 to be connected to the pre-stage pull-down node QB when the potential of the pre-stage pull-up node Q is the first potential, so that the second clock terminal CLK2 transmits the second clock signal to the pre-stage pull-down node QB; and can control the second clock terminal CLK2 to be disconnected from the pre-stage pull-down node QB when the potential of the pre-stage pull-up node Q is the second potential.

[0156] Optionally, in some embodiments, the second power terminal VGL connected by the pre-stage pull-down control circuit 15 can also be shared with the second clock terminal CLK2. In this way, the wiring can be simplified.

[0157] The pre-stage pull-down circuit 16 can be connected with the pre-stage pull-down node QB, the first power terminal VGH, the pre-stage pull-up node Q and at least two pre-stage output terminals Scout1, …, Scoutn respectively, and can be configured to control the connection between the first power terminal VGH and the pre-stage pull-up node Q in response to the potential of the pre-stage pull-down node QB, and control the connection between the first power terminal VGH and each pre-stage output terminal, so as to output the gate drive signal through the pre-stage output terminal. In this way, the pre-stage decoding circuit 10 can be a shift register unit included in the gate drive circuit.

[0158] For example, the pre-stage pull-down circuit 16 can control the first power supply end VGH to be connected with the pre-stage pull-up node Q and each pre-stage output end when the potential of the pre-stage pull-down node QB is the first potential, and can control the first power supply end VGH to be disconnected from the pre-stage pull-up node Q and each pre-stage output end when the potential of the pre-stage pull-down node QB is the second potential.

[0159] Optionally, with continuous reference to Fig. 9, it can also be seen that the pre-stage decoding circuit 10 can further include a first pre-stage isolation circuit 17 and a second pre-stage isolation circuit 18.

[0160] The first pre-stage isolation circuit 17 can be connected between the control node P and the pre-stage pull-down control circuit 15, and can also be connected with the second power supply end VGL, and can be used to control the control node P to be connected with the pre-stage pull-down control circuit 15 in response to the second power supply signal.

[0161] It can be understood that, by setting the first pre-stage isolation circuit 17, the pre-stage pull-down control circuit 15 can be prevented from being mis-operated due to the leakage of the control node P, i.e., the working reliability of the pre-stage pull-down control circuit 15 can be ensured to be better.

[0162] The second pre-stage isolation circuit 18 can be connected between the pre-stage pull-up node Q and the at least two pre-stage output circuits 14, and can also be connected with the second power supply end VGL, and can be used to control the pre-stage pull-up node Q to be connected with the at least two pre-stage output circuits 14 in response to the second power supply signal.

[0163] Like the first pre-stage isolation circuit 17, by setting the second pre-stage isolation circuit 18, the pre-stage output circuit 14 can be prevented from being mis-operated due to the leakage of the pre-stage pull-up node Q, i.e., the working reliability of the pre-stage output circuit 14 can be ensured to be better. In addition, by setting the second pre-stage isolation circuit 18, the potential of the pull-up node Q can also be prevented from being affected due to the change of the potential at the node connected with the second isolation circuit 08 and the output circuit 04, i.e., the potential stability of the pull-up node Q can also be ensured to be better.

[0164] Optionally, based on Fig. 9, Fig. 10 shows a structural schematic diagram of another pre-stage decoding circuit. As shown in Fig. 10, the pre-charge circuit 11 can include a gating sub-circuit 111, an auxiliary control sub-circuit 112 and a pre-charge sub-circuit 113.

[0165] The gate sub-circuit 111 can be connected with at least two gate terminals D0...Dm, a second clock terminal CLK2 and an intermediate node N respectively, and can be configured to control the connection between the second clock terminal CLK2 and the intermediate node N in response to a gate signal provided by each of the gate terminals. The gate sub-circuit 111 can also be referred to as a decoding circuit.

[0166] For example, the gate sub-circuit 111 can control the second clock terminal CLK2 to be connected to the intermediate node N when the gate signal provided by any of the gate terminals has a first potential, so that the second clock terminal CLK2 transmits the second clock signal to the intermediate node N; and can control the second clock terminal CLK2 to be disconnected from the intermediate node N when the gate signal provided by each of the gate terminals has a second potential.

[0167] The auxiliary control circuit 112 can be connected with the first clock terminal CLK1, the second clock terminal CLK2 and the intermediate node N respectively, and can be configured to control the connection between the second clock terminal CLK2 and the intermediate node N in response to the first clock signal.

[0168] For example, the auxiliary control circuit 112 can control the second clock terminal CLK2 to be connected to the intermediate node N when the first clock signal has a first potential, so that the second clock terminal CLK2 transmits the second clock signal to the intermediate node N; and can control the second clock terminal CLK2 to be disconnected from the intermediate node N when the first clock signal has a second potential.

[0169] The pre-charge sub-circuit 113 can be connected with the intermediate node N, the first clock terminal CLK1, a second power terminal VGL and a control node P respectively, and can be configured to control the connection between the first clock terminal CLK1 and the control node P in response to the potential of the intermediate node N and the first clock signal, and store the potential of the control node P based on a second power signal.

[0170] For example, the pre-charge sub-circuit 113 can control the first clock terminal CLK1 to be connected to the control node P when the potential of the intermediate node N is a first potential and / or the potential of the first clock signal is a first potential, so that the first clock terminal CLK1 transmits the first clock signal to the control node P; and can control the first clock terminal CLK1 to be disconnected from the control node P when the potential of the intermediate node N is a second potential and the potential of the first clock signal is a second potential.

[0171] Optionally, with reference back to FIG. 10, it can also be seen that the second front-stage isolation circuit 18 can include at least two isolation sub-circuits 181.

[0172] The at least two isolation sub-circuits 181 can be connected to the at least two front-stage output circuits 14 one by one, and can also be connected to the second power supply end VGL and the front-stage pull-up node Q. Each isolation sub-circuit 181 can be used to control the front-stage pull-up node Q and the corresponding one of the front-stage output circuits 04 to be turned on or turned off in response to the first power supply signal.

[0173] That is, in the embodiment of the present disclosure, for each front-stage output circuit 14, one isolation sub-circuit 181 can be correspondingly arranged to isolate the front-stage pull-up node Q and the front-stage output circuit 04, so as to ensure that each front-stage output circuit 14 can work reliably.

[0174] Optionally, it can also be seen from FIGS. 9 and 10 that the shift register unit shown therein includes four front-stage output circuits 14, i.e., n is 4. Correspondingly, the four front-stage output circuits 14 can be connected to one by one corresponding four output clock ends CLKS1, CLKS2, CLKS3 and CLKS4, and can be connected to one by one corresponding four output ends Scout(i), Scout(i+1), Scout(i+2) and Scout(i+3). i is an integer greater than 0 and less than or equal to n. For example, i is 1, and the four output ends are Scout(1) to Scout(4) respectively.

[0175] In addition, the second front-stage isolation circuit 18 can include four isolation sub-circuits 181 as shown in FIG. 10. In the figure, the nodes where the four isolation sub-circuits 181 are connected to the four front-stage output circuits 14 are respectively identified as Q1, Q2, Q3 and Q4, also called output nodes. On this basis, it can be considered that each front-stage output circuit 14 controls the corresponding output clock end and the front-stage output end to be turned on or turned off in response to the potential of the corresponding output node.

[0176] Optionally, it can also be seen from FIGS. 9 and 10 that in the shift register unit shown therein, the gating sub-circuit 011 is connected to eight gating ends D0, D1, D2, D3, D4, D5, D6 and D7. That is, m is 7.

[0177] Optionally, on the basis of FIG. 10, FIG. 11 shows a circuit structure schematic diagram of a front-stage decoding circuit provided by an embodiment of the present disclosure. As shown in FIG. 11, the gating sub-circuit 111 can include at least two gating transistors T11…T1m. The auxiliary control sub-circuit 112 can include an auxiliary control transistor T20. The pre-charging sub-circuit 113 can include a first pre-charging transistor T31, a second pre-charging transistor T32 and a first storage capacitor Cst1.

[0178] The gates of the at least two gating transistors T11…T1m can be connected to the at least two gating terminals D0…Dm one by one, the first poles of the at least two gating transistors T11…T1m can be connected to the second clock terminal CLK2, and the second poles of the at least two gating transistors T11…T1m can be connected to the intermediate node N. It can be understood that, since the structure shown in FIG. 10 includes eight gating terminals D0 to D7, the circuit structure shown in FIG. 11 includes eight gating transistors T11 to T18. The gates of the eight gating transistors T11 to T18 are connected to the eight gating terminals D0 to D7 one by one.

[0179] The gate of the auxiliary control transistor T20 can be connected to the first clock terminal CLK1, the first pole of the auxiliary control transistor T20 can be connected to the second clock terminal CLK2, and the second pole of the auxiliary control transistor T20 can be connected to the intermediate node N.

[0180] The gate of the first pre-charge transistor T31 can be connected to the intermediate node N, the first pole of the first pre-charge transistor T31 can be connected to the first clock terminal CLK1, and the second pole of the first pre-charge transistor T31 can be connected to the control node P.

[0181] The gate and the first pole of the second pre-charge transistor T32 can be connected to the first clock terminal CLK1, and the second pole of the second pre-charge transistor T32 can be connected to the control node P.

[0182] One end of the first storage capacitor Cst1 can be connected to the second power terminal VGL, and the other end of the first storage capacitor Cst1 can be connected to the control node P. That is, the first storage capacitor Cst1 can be connected in series between the second power terminal VGL and the control node P.

[0183] Optionally, it can be seen with reference to FIG. 11 that the front-stage pull-down control circuit 15 can include a first pull-down control transistor T41, a second pull-down control transistor T42, a third pull-down control transistor T43, a fourth pull-down control transistor T44, and a second storage capacitor Cst2.

[0184] The gate of the first pull-down control transistor T41 can be connected to the control node P, the first pole of the first pull-down control transistor T41 can be connected to the second pole of the second pull-down control transistor T42, and the second pole of the first pull-down control transistor T41 can be connected to the front-stage pull-down node QB.

[0185] The gate of the second pull-down control transistor T42 can be connected to the third clock terminal CLK3, and the first pole of the second pull-down control transistor T42 can be connected to the second clock terminal CLK2.

[0186] The gate of the third pull-down control transistor T43 can be connected with the second clock end CLK2, the first pole of the third pull-down control transistor T43 can be connected with the second power supply end VGL, and the second pole of the third pull-down control transistor T43 can be connected with the previous-stage pull-down node QB.

[0187] The gate of the fourth pull-down control transistor T44 can be connected with the previous-stage pull-up node Q, the first pole of the fourth pull-down control transistor T44 can be connected with the second clock end CLK2, and the second pole of the fourth pull-down control transistor T44 can be connected with the previous-stage pull-down node QB.

[0188] One end of the second storage capacitor Cst2 can be connected with the first power supply end VGH, and the other end of the second storage capacitor Cst2 can be connected with the previous-stage pull-down node QB. That is, the second storage capacitor Cst2 can be connected in series between the first power supply end VGH and the previous-stage pull-down node QB.

[0189] Optionally, continuing to refer to FIG. 11, it can be seen that the previous-stage pull-down circuit 16 can include a first pull-down transistor T50 and at least two second pull-down transistors T51…T5n.

[0190] The gate of the first pull-down transistor T50 can be connected with the previous-stage pull-down node QB, the first pole of the first pull-down transistor T50 can be connected with the first power supply end VGH, and the second pole of the first pull-down transistor T50 can be connected with the previous-stage pull-up node Q.

[0191] The gates of the at least two second pull-down transistors T51…T5n can be connected with the previous-stage pull-down node QB, the first poles of the at least two second pull-down transistors T51…T5n can be connected with the first power supply end VGH, and the second poles of the at least two second pull-down transistors T51…T5n can be connected with the at least two previous-stage output ends Scout1…Scoutn one by one. It can be understood that, since the structure shown in FIG. 10 includes four output circuits 04 corresponding to the four output ends Scout(i) to Scout(i+3), the circuit structure shown in FIG. 11 includes four second pull-down transistors T51, T52, T53 and T54. The second poles of the four second pull-down transistors T51 to T54 can be connected with the four previous-stage output ends Scout(i) to Scout(i+3) one by one.

[0192] Optionally, continuing to refer to FIG. 11, it can be seen that the first previous-stage isolation circuit 17 can include a first isolation transistor T60. Each isolation sub-circuit 181 in the second previous-stage isolation circuit 18 can include a second isolation transistor T6x.

[0193] The gate of the first isolation transistor T60 can be connected with the second power supply end VGL, the first pole of the first isolation transistor T60 can be connected with the control node P, and the second pole of the first isolation transistor T60 can be connected with the front-stage pull-down control circuit 15. It can be understood that it can be connected with the gate of the first pull-down control transistor T41 in the front-stage pull-down control circuit 15. That is, the gate of the first pull-down control transistor T41 can be indirectly connected with the control node P through the first isolation transistor T60.

[0194] The gate of the second isolation transistor T6x can be connected with the second power supply end VGL, the first pole of the second isolation transistor T6x can be connected with the front-stage pull-up node Q, and the second pole of the second isolation transistor T6x can be connected with the corresponding front-stage output circuit 14. It can be understood that it can be connected with the output node. Based on the structure including four isolation sub-circuits 181 shown in FIG. 10, the circuit structure shown in FIG. 11 includes four second isolation transistors T61, T62, T63 and T64. The four second isolation transistors T61 to T64 are respectively connected with the four output nodes Q1 to Q4 in one-to-one correspondence.

[0195] Optionally, it can be seen from FIG. 11 that the charging circuit 12 can include a first charging transistor T71, a second charging transistor T72 and a third charging transistor T73.

[0196] The gate of the first charging transistor T71 can be connected with the control node P, the first pole of the first charging transistor T71 can be connected with the second power supply end VGL, and the second pole of the first charging transistor T71 can be connected with the first pole of the second charging transistor T72.

[0197] The gate of the second charging transistor T72 can be connected with the third clock end CLK3, and the second pole of the second charging transistor T72 can be connected with the front-stage pull-up node Q.

[0198] The gate of the third charging transistor T73 can be connected with the second clock end CLK2, the first pole of the third charging transistor T73 can be connected with the third clock end CLK3, and the second pole of the third charging transistor T73 can be connected with the front-stage pull-up node Q.

[0199] Optionally, it can be seen from FIG. 11 that the reset circuit 13 can include a first reset transistor T81 and a second reset transistor T82.

[0200] The gate of the first reset transistor T81 and the gate of the second reset transistor T82 can be connected with the reset terminal TRS, the first electrode of the first reset transistor T81 and the first electrode of the second reset transistor T82 can be connected with the first power supply terminal VGH, the second electrode of the first reset transistor T81 can be connected with the control node P, and the second electrode of the second reset transistor T82 can be connected with the front-stage pull-up node Q.

[0201] Optionally, referring to FIG. 11, it can be seen that each front-stage output circuit 14 can include an output transistor T9x and a third storage capacitor Cst3x.

[0202] The gate of the output transistor T9x can be connected with the front-stage pull-up node Q, the first electrode of the output transistor T9x can be connected with the corresponding output clock terminal, and the second electrode of the output transistor T9x can be connected with the corresponding front-stage output terminal.

[0203] One end of the third storage capacitor Cst3x can be connected with the front-stage pull-up node Q, and the other end of the third storage capacitor Cst3x can be connected with the corresponding front-stage output terminal.

[0204] It can be understood that, on the basis of the second front-stage isolation circuit 18, the gate of the output transistor T9x can be indirectly connected with the front-stage pull-up node Q through the second isolation transistor T6x, and one end of the third storage capacitor Cst3x can be indirectly connected with the front-stage pull-up node Q through the second isolation transistor T6x. The connection node of the gate of the output transistor T9x and one end of the third storage capacitor Cst3x with the second isolation transistor T6x is referred to as an output node. For example, on the basis of the structure including four front-stage output circuits 14 shown in FIG. 9, the circuit structure shown in FIG. 10 includes four output transistors T91, T92, T93 and T94, and includes four third storage capacitors Cst31, Cst32, Cst33 and Cst34. The gates of the four output transistors T91 to T94 are connected with the four output nodes Q1 to Q4 in a one-to-one correspondence, the first electrodes of the four output transistors T91 to T94 are connected with the four output clock terminals CLKS1 to CLKS4 in a one-to-one correspondence, and the second electrodes of the four output transistors T91 to T94 are connected with the four front-stage output terminals Scout(i) to Scout(i+3) in a one-to-one correspondence. One end of the four third storage capacitors Cst31, Cst32, Cst33 and Cst34 is connected with the four output nodes Q1 to Q4 in a one-to-one correspondence, and the other end of the four third storage capacitors Cst31, Cst32, Cst33 and Cst34 is connected with the four front-stage output terminals Scout(i) to Scout(i+3) in a one-to-one correspondence.

[0205] Optionally, each of the transistors in the circuit structure shown in FIGS. 5-8 and FIG. 11 is a P-type transistor. Correspondingly, as described above, the first potential can be a low potential and the second potential can be a high potential. Of course, in some other embodiments, each of the transistors can be an N-type transistor, on the basis of which, as described above, the first potential can be a high potential and the second potential can be a low potential; or, some of the transistors can be P-type transistors and the other transistors can be N-type transistors.

[0206] Optionally, on the basis that the pre-stage decoding circuit 11 includes four pre-stage output circuits 14, as can be seen from another structural schematic diagram of a shift register unit shown in FIG. 12, the shift register unit can include four post-stage driving circuits 00, which are identified as EM GOA1-EM GOA4.

[0207] Further, as described above, the four post-stage driving circuits 00 (i.e., EM GOA1-EM GOA4) can be connected to the four post-stage output terminals (e.g., EM1-EM4) one by one, connected to the four different input clock terminals CLKP1-CLKP4 one by one, and connected to the four different control clock terminals CLKE10-CLKE12 one by one, respectively. In addition, the four post-stage driving circuits 00 can be connected to the same pre-stage decoding circuit 10 (identified as the decoder GOA) to the same control node P. For example, on the basis of FIG. 12, in combination with FIGS. 6 and 11, FIG. 13 shows a circuit structural diagram of another shift register unit.

[0208] In summary, the embodiments of the present disclosure provide a shift register unit. The shift register unit includes a pre-stage decoding circuit and at least two post-stage driving circuits. The pre-stage decoding circuit can control the potential of a control node based on a gate signal provided by at least one gate terminal and a clock signal provided by a clock terminal. In each post-stage driving circuit, an input circuit and a post-stage pull-down control circuit can control the potential of a post-stage pull-up node and the potential of a post-stage pull-down node, respectively, based on the potential of the control node, so that a post-stage pull-down circuit outputs a first power signal to a post-stage output terminal based on the potential of the post-stage pull-down node, and a post-stage output circuit outputs a second power signal to the post-stage output terminal based on the potential of the post-stage pull-up node. In this way, the partitioned gating can be realized by flexibly setting the gate signal, so that each post-stage driving circuit in different shift register units flexibly outputs a light-emitting control signal to multiple rows of pixels to drive the multiple rows of pixels to emit light. That is, the shift register unit provided by the embodiments of the present disclosure can flexibly refresh the pixels according to the partitioning of the display picture.

[0209] FIG. 14 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure, which is used to drive the shift register unit shown in any one of FIGS. 1 to 13. As shown in FIG. 14, the method comprises the following steps.

[0210] In step 1401, in the first stage, the pre-charge circuit in the front-stage decoding circuit controls the first clock terminal to be conductive with the control node in response to the gate signal provided by each of the at least two gate terminals, the first clock signal provided by the first clock terminal, and the second clock signal provided by the second clock terminal.

[0211] In step 1402, in the second stage, the input circuit in each of the back-stage driving circuits controls the input clock terminal to be conductive with the back-stage pull-up node in response to the potential of the control node, the control clock signal provided by the control clock terminal, and the input clock signal provided by the input clock terminal, the back-stage pull-down control circuit controls the control clock terminal to be conductive with the back-stage pull-down node in response to the potential of the control node, and the back-stage pull-down circuit controls the first power supply terminal to be conductive with the back-stage output terminal in response to the potential of the back-stage pull-down node.

[0212] In step 1403, in the third stage, the input circuit in each of the back-stage driving circuits controls the input clock terminal to be conductive with the back-stage pull-up node in response to the input clock signal, the back-stage pull-down control circuit controls the control clock terminal to be conductive with the back-stage pull-down node in response to the potential of the control node and the potential of the back-stage pull-up node, and the back-stage output circuit controls the second power supply terminal to be conductive with the back-stage output terminal in response to the potential of the back-stage pull-up node.

[0213] It can be understood that the driving method has substantially the same technical effects as the aforementioned shift register unit embodiments, and thus the technical effects of the driving method will not be described again for the sake of brevity.

[0214] FIG. 15 is a structural diagram of a light-emitting control circuit according to an embodiment of the present disclosure. As shown in FIG. 15, the light-emitting control circuit comprises a plurality of groups of shift register units GOA0, each group of shift register units GOA0 comprising at least two shift register units GOA shown in FIGS. 1 to 13.

[0215] Each group of shift register units GOA shares the first clock terminal CLK1, the second clock terminal CLK2, the control clock terminal CLKE, the input clock terminal CLKP, and the gate terminals D0 to Dm, and each group of shift register units GOA can be configured to receive different gate signals provided by the at least two gate terminals.

[0216] Further, based on FIG. 10, it can also be seen from FIG. 15 that each group of shift register units GOA also shares the first clock terminal CLK1, the second clock terminal CLK2, the third clock terminal CLK3, and the output clock terminals CLKS1…CLKS n.

[0217] For example, in the light emission control circuit shown in FIG. 15, each group of shift register units GOA0 includes three shift register units GOA. Each shift register unit GOA can include one front-stage decoding circuit Gate GOA and at least two back-stage driving circuits EM GOA. Each front-stage decoding circuit Gate GOA is connected to four front-stage output terminals Scout(i) to Scout(i+3). For example, the first front-stage decoding circuit Gate GOA1 is connected to four front-stage output terminals Scout(1) to Scout(4); the second front-stage decoding circuit Gate GOA2 is connected to four front-stage output terminals Scout(5) to Scout(8); and so on. Correspondingly, each shift register unit GOA can include four back-stage driving circuits connected one-to-one to four back-stage output terminals EM(i) to EM(i+3). For example, the four back-stage driving circuits EM GOA1 to EM GOA4 are connected one-to-one to EM1 to EM4.

[0218] Further, referring to FIG. 15, the first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 can be connected to three clock signal lines, which are also denoted as CLK1 to CLK3. The four output clock terminals CLKS1 to CLKS4 corresponding to the four front-stage output terminals Scout(i) to Scout(i+3) can be connected to twelve clock signal lines CLKE1 to CLKE12. The four input clock terminals CLKP1 to CLKP4 corresponding to the four back-stage driving circuits can be connected to six clock signal lines CLKP1 to CLKP6. Further, the four control clock terminals CLKE corresponding to the four back-stage driving circuits can be shared by four clock signal lines (e.g., CLKE10, CLKE11, CLKE12, and CLKE1) of the twelve clock signal lines CLKE1 to CLKE12. In this way, the wiring can be simplified.

[0219] In addition, referring to FIG15 , each group of shift register units GOA0 shown therein is connected to eight strobe terminals D0 to D7. The difference is that the first group of shift register units GOA0 receives strobe signals provided by the eight strobe terminals D0 to D7; the second group of shift register units GOA0 receives strobe signals provided by the eight strobe terminals D0′ and D1 to D7. The strobe signal provided by D0′ is the inverse of the strobe signal provided by D0. For example, if the strobe signal provided by D0 is 1, indicating a high potential, the strobe signal provided by D0′ is 0, indicating a low potential.

[0220] For example, FIG13 is combined with the structure shown in FIG15 as an example, FIG16 shows a timing diagram of the operation of a shift register unit. In addition, FIG16 shows a timing diagram corresponding to the shift register unit connecting the pixels in rows 1 to 4. Referring to FIG16 , it can be seen that the operation of the shift register unit can be divided into 6 stages t01 to t06. It can be understood that in FIG16 , the four front-stage output terminals are respectively identified as Scout (1) to Scout (4); and the four rear-stage output terminals are respectively identified as EM (1) to EM (4).

[0221] Before stage t01, the reset terminal TRS can first provide a low-level reset signal, so that the first reset transistor T81 and the second reset transistor T82 are both turned on, thereby causing the second power supply terminal VGH to transmit a high-level second power supply signal to both the control node P and the previous stage pull-up node Q.

[0222] At stage t01, the clock signal line CLK1 connected to the first clock terminal CLK1 can provide a low-potential first clock signal, turning on both the auxiliary control transistor T20 and the second pre-charge transistor T32. This allows the first clock terminal CLK1 to transmit the low-potential first clock signal to the control node P, and allows the second clock terminal CLK2 to transmit the high-potential second clock signal to the intermediate node N. That is, at stage t01, the potential of the control node P can be set low. Accordingly, stage t01 is also referred to as the point P setting stage. Furthermore, referring to FIG16 , it can be seen that at stage t01, the eight selection terminals D0 to D7 all provide low-potential selection signals, meaning that the potentials of the selection signals are all set low, and the selection stage has not yet begun.

[0223] In stage t02, firstly, because each shift register unit is connected with eight gate terminals D0 to D7, it is known that the eight gate terminals D0 to D7 can provide the gate signals corresponding to 256 states. And in stage t02, for the first group of shift register unit connected with the first 16 output terminals Scout(1) to Scout(16), the potentials of the gate signals provided by the eight gate terminals D0 to D7 are all high. Correspondingly, the eight gate transistors T11 to T18 in the first group of shift register units are all turned off, and the potential of the intermediate node N keeps the high potential of the last stage. And for the second group of shift register unit connected with the 16 output terminals Scout(17) to Scout(32), the potential of the gate signal provided by the gate terminal D0 of the eight gate terminals D0 to D7 can be low, and the potentials of the gate signals provided by the rest of the gate terminals can be high. Correspondingly, at least the gate transistor T11 in the second group of shift register units can be turned on, so that the second clock signal can be transmitted from the second clock terminal CLK2 to the intermediate node N. In addition, in stage t02, because the clock signal line CLK2 connected with the second clock terminal CLK2 can provide the low potential second clock signal, the potential of the intermediate node N can be lowered through the turned-on gate transistor T11.

[0224] In stage t03, the clock signal line CLKP1 connected with the input clock terminal CLKP1 can provide the high potential input clock signal, and the clock signal line CLKE10 connected with the control clock terminal CLKE10 can provide the low potential control clock signal, so that the third transistor T3 and the ninth transistor T9 are both turned on. And because the potential of the control node P can keep the low potential of the last stage under the holding action of the first storage capacitor Cst1, the first transistor T1 and the eighth transistor T8 are both turned on, so that the high potential input clock signal can be transmitted from the input clock terminal CLKP1 to the back-stage pull-up node Q_em, and the low potential control clock signal can be transmitted from the control clock terminal CLKE to the back-stage pull-down node QB_em. That is, in stage t03, the potential of the back-stage pull-up node Q_em can be high, and the potential of the back-stage pull-down node QB_em can be low. Then, the fifth transistor T5 can be turned on, so that the high potential first power signal can be transmitted from the first power terminal VGH to the back-stage output terminal EM. That is, in stage t03, the potential of the back-stage output terminal EM can be high. Here, it can refer to the first back-stage output terminal EM(1).

[0225] In stage t04, firstly, the clock signal line CLK3 connected with the third clock end CLK3 can provide the third clock signal with low potential, so that the second charging transistor T72 is turned on. Because the potential of the control node P can be kept as the low potential of the last stage under the holding action of the first storage capacitor Cst1, the first charging transistor T71 is also turned on, and the first power supply end VGL transmits the first power supply signal with low potential to the pull-up node Q. Because the four second isolation transistors T61 to T64 can be kept on based on the first power supply signal with low potential, the potentials of the four output nodes Q1 to Q4 are further lowered, and the four output transistors T91 to T94 are turned on. In addition, on the basis that the potential of the control node P and the potential of the third clock signal are both low, and the potential of the pull-up node Q is low, the first pull-down control transistor T41, the second pull-down control transistor T42 and the fourth pull-down control transistor T44 are turned on, and the first clock signal and the second clock signal are transmitted to the pull-down control node QB from the first clock end CLK1 and the second clock end CLK2 respectively. Because the potential of the first clock signal and the potential of the second clock signal are both high in stage t04, the potential of the pull-down control node QB is high. Secondly, the clock signal line CLK3 can provide the third clock signal with high potential, and under the coupling action of the third storage capacitor Cst3, the potentials of the four output nodes Q1 to Q4 are further lowered in sequence, so that the four output transistors T91 to T94 are fully turned on. The clock signal lines CLKE1 to CLKE4 connected with the four output clock ends CLKS1 to CLKS4 provide the clock signals with low potential in sequence. Then, the signals with low potential can be output to the four output ends Scout1 to Scout4 in sequence.

[0226] In stage t05, the clock signal line CLKP1 connected with the input clock end CLKP1 can provide the input clock signal with low potential, and the clock signal line CLKE10 connected with the control clock end CLKE10 can provide the control clock signal with high potential, so that the seventh transistor T7 is turned on, and the input clock end CLKP1 transmits the input clock signal with low potential to the pull-up node Q_em of the next stage. That is, in stage t03, the potential of the pull-up node Q_em of the next stage is low. Because the fourth transistor T4 is always on, the tenth transistor T10 is turned on, and the second transistor T2 is also turned on. Then, the first power supply end VGH transmits the first power supply signal with high potential to the pull-down node QB_em of the next stage, and the second power supply end VGL transmits the second power supply signal with low potential to the output end EM of the next stage. That is, in stage t03, the potential of the pull-down node QB_em of the next stage is high, and the potential of the output end EM of the next stage is low. Here, the output end EM of the next stage can be referred to as the first output end EM(1) of the next stage.

[0227] At stage t06, among the eight strobe terminals D0 to D7, the strobe signal provided by the strobe terminal D0 jumps to low level, so that the second group of shift register units is strobed, while the first group of shift register units is no longer strobed. At this time, for the second group of shift register units, the included strobe transistor T11 can be turned on, the second clock terminal CLK2 can transmit the low-level second clock signal to the intermediate node N, and the electrical position of the intermediate node N is lowered. Correspondingly, the first pre-charge transistor T31 can be turned on, and the first clock terminal CLK1 can transmit the low-level first clock signal to the control node P, and the electrical position of the control node P is lowered. In combination with the low-level third clock signal provided by the third clock terminal CLK3, the first pull-down control transistor T41 and the second pull-down control transistor T42 can be turned on, and the second clock terminal CLK2 also transmits the low-level second clock signal to the pull-down control node QB, and the electrical position of the pull-down control node QB is lowered. Correspondingly, the first pull-down transistor T50 and the four second pull-down transistors T51 to T54 can be turned on, and then the second power supply terminal VGH can output the high-level second power supply signal to the front-stage pull-up node Q and the four front-stage output terminals Scout1 to Scout4, and the electrical position of the front-stage pull-up node Q and the electrical position of the signals output by the four front-stage output terminals Scout1 to Scout4 are all high. On the basis of the electrical position of the front-stage pull-up node Q being high, because the four second isolation transistors T61 to T64 can be kept turned on based on the low-level first power supply signal, the electrical positions of the four output nodes Q1 to Q4 can be further raised. The stage t06 can also be called a reset stage, and the stage t06 can be repeatedly executed when the shift register unit is not strobed.

[0228] It can be understood that in combination with FIG. 16, it can also be seen that the stage t06 can actually be divided into three stages t06a, t06b and t06c executed in turn.

[0229] In the stage t06a, the clock signal line CLK2 connected with the second clock terminal CLK2 can provide the second clock signal with low potential, while the potential of the first clock signal and the potential of the third clock signal can both be high potential, and the potential of the strobe signal provided by the strobe terminal D0 can be low potential. Correspondingly, the third pull-down control transistor T43 and the strobe transistor T11 can both be turned on, so that the second clock terminal CLK2 can transmit the second clock signal with low potential to the intermediate node N, and the second power supply terminal VGL can transmit the second power signal with low potential to the pull-down control node QB, i.e., the potential of the intermediate node N and the potential of the pull-down control node QB are both set to low. Correspondingly, the first pre-charge transistor T31 can be turned on, so that the first clock terminal CLK1 can transmit the first clock signal to the control node P. Since the potential of the first clock signal is high in the stage t06a, the potential of the control node P is set to high. In addition, the first pull-down transistor T50 and the four second pull-down transistors T51-T54 can all be turned on, so that the first power supply terminal VGH can output the first power signal with high potential to the front-stage pull-up node Q and the four front-stage output terminals Scout1-Scout4, i.e., the potential of the front-stage pull-up node Q and the potential of the signals output by the four output terminals Scout1-Scout4 are both set to high. On the basis that the potential of the front-stage pull-up node Q is set to high, the four output transistors T91-T94 can all be turned off.

[0230] In the stage t06b, the clock signal line CLK3 connected with the third clock terminal CLK3 can provide the second clock signal with low potential, while the potential of the first clock signal and the potential of the second clock signal can both be high potential, and the potential of the strobe signal provided by the strobe terminal D0 can be low potential. Correspondingly, the strobe transistor T11 can be turned on, so that the second clock terminal CLK2 can transmit the second clock signal with high potential to the intermediate node N, i.e., the potential of the intermediate node N is set to high, so that the first pre-charge transistor T31 is turned off. In addition, since the potential of the first clock signal is high, the second pre-charge transistor T32 can also be turned off. It can be known that in the stage t06b, the control node P can be in a floating state, maintaining the high potential in the previous stage (i.e., the stage t06a). Correspondingly, the first pull-down control transistor T41 can be turned off. In addition, under the storage effect of the second storage capacitor Cst2, the potential of the pull-down control node QB can also maintain the low potential in the previous stage (i.e., the stage t06a).

[0231] At stage t06c, the clock signal line CLK1 connected with the first clock terminal CLK1 can provide the first clock signal with a low potential, the potential of the second clock signal and the potential of the third clock signal can both be high potentials, and the potential of the strobe signal provided by the selection terminal D0 can be a low potential. Correspondingly, the selection transistor T11, the auxiliary control transistor T20 and the second pre-charge transistor T32 can all be turned on, so that the first clock terminal CLK1 can transmit the first clock signal with a low potential to the control node P, and the second clock terminal CLK2 can transmit the second clock signal with a high potential to the intermediate node N, i.e., the potential of the control node P can be lowered and the potential of the intermediate node N can be raised.

[0232] In addition, as shown in FIG. 15, for the plurality of shift register units GOA0, the potentials of the strobe signals provided by the eight selection terminals D0 to D7 can be controlled to select the front-stage decoding circuit Gate GOA in any one of the plurality of shift register units GOA0, so that the selected one of the plurality of shift register units GOA0 can output the gate driving signal to the connected pixels through the front-stage output terminal, and the other unselected ones of the plurality of shift register units GOA0 can not output the gate driving signal, thereby flexibly controlling the refresh frequency of the pixels connected with any one of the plurality of shift register units GOA0.

[0233] In addition, FIG. 17 also shows a timing diagram of the strobe signals. As shown in FIG. 17, among the eight selection terminals D0 to D7, the frequencies of the strobe signals provided by the first selection terminal D0 to the eighth selection terminal D7 can also be sequentially reduced as described above. In FIG. 17, the first selection terminal D0 is taken as an example. D0 can refer to the invalid-potential strobe signal provided by the selection terminal D0, and De0 can refer to the effective-potential strobe signal provided by the selection terminal D0. The other selection terminals are the same, and will not be described here.

[0234] It can be understood that the gate driving circuit has basically the same technical effects as the foregoing shift register unit embodiments, and therefore the technical effects of the gate driving circuit will not be described again for the purpose of brevity.

[0235] FIG. 18 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 18, the display device includes a display panel 100 and the light-emitting control circuit 000 shown in FIG. 15.

[0236] The display panel 100 includes a plurality of pixels, and the light-emitting control circuit 000 is connected with the plurality of pixels and is configured to transmit a light-emitting control signal to the plurality of pixels to drive the plurality of pixels to emit light.

[0237] It can be understood that the light emitting control circuit 000 can include the front stage decoding circuit 10 and the rear stage driving circuit 00. Only part of the front stage decoding circuit 10 can be used as a gate driving circuit to transmit a gate driving signal to a plurality of pixels.

[0238] Optionally, FIG. 19 shows a schematic diagram of a circuit structure of a pixel. As shown in FIG. 19, the pixel can include a pixel circuit and a light emitting element L1. The pixel circuit can include seven transistors M1 to M7 and one capacitor Cst. The pixel circuit is connected with six signal lines, i.e., a pull-up power supply line ELVDD, a gate line Scan(i), a reset control line Scan(i-1), a light emitting control line EM(i), a data signal line Data, and a reset line Init, respectively. The pixel circuit of this architecture is also referred to as a 7T-1C-6L (i.e., seven transistors, one capacitor, and six signal lines) circuit architecture. In addition, the light emitting element L1 is also connected with a pull-down power supply line ELVSS.

[0239] In the pixel circuit, the transistor M1 is a driving transistor, the transistors M2 to M7 are switch transistors, a gate-source voltage difference Vgs of the transistor T1 can be stored in the capacitor Cst, and a driving current I is determined according to the gray scale data. In addition, the transistors M2 and M7 can control the transistor M1 to output the driving current to the light emitting element L1 as a light emitting driving signal under the control of signals provided by the six signal lines, so that the light emitting element L1 can reliably emit light based on the light emitting driving signal and a pull-down power supply signal provided by the pull-down power supply line ELVSS. The transistors M5 and M6 in the transistors M2 to M7 are mainly used to control the transistor M1 to be turned on or turned off with the light emitting element L1 based on a signal provided by the light emitting control line EM(i), i.e., to block the driving current I or to make the driving current I flow into the light emitting element L1. Accordingly, it can be known that the signal provided by the light emitting control line EM(i) can be used for dimming.

[0240] Optionally, the light emitting element L1 can be an organic light-emitting diode (OLED), and FIG. 19 also schematically shows a parasitic capacitor Coled formed between the cathode and the anode of the OLED. In addition, each transistor in the pixel shown in FIG. 19 is a P-type transistor.

[0241] Taking the structure shown in FIG. 19 as an example, FIG. 20 schematically shows a working timing diagram of a pixel. As can be seen from FIG. 20, the pixel light emission can include a stage 1, a stage 2, and a stage 3.

[0242] In the stage 1, the reset control line Scan(i-1) can provide a reset control signal with an effective potential, so that the transistor M4 is turned on, and then the reset line Init outputs a reset signal to the gate of the transistor M1, so as to reset the gate of the transistor M1. In the stage 2, the gate line Scan(i) can provide a gate drive signal with an effective potential, so that the transistors M2, M3 and M7 are all turned on, and then the data line Data outputs a data signal to the first electrode of the transistor M1, the reset line Init outputs a reset signal to the light emitting element L1 to reset the light emitting element L1, and the gate and the second electrode of the transistor M1 are turned on. In the stage 3, the light emitting control line EM(i) can provide a light emitting control signal with an effective potential, so that the transistors M5 and M6 are all turned on, and then the transistor M1 generates a drive current, and the drive current is output to the light emitting element L1, so as to drive the light emitting element L1 to emit light.

[0243] Therefore, it can be known that, in the light emitting control circuit provided by the embodiment of the present disclosure, the output end EM(i) of the later stage of the shift register unit can be connected with the light emitting control line EM(i) in the pixel shown in FIG. 19, and is used to output the light emitting control signal shown in FIG. 20 to the light emitting control line EM(i), so as to drive the pixel to emit light.

[0244] In addition, the output end Scout(i) of the front stage of the shift register unit can be connected with the gate line Scan(i) in the pixel shown in FIG. 19, and is used to output the gate drive signal shown in FIG. 20 to the gate line Scan(i), so as to drive the pixel to emit light.

[0245] Optionally, the display device described in the embodiment of the present disclosure can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

[0246] It can be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by those skilled in the art to which the present disclosure belongs.

[0247] As used in the specification and claims of this patent application, the terms "first", "second", or "third" and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another, and the terms "one" or "another" or the like mean at least one. The terms "comprises", "comprising", "includes", "including" and the like can mean containing in addition to clean the elements listed after such terms or phrases. The terms "above", "below", "left" or "right" and the like merely indicate relative positions, and when the absolute positions of the described objects change, the relative positions may also change accordingly. "Connected" means electrical connection. "And / or" means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0248] The above description is only optional embodiments of the present disclosure, and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A shift register unit, the shift register unit comprising: The front-stage decoding circuit and the at least two back-stage driving circuits; The front-stage decoding circuit comprises: a pre-charge circuit connected with at least two gate terminals, a first clock terminal, a second clock terminal and a control node respectively, and configured to control the on-off of the first clock terminal and the control node in response to a gate signal provided by each of the gate terminals, a first clock signal provided by the first clock terminal and a second clock signal provided by the second clock terminal; and each of the back-stage driving circuits comprises: an input circuit connected with the control node, a control clock terminal, an input clock terminal and a back-stage pull-up node respectively, and configured to control the on-off of the input clock terminal and the back-stage pull-up node in response to the potential of the control node, a control clock signal provided by the control clock terminal and an input clock signal provided by the input clock terminal; a back-stage pull-down control circuit connected with the control node, the control clock terminal, the back-stage pull-up node, a first power terminal and a back-stage pull-down node respectively, and configured to control the on-off of the control clock terminal and the back-stage pull-down node in response to the potential of the control node, and control the on-off of the first power terminal and the back-stage pull-down node in response to the potential of the back-stage pull-up node; a back-stage pull-down circuit connected with the back-stage pull-down node, the first power terminal and a back-stage output terminal respectively, and configured to control the on-off of the first power terminal and the back-stage output terminal in response to the potential of the back-stage pull-down node; a back-stage output circuit connected with the back-stage pull-up node, a second power terminal and the back-stage output terminal respectively, and configured to control the on-off of the second power terminal and the back-stage output terminal in response to the potential of the back-stage pull-up node, so as to output a light-emitting control signal through the back-stage output terminal.

2. The shift register cell of claim 1, wherein, The back-stage pull-down control circuit comprises: a first pull-down control sub-circuit connected with the control node, the control clock terminal and the back-stage pull-down node respectively, and configured to control the on-off of the control clock terminal and the back-stage pull-down node in response to the potential of the control node; a second pull-down control sub-circuit connected with the back-stage pull-up node, the first power terminal and the back-stage pull-down node respectively, and configured to control the on-off of the first power terminal and the back-stage pull-down node in response to the potential of the back-stage pull-up node. The first pull-down control sub-circuit comprises: a first transistor; 3. The shift register cell of claim 2, wherein, a gate of the first transistor is connected with the control node, a first pole of the first transistor is connected with the control clock terminal, and a second pole of the first transistor is connected with the back-stage pull-down node. The second pull-down control sub-circuit comprises: a second transistor; 4. The shift register cell of claim 2 or 3, wherein, a gate of the second transistor is connected with the back-stage pull-up node, a first pole of the second transistor is connected with the first power terminal, and a second pole of the second transistor is connected with the back-stage pull-down node. The back-stage driving circuit further comprises:

5. The shift register cell of any of claims 2 to 4, wherein, a first holding circuit connected between the first pull-down control sub-circuit and the back-stage pull-down node, and further connected with the control clock terminal, and configured to control the on-off of the first pull-down control sub-circuit and the back-stage pull-down node in response to the control clock signal. ​ 6. The shift register cell of claim 5, wherein, The first holding circuit comprises a third transistor; a gate of the third transistor is connected with the control clock terminal, a first pole of the third transistor is connected with the first pull-down control sub-circuit, and a second pole of the third transistor is connected with the rear-stage pull-down node.

7. The shift register cell of any one of claims 1 to 6, wherein, The rear-stage driving circuit further comprises: a second holding circuit connected with the first power supply terminal and the rear-stage pull-down node respectively, and configured to hold the potential of the rear-stage pull-down node based on a first power supply signal provided by the first power supply terminal.

8. The shift register cell of claim 7, wherein, The second holding circuit comprises a first capacitor; one end of the first capacitor is connected with the first power supply terminal, and the other end of the first capacitor is connected with the rear-stage pull-down node.

9. The shift register cell of any of claims 1 to 8, wherein, The rear-stage driving circuit further comprises: a rear-stage isolation circuit connected between the rear-stage pull-up node and the rear-stage output circuit, and further connected with the second power supply terminal, and configured to control the rear-stage pull-up node and the rear-stage output circuit to be conductive in response to the second power supply signal.

10. The shift register cell of claim 9, wherein, The rear-stage isolation circuit comprises a fourth transistor; a gate of the fourth transistor is connected with the second power supply terminal, a first pole of the fourth transistor is connected with the rear-stage pull-up node, and a second pole of the fourth transistor is connected with the rear-stage output circuit.

11. The shift register cell of any one of claims 1 to 10, wherein, The rear-stage pull-down circuit comprises a fifth transistor; a gate of the fifth transistor is connected with the rear-stage pull-down node, a first pole of the fifth transistor is connected with the first power supply terminal, and a second pole of the fifth transistor is connected with the rear-stage output terminal.

12. The shift register cell of claim 11, wherein, The fifth transistor comprises a first sub-transistor and a second sub-transistor connected in series; a gate of the first sub-transistor and a gate of the second sub-transistor are both connected with the rear-stage pull-down node, a first pole of the first sub-transistor is connected with the first power supply terminal, a second pole of the first sub-transistor is connected with a first pole of the second sub-transistor, and a second pole of the second sub-transistor is connected with the rear-stage output terminal; the rear-stage driving circuit further comprises: an anti-leakage circuit connected with the rear-stage output terminal, the second power supply terminal, and a series connection node of the first sub-transistor and the second sub-transistor respectively, and configured to control the second power supply terminal and the series connection node to be conductive or not in response to the potential of the rear-stage output terminal.

13. The shift register cell of claim 12, wherein, The anti-leakage circuit comprises a sixth transistor; a gate of the sixth transistor is connected with the rear-stage output terminal, a first pole of the sixth transistor is connected with the second power supply terminal, and a second pole of the sixth transistor is connected with the series connection node.

14. The shift register cell of any one of claims 1 to 13, wherein, The input circuit comprises a seventh transistor, an eighth transistor, and a ninth transistor; a gate and a first pole of the seventh transistor are both connected with the input clock terminal, and a second pole of the seventh transistor is connected with the rear-stage pull-up node; a gate of the eighth transistor is connected with the control node, a first pole of the eighth transistor is connected with a second pole of the ninth transistor, and a second pole of the eighth transistor is connected with the rear-stage pull-up node; a gate of the ninth transistor is connected with the control clock terminal, and a first pole of the ninth transistor is connected with the input clock terminal.

15. The shift register cell of any one of claims 1 to 14, wherein, The post-stage output circuit comprises a tenth transistor and a second capacitor; a gate of the tenth transistor is connected with the post-stage pull-up node, a first pole of the tenth transistor is connected with the second power supply end, and a second pole of the tenth transistor is connected with the post-stage output end; one end of the second capacitor is connected with the post-stage pull-up node, and the other end of the second capacitor is connected with the post-stage output end.

16. The shift register cell of any one of claims 1 to 15, wherein, The pre-charge circuit is further connected with the second power supply end, and is used for storing the potential of the control node based on the second power supply signal; The pre-stage decoding circuit further comprises: a charging circuit connected with the control node, the second clock end, the third clock end, the second power supply end and the pre-stage pull-up node respectively, and used for controlling the on-off of the second power supply end and the pre-stage pull-up node in response to the potential of the control node and the third clock signal provided by the third clock end, and controlling the on-off of the third clock end and the pre-stage pull-up node in response to the second clock signal; a reset circuit connected with the reset end, the first power supply end, the control node and the pre-stage pull-up node respectively, and used for controlling the on-off of the first power supply end and the control node in response to the reset signal provided by the reset end, and controlling the on-off of the first power supply end and the pre-stage pull-up node; at least two pre-stage output circuits connected with the pre-stage pull-up node, one-to-one corresponding at least two output clock ends and one-to-one corresponding at least two pre-stage output ends respectively, each of the pre-stage output circuits being used for controlling the on-off of a corresponding one of the output clock ends and one of the pre-stage output ends in response to the potential of the pre-stage pull-up node; a pre-stage pull-down control circuit connected with the control node, the second clock end, the third clock end, the first power supply end, the second power supply end, the pre-stage pull-up node and a pre-stage pull-down node, and used for controlling the on-off of the second clock end and the pre-stage pull-down node in response to the potential of the control node and the third clock signal, controlling the on-off of the second power supply end and the pre-stage pull-down node in response to the second clock signal, controlling the on-off of the second clock end and the pre-stage pull-down node in response to the potential of the pre-stage pull-up node, and storing the potential of the pre-stage pull-down node based on the first power supply signal; a pre-stage pull-down circuit connected with the pre-stage pull-down node, the first power supply end, the pre-stage pull-up node and the at least two pre-stage output ends respectively, and used for controlling the on-off of the first power supply end and the pre-stage pull-up node in response to the potential of the pre-stage pull-down node, and controlling the on-off of the first power supply end and each of the pre-stage output ends, so as to output a gate driving signal through the pre-stage output end. The pre-stage decoding circuit further comprises:

17. The shift register cell of claim 16, wherein, a first pre-stage isolation circuit connected between the control node and the pre-stage pull-down control circuit, and further connected with the second power supply end, and used for controlling the conduction of the control node and the pre-stage pull-down control circuit in response to the second power supply signal; ​ A second pre-stage isolation circuit is connected between the pre-stage pull-up node and the at least two pre-stage output circuits, and is also connected with the second power supply end, and is configured to control the pre-stage pull-up node and the at least two pre-stage output circuits to be conductive in response to the second power supply signal.

18. A driving method of a shift register unit, configured to drive the shift register unit according to any one of claims 1 to 17; the method comprising: In a first stage, in the pre-stage decoding circuit, the pre-charge circuit controls the first clock end and the control node to be conductive in response to a gate signal provided by each of the at least two gate ends, a first clock signal provided by the first clock end, and a second clock signal provided by the second clock end; In a second stage, in each of the post-stage driving circuits, the post-stage input circuit controls the input clock end and the post-stage pull-up node to be conductive in response to a potential of the control node, a control clock signal provided by the control clock end, and an input clock signal provided by the input clock end, the post-stage pull-down control circuit controls the control clock end and the post-stage pull-down node to be conductive in response to the potential of the control node, and the post-stage pull-down circuit controls the first power supply end and the post-stage output end to be conductive in response to a potential of the post-stage pull-down node; In a third stage, in each of the post-stage driving circuits, the post-stage input circuit controls the input clock end and the post-stage pull-up node to be conductive in response to the input clock signal, the post-stage pull-down control circuit controls the control clock end and the post-stage pull-down node to be conductive in response to the potential of the control node and the potential of the post-stage pull-up node, and the post-stage output circuit controls the second power supply end and the post-stage output end to be conductive in response to the potential of the post-stage pull-up node. A plurality of groups of shift register units, each group of the shift register units comprising: at least two shift register units according to any one of claims 1 to 17; 19. A light emission control circuit, the light emission control circuit comprising: In each group of the shift register units, the first clock end, the second clock end, the control clock end, the input clock end, and the gate end are shared, and each group of the shift register units is configured to receive different gate signals provided by the at least two gate ends. A display panel, and the light emitting control circuit according to claim 19; 20. A display device comprising: The display panel comprises a plurality of pixels, and the light emitting control circuit is connected with the plurality of pixels and configured to transmit a light emitting control signal to the plurality of pixels to drive the plurality of pixels to emit light. ​

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