Light-emitting diode epitaxial structure, manufacturing method, and chip

Abstract

Disclosed in the present invention are a light-emitting diode epitaxial structure, a manufacturing method, and a chip. The light-emitting diode epitaxial structure comprises an N-type semiconductor stack structure, a P-type semiconductor stack structure, quantum well light-emitting layers, and a P-type waveguide layer which are stacked. The quantum well light-emitting layers are arranged between the N-type semiconductor stack structure and the P-type semiconductor stack structure. The P-type waveguide layer is arranged between the quantum well light-emitting layers and the P-type semiconductor stack structure, a P-type dopant and an N-type dopant are doped in the P-type waveguide layer, and in the P-type waveguide layer, the concentration of the P-type dopant is greater than that of the N-type dopant. Under the condition that the concentration of the P-type dopant is not reduced, the compensation effect between the N-type dopant and the P-type dopant is utilized to decrease the conductivity of the P-type waveguide layer, so that when a device employing the present invention is energized, lateral current spreading can be suppressed when a current passes through the P-type waveguide layer, avoiding light emission from the adjacent quantum well light-emitting layers, and reducing optical crosstalk.

Description

Light-emitting diode epitaxial structure, preparation method and chip Technical Field

[0001] The present invention relates to the field of micro-display technology, and in particular to a light emitting diode epitaxial structure, a preparation method and a chip. Background Art

[0002] In the epitaxial structure of Micro LED, the functional layer connected to the quantum well light-emitting layer has high conductivity. In particular, the Mg atoms doped in the functional layer are easier to diffuse, and the quantum well light-emitting layers of adjacent pixels are arranged continuously, causing the current to diffuse laterally to the quantum well light-emitting layer area of ​​the adjacent pixels, causing the surrounding pixels to emit light.

[0003] Due to the tiny size of Micro LED and the small spacing between panel pixels, when the device is working, the lighting of a certain pixel will cause the lighting of surrounding pixels, causing optical crosstalk, thereby affecting the quality of the picture presentation.

[0004] Summary of the Invention

[0005] The present invention provides a light-emitting diode epitaxial structure, a preparation method, and a chip. A P-type dopant and an N-type dopant are simultaneously doped in a P-type waveguide layer and an N-type waveguide layer of the light-emitting diode epitaxial structure. The concentration of the P-type dopant in the P-type waveguide layer is greater than that of the N-type dopant, and the concentration of the N-type dopant in the N-type waveguide layer is greater than that of the P-type dopant. Utilizing the compensatory effect of the two dopants, the conductivity of the P-type waveguide layer and the N-type waveguide layer can be reduced. When a device using the present invention is energized, when current passes through the P-type waveguide layer and the N-type waveguide layer and enters the light-emitting layer, lateral diffusion of the current can be suppressed, thereby preventing adjacent quantum well light-emitting layers from emitting light and reducing optical crosstalk, thereby ensuring the image quality presented by the device using the structure.

[0006] The present invention provides a light emitting diode epitaxial structure, comprising:

[0007] N-type semiconductor stack structure;

[0008] P-type semiconductor stack structure;

[0009] A quantum well light-emitting layer, wherein the N-type semiconductor stack structure, the P-type semiconductor stack structure, and the quantum well light-emitting layer are stacked, and the quantum well light-emitting layer is arranged between the N-type semiconductor stack structure and the P-type semiconductor stack structure; and

[0010] A P-type waveguide layer is arranged between the quantum well light-emitting layer and the P-type semiconductor stack structure, and the P-type waveguide layer is doped with a P-type dopant and an N-type dopant, and the concentration of the P-type dopant in the P-type waveguide layer is greater than the concentration of the N-type dopant.

[0011] The light-emitting diode epitaxial structure further includes an N-type waveguide layer, which is arranged between the quantum well light-emitting layer and the N-type semiconductor stack structure, and is doped with an N-type dopant.

[0012] The N-type waveguide layer is further doped with a P-type dopant, and the concentration of the P-type dopant in the N-type waveguide layer is lower than the concentration of the N-type dopant.

[0013] Wherein, the material of the P waveguide layer and the N waveguide layer is Al x Ga y In 1-x-y P or Al w In 1-w P, where 0.6≤x<1, 0<y≤0.4, (x+y)<1, 0.45<w<0.55.

[0014] The concentration of the P-type dopant in the P-type waveguide layer is 0.4×10 18 cm -3 ~1.0×10 18 cm -3 The concentration of the N-type dopant in the N-type waveguide layer is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 .

[0015] The light-emitting diode epitaxial structure further includes a substrate and a buffer layer. The substrate is arranged on a side of the N-type semiconductor stack structure away from the quantum well light-emitting layer, and the buffer layer is arranged between the substrate and the N-type semiconductor stack structure.

[0016] The light-emitting diode epitaxial structure further includes a corrosion stop layer, and the corrosion stop layer is arranged between the buffer layer and the N-type semiconductor stack structure.

[0017] Wherein, along the direction away from the quantum well light-emitting layer, the N-type semiconductor stack structure includes an N-type confinement layer, an N-type current spreading layer and an N-type ohmic contact layer stacked in sequence; and

[0018] Along a direction away from the quantum well light-emitting layer, the P-type semiconductor stack structure includes a P-type confinement layer, a P-type transition layer and a P-type current spreading layer stacked in sequence.

[0019] The P-type dopant includes at least one of Mg, C and Zn, and the N-type dopant includes Si and / or Te.

[0020] The present invention also provides a method for preparing a light-emitting diode epitaxial structure, comprising the following steps:

[0021] Providing a substrate, and placing the substrate in an epitaxial growth device;

[0022] forming an N-type semiconductor stack structure on the substrate;

[0023] forming a quantum well light-emitting layer on the N-type semiconductor stack structure;

[0024] forming a P-type waveguide layer on the quantum well light-emitting layer, wherein the P-type waveguide layer is doped with a P-type dopant and an N-type dopant, and a concentration of the P-type dopant in the P-type waveguide layer is greater than a concentration of the N-type dopant; and

[0025] A P-type semiconductor stacking structure is formed on the P-type waveguide layer.

[0026] Before forming the quantum well light-emitting layer on the N-type semiconductor stack structure, the method for preparing the light-emitting diode epitaxial structure further comprises the following steps:

[0027] An N-type waveguide layer is formed on the N-type semiconductor stack structure, wherein the N-type waveguide layer is doped with an N-type dopant.

[0028] Before forming the quantum well light-emitting layer on the N-type semiconductor stack structure, the method for preparing the light-emitting diode epitaxial structure further comprises the following steps:

[0029] An N-type waveguide layer is formed on the N-type semiconductor stack structure, wherein the N-type waveguide layer is doped with an N-type dopant and a P-type dopant, and the concentration of the N-type dopant in the N-type waveguide layer is greater than the concentration of the P-type dopant.

[0030] Before forming the N-type semiconductor stacked structure on the substrate, the method for preparing the light-emitting diode epitaxial structure further comprises the following steps:

[0031] forming a buffer layer on the substrate, and doping the buffer layer with an N-type dopant; and

[0032] An etch stop layer is formed on the buffer layer, and an N-type dopant is doped into the etch stop layer.

[0033] The step of forming the N-type semiconductor stack structure on the substrate includes the following steps:

[0034] forming an N-type ohmic contact layer on the etching stop layer;

[0035] forming an N-type current spreading layer on the N-type ohmic contact layer; and

[0036] An N-type confinement layer is formed on the N-type current spreading layer.

[0037] The step of forming the P-type semiconductor stacked structure on the quantum well light-emitting layer includes the following steps:

[0038] forming a P-type confinement layer on the P-type waveguide layer;

[0039] forming a P-type transition layer on the P-type confinement layer; and

[0040] A P-type current spreading layer is formed on the P-type transition layer.

[0041] The present invention also provides a method for preparing a light-emitting diode epitaxial structure, comprising the following steps:

[0042] Providing a substrate, and placing the substrate in an epitaxial growth device;

[0043] forming a P-type semiconductor stack structure on the substrate;

[0044] forming a P-type waveguide layer on the P-type semiconductor stack structure, wherein the P-type waveguide layer is doped with a P-type dopant and an N-type dopant, and a concentration of the P-type dopant in the P-type waveguide layer is greater than a concentration of the N-type dopant;

[0045] forming a quantum well light-emitting layer on the P-type waveguide layer; and

[0046] An N-type semiconductor stacking structure is formed on the quantum well light-emitting layer.

[0047] The present invention also provides a chip, comprising the above-mentioned light-emitting diode epitaxial structure, wherein the quantum well light-emitting layers of adjacent light-emitting diode epitaxial structures are continuously arranged. Beneficial effects:

[0048] (1) P-type dopants and N-type dopants are doped simultaneously in the P-type waveguide layer and the N-type waveguide layer. By utilizing the compensatory effect of the two dopants, the conductivity of the P-type waveguide layer and the N-type waveguide layer can be reduced. When the device to which the present invention is applied is energized, the lateral diffusion of the current can be suppressed when the current passes through the P-type waveguide layer and the N-type waveguide layer into the light-emitting layer, thereby preventing the adjacent quantum well light-emitting layers from emitting light and reducing optical crosstalk.

[0049] (2) The AlGaInP or AlInP material used in the P-type waveguide layer and the N-type waveguide layer has good light transmittance, thereby reducing the loss of light emitted by the quantum well light-emitting layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0051] FIG1 is a schematic structural diagram of a light emitting diode epitaxial structure according to an embodiment of the present invention;

[0052] FIG2 is a schematic structural diagram of a light emitting diode epitaxial structure according to another embodiment of the present invention;

[0053] FIG3 is a flow chart of the steps of a method for preparing a light-emitting diode epitaxial structure according to an embodiment of the present invention;

[0054] FIG4 is a flow chart of the steps further included in the method for preparing the light emitting diode epitaxial structure in FIG3 ;

[0055] FIG5 is a flowchart of the steps further included in the method for preparing the light-emitting diode epitaxial structure in FIG3 ;

[0056] FIG6 is a flow chart of sub-steps of step S20 in FIG3 ;

[0057] FIG. 7 is a flowchart of sub-steps of step S50 in FIG. 3 . DETAILED DESCRIPTION

[0058] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0059] Some embodiments of the present invention provide a light emitting diode epitaxial structure.

[0060] FIG1 is a schematic diagram of the structure of a light-emitting diode epitaxial structure provided by one embodiment of the present invention. As shown in FIG1 , the light-emitting diode epitaxial structure provided by the present invention includes an N-type semiconductor stack structure 40, a P-type semiconductor stack structure 80, a quantum well light-emitting layer 60, and a P-type waveguide layer 70. The N-type semiconductor stack structure 40, the P-type semiconductor stack structure 80, and the quantum well light-emitting layer 60 are stacked, and the quantum well light-emitting layer 60 is arranged between the N-type semiconductor stack structure 40 and the P-type semiconductor stack structure 80. In some embodiments, the material of the quantum well light-emitting layer 60 is Al a Ga b In 1-a-bP, where 0<a<1, 0<b<1, (a+b)<1, and the quantum well light emitting layer 60 is undoped. The P-type waveguide layer 70 is disposed between the quantum well light emitting layer 60 and the P-type semiconductor stacked structure 80. The P-type waveguide layer 70 is doped with a P-type dopant and an N-type dopant, and the concentration of the P-type dopant in the P-type waveguide layer 70 is greater than the concentration of the N-type dopant. In some embodiments, the P-type dopant doped in the P-type waveguide layer 70 is at least one of Mg, C, and Zn, and the concentration of the doped P-type dopant is 0.4×10 18 cm -3 ~1.0×10 18 cm -3 . In some embodiments, the N-type dopant doped in the P-type waveguide layer 70 is Si and / or Te. The P-type waveguide layer 70 is doped with P-type dopants, which has higher conductivity, and current will diffuse into the adjacent quantum well light-emitting layer 60, causing the adjacent quantum well light-emitting layer 60 to emit light, resulting in optical crosstalk. N-type dopants are further doped in the P-type waveguide layer 70, and the N-type dopant and the P-type dopant have a compensatory effect, which can reduce the conductivity of the P-type waveguide layer 70. The concentration of the N-type dopant is less than that of the P-type dopant. Therefore, under the condition of not reducing the concentration of the P-type dopant, that is, under the condition of ensuring the brightness of the pixel, the device using this structure is powered on. When the current passes through the P-type waveguide layer 70 into the quantum well light-emitting layer 60, the lateral diffusion of the current can be suppressed, thereby avoiding the adjacent quantum well light-emitting layer 60 from emitting light and reducing optical crosstalk.

[0061] As shown in FIG1 , the light emitting diode epitaxial structure further includes an N-type waveguide layer 50. The N-type waveguide layer 50 is disposed between the quantum well light emitting layer 60 and the N-type semiconductor stack structure 40, and is doped with an N-type dopant. In some embodiments, the N-type dopant doped in the N-type waveguide layer 50 is Si and / or Te, and the concentration of the doped N-type dopant is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 .

[0062] Furthermore, the N-type waveguide layer 50 is further doped with a P-type dopant. In some embodiments, the P-type dopant doped in the N-type waveguide layer 50 is at least one of Mg, C, and Zn. The concentration of the P-type dopant doped in the N-type waveguide layer 50 is lower than the concentration of the N-type dopant. The N-type waveguide layer 50 doped with the N-type dopant has a high conductivity, and current may diffuse into the adjacent quantum well light-emitting layer 60, causing the adjacent quantum well light-emitting layer 60 to emit light, resulting in optical crosstalk. By further doping the N-type waveguide layer 50 with a P-type dopant, the N-type dopant and the P-type dopant have a compensatory effect, which can reduce the conductivity of the N-type waveguide layer 50. The concentration of the P-type dopant is lower than that of the N-type dopant. Therefore, without reducing the concentration of the N-type dopant, that is, while ensuring the brightness of the pixel, when the device using this structure is powered on, when the current passes through the N-type waveguide layer 50 into the quantum well light-emitting layer 60, the lateral diffusion of the current can be suppressed, thereby preventing the adjacent quantum well light-emitting layer 60 from emitting light and reducing optical crosstalk.

[0063] Furthermore, the material of the P-type waveguide layer 70 and the N-type waveguide layer 50 is Al x Ga y In 1-x-y P or Al w In 1-w P, where 0.6≤x<1, 0<y≤0.4, (x+y)<1, 0.45<w<0.55. Specifically, the material of the P-type waveguide layer 70 is or Where 0.6≤x1<1, 0<y1≤0.4, (x1+y1)<1, 0.45<w1<0.55. The material of the N-type waveguide layer is or Wherein 0.6≤x2<1, 0<y2≤0.4, (x2+y2)<1, 0.45<w2<0.55. In some embodiments, the material of the P-type waveguide layer 70 is the same as the material of the N-type waveguide layer 50, and the proportions of the components in the materials are also the same. In other embodiments, the material of the P-type waveguide layer 70 is the same as the material of the N-type waveguide layer 50, but the proportions of the components in the materials are not exactly the same. In still other embodiments, the material of the P-type waveguide layer 70 is different from the material of the N-type waveguide layer 50. Al x Ga y In 1-x-y P material and Al w In 1-w P materials all have good light transmittance, thereby reducing the loss of light emitted by the quantum well light-emitting layer 60.

[0064] As shown in FIG1 , the light emitting diode epitaxial structure further includes a substrate 10 and a buffer layer 20. The substrate 10 is disposed on a side of the N-type semiconductor stack structure 40 away from the quantum well light emitting layer 60. The material of the substrate 10 is GaAs. The concentration of the dopant in the substrate 10 is 0.4×10 18 cm -3 ~4.0×10 18 cm -3 In some embodiments, the substrate 10 is doped with an N-type dopant, such as Si and / or Te. In other embodiments, the substrate 10 is doped with a P-type dopant, such as at least one of Mg, C, and Zn. The buffer layer 20 is disposed between the substrate 10 and the N-type semiconductor stack structure 40. The material of the buffer layer 20 is GaAs. The concentration of the dopant doped in the buffer layer 20 is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 In some embodiments, the buffer layer 20 is doped with an N-type dopant, such as Si and / or Te. Growing the GaAs buffer layer 20 on the GaAs substrate 10 can produce a new GaAs surface layer. Compared to growing an epitaxial structure directly on the substrate 10, growing an epitaxial structure on the GaAs buffer layer 20 can reduce the impact of impurities and dislocations in the substrate 10 on the subsequent material growth of the epitaxial layer structure.

[0065] As shown in FIG1 , the light emitting diode epitaxial structure further includes an etch stop layer 30. The etch stop layer 30 is disposed between the buffer layer 20 and the N-type semiconductor stack structure 40. In some embodiments, the material of the etch stop layer 30 is Ga 0.5 In 0.5 In other embodiments, the material of the corrosion stop layer 30 is Al c Ga d In 1-c-d P, where 0<c<1, 0<d<1, (c+d)<1. The etching stop layer 30 is doped with an N-type dopant. In some embodiments, the etching stop layer 30 is doped with Si and / or Te. The concentration of the dopant is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 The provided etching stop layer 30 can prevent damage to the functional layer of the epitaxial layer during the substrate 10 removal process.

[0066] As shown in FIG1 , in a direction away from the quantum well light-emitting layer 60, the N-type semiconductor stack structure 40 includes an N-type confinement layer 401, an N-type current spreading layer 402, and an N-type ohmic contact layer 403 stacked in sequence. The N-type confinement layer 401 is used to provide electrons to the quantum well light-emitting layer. The N-type confinement layer 401 is doped with an N-type dopant. In some embodiments, the N-type confinement layer 401 is doped with Si and / or Te, and the concentration of the N-type dopant is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 The material of the N-type confinement layer 401 is Al e In 1-e P, where 0<e<1. The N-type current spreading layer 402 is used to spread the current of the N-type semiconductor stack structure 40. The N-type current spreading layer 402 is doped with an N-type dopant. In some embodiments, the N-type current spreading layer 402 is doped with Si and / or Te, and the concentration of the N-type dopant is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 The material of the N-type current spreading layer 402 is Al f Ga g In 1-f-g P, where 0<f<1, 0<g<1, (f+g)<1. The N-type ohmic contact layer 403 is an N-electrode contact layer. The N-type ohmic contact layer 403 is doped with an N-type dopant. In some embodiments, the N-type ohmic contact layer 403 is doped with Si and / or Te, and the concentration of the N-type dopant is greater than 5.0×10 18 cm -3 The material of the N-type ohmic contact layer 403 is GaAs.

[0067] As shown in FIG1 , along a direction away from the quantum well light-emitting layer 60, the P-type semiconductor stack structure 80 includes a P-type confinement layer 801, a P-type transition layer 802, and a P-type current spreading layer 803 stacked in sequence. The P-type confinement layer 801 is used to provide holes to the quantum well light-emitting layer 60. The P-type confinement layer 801 is doped with a P-type dopant. In some embodiments, the P-type confinement layer 801 is doped with at least one of Mg, C, and Zn, and the concentration of the P-type dopant is 0.4×10 18 cm -3 ~1.0×10 18 cm -3 The material of the P-type confinement layer 801 is Al h In 1-hP, where 0<h<1. The P-type transition layer 802 is doped with a P-type dopant. In some embodiments, the P-type transition layer 802 is doped with one or more of Mg, C, and Zn, and the concentration of the P-type dopant is 1.0×10 18 cm -3 ~3.0×10 18 cm -3 The material of the P-type transition layer 802 is Al i Ga j In 1-i-j P, where 0<i<1, 0<j<1, (i+j)<1. The P-type current spreading layer 803 is used to spread the current of the P-type semiconductor stacked structure 80; and the P-type current spreading layer 803 is a P electrode. The P-type current spreading layer 803 is doped with a P-type dopant. In some embodiments, the P-type current spreading layer 803 is doped with one or more of Mg, C, and Zn, and the concentration of the P-type dopant is greater than 3.0×10 18 cm -3 . The material of the P-type current spreading layer 803 is GaP. The materials of the P-type limiting layer 801 and the P-type current spreading layer 803 are different, and the P-type current spreading layer 803 is thicker. There is a large lattice mismatch between the P-type limiting layer 801 and the P-type current spreading layer 803. Therefore, the provision of the P-type transition layer 802 is conducive to better crystal growth of the P-type current spreading layer 803, thereby ensuring better current diffusion of the P-type semiconductor stack structure 80, and is also beneficial to the performance and life of devices using this structure.

[0068] Figure 2 is a schematic structural diagram of a light-emitting diode epitaxial structure according to another embodiment of the present invention. Different from the previous embodiment, in this embodiment, the substrate 10 is arranged on the side of the P-type semiconductor stacking structure 80 away from the quantum well light-emitting layer 60. The buffer layer 20 is arranged between the substrate 10 and the P-type semiconductor stacking structure 80. The buffer layer 20 is doped with a P-type dopant, such as at least one of Mg, C and Zn. The corrosion stop layer 30 is arranged between the buffer layer 20 and the P-type semiconductor stacking structure 80. The corrosion stop layer 30 is doped with a P-type dopant, such as at least one of Mg, C and Zn. Along the direction away from the quantum well light-emitting layer 60, the P-type semiconductor stacking structure 80 includes a P-type confinement layer 801, a P-type current spreading layer 803 and a P-type ohmic contact layer 804 stacked in sequence. In some embodiments, the material of the P-type current spreading layer 803 is Al k Ga l In 1-k-lP, where 0 < k < 1, 0 < l < 1, and (k + l) < 1. Along a direction away from the quantum well light-emitting layer 60, the N-type semiconductor stack structure 40 includes an N-type confinement layer 401, an N-type transition layer 404, and an N-type current spreading layer 402 stacked in sequence. In some embodiments, the material of the N-type current spreading layer 402 is GaP.

[0069] Some embodiments of the present invention provide a method for preparing a light emitting diode epitaxial structure.

[0070] Figure 3 is a flowchart of the steps of a method for preparing a light emitting diode epitaxial structure according to an embodiment of the present invention. As shown in Figure 3, the method for preparing a light emitting diode epitaxial structure provided by the present invention includes steps S10 to S50.

[0071] In step S10, a substrate 10 is provided and placed in an epitaxial growth apparatus. After the substrate 10 is placed in the epitaxial growth apparatus, the following step is further included: doping the substrate 10. In some embodiments, the dopant in the substrate 10 is an N-type dopant, such as Si and / or Te. In other embodiments, the dopant in the substrate 10 is a P-type dopant, such as at least one of Mg, C, and Zn.

[0072] In step S20 , an N-type semiconductor stacked structure 40 is formed on the substrate 10 .

[0073] In step S30, a quantum well light emitting layer 60 is formed on the N-type semiconductor stack structure 40. In some embodiments, the process of forming the quantum well light emitting layer 60 includes the following steps: maintaining a phosphine atmosphere in the reaction chamber of the epitaxial growth equipment, providing growth materials trimethylaluminum, trimethylgallium and trimethylindium to the epitaxial growth equipment, and forming the quantum well light emitting layer 60 on the N-type semiconductor stack structure 40 with a material of Al; a Ga b In 1-a-b P, where 0<a<1, 0<b<1, (a+b)<1.

[0074] In step S40, a P-type waveguide layer 70 is formed on the quantum well light-emitting layer 60, wherein the P-type waveguide layer 70 is doped with a P-type dopant and an N-type dopant, and the concentration of the P-type dopant in the P-type waveguide layer 70 is greater than the concentration of the N-type dopant. Specifically, during the formation of the P-type waveguide layer, the pressure of the reaction chamber of the epitaxial growth equipment is set to 35mbar-60mbar, and the reaction chamber maintains a phosphine atmosphere, and the growth material and the P-type dopant, such as at least one of Mg, C and Zn, and the N-type dopant, such as Si and / or Te, are introduced into the reaction chamber together to form the P-type waveguide layer 70 on the quantum well light-emitting layer 60, wherein the amount of the N-type dopant introduced is to ensure that the concentration of the N-type dopant in the P-type waveguide layer 70 is less than the concentration of the P-type dopant. In some embodiments, the growth material is trimethylaluminum, trimethylgallium and trimethylindium, and the material of the formed P-type waveguide layer is Wherein 0.6≤x1<1, 0<y1≤0.4, (x1+y1)<1. In other embodiments, the growth material is trimethylaluminum and trimethylindium, and the material of the formed P-type waveguide layer is Among them, 0.45<w1<0.55.

[0075] In step S50 , a P-type semiconductor stacked structure 80 is formed on the P-type waveguide layer 70 .

[0076] Fig. 4 is a flow chart of the steps further included in the method for preparing the light emitting diode epitaxial structure in Fig. 3. As shown in Fig. 4, in some embodiments, before the above step S30, step S60 is further included.

[0077] In step S60 , an N-type waveguide layer 50 is formed on the N-type semiconductor stack structure 40 .

[0078] In some embodiments, during the process of forming the N-type waveguide layer 50 on the N-type semiconductor stack structure 40, an N-type dopant is doped into the N-type waveguide layer 50. Specifically, during the process of forming the N-type waveguide layer 50, the pressure of the reaction chamber of the epitaxial growth equipment is set to 35 mbar-60 mbar, and the reaction chamber maintains a phosphine atmosphere. Growth material and N-type dopants, such as Si and / or Te, are introduced into the reaction chamber to form the N-type waveguide layer 50 on the N-type semiconductor stack structure 40.

[0079] In other embodiments, during the process of forming the N-type waveguide layer 50 on the N-type semiconductor stack structure 40, an N-type dopant and a P-type dopant are doped into the N-type waveguide layer 50, and the concentration of the N-type dopant in the N-type waveguide layer 50 is greater than the concentration of the P-type dopant. Specifically, during the process of forming the N-type waveguide layer 50, the pressure of the reaction chamber of the epitaxial growth equipment is set to 35 mbar to 60 mbar, and the reaction chamber is maintained in a phosphine atmosphere. Growth material, an N-type dopant, such as Si and / or Te, and a P-type dopant, such as at least one of Mg, C, and Zn, are introduced into the reaction chamber to form the N-type waveguide layer 50 on the N-type semiconductor stack structure 40. The amount of P-type dopant introduced is sufficient to ensure that the concentration of the P-type dopant in the N-type waveguide layer 50 is less than the concentration of the N-type dopant.

[0080] In some embodiments, during the process of forming the N-type waveguide layer 50 on the N-type semiconductor stack structure 40, the growth material is trimethylaluminum, trimethylgallium and trimethylindium, and the material of the formed N-type waveguide layer is Wherein 0.6≤x2<1, 0<y2≤0.4, (x2+y2)<1. In other embodiments, the growth material is trimethylaluminum and trimethylindium, and the material of the formed N-type waveguide layer is Among them, 0.45<w2<0.55.

[0081] Figure 5 is a flowchart of steps further included in the method for preparing the light emitting diode epitaxial structure in Figure 3. As shown in Figure 5, in some embodiments, before the above step S20, the method for preparing the light emitting diode epitaxial structure further includes steps S70 and S80.

[0082] In step S70, a buffer layer 20 is formed on the substrate 10, and an N-type dopant is doped into the buffer layer 20. In some embodiments, during the formation of the buffer layer 20, trimethylgallium, trimethylarsenic, and an N-type dopant, such as Si and / or Te, are introduced into a reaction chamber of an epitaxial growth apparatus to form the buffer layer 20 on the substrate 10. The buffer layer 20 is made of GaAs and doped with the N-type dopant.

[0083] In step S80, an etch stop layer 30 is formed on the buffer layer 20, and an N-type dopant is doped into the etch stop layer 30. Specifically, during the formation of the etch stop layer 30, the reaction chamber of the epitaxial growth equipment maintains a phosphine atmosphere, and the growth material and the N-type dopant, such as Si and / or Te, are introduced into the reaction chamber together to form the etch stop layer 30 doped with the N-type dopant on the buffer layer 20. In some embodiments, during the formation of the etch stop layer 30, the growth material is trimethylgallium and trimethylindium, and the material of the formed etch stop layer 30 is Ga. 0.5 In 0.5In other embodiments, during the formation of the corrosion stop layer 30, the growth material is trimethylaluminum, trimethylgallium and trimethylindium, and the material of the corrosion stop layer 30 is Al c Ga d In 1-c-d P, where 0<c<1, 0<d<1, (c+d)<1.

[0084] Figure 6 is a flowchart of sub-steps of step S20 in Figure 3. As shown in Figure 6, in some embodiments, the above step S20 includes sub-steps S201 to S203.

[0085] In sub-step S201, an N-type ohmic contact layer 403 is formed on the substrate 10. As shown in FIG5 , before step S20, the method for preparing a light-emitting diode epitaxial structure may further include steps S70 and S80, in which a buffer layer 20 and an etching stop layer 30 are formed on the substrate 10. Therefore, in other embodiments, sub-step S201 is to form the N-type ohmic contact layer 403 on the etching stop layer 30. Specifically, during the process of forming the N-type ohmic contact layer 403, trimethylgallium, trimethylarsenic, and an N-type dopant, such as Si and / or Te, are introduced into the reaction chamber of the epitaxial growth equipment to form the N-type ohmic contact layer 403 made of GaAs on the substrate 10 or the etching stop layer 30.

[0086] In sub-step S202, an N-type current spreading layer 402 is formed on the N-type ohmic contact layer 403. Specifically, during the process of forming the N-type current spreading layer 402, the reaction chamber of the epitaxial growth equipment maintains a phosphine atmosphere, and trimethylaluminum, trimethylgallium, trimethylindium, and an N-type dopant, such as Si and / or Te, are introduced into the reaction chamber to form an Al-based layer on the N-type ohmic contact layer 403. f Ga g In 1-f-g The N-type current spreading layer 402 of P, wherein 0<f<1, 0<g<1, (f+g)<1.

[0087] In sub-step S203, an N-type confinement layer 401 is formed on the N-type current spreading layer 402. Specifically, during the formation of the N-type confinement layer 401, the reaction chamber of the epitaxial growth equipment maintains a phosphine atmosphere, and trimethylaluminum, trimethylindium, and an N-type dopant, such as Si and / or Te, are introduced into the reaction chamber to form an Al-based confinement layer on the N-type current spreading layer 402. e In 1-e The N-type confinement layer 401 of P, wherein 0<e<1.

[0088] Figure 7 is a flowchart of sub-steps of step S50 in Figure 3. As shown in Figure 7, in some embodiments, the above step S50 includes sub-steps S501 to S503.

[0089] In sub-step S501, a P-type confinement layer 801 is formed on the P-type waveguide layer 70. Specifically, during the formation of the P-type confinement layer 801, the reaction chamber of the epitaxial growth equipment maintains a phosphine atmosphere, and trimethylaluminum, trimethylindium, and a P-type dopant, such as at least one of Mg, C, and Zn, are introduced into the reaction chamber to form an Al-based confinement layer on the P-type waveguide layer 70. h In 1-h A P-type confinement layer 801 of P, where 0<h<1.

[0090] In sub-step S502, a P-type transition layer 802 is formed on the P-type confinement layer 801. Specifically, during the process of forming the P-type transition layer 802, the reaction chamber of the epitaxial growth equipment maintains a phosphine atmosphere, and trimethylaluminum, trimethylgallium, trimethylindium, and a P-type dopant, such as at least one of Mg, C, and Zn, are introduced into the reaction chamber to form an Al-based transition layer on the P-type confinement layer 801. i Ga j In 1-i-j P-type transition layer 802, wherein 0<i<1, 0<j<1, (i+j)<1.

[0091] In sub-step S503, a P-type current spreading layer 803 is formed on the P-type transition layer 802. Specifically, during the formation of the P-type current spreading layer 803, a phosphine atmosphere is maintained in the reaction chamber of the epitaxial growth equipment, and trimethylgallium and a P-type dopant, such as at least one of Mg, C, and Zn, are introduced into the reaction chamber to form the P-type current spreading layer 803 made of GaP on the P-type transition layer 802.

[0092] In other embodiments, the buffer layer 20 is doped with a P-type dopant. The etch-stop layer 30 on the buffer layer 20 is doped with a P-type dopant. A P-type ohmic contact layer 804, a P-type current spreading layer 803, and a P-type confinement layer 801 are sequentially formed on the etch-stop layer 30. A P-type waveguide layer 70 is formed on the P-type confinement layer 801. A quantum well light-emitting layer 60 is formed on the P-type waveguide layer 70. An N-type waveguide layer 50, an N-type confinement layer 401, an N-type transition layer 404, and an N-type current spreading layer 402 are sequentially formed on the quantum well light-emitting layer 60.

[0093] Some embodiments of the present invention provide a chip.

[0094] In some embodiments, the chip is a MicroLED chip. The chip includes the aforementioned LED epitaxial structure, and the quantum well light-emitting layers 60 of adjacent LED epitaxial structures are arranged continuously. During the chip manufacturing process, the quantum well light-emitting layers 60 are not etched through, that is, the quantum well light-emitting layers 60 of adjacent LED epitaxial structures are continuous, which can reduce the impact of sidewall effects on chip performance.

[0095] Some embodiments of the present invention further provide a micro display panel, which includes the above-mentioned light emitting diode epitaxial structure.

[0096] Among them, the above-mentioned micro display panel has a very small volume, and the length and width dimensions are between 500μm and 50,000μm. The area of ​​the light-emitting area of ​​the above-mentioned micro display panel is very small, such as 1mm×1mm, 2.64mm×2.02mm, 3mm×5mm, etc. The light-emitting area of ​​the above-mentioned micro display panel includes a plurality of micro LED pixels arranged in an array, and the specific pixel arrangement can be one of 320×240, 640×480, 1600×1200, 1920×1080, and 2560×1440. The size of a single micro LED pixel is between 100nm and 100μm. In some embodiments, the size of a single micro LED pixel is between 150nm and 15μm. In some embodiments, the size of a single micro LED pixel can also be less than 10μm.

[0097] A driver backplane is located behind the micro-LED pixel array. It is electrically connected to the micro-LEDs within the array and receives signals such as image data from the outside world, controlling the corresponding micro-LEDs to illuminate or not illuminate. The driver backplane is typically a TFT (Thin Film Transistor) board or an IC (Integrated Circuit) board.

[0098] For example, the driving backplane of the above-mentioned micro display panel integrates a frame buffer, a column driving circuit, and a row driving circuit. The frame buffer includes a first pixel storage area, and the micro LED pixel array includes a second pixel storage area. A complete frame of pixel grayscale data from the outside world can first enter the first pixel storage area of ​​the frame buffer, and the column driving circuit can load the pixel grayscale data in the first pixel storage area of ​​the frame buffer into the second pixel storage area of ​​the micro LED pixel array. The row driving circuit can scan the pixel grayscale data in the second pixel storage area and generate a pulse modulation signal to achieve the purpose of displaying different grayscales. When driving multiple micro LED pixels in the micro LED pixel array, it is possible to adopt a single pixel independent driving method or a multiple pixel unit independent driving method. The specific driving method should not constitute a limitation to the present invention.

[0099] It should be noted that the application of the above-mentioned light-emitting diode epitaxial structure in a micro display panel should not constitute a limitation on the application of the present invention.

[0100] It should be noted that relational terms in this document, such as "first" and "second", are used only to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. In addition, the words "include", "have" and "include" and other similar forms are intended to be equivalent in meaning and are open-ended, and one or more items following any of these words are not intended to be an exhaustive list of such one or more items, or to be limited to the listed one or more items.

[0101] As used herein, unless expressly stated otherwise, the term "or" encompasses all possible combinations unless not feasible. For example, if a component is stated to include either A or B, then unless expressly stated otherwise or not feasible, the component may include A, or B, or A and B. As a second example, if a component is stated to include either A, B, or C, then unless expressly stated otherwise or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0102] In the foregoing description, embodiments have been described with reference to many specific details, which may vary depending on the implementation. Certain changes and modifications may be made to the described embodiments. Other embodiments will be clear to those skilled in the art in view of the description and practice of the invention disclosed herein. The description and examples are intended to be regarded as merely exemplary, with the true scope and spirit of the invention being indicated by the following claims. The order of steps shown in the accompanying drawings is also intended to be for illustrative purposes only and is not intended to be limited to any particular order of steps. Therefore, it will be understood by those skilled in the art that these steps may be performed in different orders while implementing the same method.

[0103] In the drawings and the specification, exemplary embodiments have been disclosed. However, many variations and modifications may be made to these embodiments. Therefore, although specific terms are employed, they are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A light-emitting diode epitaxial structure, characterized in that: include: an N-type semiconductor stack structure; A P-type semiconductor stack structure; a quantum well light-emitting layer, wherein the N-type semiconductor stack structure, the P-type semiconductor stack structure, and the quantum well light-emitting layer are stacked, and the quantum well light-emitting layer is arranged between the N-type semiconductor stack structure and the P-type semiconductor stack structure; as well as A P-type waveguide layer is provided between the quantum well light-emitting layer and the P-type semiconductor stack structure, the P-type waveguide layer is doped with a P-type dopant and an N-type dopant, and the concentration of the P-type dopant in the P-type waveguide layer is greater than the concentration of the N-type dopant.

2. The light emitting diode epitaxial structure according to claim 1, characterized in that: The invention further comprises an N-type waveguide layer, wherein the N-type waveguide layer is arranged between the quantum well light-emitting layer and the N-type semiconductor stack structure, and the N-type waveguide layer is doped with an N-type dopant.

3. The light emitting diode epitaxial structure according to claim 2, characterized in that: The N-type waveguide layer is further doped with a P-type dopant, and the concentration of the P-type dopant in the N-type waveguide layer is lower than the concentration of the N-type dopant.

4. The light emitting diode epitaxial structure according to claim 2, characterized in that: The material of the P-type waveguide layer and the N-type waveguide layer is Al x Ga y In 1-x-y P or Al w In 1-w P, where 0.6≤x<1, 0<y≤0.4, (x+y)<1, 0.45<w<0.

55.

5. The light emitting diode epitaxial structure according to claim 2, characterized in that: The concentration of the P-type dopant in the P-type waveguide layer is 0.4×10 18 cm -3 ~1.0×10 18 cm -3 The concentration of the N-type dopant in the N-type waveguide layer is 1.0×10 18 cm -3 ~2.0×10 18 cm -3 .

6. The light emitting diode epitaxial structure according to claim 1, characterized in that: It further includes a substrate and a buffer layer, wherein the substrate is arranged on a side of the N-type semiconductor stack structure away from the quantum well light-emitting layer, and the buffer layer is arranged between the substrate and the N-type semiconductor stack structure.

7. The light emitting diode epitaxial structure according to claim 6, characterized in that: The method further includes a corrosion stop layer, wherein the corrosion stop layer is arranged between the buffer layer and the N-type semiconductor stack structure.

8. The light emitting diode epitaxial structure according to claim 7, characterized in that: Along a direction away from the quantum well light-emitting layer, the N-type semiconductor stack structure includes an N-type confinement layer, an N-type current spreading layer and an N-type ohmic contact layer stacked in sequence; as well as Along a direction away from the quantum well light-emitting layer, the P-type semiconductor stack structure includes a P-type confinement layer, a P-type transition layer and a P-type current spreading layer stacked in sequence.

9. The light emitting diode epitaxial structure according to claim 3, characterized in that: The P-type dopant includes at least one of Mg, C, and Zn, and the N-type dopant includes Si and / or Te.

10. A method for preparing a light-emitting diode epitaxial structure, characterized in that: The following steps are involved: Providing a substrate, and placing the substrate in an epitaxial growth device; forming an N-type semiconductor stack structure on the substrate; forming a quantum well light-emitting layer on the N-type semiconductor stack structure; forming a P-type waveguide layer on the quantum well light-emitting layer, wherein the P-type waveguide layer is doped with a P-type dopant and an N-type dopant, and the concentration of the P-type dopant in the P-type waveguide layer is greater than the concentration of the N-type dopant; and A P-type semiconductor stacking structure is formed on the P-type waveguide layer.

11. The method for preparing a light emitting diode epitaxial structure according to claim 10, wherein: Before forming the quantum well light-emitting layer on the N-type semiconductor stack structure, the method further includes the following steps: An N-type waveguide layer is formed on the N-type semiconductor stack structure, wherein the N-type waveguide layer is doped with N-type dopants.

12. The method for preparing a light emitting diode epitaxial structure according to claim 10, characterized in that: Before forming the quantum well light-emitting layer on the N-type semiconductor stack structure, the method further includes the following steps: An N-type waveguide layer is formed on the N-type semiconductor stack structure, wherein the N-type waveguide layer The N-type waveguide layer is doped with an N-type dopant and a P-type dopant, and the concentration of the N-type dopant in the N-type waveguide layer is greater than the concentration of the P-type dopant.

13. The method for preparing a light emitting diode epitaxial structure according to claim 11 or 12, characterized in that: Before forming the N-type semiconductor stacked structure on the substrate, the method further includes the following steps: forming a buffer layer on the substrate and doping the buffer layer with an N-type dopant; and An etch stop layer is formed on the buffer layer, and an N-type dopant is doped into the etch stop layer.

14. The method for preparing a light emitting diode epitaxial structure according to claim 13, wherein: The step of forming the N-type semiconductor stacked structure on the substrate includes the following steps: forming an N-type ohmic contact layer on the etching stop layer; forming an N-type current spreading layer on the N-type ohmic contact layer; and An N-type confinement layer is formed on the N-type current spreading layer.

15. The method for preparing a light emitting diode epitaxial structure according to claim 10, characterized in that: The step of forming the P-type semiconductor stacked structure on the quantum well light-emitting layer includes the following steps: forming a P-type confinement layer on the P-type waveguide layer; forming a P-type transition layer on the P-type confinement layer; and A P-type current spreading layer is formed on the P-type transition layer.

16. A method for preparing a light emitting diode epitaxial structure, characterized in that: The following steps are involved: Providing a substrate, and placing the substrate in an epitaxial growth device; forming a P-type semiconductor stack structure on the substrate; forming a P-type waveguide layer on the P-type semiconductor stack structure, wherein the P-type waveguide layer is doped with a P-type dopant and an N-type dopant, and a concentration of the P-type dopant in the P-type waveguide layer is greater than a concentration of the N-type dopant; forming a quantum well light-emitting layer on the P-type waveguide layer; as well as An N-type semiconductor stacking structure is formed on the quantum well light-emitting layer.

17. A chip, characterized in that: The light-emitting diode epitaxial structure comprises any one of items 1 to 9, and the quantum well light-emitting layers of adjacent light-emitting diode epitaxial structures are continuously arranged.

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