Inverter and photovoltaic power generation system

Abstract

An inverter (100) and a photovoltaic power generation system. The inverter (100) comprises: an isolation circuit (10), a direct-current bus (20), a balance circuit (30), and an inverter circuit (40), wherein the isolation circuit (10) comprises a primary-side circuit (11) connected to a direct-current source, and a secondary-side circuit (13); the direct-current bus (20) comprises a positive bus capacitor (21) and a negative bus capacitor (23); the balance circuit (30) comprises a first switch (31) and a second switch (33) connected to each other, and an inductor (35), the first switch (31) being connected to the positive bus capacitor (21), the second switch (33) being connected to the negative bus capacitor (23), and the inductor (35) being connected to the midpoint of the direct-current bus (20); and the inverter circuit (40) comprises a plurality of loops (41), the loops (41) being configured to output voltages of different phases.

Description

Inverters and photovoltaic power generation systems

[0001] Priority information

[0002] This application claims priority and benefits of patent application No. 202420287445.1 filed with the State Intellectual Property Office of China on February 6, 2024, and the entire text of which is incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of inverters, and more specifically, to an inverter and a photovoltaic power generation system. Background Art

[0004] When the power grid is split-phase, different loads require output voltages from corresponding phases to power them. Therefore, when the grid system composed of inverters is off-grid, the inverters must be able to output voltages from different phases to operate normally with load. In related technologies, because the inverter continuously draws power from the same bus capacitor when operating with half-wave load, the voltages of multiple bus capacitors become unbalanced, which may trigger the inverter's protection mechanism, causing the inverter to stop working and thus preventing the inverter from stably delivering split-phase output.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide an inverter and a photovoltaic power generation system.

[0007] An embodiment of the present application provides an inverter, comprising an isolation circuit, a DC bus, a balancing circuit, and an inverter circuit; wherein the isolation circuit comprises a primary circuit and a secondary circuit, the input end of the primary circuit being connected to a DC source; the DC bus comprising a positive bus capacitor and a negative bus capacitor, the first electrode of the positive bus capacitor being connected to the positive output electrode of the secondary circuit, the second electrode of the positive bus capacitor being connected to the first electrode of the negative bus capacitor, and the second electrode of the negative bus capacitor being connected to the negative output electrode of the secondary circuit; the balancing circuit comprising a first switch, a second switch, and an inductor, the first end of the first switch being connected to the first electrode of the positive bus capacitor, the second end of the first switch being connected to the first end of the second switch, and the second end of the second switch being connected to the second electrode of the negative bus capacitor; the first end of the inductor being connected to the second end of the first switch and the first end of the second switch, and the second end of the inductor being connected to the second electrode of the positive bus capacitor and the first electrode of the negative bus capacitor; the inverter circuit being connected to the DC bus, the inverter circuit comprising multiple loops, each of the loops being configured to output a voltage of a different phase.

[0008] In this way, the DC bus and the DC source can be isolated at high frequency through the isolation circuit to avoid damage to the components in the inverter; a balancing circuit is set to balance the voltage of the positive bus capacitor and the negative bus capacitor to avoid the voltage imbalance between the positive bus capacitor and the negative bus capacitor when the inverter is biased or half-wave loaded, which causes the circuit to be unable to stably output voltages of different phases, thereby enabling the inverter to stably output in phases to power different loads.

[0009] In some embodiments, the first switch includes a first balancing transistor, and the second switch includes a second balancing transistor. When the voltage of the positive bus capacitor is less than that of the negative bus capacitor, the duty cycle of the first balancing transistor is less than the duty cycle of the second balancing transistor, so as to control the charging of the positive bus capacitor so that the voltages of the positive bus capacitor and the negative bus capacitor are the same.

[0010] In this way, by controlling the duty cycle of the first balancing transistor, the charging of the first bus capacitor can be controlled. When the voltages of the two bus capacitors are the same, the duty cycles of any two balancing transistors are the same. When the voltage of a certain bus capacitor is low, the duty cycle of the balancing transistor corresponding to the bus capacitor is relatively small to control the charging of the bus capacitor, so that the voltages of the two bus capacitors are the same.

[0011] In certain embodiments, the first switch includes a first balancing transistor, and the second switch includes a second balancing transistor. When the voltage of the positive bus capacitor is greater than the voltage of the negative bus capacitor, the duty cycle of the first balancing transistor is greater than the duty cycle of the second balancing transistor, thereby controlling the charging of the negative bus capacitor so that the voltages of the positive and negative bus capacitors are the same. Thus, by controlling the duty cycle of the second balancing transistor, the charging of the negative bus capacitor can be controlled. When the voltages of the two bus capacitors are the same, the duty cycles of any two balancing transistors are the same. When the voltage of the positive bus capacitor is higher, the duty cycle of the balancing transistor corresponding to the positive bus capacitor is larger, thereby controlling the charging of the negative bus capacitor so that the voltages of the two bus capacitors are the same.

[0012] In this way, by controlling the duty cycle of the second balancing transistor, the charging of the negative bus capacitor can be controlled. When the voltages of the two bus capacitors are the same, the duty cycles of any two balancing transistors are the same. When the voltage of the positive bus capacitor is higher, the duty cycle of the balancing transistor corresponding to the positive bus capacitor is larger to control the charging of the negative bus capacitor, thereby making the voltages of the two bus capacitors the same.

[0013] In some embodiments, the loop includes at least two transistors and an output end, the transistors and the bus capacitor are connected in parallel, and the transistors of any two loops are connected in parallel with each other; one end of the output end is connected to the two transistors, and the other end of the output end is connected to the second pole of the positive bus capacitor and the first pole of the negative bus capacitor, and the output end is used to output the output voltage.

[0014] In this way, the output voltage of the output terminal of the same loop can be controlled by the transistors in the loop.

[0015] In some embodiments, the transistor includes a first transistor and a second transistor, the first end of the first transistor is connected to the first electrode of the positive bus capacitor, the second end of the first transistor is connected to the first end of the second transistor, and the second end of the second transistor is connected to the negative bus capacitor, and the conduction time of the first transistor and the second transistor is different so that the output voltage at the output end is an AC voltage.

[0016] In this way, by controlling the on-times of the multiple transistors in the loop to be different, the output voltage outputted from the output end of the loop can be made an AC voltage, thereby achieving the conversion from a DC voltage to an AC voltage.

[0017] In some embodiments, the conduction time of the first transistors of any two of the loops is different, the conduction time of the second transistors of any two of the loops is also different, and the phases of the output voltages output by any two of the loops are different.

[0018] In this way, by controlling the on-times of the first transistors of any two loops to be different and the on-times of the second transistors of any two loops to be different, the phases of the output voltages of any two loops can be made different, thereby achieving phase-split output.

[0019] In certain embodiments, when the inverter is in an off-grid state, each loop outputs voltages of different phases.

[0020] In this way, when in an off-grid state, multiple circuits of the inverter can output output voltages of different phases, thereby being able to supply power to different loads.

[0021] In certain embodiments, when the inverter is in a grid-connected state, the phases of the voltages output by all the loops of the inverter are the same.

[0022] Thus, when in the grid-connected state, the inverter controls the on-off time of the transistors in all the circuits so that the inverter circuit composed of all the circuits outputs an AC voltage.

[0023] In some embodiments, the primary circuit includes a primary winding and a switching tube, and the secondary circuit includes a secondary winding. When the switching tube is turned on, the DC source charges the primary winding; when the switching tube is closed, the DC source does not charge the primary winding, and the secondary winding charges the DC bus.

[0024] In this way, by controlling the DC source to charge the primary winding and the secondary winding to charge the DC bus at different times, isolation of the DC source and the DC bus can be achieved.

[0025] In some embodiments, when the input voltage of the DC source is less than a set voltage, the isolation circuit is configured to boost the input voltage.

[0026] In this way, by boosting the input voltage through the isolation circuit, the bus voltage can be raised to the rated bus voltage while performing high-frequency isolation, so that the output voltage output by the subsequent circuit based on the bus voltage meets the rated output voltage.

[0027] An embodiment of the present application provides a photovoltaic power generation system, which includes the inverter and a control module of any of the above embodiments, and the control module is used to control the balancing circuit to balance the voltage of the bus capacitor.

[0028] In this way, the DC bus and the DC source can be isolated at high frequency through the isolation circuit to avoid damage to the components in the inverter; a balancing circuit is set to balance the voltage of the positive bus capacitor and the negative bus capacitor to avoid the voltage imbalance between the positive bus capacitor and the negative bus capacitor when the inverter is biased or half-wave loaded, which causes the circuit to be unable to stably output voltages of different phases, thereby enabling the inverter to stably output in phases to power different loads.

[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0031] FIG1 is a circuit diagram of an inverter according to an embodiment of the present application;

[0032] FIG2 is a circuit diagram of a DC bus and a loop according to an embodiment of the present application;

[0033] FIG3 is a circuit diagram of a DC bus and a loop according to an embodiment of the present application;

[0034] FIG4 is a circuit diagram of a DC bus and a balancing circuit according to an embodiment of the present application;

[0035] FIG5 is a circuit diagram of an isolation circuit and a DC bus according to an embodiment of the present application;

[0036] FIG6 is a circuit diagram of an inverter according to an embodiment of the present application;

[0037] FIG7 is a circuit diagram of an inverter according to an embodiment of the present application;

[0038] FIG8 is a circuit diagram of an inverter according to an embodiment of the present application;

[0039] FIG9 is a circuit diagram of an inverter according to an embodiment of the present application;

[0040] FIG10 is a circuit diagram of an inverter according to an embodiment of the present application;

[0041] FIG11 is a circuit diagram of an inverter according to an embodiment of the present application;

[0042] FIG12 is a circuit diagram of an inverter according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] The embodiments of the present application are described in detail below. Implementations of the embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0044] When the power grid is split-phase, different loads require output voltages from corresponding phases to power them. Therefore, when the grid system composed of inverters is off-grid, the inverters must be able to output voltages from different phases to operate normally with load. In related technologies, because the inverter continuously draws power from the same bus capacitor when operating with half-wave load, the voltages of multiple bus capacitors become unbalanced, which may trigger the inverter's protection mechanism, causing the inverter to stop working and thus preventing the inverter from stably delivering split-phase output.

[0045] Referring to Figures 1 to 4, an embodiment of the present application provides an inverter 100, which includes an isolation circuit 10, a DC bus 20, a balancing circuit 30, and an inverter circuit 40; wherein the isolation circuit 10 includes a primary circuit 11 and a secondary circuit 13, and the input end of the primary circuit 11 is used to connect to a DC source; the DC bus 20 includes a positive bus capacitor 21 and a negative bus capacitor 23, the first electrode of the positive bus capacitor 21 is connected to the output positive electrode of the secondary circuit 13, the second electrode of the positive bus capacitor 21 is connected to the first electrode of the negative bus capacitor 23, and the second electrode of the negative bus capacitor 23 is connected to the output negative electrode of the secondary circuit 13; the balancing circuit 30 includes a first switch 31, a second switch 33 and an inductor 35. The first end of the first switch 31 is connected to the first pole of the positive bus capacitor 21, the second end of the first switch 31 is connected to the first end of the second switch 33, the second end of the second switch 33 is connected to the second pole of the negative bus capacitor 23, the first end of the inductor 35 is connected to the second end of the first switch 31 and the first end of the second switch 33, and the second end of the inductor 35 is connected to the second pole of the positive bus capacitor 21 and the first pole of the negative bus capacitor 23; the inverter circuit 40 is connected to the DC bus 20, and the inverter circuit 40 includes multiple loops 41, each loop 41 is used to output a voltage of a different phase.

[0046] Specifically, when connected to a split-phase power grid, since the power grid has a neutral point, the inverter 100 only needs to output AC power of a uniform phase, which is then output to different loads in phases by the power grid. When the inverter 100 is separated from the power grid, if the inverter 100 supplies power to a load, different loads need to be supplied with power at different phases, which requires the inverter 100 to output voltages of different phases. Therefore, multiple loops 41 are provided, each of which can convert the voltage of the bus capacitor and output output voltages of different phases, thereby supplying power to different loads. The inverter circuit 40 can be an h4 inverter bridge, an h5 inverter bridge, an h6 inverter bridge, etc. In one embodiment, the inverter circuit 40 is an h4 inverter bridge, and the loop 41 includes a first loop and a second loop. The first loop and the second loop share a node N, which can serve as a neutral point. The output terminal L1N of the first loop outputs a voltage of the first phase, and the output terminal L2N of the second loop outputs a voltage of the second phase. Since, when performing phase splitting, if the voltage of the DC bus 20 is unbalanced, the output voltage of the outputs of the multiple loops 41 will be unstable, a balancing circuit 30 is provided to balance the voltages of the multiple bus capacitors, so that the voltages of the positive bus capacitor 21 and the negative bus capacitor 23 are the same, so as to obtain a balanced bus voltage, thereby ensuring that the output voltage of the phase split output of the loop 41 is stable. The first switch 31 of the balancing circuit 30 is connected in parallel with the positive bus capacitor 21, and the second switch 33 is connected in parallel with the negative bus capacitor 23; the positive bus capacitor 21 can be capacitor CS1, and the negative bus capacitor 23 can be capacitor CS2, then the first switch 31 is connected in parallel with the positive bus capacitor CS1, and the second switch 33 is connected in parallel with the negative bus capacitor CS2, the first pole of the positive bus capacitor CS1 is connected to the output positive pole of the secondary circuit 13, the second pole of the positive bus capacitor CS1 is connected to the first pole of the negative bus capacitor CS2, and the second pole of the negative bus capacitor CS2 is connected to the secondary circuit 13 output negative electrode; the balancing circuit 30 includes a first switch 31, a second switch 33, and an inductor Ls1. The first end of the first switch 31 is connected to the first electrode of the positive bus capacitor CS1, the second end of the first switch 31 is connected to the first end of the second switch 33, and the second end of the second switch 33 is connected to the second electrode of the negative bus capacitor CS2. The first end of the inductor Ls1 is connected to the second end of the first switch 31 and the first end of the second switch 33, and the second end of the inductor Ls1 is connected to the second electrode of the positive bus capacitor CS1 and the first electrode of the negative bus capacitor CS2. Referring to Figures 5 to 8, the isolation circuit 10 is an isolated DC-DC circuit. The isolation circuit 10 can be a single-transistor flyback circuit (as shown in Figure 5), a dual-transistor flyback circuit (as shown in Figure 6), a single-transistor forward circuit (as shown in Figure 7), a dual-transistor forward circuit (as shown in Figure 8), etc. Among them, the flyback circuit has a simple circuit structure, is easy to control, and is suitable for low-power application scenarios; the forward circuit has a more complex circuit structure, but can be used in high-power application scenarios. The isolation circuit 10 can be flexibly selected according to actual conditions to meet isolation requirements.In addition, the isolation circuit 10 can also cooperate with the control module to perform a maximum power point tracking (MPPT) function to obtain the maximum output power.

[0047] In one embodiment, the isolation circuit 10 is a single-tube flyback circuit, which includes a capacitor C1, a switch tube Q1, a winding T1 and a diode D1. The single-tube flyback circuit can meet the isolation requirements of the inverter circuit 40 to perform high-frequency isolation on the inverter circuit 40.

[0048] In this way, the bus capacitor and the DC source can be isolated at high frequency through the isolation circuit 10 to prevent damage to the components in the inverter 100; a balancing circuit 30 is set to balance the voltage of the bus capacitor to prevent the circuit 41 from being unable to stably output voltages of different phases due to the unbalanced voltage of the bus capacitor when the inverter 100 is biased loaded or half-wave loaded, thereby enabling the inverter 100 to stably output in phases to power different loads.

[0049] Please refer to Figure 4. In some embodiments, the first switch 31 includes a first balancing transistor 411, and the second switch 33 includes a second balancing transistor 411. When the voltage of the positive bus capacitor 21 is less than that of the negative bus capacitor 23, the duty cycle of the first balancing transistor 411 is less than the duty cycle of the second balancing transistor 411, so as to control the charging of the positive bus capacitor 21 so that the voltages of the positive bus capacitor 21 and the negative bus capacitor 23 are the same.

[0050] Specifically, a first balancing transistor Q2 is connected in parallel with the positive bus capacitor CS1, and a second balancing transistor Q3 is connected in parallel with the negative bus capacitor CS2. When the voltages of the positive bus capacitor CS1 and the negative bus capacitor CS2 are the same, the voltages of the two bus capacitors are balanced, and the duty cycles of the first balancing transistor Q2 and the second balancing transistor Q3 are the same. When the voltage of the positive bus capacitor CS1 is lower than the voltage of the negative bus capacitor CS2, the duty cycle of the first balancing transistor Q2 corresponding to the lower voltage positive bus capacitor CS1 is smaller than the duty cycle of the second balancing transistor Q3, thereby controlling the charging of the lower voltage positive bus capacitor CS1. This is done until the voltage of the positive bus capacitor CS1 is equal to the voltage of the negative bus capacitor CS2. The duty cycles of the first balancing transistor Q2 and the second balancing transistor Q3 are then controlled to return to the same value, thereby stopping the charging of the positive bus capacitor CS1.

[0051] In one embodiment, the drain of the first balancing transistor Q2 is connected to one end of the positive bus capacitor CS1, the source of the first balancing transistor Q2 is connected to the other end of the positive bus capacitor CS1 through the inductor 35, and the other end of the positive bus capacitor CS1 is connected to one end of the negative bus capacitor CS2. The drain of the second balancing transistor Q3 is connected to one end of the negative bus capacitor CS2 connected to the positive bus capacitor CS1 through the inductor 35, the source of the first balancing transistor Q2 is connected to the other end of the negative bus capacitor CS2, and the gate of the first balancing transistor Q2 and the gate of the second balancing transistor Q3 are respectively connected to a control module, and the control module can control the duty cycle of the first balancing transistor Q2 and the second balancing transistor Q3. The control module controls the duty cycle of the first balancing transistor Q2 and the second balancing transistor Q3 according to the voltages of the positive bus capacitor CS1 and the negative bus capacitor CS2. When the voltages of the positive bus capacitor CS1 and the negative bus capacitor CS2 are the same, the duty cycles of the first balancing transistor Q2 and the second balancing transistor Q3 are controlled to be the same. When the voltage of the positive bus capacitor CS1 is lower than the voltage of the negative bus capacitor CS2, the duty cycle of the first balancing transistor Q2 is controlled to be smaller than the duty cycle of the second balancing transistor Q3 to control the charging of the positive bus capacitor CS1. When the voltage of the negative bus capacitor CS2 is lower than the voltage of the positive bus capacitor CS1, the duty cycle of the second balancing transistor Q3 is controlled to be smaller than the duty cycle of the first balancing transistor Q2 to control the charging of the negative bus capacitor CS2.

[0052] In this way, by controlling the duty cycle of the first balancing transistor 411 and the second balancing transistor 411, the charging of the bus capacitor can be controlled. When the voltages of the two bus capacitors are the same, the duty cycles of the two balancing transistors 411 are the same; when the voltage of the positive bus capacitor 21 is low, the duty cycle of the first transistor 411 corresponding to the positive bus capacitor 21 is relatively small, so as to control the charging of the positive bus capacitor 21, thereby making the voltages of the two bus capacitors the same.

[0053] In some embodiments, the first switch 31 includes a first balancing transistor 411, and the second switch 33 includes a second balancing transistor 411. When the voltage of the positive bus capacitor 21 is greater than the voltage of the negative bus capacitor 23, the duty cycle of the first balancing transistor 411 is greater than the duty cycle of the second balancing transistor 411 to control the charging of the negative bus capacitor 23 so that the voltages of the positive bus capacitor 21 and the negative bus capacitor 23 are the same.

[0054] Specifically, when the voltage of the negative bus capacitor CS2 is lower than the voltage of the positive bus capacitor CS1, the duty cycle of the second balancing transistor Q3 corresponding to the negative bus capacitor CS2 with the lower voltage is smaller than the duty cycle of the first balancing transistor Q2, so as to control the charging of the negative bus capacitor CS2 with the lower voltage until the voltage of the negative bus capacitor CS2 is the same as the voltage of the positive bus capacitor CS1, and then the duty cycles of the second balancing transistor Q3 and the first balancing transistor Q2 are controlled to be restored to the same, so as to stop the charging of the negative bus capacitor CS2.

[0055] In this way, by controlling the duty cycle of the second balancing transistor 411, the charging of the negative bus capacitor 23 can be controlled. When the voltages of the two bus capacitors are the same, the duty cycles of any two balancing transistors 411 are the same; when the voltage of the positive bus capacitor 21 is higher, the duty cycle of the balancing transistor 411 corresponding to the positive bus capacitor 21 is larger to control the charging of the negative bus capacitor 23, so that the voltages of the two bus capacitors are the same.

[0056] Please refer to Figure 2. In some embodiments, the loop 41 includes at least two transistors 411 and an output terminal 413. The transistors 411 and the bus capacitors are connected in parallel, and the transistors 411 of any two loops 41 are connected in parallel with each other; one end of the output terminal 413 is connected to the two transistors 411, and the other end of the output terminal 413 is connected to the second pole of the positive bus capacitor 21 and the first pole of the negative bus capacitor 23. The output terminal 413 is used to output voltage.

[0057] Specifically, two transistors 411 and two bus capacitors can form a half-bridge circuit, and multiple transistors 411 in a loop 41 are connected in series. One end of the output terminal 413 is connected to the ends of the two transistors 411 that are connected to each other, and the other end of the output terminal 413 is connected to the ends of the two bus capacitors that are connected to each other. The output terminal 413 is used to output a voltage. The loop 41 may also include a filter module 4155, which is used to perform high-frequency filtering. The filter module 4155 includes a filter inductor 35 and a filter capacitor. The filter inductor 35 and the filter capacitor together form an LC filter circuit, wherein the filter inductor 35 is connected in series with the output terminal 413, and the filter capacitor is connected in parallel with the output terminal 413.

[0058] In one embodiment, the first circuit includes transistors Q4 and Q6, as well as a filter inductor Ls2 and a filter capacitor. The drain of transistor Q4 is connected to one end of the positive bus capacitor CS1, the source of transistor Q4 is connected to the drain of transistor Q6, the source of transistor Q4 and the drain of transistor Q6 are both connected to one end L1 of output terminal 413, the source of transistor Q6 is connected to one end of the negative bus capacitor CS2, the other end of the positive bus capacitor CS1 is connected to the other end of the negative bus capacitor CS2, and the positive bus capacitor CS1 and the negative bus capacitor CS2 are both connected to the other end N of output terminal 413. The gates of transistors Q4 and Q6 are both connected to a control module, which controls the output voltage of output terminal L1N by controlling the on-time and duty cycle of transistors Q4 and Q6.

[0059] In this way, the output voltage outputted by the output terminal 413 of the same loop 41 can be controlled by the transistor 411 of the loop 41 .

[0060] In some embodiments, the transistor 411 includes a first transistor 4111 and a second transistor 4113, the first end of the first transistor 4111 is connected to the first electrode of the positive bus capacitor 21, the second end of the first transistor 4111 is connected to the first end of the second transistor 4113, and the second end of the second transistor 4113 is connected to the negative bus capacitor 23, and the conduction time of the first transistor 4111 and the second transistor 4113 is different, so that the output voltage of the output terminal 413 is an AC voltage.

[0061] Specifically, the first end of the first transistor 4111 is connected to the first terminal of the positive bus capacitor 21, the second end of the first transistor 4111 is connected to the first terminal of the second transistor 4113, the second end of the second transistor 4113 is connected to the negative bus capacitor 23, the junction between the first transistor 4111 and the second transistor 4113 is connected to the first terminal of the output terminal 413, and the second terminal of the positive bus capacitor 21 and the first terminal of the negative bus capacitor 23 are connected to the second terminal of the output terminal 413. When the first transistor 4111 is turned on, the second transistor 4113 is turned off, and the output terminal 413 and the first transistor 4111 form a loop 41, so that the output terminal 413 outputs a voltage in a first direction; when the second transistor 4113 is turned on, the first transistor 4111 is turned off, and the output terminal 413 and the second transistor 4113 form a loop 41, so that the output terminal 413 outputs a voltage in a second direction, the first direction and the second direction being opposite. By alternately controlling the conduction of the first transistor 4111 and the second transistor 4113, the output terminal 413 is able to output an AC voltage, thereby achieving conversion from a DC voltage to an AC voltage. In addition, when the first transistor 4111 is closed, the second transistor 4113 is not turned on immediately, but is turned on after a set time to prevent a path caused by the first transistor 4111 not being completely closed and the second transistor 4113 being turned on, thereby avoiding the generation of a large current to damage the component.

[0062] In one embodiment, when the transistor Q4 in the first loop is turned on, the transistor Q6 is not turned on, and the direction of the voltage output by the output terminal 413 is from the node L1 to the node N; when the transistor Q6 in the first loop is turned on, the transistor Q4 is not turned on, and the direction of the voltage output by the output terminal 413 is from the node N to the node L1.

[0063] In this way, by controlling the different conduction times of the multiple transistors 411 in the loop 41 , the output voltage outputted by the output terminal 413 of the loop 41 can be made an AC voltage, thereby achieving the conversion from a DC voltage to an AC voltage.

[0064] In some embodiments, the on-times of the first transistors 4111 of any two loops 41 are different, the on-times of the second transistors 4113 of any two loops 41 are also different, and the phases of the output voltages output by any two loops 41 are different.

[0065] Specifically, within the same loop 41, the on-times of multiple transistors 411 differ, resulting in an AC voltage at the output terminal 413 of the loop 41. The on-times of the first transistors 4111 of any two loops 41 differ, resulting in different periods of time when the output voltage of the two loops 41 is in the first direction. The on-times of the second transistors 4113 of any two loops 41 differ, resulting in different periods of time when the output voltage of the two loops 41 is in the second direction. This results in different phases of the output voltages of any two loops 41, achieving phase separation.

[0066] In one embodiment, the second loop includes a transistor Q5 and a transistor Q7. The on-time of the transistor Q5 of the second loop is different from that of the transistor Q4 of the first loop. The on-time of the transistor Q7 of the second loop is different from that of the transistor Q6 of the first loop. This causes the phase of the output voltage at the output terminal L2N of the second loop to be different from the phase of the output voltage at the output terminal L1N of the first loop.

[0067] In this way, by controlling the on-time of the first transistor 4111 of any two loops 41 to be different, and the on-time of the second transistor 4113 of any two loops 41 to be different, the phases of the output voltages output by any two loops 41 can be made different, thereby achieving phase-split output.

[0068] In some embodiments, when the inverter 100 is in an off-grid state, each loop 41 outputs voltages of different phases.

[0069] Specifically, in the event of a power outage or other circumstance, inverter 100 is disconnected from the grid, entering an off-grid state. In this off-grid state, each circuit 41 operates in half-bridge mode. In this half-bridge mode, each circuit 41 outputs voltages of different phases. For example, for a 200V or 240V grid, the phase difference between the output voltage of the first circuit and the output voltage of the second circuit is 180°. For a 208V grid, the phase difference between the output voltage of the first circuit and the output voltage of the second circuit is 120°.

[0070] In this way, in an off-grid state, the multiple loops 41 of the inverter 100 can output output voltages of different phases, thereby being able to supply power to different loads.

[0071] In some embodiments, when the inverter 100 is in a grid-connected state, the phases of the voltages output by all loops 41 are the same.

[0072] Specifically, when the inverter 100 is connected to the power grid, since the power grid provides a neutral point, the inverter 100 does not need to perform phase-splitting output. Therefore, all the loops 41 of the inverter 100 together constitute the inverter circuit 40, and all the loops 41 output voltages of the same phase. The inverter circuit 40 operates in full-bridge mode and outputs AC voltage. In one embodiment, the inverter circuit 40 includes two loops 41, that is, the inverter circuit 40 includes a transistor Q4, a transistor Q5, a transistor Q6, a transistor Q7 and an output terminal L1L2, wherein the on-time of the transistor Q4 and the transistor Q7 is the same, the on-time of the transistor Q5 and the transistor Q6 is the same, and when the transistor Q4 and the transistor Q7 are turned on, the transistor Q5 and the transistor Q6 are not turned on, so that the direction of the voltage output by the output terminal L1L2 is a first direction; when the transistor Q5 and the transistor Q6 are turned on, the transistor Q4 and the transistor Q7 are not turned on, so that the direction of the voltage output by the output terminal L1L2 is a second direction, so that by controlling the on-off time of the four transistors 411, the output terminal 413 outputs an AC voltage, thereby realizing the conversion of the DC voltage to the AC voltage.

[0073] In this way, by controlling the on-off time of the transistors 411 in all the loops 41 , the inverter circuit 40 composed of all the loops 41 can output an AC voltage.

[0074] In some embodiments, the primary circuit 11 includes a primary winding 111 and a switch tube 113, and the secondary circuit 13 includes a secondary winding 131. When the switch tube 113 is turned on, the DC source charges the primary winding 111; when the switch tube 113 is closed, the DC source does not charge the primary winding 111, and the secondary winding 131 charges the DC bus 20.

[0075] Specifically, the primary circuit also includes an energy storage capacitor 115, which can charge the primary winding 111. The first end of the primary winding 111 is connected to the first end of the energy storage capacitor 115 and the positive input end of the DC source. The second end of the primary winding 111 is connected to the first end of the switch tube 113, and the second end of the switch tube 113 is connected to the second end of the energy storage winding and the negative input end of the DC source. When the switch tube Q1 is closed, the DC source and the energy storage capacitor 115 charge the primary winding 111; when the switch tube Q1 is opened, the secondary winding 131 charges the DC bus 20. This ensures that the DC source charges the primary winding 111 and the secondary winding 131 charges the DC bus 20 at different times, thereby achieving isolation between the DC source and the DC bus 20.

[0076] In this way, by controlling the DC source to charge the primary winding 111 and the secondary winding 131 to charge the DC bus 20 at different times, the DC source and the DC bus 20 can be isolated.

[0077] In some embodiments, when the input voltage of the DC source is less than a set voltage, the isolation circuit 10 is used to boost the input voltage.

[0078] Specifically, since the subsequent balancing circuit 30 and loop 41 will step down the input voltage to a certain extent, in order to output the rated output voltage, the rated bus voltage should be higher than the rated output voltage. When the input voltage is less than the set voltage, the isolation circuit 10 can boost the input voltage to the rated bus voltage. If the rated output voltage is u, the rated bus voltage can generally be Among them, x can be set according to actual needs, for example, x can be 40. For example, for a 200V power grid, the rated bus voltage can be 322V, and for a 240V power grid, the rated bus voltage can be 334V.

[0079] In this way, by boosting the input voltage through the isolation circuit 10, the bus voltage can be raised to the rated bus voltage while performing high-frequency isolation, so that the output voltage output by the subsequent loop 41 according to the bus voltage meets the rated output voltage.

[0080] An embodiment of the present application provides a photovoltaic power generation system, which includes the inverter 100 of any of the above embodiments and a control module, and the control module is used to control the balancing circuit 30 to balance the voltage of the bus capacitor.

[0081] Specifically, referring to Figures 9 to 12, the inverter 100 can be connected to a single, two (Figures 9 and 10), four (Figures 11 and 12), six, eight, etc. input photovoltaic voltages. For single or multiple photovoltaic input voltages, voltage conversion can be achieved under the control of the control module, and AC voltage can be output. In the off-grid state, phase output can be achieved to power different loads.

[0082] In this way, the bus capacitor and the DC source can be isolated at high frequency through the isolation circuit 10 to prevent damage to the components in the inverter 100; a balancing circuit 30 is set to balance the voltage of the bus capacitor to prevent the circuit 41 from being unable to stably output voltages of different phases due to the unbalanced voltage of the bus capacitor when the inverter 100 is biased loaded or half-wave loaded, thereby enabling the inverter 100 to stably output in phases to power different loads.

[0083] In the description of this specification, the reference terms "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification, as well as features of different embodiments or examples, unless they are mutually inconsistent.

[0084] Furthermore, the term "connection" should be interpreted broadly. For example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0085] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0086] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0087] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An inverter, characterized in that: The inverter includes: an isolation circuit, a DC bus, a balancing circuit, and an inverter circuit; wherein: The isolation circuit includes a primary circuit and a secondary circuit, and the input end of the primary circuit is used to connect to a DC source; The DC bus includes a positive bus capacitor and a negative bus capacitor, wherein the first electrode of the positive bus capacitor is connected to the positive output electrode of the secondary circuit, the second electrode of the positive bus capacitor is connected to the first electrode of the negative bus capacitor, and the second electrode of the negative bus capacitor is connected to the negative output electrode of the secondary circuit; The balancing circuit includes a first switch, a second switch, and an inductor, wherein a first end of the first switch is connected to a first terminal of the positive bus capacitor, a second end of the first switch is connected to a first terminal of the second switch, and a second end of the second switch is connected to a second terminal of the negative bus capacitor. A first end of the inductor is connected to the second end of the first switch and the first end of the second switch, and a second end of the inductor is connected to the second terminal of the positive bus capacitor and the first terminal of the negative bus capacitor. The inverter circuit is connected to the DC bus, and the inverter circuit includes multiple loops, each of which is used to output voltages of different phases.

2. The inverter according to claim 1, characterized in that The first switch includes a first balancing transistor, and the second switch includes a second balancing transistor. When the voltage of the positive bus capacitor is less than the voltage of the negative bus capacitor, the duty cycle of the first balancing transistor is less than the duty cycle of the second balancing transistor, so as to control the charging of the positive bus capacitor so that the voltages of the positive bus capacitor and the negative bus capacitor are the same.

3. The inverter according to claim 1, characterized in that The first switch includes a first balancing transistor, and the second switch includes a second balancing transistor. When the voltage of the positive bus capacitor is greater than the voltage of the negative bus capacitor, the duty cycle of the first balancing transistor is greater than the duty cycle of the second balancing transistor to control the charging of the negative bus capacitor so that the voltages of the positive bus capacitor and the negative bus capacitor are the same.

4. The inverter according to claim 1, characterized in that The circuit comprises: At least two transistors, the transistors and the bus capacitor are connected in parallel, and the transistors of any two loops are connected in parallel with each other; An output end, one end of the output end is connected to the two transistors, the other end of the output end is connected to the second electrode of the positive bus capacitor and the first electrode of the negative bus capacitor, and the output end is used to output voltage.

5. The inverter according to claim 4, characterized in that: The transistor includes a first transistor and a second transistor, the first end of the first transistor is connected to the first electrode of the positive bus capacitor, the second end of the first transistor is connected to the first end of the second transistor, and the second end of the second transistor is connected to the negative bus capacitor. The conduction time of the first transistor and the second transistor is different, so that the output voltage of the output end is an AC voltage.

6. The inverter according to claim 5, characterized in that The conduction time of the first transistors of any two of the loops is different, the conduction time of the second transistors of any two of the loops is also different, and the phases of the output voltages output by any two of the loops are different.

7. The inverter according to claim 1, characterized in that When the inverter is in an off-grid state, each of the loops outputs voltages of different phases.

8. The inverter according to claim 7, characterized in that: When the inverter is in a grid-connected state, the phases of the voltages output by all the loops are the same.

9. The inverter according to claim 1, characterized in that: The primary circuit includes a primary winding and a switch tube, and the secondary circuit includes a secondary winding. When the switch tube is turned on, the DC source charges the primary winding; when the switch tube is closed, the DC source does not charge the primary winding, and the secondary winding charges the DC bus.

10. The inverter according to claim 1, characterized in that When the input voltage of the DC source is lower than a set voltage, the isolation circuit is used to boost the input voltage.

11. A photovoltaic power generation system, characterized in that: The photovoltaic power generation system comprises the inverter and the control module according to claims 1-10, and the control module is used to control the balancing circuit to balance the voltage of the bus capacitor.

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