Display panel and display device

Abstract

Disclosed in the present application are a display panel and a display device. A first input signal line is connected between a first gate driving circuit and a first input signal end, and a second input signal line is connected between the first gate driving circuit and a second input signal end; and the voltage applied to the first input signal end is the same as the voltage applied to the second input signal end.

Description

Display panel and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 8, 2024, with application number 202410179483.X, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] In a display panel, the Gate Driver On Array (GOA) technology generates a scan signal through a GOA circuit and transmits the scan signal to the pixel drive circuit within the surface to enable the pixels within the surface to emit light.

[0004] Among them, the GOA circuit scans row by row to transmit scanning signals to the pixel driving circuit of the corresponding row; for example, multiple rows of GOA units in the GOA circuit all input low-potential signals through low-potential scanning signal lines. When the pixel driving circuit of this row is fed with low-potential signals, while the pixel driving circuits of other rows are charged with high-potential scanning signals, the load of the low-potential scanning signal line will be reduced, causing the potential in the low-potential scanning signal line to be higher, thereby affecting the signal stability in the pixel driving circuit, causing uneven display on the display panel. SUMMARY OF THE INVENTION

[0005] Embodiments of the present application provide a display panel and a display device, which can improve the stability of signal transmission in a first input signal line and a second input signal line, and improve the display uniformity of the display panel.

[0006] An embodiment of the present application provides a display panel, comprising a display area and a non-display area adjacent to the display area;

[0007] The display panel further includes:

[0008] The panel body includes a first input signal terminal, a second input signal terminal, a first input signal line, a second input signal line, and a first gate driving circuit disposed in the non-display area and located on one side of the display area;

[0009] The first input signal line is connected between the first gate driving circuit and the first input signal terminal, and the second input signal line is connected between the first gate driving circuit and the second input signal terminal;

[0010] The voltage loaded on the first input signal terminal is the same as the voltage loaded on the second input signal terminal.

[0011] An embodiment of the present application further provides a display device, comprising a display panel, wherein the display panel comprises a display area and a non-display area adjacent to the display area;

[0012] The display panel further includes:

[0013] The panel body includes a first input signal terminal, a second input signal terminal, a first input signal line, a second input signal line, and a first gate driving circuit disposed in the non-display area and located on one side of the display area;

[0014] The first input signal line is connected between the first gate driving circuit and the first input signal terminal, and the second input signal line is connected between the first gate driving circuit and the second input signal terminal;

[0015] The voltage loaded on the first input signal terminal is the same as the voltage loaded on the second input signal terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a schematic diagram of a planar structure of a display panel according to an embodiment;

[0017] FIG2 is a schematic diagram of signal transmission of a display panel according to an embodiment;

[0018] 3 to 5 are signal waveform diagrams of a display panel according to an embodiment;

[0019] FIG6 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present application;

[0020] FIG7 is a schematic diagram of a circuit structure of a pixel driving circuit provided in an embodiment of the present application;

[0021] FIG8 is a signal waveform diagram of a panel body provided in an embodiment of the present application;

[0022] 9 and 10 are schematic diagrams of a circuit structure of a first gate control unit provided in an embodiment of the present application;

[0023] FIG11 is a schematic diagram of signal transmission of a panel body provided in an embodiment of the present application;

[0024] FIG12 is a schematic diagram of a signal transmission resistor structure in one embodiment;

[0025] FIG13 is a schematic diagram of a signal transmission resistor structure provided in an embodiment of the present application;

[0026] FIG14 is a schematic diagram of another planar structure of a display panel provided in an embodiment of the present application;

[0027] FIG15 is another schematic diagram of the planar structure of the display panel provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0029] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0030] Please refer to Figures 1 to 5. In one embodiment of a display panel, the display panel includes a panel body 1, a flexible circuit board 2 bound and connected to the panel body 1, and a circuit board 3 connected to the flexible circuit board 2 on a side away from the panel body 1. The signal on the circuit board 3 is transmitted to the binding terminal 4 through the flexible circuit board 3, and then transmitted to the GOA driving circuit 5 through the binding terminal 4, and then transmitted by the driving circuit 5 to the pixel driving circuit 6; for example, when the transmission signal is a low potential signal VGL, and the low potential signal can be multiple, such as VGL1 / VGL2, the binding terminal 4 transmits the low potential signal to the GOA driving circuit 5 through a wiring, and the GOA driving circuit 5 includes multiple cascade units, each cascade unit is connected to a row of pixel driving circuits 6; wherein the driving process of the pixel driving circuit 6 includes a data writing period T1 and holding period T2, and in the data writing period T1, the low potential signal VGL needs to be switched to a high potential so that the preset transistor in the preset pixel driving circuit 6 is turned on, and in the holding period T2, the low potential signal VGL needs to maintain a low potential so that the preset transistor remains turned off; therefore, when the pixel driving circuit 6 of this row is in the end section of the holding period T2, the pixel driving circuits 6 of other rows will be in the data writing period T1, at this time, the low potential signal VGL of other rows is switched to a high potential, so that the load of the low potential signal VGL is reduced, and the low potential signal VGL will be pulled up, that is, an upward sharp corner will appear, thereby affecting the signal transmission stability of the pixel driving circuit 6 of this row, causing the brightness of the light-emitting device driven by the pixel driving circuit 6 of this row to change, resulting in flickering and other display unevenness phenomena on the display panel.

[0031] 6 , an embodiment of the present application provides a display panel, which includes a display area 101 and a non-display area 102 adjacent to the display area 101 ; the display panel also includes a panel body 10 .

[0032] Among them, the panel body 10 includes a first input signal terminal 121, a second input signal terminal 122, a first input signal line 131, a second input signal line 132, and a first gate driving circuit 11 arranged in the non-display area 102 and located on one side of the display area 101; the first input signal line 131 is connected between the first gate driving circuit 11 and the first input signal terminal 121, and the second input signal line 132 is connected between the first gate driving circuit 11 and the second input signal terminal 122.

[0033] The voltage applied to the first input signal terminal 121 is the same as the voltage applied to the second input signal terminal 122 .

[0034] During the implementation process, the embodiment of the present application adds a second input signal terminal 122 in the panel body 10, and the voltage loaded on the second input signal terminal 122 is the same as the voltage loaded on the first input signal terminal 121, thereby improving the stability of the voltage signal of the first input signal line 131 and the second input signal line 132 passing into the first gate drive circuit 11, improving the stability of the scanning signal output by the first gate drive circuit 11, and thereby improving the display uniformity and display effect of the display panel.

[0035] In one embodiment of the present application, the first gate drive circuit is arranged on the first side of the panel body, the first input signal terminal is arranged on the second side of the panel body, the second input signal terminal is arranged on the third side of the panel body, and the second side and the third side are opposite sides of the panel body, and the first side is located between the second side and the third side.

[0036] In one embodiment of the present application, the first gate driving circuit includes a plurality of first gate control units, the first input signal line is connected to a portion of the first gate control units close to the second side among the plurality of first gate control units, the second input signal line is connected to another portion of the first gate control units close to the third side among the plurality of first gate control units, and the first input signal line and the second input signal line are connected in the first gate driving circuit.

[0037] In one embodiment of the present application, the display panel further includes a first flexible circuit board and a second flexible circuit board connected to the panel body, and the first flexible circuit board is bound and connected to the first input signal end, and the second flexible circuit board is bound and connected to the second input signal end.

[0038] In one embodiment of the present application, the display panel also includes a first circuit board connected to the side of the first flexible circuit board away from the panel body, and a first connecting trace arranged on the first flexible circuit board and the first circuit board, a first driving chip is provided on the first circuit board, and the first connecting trace is connected between the first driving chip and the first input signal terminal.

[0039] In one embodiment of the present application, the display panel also includes a third flexible circuit board connected between the first flexible circuit board and the second flexible circuit board, and a second connecting line located on the first circuit board, the second flexible circuit board and the third flexible circuit board, and the second connecting line is connected between the first driver chip and the second input signal terminal.

[0040] In one embodiment of the present application, the display panel also includes a second circuit board connected to the side of the second flexible circuit board away from the panel body, and a third connecting trace arranged on the second circuit board and the second flexible circuit board, a second driver chip is provided on the second circuit board, and the third connecting trace is connected between the second input signal terminal and the second driver chip.

[0041] In one embodiment of the present application, the panel body includes a source / drain layer and a gate layer;

[0042] The first input signal line includes a plurality of first line segments, and each of the plurality of first line segments is independently located in the source / drain layer or the gate layer;

[0043] The second input signal line includes a plurality of second line segments, and each of the plurality of second line segments is independently located in the source / drain layer or the gate layer.

[0044] In one embodiment of the present application, the panel body further includes a plurality of pixel driving circuits disposed in the display area, and output signal lines connected between the first gate driving circuit and the pixel driving circuits, the output signal lines being configured to transmit signals in the first input signal line and the second input signal line to the pixel driving circuits;

[0045] The pixel driving circuit includes a driving transistor and a compensation transistor, the first electrode of the driving transistor and the first electrode of the compensation transistor are both connected to a first node, the gate of the driving transistor and the second electrode of the compensation transistor are both connected to a second node, and the output signal line is connected to the gate of the compensation transistor.

[0046] In one embodiment of the present application, the compensation transistor is an N-type thin film transistor, and the voltage loaded on the first input signal terminal and the voltage loaded on the second input signal terminal are both low levels.

[0047] Specifically, referring to FIG. 6 , the display panel includes a display area 101 and a non-display area 102 , and the non-display area 102 is disposed around the display area 101 .

[0048] The display panel further includes a panel body 10 , a first flexible circuit board 21 , a second flexible circuit board 22 and a first circuit board 31 .

[0049] The panel body 10 includes a plurality of pixel driving circuits 15 disposed in the display area 101 and a first gate driving circuit 11 disposed in the non-display area 102 .

[0050] Furthermore, the panel body 10 includes a first input signal terminal 121, a second input signal terminal 122, a first input signal line 131 and a second input signal line 132, and the first input signal line 131 is connected between the first input signal terminal 121 and the first gate drive circuit 11, and the second input signal line 132 is connected between the second input signal terminal 122 and the second gate drive circuit 14; the first flexible circuit board 21 is bound and connected to the first input signal terminal 121, and the second flexible circuit board 22 is bound and connected to the second input signal terminal 122, and the voltage loaded on the first input signal terminal 121 is the same as the voltage loaded on the second input signal terminal 122.

[0051] In one embodiment, the first gate driving circuit 11 is arranged on the first side 1011 of the panel body 10, the first input signal terminal 121 is arranged on the second side 1012 of the panel body 10, and the second input signal terminal 122 is arranged on the third side 1013 of the panel body 10, and the second side 1012 and the third side 1013 are opposite sides of the panel body 10, and the first side 1011 is located between the second side 1012 and the third side 1013.

[0052] The first gate driving circuit 11 includes multiple first gate control units 111. In one embodiment, the multiple first gate control units 111 are arranged along a first direction M, where the first direction M is the direction from the second side 1012 to the third side 1013. The first input signal line 131 is connected to a portion of the multiple first gate control units 111 close to the second side 1012, and the second input signal line 132 is connected to another portion of the multiple first gate control units 111 close to the third side 1013. The first input signal line 131 and the second input signal line 132 are connected in the first gate driving circuit 11, so that the first input signal line 131 and the second input signal line 132 can jointly input signals to the first gate driving circuit 11.

[0053] The panel body 10 further includes an output signal line 16 , which is connected between the first gate driving circuit 11 and the pixel driving circuit 15 . The output signal line 16 is used to transmit signals in the first input signal line 131 and the second input signal line 132 to the pixel driving circuit 15 .

[0054] In one embodiment, a plurality of pixel driving circuits 15 are arranged in the display area 101 along a first direction M and a second direction N, and a first gate control unit 111 transmits a signal to the plurality of pixel driving circuits 15 arranged along the second direction N through an output signal line 16, and the second direction N intersects with the first direction M. Preferably, the first direction M and the second direction N are perpendicular to each other.

[0055] In one embodiment, the panel body 10 also includes a fourth side 1014 arranged opposite to the first side 1011 and a second gate driving circuit 14 arranged on the fourth side 1014 of the panel body 10, and the second gate driving circuit 14 includes a plurality of second gate control units 141 arranged along the first direction M; it can be understood that the first gate driving circuit 11 and the second gate driving circuit 14 are located on opposite sides of the panel body 10, and the circuit structure and signal transmission method of the first gate driving circuit 11 and the second gate driving circuit 14 are the same. Therefore, in the embodiment of the present application, the circuit structure and signal transmission method of the first gate driving circuit 11 are described as an example, and the circuit structure and signal transmission method of the second gate driving circuit 14 can be set with reference to the first gate driving circuit 11, and the first gate driving circuit 11 and the second gate driving circuit 14 can be symmetrically arranged relative to the display area 101.

[0056] In one embodiment, a first gate control unit 111 and a second gate control unit 141 jointly drive a plurality of pixel driving circuits 15 arranged along the second direction N through one output signal line 16 .

[0057] In the embodiment of the present application, the signal is transmitted to the first input signal terminal 121 and the second input signal terminal 122 through the first flexible circuit board 21 and the second flexible circuit board 22, and the voltage loaded on the first input signal terminal 121 is the same as the voltage loaded on the second input signal terminal 122. The signal is then transmitted to the first gate drive circuit 11 by the first input signal line 131 and the second input signal line 132 respectively, and then the signal is transmitted to the pixel drive circuit 15 through the first gate drive circuit 11 to scan and drive the pixel drive circuit 15; that is, the embodiment of the present application provides two flexible circuit boards and two input signal terminals for signal input. Compared with the structure shown in Figure 1, the stability of signal transmission and the recovery ability after fluctuations can be improved. Even if the load of signal transmission changes, the embodiment of the present application can reduce the voltage fluctuation caused by the load change and improve the display unevenness of the display panel.

[0058] Specifically, referring to Figures 6 and 7, the pixel driving circuit 15 includes a light-emitting device, a driving transistor T01, a switching transistor T02, a compensation transistor T03, a first reset transistor T04, a first light-emitting control transistor T05, a second light-emitting control transistor T06, a second reset transistor T07, a third reset transistor T08, a first capacitor Cst, and a second capacitor Cboost.

[0059] A first electrode of the driving transistor T01 is connected to the first node B, a gate of the driving transistor T01 is connected to the second node Q, and a second electrode of the driving transistor T01 is connected to the third node A.

[0060] A first electrode of the first switch transistor T02 is connected to the data signal Data, a gate of the first switch transistor T02 is connected to the first scan signal Pscan, and a second electrode of the first switch transistor T02 is connected to the third node A.

[0061] A first electrode of the compensation transistor T03 is connected to the first node B, a gate of the compensation transistor T03 is connected to the second scan signal NscanT3, and a second electrode of the compensation transistor T03 is connected to the second node Q.

[0062] A first electrode of the first reset transistor T04 is connected to the first reset signal Vi_G, a gate of the first reset transistor T04 is connected to the third scan signal NscanT4, and a second electrode of the first reset transistor T04 is connected to the second node Q.

[0063] A first electrode of the first light emitting control transistor T05 is connected to the first power supply signal VDD, a gate of the first light emitting control transistor T05 is connected to the light emitting control signal EM, and a second electrode of the first light emitting control transistor T05 is connected to the third node A.

[0064] A first electrode of the second light emitting control transistor T06 is connected to the first node B, a gate of the second light emitting control transistor T06 is connected to the light emitting control signal EM, and a second electrode of the second light emitting control transistor T06 is connected to the fourth node C.

[0065] A first electrode of the second reset transistor T07 is connected to the second reset signal Vi_ANo, a gate of the second reset transistor T07 is connected to the fourth scan signal PScan2, and a second electrode of the second reset transistor T07 is connected to the fourth node C.

[0066] A first electrode of the third reset transistor T08 is connected to the third reset signal Vi_T8 , a gate of the third reset transistor T08 is connected to the fourth scan signal PScan2 , and a second electrode of the third reset transistor T08 is connected to the third node A.

[0067] A first electrode of the light emitting device is connected to the fourth node C, and a second electrode of the light emitting device is connected to the second power signal VSS.

[0068] The first capacitor Cst is connected between the second node Q and the third node A, and the second capacitor Cboost is connected between the second node Q and the first scan signal PScan.

[0069] It should be noted that, in the embodiment of the present application, the compensation transistor T03 can be an N-type thin film transistor, and the voltage loaded on the first input signal terminal 121 and the voltage loaded on the second input signal terminal 122 are both low levels; the signal transmitted in the first input signal line 131 and the second input signal line 132 can be transmitted to the gate of the compensation transistor T03 through the first gate control unit 111, so that the compensation transistor T03 can be in a closed state. Since there is a parasitic capacitance between the gate of the compensation transistor T03 and the gate of the driving transistor T01, when the gate potential of the compensation transistor T03 fluctuates, it will have a coupling effect on the gate potential of the driving transistor T01, so that the potential of the driving transistor T01 also changes; for example, when the pixel driving circuit 15 of this row is in the end of the holding period, the pixel driving circuits 15 of other rows are in the data writing period, which will cause the load on the first input signal line 131 and the second input signal line 132 to decrease, so that the first The potentials in the input signal line 131 and the second input signal line 132 are pulled up to form a sharp angle, which in turn causes the potential of the driving transistor T01 to be coupled and changed, causing the luminance of the pixels in this row to become lower, resulting in a change in the brightness of the pixels in this row during the holding period, that is, a decrease in the brightness of the last section, causing the display panel to flicker; however, please refer to Figures 6, 7 and 8. In the embodiment of the present application, low-level signals are input simultaneously through the first input signal line 131 and the second input signal line 132, which can improve the stability of signal transmission and the recovery ability after fluctuations. Even if the load of signal transmission changes, the embodiment of the present application can also reduce the magnitude of voltage fluctuations caused by load changes. Compared with the structure shown in Figure 1, the sharp angle A generated by the voltage NscanT3 on the gate of the compensation transistor T03 can be reduced to a sharp angle a, effectively reducing the potential fluctuation of the gate of the compensation transistor T03, and improving the signal transmission stability and the display uniformity of the display panel.

[0070] Further, as shown in Figure 9, the first gate control unit 111 provided in the present application includes a signal control unit 41 and a signal generating unit 42, wherein the signal generating unit 42 can be connected to the high-level signal NVGH_T3 and the low-level signal NVGL_T3, and output the high-level signal NVGH_T3 to the signal output terminal NscanT3_out under the control of the high-level transistor TH, or output the high-level signal NVGL_T3 to the signal output terminal NscanT3_out under the control of the low-level transistor TL, and the signal output terminal NscanT3_out can be connected to the gate of the compensation transistor T03 through the output signal line 16; and the signal control unit 41 is connected to the gate of the high-level transistor TH and the gate of the low-level transistor TL to turn on the high-level transistor TH or the low-level transistor TL according to the control of multiple clock signals.

[0071] In one embodiment, as shown in Figure 10, an embodiment of the present application provides a first gate control unit 111 of a 16T3C architecture, wherein the first gate control unit 111 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0072] The first electrode of the first transistor T1 is connected to the low-level signal VGL, the gate of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the signal output terminal OUT.

[0073] A first electrode of the second transistor T2 is connected to the high level signal VGH, a gate of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the signal output terminal OUT.

[0074] A first electrode of the third transistor T3 is connected to the first node N1 , a gate of the third transistor T3 is connected to the low-level signal VGL, and a second electrode of the third transistor T3 is connected to the third node N3 .

[0075] A first electrode of the fourth transistor T4 is connected to the first node N1 , a gate of the fourth transistor T4 is connected to the first capacitor C1 , and a second electrode of the fourth transistor T4 is connected to the fourth node N4 .

[0076] A first electrode of the fifth transistor T5 is connected to the fourth node N4 , a gate of the fifth transistor T5 is connected to the low-level signal VGL, and a second electrode of the fifth transistor T5 is connected to the fifth node N5 .

[0077] A first electrode of the sixth transistor T6 is connected to the control signal IN, a gate of the sixth transistor T6 is connected to the first clock signal CK, and a second electrode of the sixth transistor T6 is connected to the fifth node N5.

[0078] A first electrode of the seventh transistor T7 is connected to the control signal IN, a gate of the seventh transistor T7 is connected to the first clock signal CK, and a second electrode of the seventh transistor T7 is connected to the third node N3.

[0079] A first electrode of the eighth transistor T8 is connected to the low-level signal VGL, a gate of the eighth transistor T8 is connected to the first clock signal CK, and a second electrode of the eighth transistor T8 is connected to the sixth node N6.

[0080] A first electrode of the ninth transistor T9 is connected to the second clock signal XCK, a gate of the ninth transistor T9 is connected to the fourth node N4, and a second electrode of the ninth transistor T9 is connected to the seventh node N7.

[0081] A first electrode of the tenth transistor T10 is connected to the first clock signal CK, a gate of the tenth transistor T10 is connected to the third node N3, and a second electrode of the tenth transistor T10 is connected to the sixth node N6; and the tenth transistor T10 may be a dual-gate transistor.

[0082] A first electrode of the eleventh transistor T11 is connected to the high-level signal VGH, a gate of the eleventh transistor T11 is connected to the sixth node N6, and a second electrode of the eleventh transistor T11 is connected to the seventh node N7.

[0083] A first electrode of the twelfth transistor T12 is connected to the high level signal VGH, a gate of the twelfth transistor T12 is connected to the third node N3, and a second electrode of the twelfth transistor T12 is connected to the second node N2.

[0084] A first electrode of the thirteenth transistor T13 is connected to the high level signal VGH, a gate of the thirteenth transistor T13 is connected to the control signal RST, and a second electrode of the thirteenth transistor T13 is connected to the third node N3.

[0085] A first electrode of the fourteenth transistor T14 is connected to the sixth node N6 , a gate of the fourteenth transistor T14 is connected to the low-level signal VGL, and a second electrode of the fourteenth transistor T14 is connected to the eighth node N8 .

[0086] A first electrode of the fifteenth transistor T15 is connected to the ninth node N9 , a gate of the fifteenth transistor T15 is connected to the second clock signal XCK, and a second electrode of the fifteenth transistor T15 is connected to the second node N2 .

[0087] A first electrode of the sixteenth transistor T16 is connected to the second clock signal XCK, a gate of the sixteenth transistor T16 is connected to the eighth node N8, and a second electrode of the sixteenth transistor T16 is connected to the ninth node N9.

[0088] The first capacitor C1 is connected between the gate of the fourth transistor T4 and the seventh node N7, the second capacitor C2 is connected between the high level signal VGH and the second node N2, and the third capacitor C3 is connected between the eighth node N8 and the ninth node N9.

[0089] As mentioned above, under the control of the second node N2, the second transistor T2 transmits the high-level signal transmitted in the first input signal line 131 or the second input signal line 132 to the signal output terminal OUT, and then transmits it to the gate of the compensation transistor T03 in the pixel driving circuit 15 through the output signal line 16.

[0090] In other embodiments of the present application, the output signal line 16 can also be connected to the gate of the first reset transistor T04 in the pixel driving circuit 15 to load the voltage signal NscanT4 thereon, and the first reset transistor T04 is an N-type thin film transistor, and the voltage signal NscanT4 is a low level; similarly, there is a coupling capacitor between the gate of the first reset transistor T04 and the gate of the driving transistor T01. Therefore, in the embodiment of the present application, the display unevenness of the display panel can be improved by improving the stability of the potential signal NscanT4 on the first reset transistor T04.

[0091] It should be noted that the potential signal NscanT4 is provided by the first gate driving circuit 11, and the circuit structure for generating the potential signal NscanT4 can be the same as the structure shown in Figures 8 and 9, and the specific connection method is not repeated here.

[0092] Continuing from the above, please refer to Figures 6, 7, 11, 12 and 13. The embodiment of the present application sets a first input signal terminal 121 and a second input signal terminal 122 on opposite sides of multiple first gate control units 111 and multiple second gate control units 141 to jointly input a voltage signal NscanT3 to the multiple first gate control units 111 and the multiple second gate control units 141. Therefore, relative to the structure shown in Figure 12, the resistance of the signal transmission process is the sum of R1 and R2. The embodiment of the present application can reduce the signal transmission path, so that the resistance of the signal transmission process in the first input signal line 131 is the sum of R1 and R2 / 2, and the resistance of the signal transmission process in the second input signal line 132 is the sum of R3 and R2 / 2, and R3 is less than R2 / 2, thereby reducing the resistance of the signal transmission process. That is, the embodiment of the present application can reduce the resistance of the voltage signal NscanT3 during transmission, thereby improving the signal transmission efficiency and the recovery speed after fluctuations.

[0093] In addition, at least one third input signal terminal 123 is further provided on the third side 1013 of the panel body 10, and a power signal VDD and / or VSS can be applied to the at least one third input signal terminal 123 via the second flexible circuit board 22. The panel body 10 also includes a third input signal line 133 connected to the third input signal terminal 123, and the third input signal line 133 is used to transmit the power signal VDD and / or VSS to the pixel driving circuit 15 in the display area 101.

[0094] It should be noted that the second side 1012 of the panel body 10 is also provided with an input signal terminal for loading the power signal VDD and / or VSS (not shown in the figure), and the power signal VDD and / or VSS is loaded thereto through the first flexible circuit board 21. That is, in the embodiment of the present application, the number of input terminals for the power signal VDD and / or VSS can be increased to improve the transmission stability and resistance of the power signal VDD and / or VSS during the transmission process, thereby improving the display effect of the display panel.

[0095] Specifically, in one embodiment of the present application, referring to Figure 14, the display panel also includes a first circuit board 31 connected to the side of the first flexible circuit board 21 away from the panel body 10, and a first connecting trace 312 arranged on the first flexible circuit board 21 and the first circuit board 31. A first driving chip 311 is provided on the first circuit board 31, and the first connecting trace 312 is connected between the first driving chip 311 and the first input signal terminal 121.

[0096] The display panel also includes a third flexible circuit board 23 connected between the first flexible circuit board 21 and the second flexible circuit board 22, and a second connecting trace 221 located on the first circuit board 31, the second flexible circuit board 22 and the third flexible circuit board 23. The second connecting trace 221 is connected between the first driver chip 311 and the second input signal terminal 122 (not shown in the figure). It can be understood that the first driver chip 311 transmits the signal to the second flexible circuit board 22 through the second connecting trace 221 on the third flexible circuit board 23, and the second flexible circuit board 22 is bound and connected to the second input signal terminal 122 to transmit the signal to the second input signal terminal 122.

[0097] The voltage transmitted by the first driver chip 311 to the first connection trace 312 and the second connection trace 221 is the same, and the third flexible circuit board 23 can be arranged on the back side of the panel body 10, that is, the side of the panel body 10 away from the light-emitting surface.

[0098] Furthermore, the third flexible circuit board 23 is also provided with connection lines for transmitting power signals VDD and / or VSS, so as to transmit the power signals VDD and / or VSS to the second flexible circuit board 22 through the first driver chip 311 and the third flexible circuit board 23.

[0099] In another embodiment of the present application, referring to FIG. 15 , the display panel further includes a first circuit board 31 connected to the first flexible circuit board 21 on a side away from the panel body 10, and a first connecting trace 312 arranged on the first flexible circuit board 21 and the first circuit board 31. A first driver chip 311 is provided on the first circuit board 31, and the first connecting trace 312 is connected between the first driver chip 311 and the first input signal terminal 121.

[0100] The display panel also includes a second circuit board 32 connected to the side of the second flexible circuit board 22 away from the panel body 10, and a third connecting trace 322 arranged on the second circuit board 32 and the second flexible circuit board 22. A second driver chip 321 is provided on the second circuit board 32. The third connecting trace 322 is connected between the second input signal terminal 122 and the second driver chip 321, and the voltage transmitted by the second driver chip 321 to the second input signal terminal 122 is the same as the voltage transmitted by the first driver chip 311 to the first input signal terminal 121.

[0101] Furthermore, the second flexible circuit board 22 is also provided with connection lines for transmitting power signals VDD and / or VSS, so as to transmit the power signals VDD and / or VSS to the third input signal terminal 123 through the second driver chip 321 and the second flexible circuit board 22.

[0102] In one embodiment, the second driver chip 321 can be used to output a reset signal and a clock signal required by the first gate driver circuit 11 .

[0103] In one embodiment, please continue to refer to Figure 6, the panel body 10 includes a substrate and a source-drain layer and a gate layer arranged on the substrate; the first input signal line 131 includes a plurality of first line segments, and the plurality of first line segments are independently located in the source-drain layer or the gate layer; for example, the non-display area 102 includes a fan-out routing area 1021 located on the second side 1012 of the panel body 10. Since the number of wirings in the fan-out routing area 1021 is large, the first line segments located in the fan-out routing area 1021 can be set in the gate layer with more wiring space, and the first line segments located in other positions can be located in the source-drain layer.

[0104] The second input signal line 132 includes multiple second line segments, and the multiple second line segments are independently located in the source and drain layer or the gate layer; for example, when the second input signal line 132 overlaps with the third input signal line 133, the second line segments in the overlapping part can be located in the gate layer, while the second line segments in other positions can be located in the source and drain layer.

[0105] Furthermore, the embodiment of the present application provides an embodiment and a comparison to verify the effect of improving the display uniformity of the display panel, wherein the embodiment adopts the signal output method shown in Figure 2, and the comparison adopts the signal input method shown in Figure 11, and the voltage signal NscanT3 is simulated to obtain the size of the sharp angle generated by the voltage signal NscanT3 in the embodiment and the comparison, and the results are shown in Table 1 below.

[0106] Table 1 Voltage signal simulation results

[0107] Example Comparative ratio The size of the sharp corner in the voltage signal NscanT3 is 10mV3mV

[0108] As can be seen from the above table, the present application can effectively reduce the size of the sharp angle of the scanning signal output by the first gate drive circuit 11 by adding a signal input method at the input signal terminal, improve the signal transmission stability, and improve the display uniformity of the display panel.

[0109] Continuing from the above, the embodiment of the present application adds a second input signal terminal 122 in the panel body 10, and the voltage loaded on the second input signal terminal 122 is the same as the voltage loaded on the first input signal terminal 121, thereby improving the stability of the voltage signal of the first input signal line 131 and the second input signal line 132 passing into the first gate drive circuit 11, improving the stability of the scanning signal output by the first gate drive circuit 11, and thereby improving the display uniformity and display effect of the display panel.

[0110] In addition, an embodiment of the present application further provides a display device, and the display device includes the display panel described in the above embodiment.

[0111] It can be understood that, since the display device includes the display panel described in the above embodiment, the display device has the same beneficial effects as in the above embodiment, which will not be described in detail here.

[0112] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel comprising a display area and a non-display area adjacent to the display area; The display panel further includes: The panel body includes a first input signal terminal, a second input signal terminal, a first input signal line, a second input signal line, and a first gate driving circuit disposed in the non-display area and located on one side of the display area; The first input signal line is connected between the first gate driving circuit and the first input signal terminal, and the second input signal line is connected between the first gate driving circuit and the second input signal terminal; The voltage loaded on the first input signal terminal is the same as the voltage loaded on the second input signal terminal.

2. The display panel according to claim 1, wherein The first gate drive circuit is arranged on the first side of the panel body, the first input signal terminal is arranged on the second side of the panel body, and the second input signal terminal is arranged on the third side of the panel body, and the second side and the third side are opposite sides of the panel body, and the first side is located between the second side and the third side.

3. The display panel according to claim 2, wherein: The first gate driving circuit includes multiple first gate control units, the first input signal line is connected to some of the first gate control units close to the second side among the multiple first gate control units, the second input signal line is connected to another part of the first gate control units close to the third side among the multiple first gate control units, and the first input signal line and the second input signal line are connected in the first gate driving circuit.

4. The display panel according to any one of claims 1 to 3, wherein: The display panel further includes a first flexible circuit board and a second flexible circuit board connected to the panel body, wherein the first flexible circuit board is bound and connected to the first input signal terminal, and the second flexible circuit board is bound and connected to the second input signal terminal.

5. The display panel according to claim 4, wherein: The display panel also includes a first circuit board connected to the side of the first flexible circuit board away from the panel body, and a first connecting trace arranged on the first flexible circuit board and the first circuit board. A first driving chip is arranged on the first circuit board, and the first connecting trace is connected between the first driving chip and the first input signal terminal. The display panel according to claim 5 , wherein: The display panel also includes a third flexible circuit board connected between the first flexible circuit board and the second flexible circuit board, and a second connecting trace located on the first circuit board, the second flexible circuit board and the third flexible circuit board, wherein the second connecting trace is connected between the first driving chip and the second input signal terminal.

7. The display panel according to claim 4, wherein: The display panel also includes a second circuit board connected to the side of the second flexible circuit board away from the panel body, and a third connecting trace arranged on the second circuit board and the second flexible circuit board. A second driver chip is arranged on the second circuit board, and the third connecting trace is connected between the second input signal terminal and the second driver chip.

8. The display panel according to claim 1, wherein: The panel body includes a source / drain layer and a gate layer; The first input signal line includes a plurality of first line segments, and each of the plurality of first line segments is independently located in the source / drain layer or the gate layer; The second input signal line includes a plurality of second line segments, and each of the plurality of second line segments is independently located in the source / drain layer or the gate layer.

9. The display panel according to claim 8, wherein: The non-display area includes a fan-out wiring area located on the second side of the panel body, and the first line segment located in the fan-out wiring area is arranged on the gate layer.

10. The display panel according to claim 1, wherein The panel body further includes a plurality of pixel driving circuits disposed in the display area, and output signal lines connected between the first gate driving circuit and the pixel driving circuits, the output signal lines being used to transmit signals in the first input signal line and the second input signal line to the pixel driving circuits; The pixel driving circuit includes a driving transistor and a compensation transistor, the first electrode of the driving transistor and the first electrode of the compensation transistor are both connected to a first node, the gate of the driving transistor and the second electrode of the compensation transistor are both connected to a second node, and the output signal line is connected to the gate of the compensation transistor.

11. The display panel according to claim 10, wherein: The compensation transistor is an N-type thin film transistor, and the voltage loaded on the first input signal terminal and the voltage loaded on the second input signal terminal are both at a low level.

12. A display device, comprising a display panel, wherein the display panel comprises a display area and a non-display area adjacent to the display area; The display panel further includes: The panel body includes a first input signal terminal, a second input signal terminal, a first input signal line, a second input signal line, and a first gate driving circuit disposed in the non-display area and located on one side of the display area; The first input signal line is connected between the first gate driving circuit and the first input signal terminal, and the second input signal line is connected between the first gate driving circuit and the second input signal terminal; The voltage loaded on the first input signal terminal is the same as the voltage loaded on the second input signal terminal.

13. The display device according to claim 12, wherein: The first gate drive circuit is arranged on the first side of the panel body, the first input signal terminal is arranged on the second side of the panel body, and the second input signal terminal is arranged on the third side of the panel body, and the second side and the third side are opposite sides of the panel body, and the first side is located between the second side and the third side.

14. The display device according to claim 13, wherein: The first gate driving circuit includes multiple first gate control units, the first input signal line is connected to some of the first gate control units close to the second side among the multiple first gate control units, the second input signal line is connected to another part of the first gate control units close to the third side among the multiple first gate control units, and the first input signal line and the second input signal line are connected in the first gate driving circuit.

15. The display device according to any one of claims 12 to 14, wherein: The display panel further includes a first flexible circuit board and a second flexible circuit board connected to the panel body, wherein the first flexible circuit board is bound and connected to the first input signal terminal, and the second flexible circuit board is bound and connected to the second input signal terminal.

16. The display device according to claim 15, wherein The display panel also includes a first circuit board connected to the side of the first flexible circuit board away from the panel body, and a first connecting trace arranged on the first flexible circuit board and the first circuit board. A first driving chip is arranged on the first circuit board, and the first connecting trace is connected between the first driving chip and the first input signal terminal.

17. The display device according to claim 16, wherein: The display panel also includes a third flexible circuit board connected between the first flexible circuit board and the second flexible circuit board, and a second connecting trace located on the first circuit board, the second flexible circuit board and the third flexible circuit board, wherein the second connecting trace is connected between the first driving chip and the second input signal terminal.

18. The display device according to claim 15, wherein The display panel also includes a second circuit board connected to the side of the second flexible circuit board away from the panel body, and a third connecting trace arranged on the second circuit board and the second flexible circuit board. A second driver chip is arranged on the second circuit board, and the third connecting trace is connected between the second input signal terminal and the second driver chip.

19. The display device according to claim 12, wherein: The panel body includes a source / drain layer and a gate layer; The first input signal line includes a plurality of first line segments, and each of the plurality of first line segments is independently located in the source / drain layer or the gate layer; The second input signal line includes a plurality of second line segments, and each of the plurality of second line segments is independently located in the source / drain layer or the gate layer.

20. The display device according to claim 12, wherein The panel body further includes a plurality of pixel driving circuits disposed in the display area, and output signal lines connected between the first gate driving circuit and the pixel driving circuits, the output signal lines being used to transmit signals in the first input signal line and the second input signal line to the pixel driving circuits; The pixel driving circuit includes a driving transistor and a compensation transistor, the first electrode of the driving transistor and the first electrode of the compensation transistor are both connected to a first node, the gate of the driving transistor and the second electrode of the compensation transistor are both connected to a second node, and the output signal line is connected to the gate of the compensation transistor.

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