Scanning driver and driving method therefor, and display screen and electronic device

Abstract

The embodiments of the present application relate to the technical field of electronics. Provided are a scanning driver and a driving method therefor, and a display screen and an electronic device, which are used for reducing the display power consumption of display screens. The scanning driver comprises a plurality of cascaded shift registers, wherein an input end of a first-stage shift register is used for receiving a start signal; an input end of a shift register at each stage, except the first-stage shift register, is coupled to a first output end of a shift register at a previous stage; and a second output end of a shift register at each stage is used for outputting a second scanning signal to a pixel circuit. A variable voltage output from a second output end of each shift register is used for adjusting the number of turn-on pulses in a second scanning signal. The number of turn-on pulses in the second scanning signal can be adjusted by adjusting high and low potential values of the variable voltage, so that the frequency of the second scanning signal is adjusted. A low refresh rate is used for a local location at which a high refresh rate is not required, thereby reducing the display power consumption of display screens.

Description

Scan driver and driving method thereof, display screen, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 5, 2024, with application number 202410168558.4 and invention name “Scan driver and driving method thereof, display screen, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a scan driver and a driving method thereof, a display screen, and an electronic device. Background Art

[0003] As electronic devices become more diverse in form factors and usage scenarios, display screens are also expanding in size. However, larger displays mean increased power consumption, impacting the overall battery life of electronic devices. Therefore, the need for low display power consumption has become a new design improvement point in the display field.

[0004] Currently, those skilled in the art have proposed enabling displays to support both low and high refresh rates, allowing for both the smoothness of high refresh rates and the power savings of low refresh rates. However, current displays can only use a single refresh rate for the entire screen, and the power consumption of displays remains relatively high at both high and low refresh rates.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide a scan driver and a driving method thereof, a display screen, and an electronic device for reducing the display power consumption of a display screen.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect of an embodiment of the present application, a scan driver is provided, which includes multiple cascaded shift registers; at least one level of shift register includes: an input end, a first output end, and a second output end; the input end of the first level shift register is used to receive a start signal; the second output end of each level shift register is used to output a second scan signal to the pixel circuit. Except for the first-stage shift register, the input terminal of each stage shift register is coupled to the first output terminal of the shift register of the previous stage; the shift register further includes a node control circuit, a pull-up node, a pull-down node, an output circuit, a variable frequency refresh circuit, and a voltage stabilization circuit; the node control circuit adjusts the potentials of the pull-up node and the pull-down node in response to a signal at the input terminal; the output circuit outputs a first scan signal from the first output terminal in response to the signals at the pull-up node and the pull-down node; the variable frequency refresh circuit transmits a first voltage signal to the second output terminal in response to the signal at the pull-up node; the variable frequency refresh circuit also transmits a second voltage signal to the second output terminal in response to a signal at the pull-down node or the first output terminal; one of the first voltage signal and the second voltage signal is a power supply voltage and the other is a variable voltage; the voltage stabilization circuit transmits the power supply voltage to the second output terminal in response to the control signal. The second scan signal serves as a drive signal for the pixel circuit, and the first scan signal serves as an input signal for the next-stage shift register.

[0009] The scan driver provided in an embodiment of the present application incorporates a variable frequency refresh circuit within a shift register. The power supply voltage output from the second output terminal of the shift register serves as the off pulse in the second scan signal, and the variable voltage output from the second output terminal of the shift register is used to adjust the number of on pulses in the second scan signal. Adjusting the high and low potentials of the variable voltage adjusts the number of on pulses in the second scan signal, thereby adjusting the frequency of the second scan signal, achieving a display effect with different refresh rates at different locations on the display screen. A low refresh rate is used for locations that do not require a high refresh rate, saving power consumption. Furthermore, the shift register also includes a voltage stabilization circuit. When enabled, the voltage stabilization circuit ensures that the power supply voltage is output to the pixel circuit as the off pulse in the second scan signal. This effectively mitigates the problem of unstable waveforms and floating states that can be output by the variable frequency refresh circuit to the pixel circuit, reduces display risks, and meets the driving requirements of large-scale displays. Furthermore, because the signals at the variable frequency enable voltage terminals of different shift registers are independently controlled, different refresh rates can be achieved at different locations on the same display screen based on the displayed content. The locations divided by different refresh rates are not physically restricted, and different refresh rates can be matched to the user interface. Moreover, the number of zones with different refresh rates that can be achieved is not physically limited, and different refresh rates in multiple zones can be matched according to the user interface.

[0010] In one possible implementation, the variable frequency refresh circuit is coupled to the pull-up node, the pull-down node, the power supply voltage terminal, the variable frequency enable voltage terminal, and the second output terminal; and the voltage stabilization circuit is coupled to the control signal terminal, the power supply voltage terminal, and the second output terminal. This is a simple implementation.

[0011] In a possible implementation, the control signal is a variable voltage, which can reduce the number of signals in the shift register and lower the signal requirements for the display driver.

[0012] In a possible implementation, the control signal is an inverse signal of the variable voltage, which allows for flexible configuration of the voltage stabilization circuit structure.

[0013] In one possible implementation, the shift register further includes an inverter that outputs a control signal in response to a variable voltage. Thus, the shift register receives the variable voltage and converts it into a control signal, which can reduce signal requirements for the display driver.

[0014] In one possible implementation, the variable frequency refresh circuit includes a first circuit and a second circuit. The first circuit is coupled to a pull-up node, one of a power supply voltage terminal and a variable frequency enable voltage terminal, and a second output terminal. The second circuit is coupled to a pull-down node, the other of the power supply voltage terminal and the variable frequency enable voltage terminal, and the second output terminal. This is a simple implementation.

[0015] In one possible implementation, the first circuit includes a first transistor, and the second circuit includes a second transistor; the control electrode of the first transistor is coupled to a pull-up node, the first electrode of the first transistor is coupled to one of a power supply voltage terminal and a frequency conversion enable voltage terminal, and the second electrode of the first transistor is coupled to the second output terminal; the control electrode of the second transistor is coupled to a pull-down node, the first electrode of the second transistor is coupled to the other of the power supply voltage terminal and the frequency conversion enable voltage terminal, and the second electrode of the second transistor is coupled to the second output terminal. This is a structurally simple implementation.

[0016] In one possible implementation, the voltage stabilization circuit includes a third transistor, wherein a control electrode of the third transistor is coupled to the control signal terminal, a first electrode of the third transistor is coupled to the power supply voltage terminal, and a second electrode of the third transistor is coupled to the second output terminal. Depending on the type of the control signal, the third transistor can be an N-type transistor or a P-type transistor. This is a simple implementation.

[0017] In one possible implementation, the first electrode of the first transistor is coupled to the frequency conversion enable voltage terminal, and the first electrode of the second transistor is coupled to the power supply voltage terminal, which is a low-level power supply voltage terminal. In this way, the scan driver can output a second scan signal for controlling the N-type transistor.

[0018] In a possible implementation, the control signal is a variable voltage, and the first transistor, the second transistor, and the third transistor are all transistors of the same type. For example, the first transistor, the second transistor, and the third transistor are all P-type transistors.

[0019] In one possible implementation, the control signal is a reverse signal of a variable voltage, the first transistor and the second transistor are transistors of the same type, and the third transistor is a transistor of a different type. For example, the first transistor and the second transistor are both P-type transistors, and the third transistor is an N-type transistor.

[0020] In one possible implementation, the low-level signal at the variable frequency enable voltage terminal is less than (Vgl-1)v, where Vgl is the low-level power supply voltage at the low-level power supply voltage terminal. This ensures the normal start-up of the voltage stabilization circuit and improves the problem of the output floating signal.

[0021] In one possible implementation, the first electrode of the first transistor is coupled to a power supply voltage terminal, the first electrode of the second transistor is coupled to a frequency conversion enable voltage terminal, and the power supply voltage terminal is a high-level power supply voltage terminal. In this way, the scan driver can output a second scan signal for controlling the P-type transistor.

[0022] In one possible implementation, the control signal is a variable voltage, the first transistor and the second transistor are transistors of the same type, and the third transistor is a transistor of a different type. For example, the first transistor and the second transistor are both P-type transistors, and the third transistor is an N-type transistor.

[0023] In a possible implementation, the control signal is a reverse signal of a variable voltage, and the first transistor, the second transistor, and the third transistor are all transistors of the same type. For example, the first transistor, the second transistor, and the third transistor are all P-type transistors.

[0024] In one possible implementation, the high-level signal at the variable frequency enable voltage terminal is greater than (Vgh-1)v, where Vgh is the high-level power supply voltage at the high-level power supply voltage terminal. This ensures normal startup of the voltage stabilization circuit and improves the problem of outputting a floating signal.

[0025] In one possible implementation, the output circuit includes a pull-up output circuit and a pull-down output circuit. The pull-up output circuit transmits a high-level power supply voltage from the high-level power supply voltage terminal to the first output terminal in response to a signal from a pull-up node. The pull-down output circuit transmits a low-level power supply voltage from the low-level power supply voltage terminal or a clock signal from the clock signal terminal to the first output terminal in response to a signal from a pull-down node. This is a simple implementation.

[0026] A second aspect of the present application provides a display screen, comprising a scan driver and a plurality of pixel circuits arranged in an array; the scan driver comprises any of the scan drivers of the first aspect, and a second output terminal of the scan driver is coupled to the pixel circuits. The display screen provided in the second aspect of the present application includes the scan driver of the first aspect, and the beneficial effects thereof are the same as those of the scan driver and are not further described here.

[0027] A third aspect of the embodiments of the present application provides an electronic device, comprising a display screen and a middle frame, wherein the display screen is disposed on the middle frame, and the display screen comprises the display screen of the second aspect. The electronic device provided in the third aspect of the embodiments of the present application includes the scan driver provided in the first aspect, and the beneficial effects thereof are the same as those of the scan driver and are not further described here.

[0028] According to a fourth aspect of the embodiments of the present application, a driving method of a scan driver is provided, wherein the scan driver includes a plurality of cascaded shift registers; the shift register includes: an input terminal, a node control circuit, a pull-up node, a pull-down node, an output circuit, a first output terminal, a second output terminal, a variable frequency refresh circuit, and a voltage stabilizing circuit; the input terminal of the first-stage shift register is used to receive a start signal; except for the first-stage shift register, the input terminal of each stage shift register is coupled to the first output terminal of the previous stage shift register; the driving method of the scan driver includes: the node control circuit responds to the signal at the input terminal, adjusts the The output circuit outputs a first scanning signal from the first output terminal in response to the signals of the pull-up node and the pull-down node; the variable frequency refresh circuit transmits a first voltage signal to the second output terminal in response to the signal of the pull-up node; the variable frequency refresh circuit also transmits a second voltage signal to the second output terminal in response to the signal of the pull-down node or the first output terminal; one of the first voltage signal and the second voltage signal is a power supply voltage and the other is a variable voltage; the voltage stabilization circuit transmits the power supply voltage to the second output terminal in response to the control signal; the second output terminal outputs a second scanning signal to the pixel circuit. The beneficial effects of the driving method of the scanning driver provided in the fourth aspect of the embodiment of the present application are the same as the beneficial effects of the scanning driver provided in the first aspect, and will not be repeated here.

[0029] In one possible implementation, the power supply voltage is a low-level power supply voltage; the variable frequency refresh circuit transmits the variable voltage to the second output terminal in response to the signal of the pull-up node; the variable frequency refresh circuit transmits the low-level power supply voltage to the second output terminal in response to the signal of the pull-down node or the first output terminal; after the variable voltage jumps from high to low, the voltage stabilizing circuit transmits the low-level power supply voltage to the second output terminal in response to the control signal.

[0030] In a possible implementation, the low-level signal of the variable voltage is less than (Vgl-1)v, where Vgl is a low-level power supply voltage.

[0031] In one possible implementation, the power supply voltage is a high-level power supply voltage; the variable frequency refresh circuit transmits the variable voltage to the second output terminal in response to the signal of the pull-down node or the first output terminal; the variable frequency refresh circuit transmits the high-level power supply voltage to the second output terminal in response to the signal of the pull-up node; after the variable voltage jumps from low to high, the voltage stabilizing circuit transmits the high-level power supply voltage to the second output terminal in response to the control signal.

[0032] In a possible implementation, the high-level signal of the variable voltage is greater than (Vgh-1)v, where Vgh is a high-level power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0034] FIG2A is a schematic diagram of a topological structure of a pixel circuit provided in an embodiment of the present application;

[0035] FIG2B is a schematic diagram of a scan driver according to an embodiment of the present application;

[0036] FIG2C is a topological diagram of a shift register provided in an embodiment of the present application;

[0037] 3A and 3B are diagrams of a display interface of a display screen provided in an embodiment of the present application;

[0038] FIG4 is a schematic diagram of the layout of a display screen provided in an embodiment of the present application;

[0039] FIG5 is a diagram showing the architecture of a scan driver according to an embodiment of the present application;

[0040] FIG6 is an architecture diagram of a shift register provided in an embodiment of the present application;

[0041] FIG7A is a structural diagram of a shift register provided in an embodiment of the present application;

[0042] FIG7B is a topological diagram of a shift register provided in an embodiment of the present application;

[0043] FIG8 is a topological diagram of a shift register provided in an embodiment of the present application;

[0044] FIG9A is a driving timing diagram of a shift register provided in an embodiment of the present application;

[0045] 9B is a timing diagram of a first scanning signal and a second scanning signal output by a shift register provided in an embodiment of the present application;

[0046] FIG10A is a structural diagram of a shift register provided in an embodiment of the present application;

[0047] FIG10B is a topological diagram of a shift register provided in an embodiment of the present application;

[0048] FIG10C is a driving timing diagram of a shift register provided in an embodiment of the present application;

[0049] 10D is a timing diagram of a first scanning signal and a second scanning signal output by a shift register provided in an embodiment of the present application;

[0050] FIG11A is a structural diagram of a shift register provided in an embodiment of the present application;

[0051] 11B and 11C are topological diagrams of a shift register provided in an embodiment of the present application;

[0052] 12A and 12B are structural diagrams of a shift register provided in an embodiment of the present application;

[0053] 12C and 12D are topological diagrams of a shift register provided in an embodiment of the present application;

[0054] 13A and 13B are structural diagrams of a shift register provided in an embodiment of the present application;

[0055] 13C and 13D are topological diagrams of a shift register provided in an embodiment of the present application;

[0056] FIG14A is a distribution diagram of a display screen provided in an embodiment of the present application;

[0057] FIG14B is a schematic diagram of signal output of a scan driver provided in an embodiment of the present application;

[0058] Figures 15A-15C are display interface diagrams of a display screen provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0060] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0061] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0062] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0063] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0064] An embodiment of the present application provides an electronic device, which may be, for example, a foldable electronic device, or a bar-type electronic device. The electronic device may be, for example, a mobile phone, a tablet computer, a laptop computer, an e-reader, a personal computer (PC), a personal digital assistant (PDA), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, etc.

[0065] The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device. For the convenience of explanation, the following embodiments are all illustrated by taking the electronic device as a mobile phone.

[0066] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.

[0067] As shown in Figure 1, the electronic device 1 mainly includes a display screen 10, a display driver 20, and a drive controller 30. Figure 1 takes the terminal 1 as a straight-screen mobile phone as an example, which is only an example in the embodiment of the present application.

[0068] The driving controller 30 receives the image signal RGB and the control signal CTRL and outputs the image data signal DATA matching the interface specification of the display driver 20 according to the image signal RGB. The driving controller 30 also outputs the data control signal DCS.

[0069] The display driver 20 receives a data control signal DCS and an image data signal DATA from the drive controller 30. The display driver 20 converts the image data signal DATA into a data signal and outputs the data signal to a plurality of data signal lines DL1-DLm. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA. The display driver 20 is also configured to output a scan control signal SCS required for display to the display screen 10.

[0070] In one possible embodiment, the display screen 10 is a liquid crystal display (LCD). Accordingly, the electronic device 1 further includes a backlight unit (BLU) located on the back of the LCD. The backlight unit can provide light to the LCD so that each sub-pixel in the LCD can emit light to display an image.

[0071] In another possible embodiment, the display screen 10 is a self-luminous display module such as an organic light emitting diode (OLED) display module, an active-matrix organic light-emitting diode (AMOLED) display module, a mini organic light-emitting diode (Mini-OLED) display module, a micro light-emitting diode (Micro-LED) display module, a micro organic light-emitting diode (Micro-OLED) display module, or a quantum dot light emitting diode (QLED) display module. In this case, the display screen 10 can be a rigid display module or a flexible display module.

[0072] For any of the above-described display screens 10, the display screen 10 includes an active display area (AA) and a non-display area BB located around the active display area AA. The active display area AA is used to display images and includes multiple sub-pixels (SP), each of which is provided with a pixel circuit 11. The non-display area BB includes a scan driver 12.

[0073] In this application, the pixel circuits 11 are described by taking a matrix arrangement as an example. The pixel circuits 11 arranged in a row along the horizontal direction X are called pixel circuits 11 in the same row, and the pixel circuits 11 arranged in a row along the vertical direction Y are called pixel circuits 11 in the same column.

[0074] In some embodiments, the pixel circuit 11 generally includes a driving circuit composed of multiple transistors and a light-emitting unit. The driving circuit generates a driving current to drive the light-emitting unit to emit light, thereby realizing the light-emitting of the pixel circuit 11.

[0075] In some embodiments, the electronic device 1 further includes a middle frame, and the display screen 10 is disposed on and supported by the middle frame.

[0076] As electronic devices 1 become more diverse in form and use, the size of display screens 10 is also gradually expanding. However, larger display screens 10 mean a relatively increased display power consumption, impacting the overall battery life of electronic devices 1. Therefore, the demand for low-power display screens 10 has become a new design improvement point in the display field. For example, using the "picture-in-picture" function on mobile phones, a video can be suspended at the top of the display screen 10, while the bottom is static for reading. Alternatively, using "parallel vision" on tablets, during use, the left side of the application is mostly static, while the right side changes dynamically as you scroll through the application.

[0077] In order to allow the same display screen 10 to simultaneously support high refresh rates (such as 120Hz) and low refresh rates (such as 1Hz), as well as to smoothly switch between high refresh rates and low refresh rates on any row of the display screen 10, the high mobility of low-temperature polysilicon thin-film transistors (LTPS TFTs) and the low leakage characteristics of indium gallium zinc oxide thin-film transistors (IGZO TFTs) can be comprehensively utilized in the pixel circuit of the display screen 10 to perform relevant circuit designs. This is to achieve both the smoothness of high refresh rates and the power saving of low refresh rates. The combination of LTPS TFTs and IGZO TFTs as the driving circuit of the pixel circuit 11 can simultaneously achieve high refresh rates, low refresh rates, and seamless switching between different refresh rates, meeting the needs of dynamic frame changes, and has broad application prospects in OLED display screens.

[0078] FIG2A is a schematic diagram of a topological structure of a pixel circuit provided in an embodiment of the present application.

[0079] 2A , the pixel circuit 11 includes a first node initialization circuit 111, a write and threshold compensation circuit 112, a light emitting control circuit 113, and a light emitting unit 114. The pixel circuit 11 shown in FIG2A is merely an example and does not constitute any limitation.

[0080] In the embodiment of the present application, the first power supply voltage terminal ELVDD is a high-level power supply voltage terminal, and the second power supply voltage terminal ELVSS is a low-level power supply voltage terminal. However, this is not limiting.

[0081] In some embodiments, referring to FIG2A , the first node initialization circuit 111 includes a fourth transistor T4 and a third transistor T3. The write and threshold compensation circuit 112 includes a second transistor T2, a first transistor T1, a third transistor T3, and a storage capacitor Cst. The light-emission control circuit 113 includes a fifth transistor T5 and a sixth transistor T6. The first transistor T1 is a driving transistor, and the remaining transistors are switching transistors. The first node initialization circuit 111 and the write and threshold compensation circuit 112 share the third transistor T3. The light-emitting unit 114 is, for example, an OLED.

[0082] In the following description, the control electrode of the transistor may be, for example, the gate electrode of the transistor, and the first electrode of the transistor and the second electrode of the transistor may be the source electrode and the drain electrode of the transistor, respectively.

[0083] A control electrode of the fourth transistor T4 is coupled to the initialization scan signal terminal SC, a first electrode of the fourth transistor T4 is coupled to the initialization voltage terminal Vinit, and a second electrode of the fourth transistor T4 is coupled to the fourth node N4.

[0084] A control electrode of the third transistor T3 is coupled to the compensation scan signal terminal SB, a first electrode of the third transistor T3 is coupled to the fourth node N4, and a second electrode of the third transistor T3 is coupled to the first node N1.

[0085] A control electrode of the second transistor T2 is coupled to the write scan signal terminal SX, a first electrode of the second transistor T2 is coupled to the data voltage terminal Vdata, and a second electrode of the second transistor T2 is coupled to the third node N3.

[0086] The control electrode of the first transistor T1 is coupled to the first node N1, the first electrode of the first transistor T1 is coupled to the third node N3, the second electrode of the first transistor T1 is coupled to the second node N2, and the second node N2 is further coupled to the fourth node N4.

[0087] One end of the storage capacitor Cst is coupled to the first node N1 , and the other end of the storage capacitor Cst is coupled to the first power voltage terminal ELVDD.

[0088] A control electrode of the fifth transistor T5 is coupled to the light emitting control signal terminal EM, a first electrode of the fifth transistor T5 is coupled to the first power supply voltage terminal ELVDD, and a second electrode of the fifth transistor T5 is coupled to the third node N3.

[0089] The control electrode of the sixth transistor T6 is coupled to the light emitting control signal terminal EM, the first electrode of the sixth transistor T6 is coupled to the second node N2, and the second electrode of the sixth transistor T6 is coupled to the anode of the light emitting unit 114. The cathode of the light emitting unit 114 is coupled to the second power supply voltage terminal ELVSS.

[0090] For example, in the pixel circuit 11, the third transistor T3 and the fourth transistor T4 are IGZO TFTs, which are N-type transistors and are turned on under the control of a high-level signal. The third transistor T3 and the fourth transistor T4 can also be other types of transistors, which are not limited in the embodiment of the present application. The first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are LTPS TFTs, which are P-type transistors and are turned on under the control of a low-level signal.

[0091] The initialization scan signal terminal SC of the pixel circuit 11 is coupled to the initialization scan signal line SCL, the compensation scan signal terminal SB of the pixel circuit 11 is coupled to the compensation scan signal line SBL, the write scan signal terminal SX of the pixel circuit 11 is coupled to the write scan signal line SXL, the emission control signal terminal EM of the pixel circuit 11 is coupled to the emission control scan signal line EML, and the data voltage terminal Vdata of the pixel circuit 11 is coupled to the data signal line DL. The voltages of the initialization voltage terminal Vinit, the first power supply voltage terminal ELVDD, and the second power supply voltage terminal ELVSS can be provided by a voltage generator in the electronic device.

[0092] Taking the compensation scanning signal line SBL in the scanning signal line as an example, FIG1 illustrates a row of pixel circuits 11 coupled to the same compensation scanning signal line SBL. The same row of pixel circuits 11 can also be coupled to multiple compensation scanning signal lines SBL. For example, the pixel circuits 11 in the left half of a row are coupled to one compensation scanning signal line SBL, and the pixel circuits 11 in the right half are coupled to another row of compensation scanning signal lines SBL. Similarly, FIG1 illustrates an example of the pixel circuits 11 in the same column being coupled to the same data signal line DL. The same column of pixel circuits 11 can also be coupled to multiple data signal lines DL. For example, the pixel circuits 11 in the upper half of a column are coupled to one data signal line DL, and the pixel circuits 11 in the lower half are coupled to another data signal line DL.

[0093] The scan driver 12 receives a scan control signal SCS from the drive controller 30. In response to the scan control signal SCS, the scan driver 12 can output scan signals to the scan signal lines. The scan signal lines include, for example, initialization scan signal lines SCL1-SCLn, compensation scan signal lines SBL1-SBLn, write scan signal lines SXL1-SXLn, and emission control scan signal lines EML1-EMLn. In response to the scan control signal SCS, the scan driver 12 can output initialization scan signals to the initialization scan signal lines SCL1-SCLn, compensation scan signals to the compensation scan signal lines SBL1-SBLn, write scan signals to the write scan signal lines SXL1-SXLn, and emission control signals to the emission control scan signal lines EML1-EMLn.

[0094] For example, the scan driver 12 may be an array substrate gate driver circuit (GOA) and an array substrate emission circuit (EOA). The EOA is used to output emission control signals to the emission control scan signal lines EML1 to EMLn, and the GOA is used to output initialization scan signals to the initialization scan signal lines SCL1 to SCLn, output compensation scan signals to the compensation scan signal lines SBL1 to SBLn, and output write scan signals to the write scan signal lines SXL1 to SXLn. For example, the first array substrate gate driver circuit GOA1 is used to output initialization scan signals to the initialization scan signal lines SCL1 to SCLn, the second array substrate gate driver circuit GOA2 is used to output compensation scan signals to the compensation scan signal lines SBL1 to SBLn, and the third array substrate gate driver circuit GOA3 is used to output write scan signals to the write scan signal lines SXL1 to SXLn.

[0095] FIG. 2B is an architecture diagram of a scan driver provided in an embodiment of the present application.

[0096] Regarding the structure of the GOA or EOA, in some embodiments, as shown in FIG. 2B , the scan driver 12 includes at least two stages of cascaded shift registers RS1 -RSn.

[0097] The signal input terminal I of the first-stage shift register RS1 is coupled to the start signal terminal STV. Except for the first-stage shift register RS1, the signal input terminal I of each stage shift register RS(m) is coupled to the output terminal O of the previous-stage shift register RS(m-1). Except for the last-stage shift register, the reset signal terminal RST of each stage shift register RS(m) is coupled to the output terminal O of the next-stage shift register RS(m+1). The reset signal terminal RST of the last-stage shift register RSn is coupled to the start signal terminal STV.

[0098] When a start signal is input to the start signal terminal STV, the first-stage shift register RS1 of the scan driver 12 starts to work, and then the multi-stage shift registers start to work stage by stage.

[0099] Taking the compensation scanning signal line SBL in the scanning signal line as an example, the output end O of each level of shift register RS(m) can be coupled to a compensation scanning signal line SBL, for example. The output end O of each level of shift register RS(m) can also be coupled to multiple (for example, 4, 5, 6, 8, 10, etc.) compensation scanning signal lines SBL, which is not limited to the embodiments of the present application.

[0100] FIG2C is a topological diagram of a shift register provided in an embodiment of the present application.

[0101] Regarding the structure of the shift register, in some embodiments, as shown in FIG2C , the shift register SR includes a node control circuit and an output circuit. The node control circuit adjusts the potentials of the pull-up node U and the pull-down node P in response to the signal at the input terminal I. The output circuit outputs a signal of the high-level power supply voltage terminal VGH from the output terminal O in response to the signal at the pull-up node U. The output circuit also outputs a signal of the low-level power supply voltage terminal VGL from the output terminal O in response to the signal at the pull-down node D, so that the output terminal O outputs a scan signal.

[0102] 3A and 3B are diagrams of a display interface of a display screen provided in an embodiment of the present application.

[0103] In some embodiments, based on the above-mentioned pixel circuit 11, as shown in FIG3A , when the “parallel horizon” function is used, the refresh rate of the entire screen in the initial state is 1 Hz. When the secondary directory content on the right is slid, the refresh rate of the entire screen will change from 1 Hz when it is stationary and not operated to 120 Hz. Not only is the secondary directory content on the right refreshed and displayed at 120 Hz, but the primary directory content on the left is also refreshed and displayed at 120 Hz. However, the function of refreshing at 1 Hz on the left even when the secondary directory on the right is slid cannot be achieved. That is, the frequency of the signals output by the n shift registers RS in the scan driver 12 is always the same. The display screen 10 can only achieve a global refresh rate for the entire screen, and cannot achieve multiple local refresh rates on the same screen at the same time. It is not possible to achieve different refresh rates locally at different locations on the same display screen 10 according to different display contents.

[0104] As shown in FIG3B , when the "picture-in-picture" video floating function is used (the video is not played in full screen) and reading is performed, the entire screen refreshes at 60 Hz when no operation is performed, and refreshes at 120 Hz when an operation is performed. However, it is not possible to refresh the reading scene at 1 Hz even when watching a video and not performing any operation. That is, the frequency of the signals output by the n shift registers RS in the scan driver 12 is always the same. It is not possible to locally achieve different refresh rates at different locations on the same display screen 10 according to different display content.

[0105] FIG4 is a schematic diagram of the layout of a display screen provided in an embodiment of the present application.

[0106] In other embodiments, as shown in FIG4 , multiple rows of pixel circuits 11 in the display screen 10 are no longer controlled by the same scan driver 12 , but are controlled by multiple independent scan drivers 12 , thereby enabling area A, area B, and area C of the display screen 10 to have independent frequency conversion functions.

[0107] Although different refresh rates can be achieved locally at different locations on the same display screen 10 in this way, the pixel circuits 11 coupled to multiple independent scan drivers 12 are always fixed. Therefore, the division method of area A, area B, and area C is always fixed, so the position of the partition frequency conversion is fixed and cannot be changed accordingly with the frequency division requirements of the display screen.

[0108] An embodiment of the present application provides a scan driver 12 , which can be used to enable the display screen 10 to display multiple local refresh rates simultaneously on the same screen, thereby reducing display power consumption.

[0109] FIG5 is an architecture diagram of a scan driver provided in an embodiment of the present application.

[0110] The present embodiment provides a scan driver 12, which is applied to a display screen 10. Scan driver 12 may be a GOA or EOA within display screen 10, but this embodiment is not limited thereto. As shown in FIG5 , scan driver 12 includes a plurality of cascaded shift registers RS1 to RSn, each stage of shift register RS ​​including a first output terminal O1 and a second output terminal O2.

[0111] The input terminal I of the first-stage shift register RS1 is used to receive a start signal (e.g., coupled to the start signal terminal STV). Except for the first-stage shift register RS1, the input terminal I of each stage shift register RS(m) is coupled to the first output terminal O1 of the previous stage shift register RS(m-1). The first output terminal O1 of the last stage shift register RS(n) can be left floating, for example.

[0112] The second output terminal O2 of each stage of the shift register RS ​​is used to output a second scanning signal to the pixel circuit 11 . For example, the second output terminal O2 is coupled to the pixel circuit 11 through a scanning signal line.

[0113] In the scan driver 12 provided in the embodiment of the present application, the signal outputted by the first output terminal O1 is used to drive the cascade drive of the shift register RS, and the signal outputted by the second output terminal O2 is used to drive the pixel circuit 11 .

[0114] For example, the scan driver 12 is an initialization GOA, and is used to couple with the initialization scan signal lines SCL1 -SCLn. The second output terminal O2 of each stage of the shift register RS ​​is coupled with one or more adjacent initialization scan signal lines SCL.

[0115] Or, for example, the scan driver 12 is a compensation GOA, and is used to couple with the compensation scan signal lines SBL1 -SBLn. The second output terminal O2 of each stage shift register RS ​​is coupled with one or more adjacent compensation scan signal lines SBL.

[0116] Or, for example, the scan driver 12 is a write GOA, and is used to couple with the write scan signal lines SXL1 to SXLn. The second output terminal O2 of each stage of the shift register RS ​​is coupled with one or more adjacent write scan signal lines SXL.

[0117] Or, for example, the scan driver 12 is an EOA, which is used to couple with the light-emitting control scan signal lines EML1 to EMLn, and the second output terminal O2 of each stage shift register RS ​​is coupled with one or more adjacent light-emitting control scan signal lines EML.

[0118] FIG6 is an architectural diagram of a shift register provided in an embodiment of the present application.

[0119] In some embodiments, as shown in FIG6 , the shift register RS ​​includes an input terminal I, a node control circuit 31 , a pull-up node U, a pull-down node D, an output circuit 32 , a first output terminal O1 , a second output terminal O2 , a variable-frequency refresh circuit (VFR), and a voltage stabilization circuit 33 .

[0120] In a first implementation, the node control circuit 31 adjusts the potentials of the pull-up node U and the pull-down node D in response to a signal at the input terminal I. The output circuit 32 outputs a first scan signal from the first output terminal O1 in response to signals at the pull-up node U and the pull-down node G. The variable frequency refresh circuit VFR transmits a first voltage signal to the second output terminal O2 in response to the signal at the pull-up node U. The variable frequency refresh circuit VFR also transmits a second voltage signal to the second output terminal O2 in response to a signal at the pull-down node D. One of the first and second voltage signals is a power supply voltage, and the other is a variable voltage. The voltage stabilization circuit 33 transmits the aforementioned power supply voltage signal to the second output terminal O2 in response to a control signal.

[0121] For example, the variable frequency refresh circuit VFR is coupled to the pull-up node U, the pull-down node D, the power supply voltage terminal V, the variable frequency enable voltage terminal (variable frequency_enable, VFE), and the second output terminal O2. The voltage stabilization circuit 33 is coupled to the control signal terminal C, the power supply voltage terminal V, and the second output terminal O2. The power supply voltage terminal V is used to transmit the power supply voltage, and the variable frequency enable voltage terminal VFE is used to transmit the variable voltage Vfe.

[0122] Figure 7A is a structural diagram of a shift register provided in an embodiment of the present application. Figure 7B is a topological diagram of a shift register provided in an embodiment of the present application.

[0123] In some embodiments, the variable frequency refresh circuit VFR transmits a variable voltage to the second output terminal O2 in response to a signal at the pull-up node U. The variable frequency refresh circuit VFR also transmits a power supply voltage to the second output terminal O2 in response to a signal at the pull-down node D.

[0124] For example, as shown in FIG7A , the variable frequency refresh circuit VFR includes a first circuit R1 and a second circuit R2, wherein the power supply voltage terminal V is a low-level power supply voltage terminal VGL. The first circuit R1 transmits the variable voltage of the variable frequency enable voltage terminal VFE to the second output terminal O2 in response to a signal at a pull-up node U. The second circuit R2 transmits the low-level power supply voltage of the low-level power supply voltage terminal VGL to the second output terminal O2 in response to a signal at a pull-down node D.

[0125] In some embodiments, as shown in FIG6 , the control signal received by the voltage regulator circuit 33 is a variable voltage VFE. For example, as shown in FIG7A , the voltage regulator circuit 33 is coupled to the low-level power supply voltage terminal VGL. In response to the variable voltage of the frequency conversion enable voltage terminal VFE, the voltage regulator circuit 33 transmits the low-level power supply voltage of the low-level power supply voltage terminal VGL to the second output terminal O2 when the voltage of the frequency conversion enable voltage terminal VFE becomes the turn-on voltage.

[0126] For example, as shown in FIG7B , the first circuit in the variable frequency refresh circuit VFR includes a first transistor T1 , and the second circuit in the variable frequency refresh circuit VFR includes a second transistor T2 .

[0127] A control electrode of the first transistor T1 is coupled to the pull-up node U, a first electrode of the first transistor T1 is coupled to one of the power supply voltage terminal V and the frequency conversion enable voltage terminal VFE (for example, the frequency conversion enable voltage terminal VFE), and a second electrode of the first transistor T is coupled to the second output terminal O2.

[0128] A control electrode of the second transistor T2 is coupled to the pull-down node D, a first electrode of the second transistor T2 is coupled to the other of the power supply voltage terminal V and the frequency conversion enable voltage terminal VFE (for example, the low-level power supply voltage terminal VGL), and a second electrode of the second transistor T2 is coupled to the second output terminal O2.

[0129] The first circuit R1 may also include a transistor connected in series and / or in parallel with the first transistor T1. The embodiments of the present application are merely illustrative, and any structure capable of implementing the functions of the first circuit R1 falls within the scope of protection of the embodiments of the present application. Similarly, the second circuit R2 may also include a transistor connected in series and / or in parallel with the second transistor T2. The embodiments of the present application are merely illustrative, and any structure capable of implementing the functions of the second circuit R2 falls within the scope of protection of the embodiments of the present application.

[0130] The control electrode of the transistor illustrated in the embodiment of the present application may be, for example, a gate electrode, and the first electrode and the second electrode of the transistor serve as the source electrode and the drain electrode of the transistor, respectively.

[0131] For example, as shown in Figure 7B, the voltage stabilizing circuit 33 includes a third transistor T3, the control electrode of the third transistor T3 is coupled to the control signal terminal C (for example, the frequency conversion enable voltage terminal VFE), the first electrode of the third transistor T is coupled to the power supply voltage terminal V (for example, the low-level power supply voltage terminal VGL), and the second electrode of the third transistor T3 is coupled to the second output terminal O2.

[0132] The voltage stabilizing circuit 33 may also include a transistor connected in series and / or in parallel with the third transistor T3. The embodiment of the present application is only an illustration, and any structure that can realize the function of the voltage stabilizing circuit 33 falls within the protection scope of the embodiment of the present application.

[0133] In some embodiments, the first transistor T1 , the second transistor T2 , and the third transistor T3 are transistors of the same type. For example, the first transistor T1 , the second transistor T2 , and the third transistor T3 are all P-type transistors.

[0134] In some embodiments, as shown in FIG. 7A , the output circuit 32 includes a pull-up output circuit 321 and a pull-down output circuit 322 .

[0135] The pull-up output circuit 321 transmits the high-level power voltage of the high-level power voltage terminal VGH to the first output terminal O1 in response to the signal of the pull-up node U.

[0136] The pull-down output circuit 322 transmits the low-level power voltage of the low-level power voltage terminal VGL to the first output terminal O1 in response to the signal of the pull-down node D.

[0137] For example, as shown in FIG7B , the pull-up output circuit in the output circuit 32 includes a fourth transistor T4 and a first capacitor C1. The control electrode of the fourth transistor T4 is coupled to the pull-up node U, the first electrode of the fourth transistor T4 is coupled to the high-level power supply voltage terminal VGH, and the second electrode of the fourth transistor T4 is coupled to the first output terminal O1. One electrode of the first capacitor C1 is coupled to the high-level power supply voltage terminal VGH, and the other electrode of the first capacitor C1 is coupled to the pull-up node U.

[0138] The pull-down output circuit in the output circuit 32 includes a fifth transistor T5, a control electrode of the fifth transistor T5 coupled to the pull-down node D, a first electrode of the fifth transistor T5 coupled to the low-level power supply voltage terminal VGL, and a second electrode of the fifth transistor T5 coupled to the first output terminal O1.

[0139] The pull-up output circuit may also include a transistor connected in series and / or in parallel with the fourth transistor T4. The embodiment of the present application is only an illustration, and any structure that can realize the function of the pull-up output circuit falls within the protection scope of the embodiment of the present application.

[0140] The pull-down output circuit may also include a transistor connected in series and / or in parallel with the fifth transistor T5. The embodiment of the present application is only an illustration, and any structure that can realize the function of the pull-down output circuit falls within the protection scope of the embodiment of the present application.

[0141] The embodiment of the present application does not limit the structure of the output circuit 32 , and the structure of the output circuit in the shift register SR in the related art is applicable to the embodiment of the present application.

[0142] FIG8 is a topological diagram of a shift register provided in an embodiment of the present application.

[0143] In some embodiments, as shown in FIG8 , the node control circuit 31 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a second capacitor C2, and a third capacitor C3. The node control circuit 31 and the output circuit 32 are a "16T3C" (including 16 transistors and 3 capacitors) structure. The connection relationship between the sixth transistor T6 to the nineteenth transistor T19 and the second capacitor C2 and the third capacitor C3 can be referred to as shown in FIG8 . The first clock signal terminal CLK1 and the second clock signal terminal CLK2 are two opposite clock signal terminals, and the reset signal terminal RST is used to reset the shift register SR.

[0144] In the embodiments of the present application, the node control circuit 31 and output circuit 32 in the shift register SR are illustrated as a "16T3C" structure. The output circuit and node control circuit structures of the shift register SR in related art are all applicable to the embodiments of the present application. For example, the node control circuit 31 and output circuit 32 may also have a "16T4C," "13T3C," "12T3C," "10T3C," "8T2C," or other structures.

[0145] In some embodiments, the transistors included in the node control circuit 31, the output circuit 32, the variable frequency refresh circuit VFR, and the voltage stabilization circuit 33 are of the same type, for example, all P-type transistors. For example, the first transistor T1 to the nineteenth transistor T19 in FIG8 are all P-type transistors. This simplifies the manufacturing process of the shift register SR and reduces production costs.

[0146] The embodiment of the present application further provides a driving method of the scan driver 12, including:

[0147] The input terminal I of the first stage shift register SR1 receives the start signal, and the first output terminal O1 of the first stage shift register SR1 outputs the first scan signal, and the second output terminal O2 of the first stage shift register SR1 outputs the second scan signal.

[0148] Except for the first-stage shift register SR1, the input terminal I of each stage shift register SR(m) receives the first scanning signal output by the first output terminal O1 of the previous-stage shift register SR(m-1), and outputs the first scanning signal from the first output terminal O1 of the current-stage shift register SR(m), and outputs the second scanning signal from the second output terminal O2 of the current-stage shift register SR(m).

[0149] Taking the shift register SR shown in FIG8 as an example, the process of each stage of the shift register SR(m) outputting the first scanning signal and the second scanning signal in response to the signal at the output terminal I is schematically described.

[0150] The driving process of each stage shift register SR(m) includes:

[0151] The node control circuit 31 adjusts the potentials of the pull-up node U and the pull-down node D in response to a signal at the input terminal I.

[0152] The output circuit 32 outputs a first scan signal from a first output terminal O1 in response to signals of the pull-up node U and the pull-down node D.

[0153] The variable frequency refresh circuit VFR responds to the signal of the pull-up node U to transmit the first voltage signal to the second output terminal O2; the variable frequency refresh circuit VFR also responds to the signal of the pull-down node D to transmit the second voltage signal to the second output terminal O2; one of the first voltage signal and the second voltage signal is the power supply voltage and the other is a variable voltage.

[0154] The voltage stabilizing circuit 33 transmits the power voltage to the second output terminal O2 in response to the control signal, and the second output terminal O2 outputs the second scan signal.

[0155] For example, the shift register SR outputs a high-level signal as a scan-on signal and a low-level signal as a scan-off signal. For example, the shift register SR is an "N-type shift register" and the scan driver 12 is an "N-type scan driver." The first voltage signal is a variable voltage, and the second signal is a power supply voltage.

[0156] FIG9A is a driving timing diagram of a shift register provided in an embodiment of the present application.

[0157] In some embodiments, as shown in FIG9A , the driving process of the shift register includes:

[0158] Phase 1 P1:

[0159] In response to the signal at the input terminal I, the node control circuit 31 adjusts the potential of the pull-up node U to a low level and adjusts the potential of the pull-down node D to a high level.

[0160] The pull-up output circuit 321 in the output circuit 32 transmits the high-level power supply voltage of the high-level power supply voltage terminal VGH to the first output terminal O1 in response to the low level of the pull-up node U. The pull-down output circuit 322 in the output circuit 32 is turned off in response to the high level of the pull-down node D. The first output terminal O1 outputs the high-level power supply voltage.

[0161] In response to a low level at the pull-up node U, the first circuit R1 in the variable frequency refresh circuit VFR transmits the signal of the variable frequency enable voltage terminal VFE to the second output terminal O2. In response to a high level at the pull-down node D, the second circuit R2 in the variable frequency refresh circuit VFR is turned off. The second output terminal O2 outputs the signal of the variable frequency enable voltage terminal VFE.

[0162] The voltage stabilizing circuit 33 shuts off or transmits the low-level power supply voltage of the low-level power supply voltage terminal VGL to the second output terminal O2 in response to the signal of the frequency conversion enabling voltage terminal VFE.

[0163] For example, when the signal at the variable frequency enable voltage terminal VFE is a high-level signal, the voltage stabilizing circuit 33 is shut down in response to the control signal. The first circuit R1 in the variable frequency refresh circuit VFR transmits the signal at the variable frequency enable voltage terminal VFE to the second output terminal O2 in response to the low level at the pull-up node U. The second output terminal O2 outputs the high-level signal at the variable frequency enable voltage terminal VFE.

[0164] After the variable voltage at the variable frequency enable voltage terminal VFE transitions from high to low, the voltage stabilizing circuit 33 transmits the low-level power supply voltage at the low-level power supply voltage terminal VGL to the second output terminal O2 in response to the control signal (the signal at the variable frequency enable voltage terminal VFE). The first circuit R1 in the variable frequency refresh circuit VFR is turned off in response to the low level at the pull-up node U. The second output terminal O2 outputs the low-level power supply voltage at the low-level power supply voltage terminal VGL.

[0165] For example, in the first and third first phases P1 of FIG. 9A , the signal at the frequency conversion enable voltage terminal VFE is a high-level signal, and the voltage stabilizing circuit 33 is turned off in response to the high-level signal at the frequency conversion enable voltage terminal VFE. The first circuit R1 in the frequency conversion refresh circuit VFR outputs the high-level signal at the frequency conversion enable voltage terminal VFE to the second output terminal O2, and the second output terminal O2 outputs a high-level scan-on signal.

[0166] In the second first phase P1 of FIG9A , the signal at the frequency conversion enable voltage terminal VFE is a low-level signal, and the first circuit R1 in the frequency conversion refresh circuit VFR is shut down. At this point, the voltage regulator circuit 33 is turned on in response to the low-level signal at the frequency conversion enable voltage terminal VFE. The low-level power supply voltage at the low-level power supply voltage terminal VGL is transmitted to the second output terminal O2, which then outputs a low-level scan-off signal. The presence of the voltage regulator circuit 33 ensures that even if the voltage jump at the frequency conversion enable voltage terminal VFE causes the first circuit R1 to fail to turn on normally, the second output terminal O2 can still output a low-level scan-off signal.

[0167] For example, the first circuit R1 includes a first transistor T1. When the frequency conversion enable voltage terminal VFE is a high-level signal, the absolute value of the difference between the low-level signal at the pull-up node U and the high-level signal at the frequency conversion enable voltage terminal VFE (the absolute value of the gate-source voltage Vgs) is greater than the threshold voltage Vth of the first transistor T1, thereby ensuring that the first transistor T1 is normally turned on. When the frequency conversion enable voltage terminal VFE is a low-level signal, the absolute value of the difference between the low-level signal at the pull-up node U and the low-level signal at the frequency conversion enable voltage terminal VFE (the absolute value of the gate-source voltage Vgs) is not guaranteed to be greater than the threshold voltage Vth of the first transistor T1, thereby ensuring that the first transistor T1 is normally turned on. However, when the frequency conversion enable voltage terminal VFE is a low-level signal, the third transistor T3 is turned on under the control of the low-level signal at the frequency conversion enable voltage terminal VFE, transmitting the low-level power supply voltage of the low-level power supply voltage terminal VGL to the second output terminal O2. The existence of the voltage stabilizing circuit 33 ensures that the second output terminal O2 can output a low-level scan cutoff signal regardless of whether the first circuit R1 is normally turned on or not.

[0168] In some embodiments, the low-level signal of the frequency conversion enable voltage terminal VFE is less than (Vgl-1)v, where Vgl is the low-level power supply voltage of the low-level power supply voltage terminal VGL.

[0169] By setting the low level signal of the variable frequency enable voltage terminal VFE to be less than (Vgl-1)v, it can be ensured that when the variable frequency enable voltage terminal VFE is a low level signal, the voltage stabilizing circuit 33 can be normally turned on without a suspended state.

[0170] In the three first phases P1 of FIG9A , the first output terminal O1 outputs a high-level signal. Comparing the output of the first output terminal O1 with the output of the second output terminal O2, it can be seen that in the second first phase P1, the signal of the second output terminal O2 is adjusted from a high-level scan-on signal to a low-level scan-off signal to adjust the frequency of the second scan signal, thereby adjusting the refresh rate of the pixel circuit 11. By adjusting the signal of the frequency conversion enable voltage terminal VFE, the signal of the second output terminal O2 can be adjusted, thereby achieving selective output of the second output terminal O2.

[0171] Phase 2 P2:

[0172] In response to the signal at the input terminal I, the node control circuit 31 adjusts the potential of the pull-up node U to a high level and adjusts the potential of the pull-down node D to a low level.

[0173] The pull-up output circuit 321 in the output circuit 32 is turned off in response to the high level of the pull-up node U. The pull-down output circuit 322 in the output circuit 32 transmits the low-level power supply voltage of the low-level power supply voltage terminal VGL to the first output terminal O1 in response to the low level of the pull-down node D. The first output terminal O1 outputs the low-level power supply voltage.

[0174] The first circuit R1 in the variable frequency refresh circuit VFR is turned off in response to a high level at the pull-up node U. The second circuit R2 in the variable frequency refresh circuit VFR transmits the low-level power supply voltage of the low-level power supply voltage terminal VGL to the second output terminal O2 in response to a low level at the pull-down node D. The second output terminal O2 outputs the low-level power supply voltage of the low-level power supply voltage terminal VGL.

[0175] The voltage stabilizing circuit 33 shuts off or transmits the low-level power supply voltage of the low-level power supply voltage terminal VGL to the second output terminal O2 in response to the signal of the frequency conversion enabling voltage terminal VFE.

[0176] For example, in the three second phases P2 of FIG. 9A , the signal at the frequency conversion enable voltage terminal VFE is a high-level signal, and the voltage stabilizing circuit 33 is turned off in response to the high-level signal at the frequency conversion enable voltage terminal VFE. The second circuit R2 in the frequency conversion refresh circuit VFR outputs the low-level power supply voltage of the low-level power supply voltage terminal VGL to the second output terminal O2, and the second output terminal O2 outputs a scan-off signal.

[0177] In the embodiment of the present application, low level and high level are relative. The low level has a lower potential than the high level, and the high level has a lower potential than the low level, but the specific potentials of the low level and the high level are not limited.

[0178] FIG9B is a timing diagram of a first scanning signal and a second scanning signal output by a shift register provided in an embodiment of the present application.

[0179] In some embodiments, as shown in FIG9B , the shift register SR normally outputs a first scanning signal at 120 Hz from the first output terminal O1. However, by regulating the variable voltage of the frequency conversion enable voltage terminal VFE, the scanning signal initially intended to be output by the shift register SR can be frequency-reduced and then output. For example, as shown in FIG9B , the shift register SR outputs a second scanning signal at 30 Hz from the second output terminal O2.

[0180] The variable frequency refresh circuit VFR can output a down-converted second scanning signal to any selected row by controlling the timing of the variable frequency enable voltage terminal VFE, thereby enabling different refresh rates at different locations on the display screen 10. The highest refresh rate supported by the display screen 10 can be, for example, evenly divided by the refresh rate supported by the display screen 10. For example, the refresh rates of the display screen 10 may include 120 Hz, 60 Hz, 30 Hz, 15 Hz, 10 Hz, 1 Hz, and the like.

[0181] In some other embodiments, the variable frequency refresh circuit VFR transmits a variable voltage to the second output terminal O2 in response to a signal at the pull-down node D. The variable frequency refresh circuit VFR also transmits a power supply voltage to the second output terminal O2 in response to a signal at the pull-up node U.

[0182] Figure 10A is a structural diagram of a shift register provided in an embodiment of the present application. Figure 10B is a topological diagram of a shift register provided in an embodiment of the present application.

[0183] For example, as shown in FIG10A , the variable frequency refresh circuit VFR includes a first circuit R1 and a second circuit R2, wherein the power supply voltage terminal V is a high-level power supply voltage terminal VGH. The first circuit R1 transmits the high-level power supply voltage of the high-level power supply voltage terminal VGH to the second output terminal O2 in response to a signal at a pull-up node U. The second circuit R2 transmits the variable voltage of the variable frequency enable voltage terminal VFE to the second output terminal O2 in response to a signal at a pull-down node D.

[0184] In some embodiments, the control signal received by the voltage regulator circuit 33 is a variable voltage. For example, the voltage regulator circuit 33 is coupled to the high-level power supply voltage terminal VGH. In response to the variable voltage of the frequency conversion enable voltage terminal VFE, the voltage regulator circuit 33 transmits the high-level power supply voltage of the high-level power supply voltage terminal VGH to the second output terminal O2 when the voltage of the frequency conversion enable voltage terminal VFE becomes the turn-on voltage.

[0185] For example, as shown in FIG10B , the first circuit in the variable frequency refresh circuit VFR includes a first transistor T1 , and the second circuit in the variable frequency refresh circuit VFR includes a second transistor T2 .

[0186] The control electrode of the first transistor T1 is coupled to the pull-up node U, the first electrode of the first transistor T1 is coupled to one of the power supply voltage terminal V and the frequency conversion enable voltage terminal VFE (for example, the high-level power supply voltage terminal VGH), and the second electrode of the first transistor T is coupled to the second output terminal O2.

[0187] A control electrode of the second transistor T2 is coupled to the pull-down node D, a first electrode of the second transistor T2 is coupled to the other of the power supply voltage terminal V and the frequency conversion enable voltage terminal VFE (for example, the frequency conversion enable voltage terminal VFE), and a second electrode of the second transistor T2 is coupled to the second output terminal O2.

[0188] For example, as shown in Figure 10B, the voltage stabilizing circuit 33 includes a third transistor T3, the control electrode of the third transistor T3 is coupled to the control signal terminal C (for example, the frequency conversion enable voltage terminal VFE), the first electrode of the third transistor T is coupled to the power supply voltage terminal V (for example, the high-level power supply voltage terminal VGH), and the second electrode of the third transistor T3 is coupled to the second output terminal O2.

[0189] In some embodiments, the first transistor T1 and the second transistor T2 are of the same type, and the third transistor T3 is of a different type. For example, the first transistor T1 and the second transistor T2 are both P-type transistors, and the third transistor T3 is an N-type transistor.

[0190] In some embodiments, as shown in FIG. 10A , the output circuit 32 includes a pull-up output circuit 321 and a pull-down output circuit 322 .

[0191] The pull-up output circuit 321 transmits the high-level power voltage of the high-level power voltage terminal VGH to the first output terminal O1 in response to the signal of the pull-up node U.

[0192] The pull-down output circuit 322 transmits the low-level power supply voltage of the low-level power supply voltage terminal VGL or the clock signal of the clock signal terminal CLK to the first output terminal O1 in response to the signal of the pull-down node D.

[0193] For example, as shown in FIG10B , the pull-up output circuit in the output circuit 32 includes a fourth transistor T4 and a first capacitor C1. The control electrode of the fourth transistor T4 is coupled to the pull-up node U, the first electrode of the fourth transistor T4 is coupled to the high-level power supply voltage terminal VGH, and the second electrode of the fourth transistor T4 is coupled to the first output terminal O1. One electrode of the first capacitor C1 is coupled to the high-level power supply voltage terminal VGH, and the other electrode of the first capacitor C1 is coupled to the pull-up node U.

[0194] The pull-down output circuit in the output circuit 32 includes a fifth transistor T5 and a fourth capacitor C4. The control electrode of the fifth transistor T5 is coupled to the pull-down node D. A first electrode of the fifth transistor T5 is coupled to the low-level power supply voltage terminal VGL (or the clock signal terminal CLK). A second electrode of the fifth transistor T5 is coupled to the first output terminal O1. One electrode of the fourth capacitor C4 is coupled to the low-level power supply voltage terminal VGL (or the clock signal terminal CLK), and the other electrode of the fourth capacitor C4 is coupled to the pull-down node D.

[0195] The structure of the node control circuit 31 may be the same as the structure of the node control circuit 31 illustrated above, and will not be described in detail here.

[0196] For example, the shift register SR outputs a low-level signal as a scan-on signal and a high-level signal as a scan-off signal. For example, the shift register SR is a "P-type shift register" and the scan driver 12 is a "P-type scan driver." The first voltage signal is a power supply voltage, and the second signal is a variable voltage.

[0197] FIG10C is a driving timing diagram of a shift register provided in an embodiment of the present application.

[0198] In some embodiments, as shown in FIG10C , the driving process of the shift register includes:

[0199] Phase 1 P1:

[0200] In response to the signal at the input terminal I, the node control circuit 31 adjusts the potential of the pull-up node U to a high level and adjusts the potential of the pull-down node D to a low level.

[0201] The pull-up output circuit 321 in the output circuit 32 is turned off in response to the high level of the pull-up node U. The pull-down output circuit 322 in the output circuit 32 transmits the low-level power supply voltage of the low-level power supply voltage terminal VGL to the first output terminal O1 in response to the low level of the pull-down node D. The first output terminal O1 outputs the low-level power supply voltage.

[0202] The first circuit R1 in the variable frequency refresh circuit VFR is turned off in response to a high level at the pull-up node U. The second circuit R2 in the variable frequency refresh circuit VFR transmits the signal of the variable frequency enable voltage terminal VFE to the second output terminal O2 in response to a low level at the pull-down node D. The second output terminal O2 outputs the signal of the variable frequency enable voltage terminal VFE.

[0203] The voltage stabilizing circuit 33 shuts off or transmits the high-level power voltage of the high-level power voltage terminal VGH to the second output terminal O2 in response to the signal of the frequency conversion enabling voltage terminal VFE.

[0204] For example, when the signal at the frequency conversion enable voltage terminal VFE is a low-level signal, the voltage stabilizing circuit 33 is turned off in response to the signal at the frequency conversion enable voltage terminal VFE. The second circuit R2 in the frequency conversion refresh circuit VFR transmits the signal at the frequency conversion enable voltage terminal VFE to the second output terminal O2 in response to the low level at the pull-down node D. The second output terminal O2 outputs the low-level signal of the frequency conversion enable voltage terminal VFE.

[0205] After the variable voltage at the variable frequency enable voltage terminal VFE jumps from low to high, the voltage stabilizing circuit 33 transmits the high-level power supply voltage at the high-level power supply voltage terminal VGH to the second output terminal O2 in response to the control signal (the signal at the variable frequency enable voltage terminal VFE). The second circuit R2 in the variable frequency refresh circuit VFR is turned off in response to the low level at the pull-down node D. The second output terminal O2 outputs the high-level power supply voltage at the high-level power supply voltage terminal VGH.

[0206] For example, in the first and third first phases P1 of FIG10C , the signal at the frequency conversion enable voltage terminal VFE is a low-level signal, and the voltage stabilizing circuit 33 is turned off in response to the low-level signal at the frequency conversion enable voltage terminal VFE. The second circuit R2 in the frequency conversion refresh circuit VFR outputs the low-level signal at the frequency conversion enable voltage terminal VFE to the second output terminal O2, and the second output terminal O2 outputs a low-level scan-on signal.

[0207] In the second first phase P1 of FIG10C , the signal at the frequency conversion enable voltage terminal VFE is high, and the second circuit R2 in the frequency conversion refresh circuit VFR is shut down. At this point, the voltage regulator circuit 33 is turned on in response to the high-level signal at the frequency conversion enable voltage terminal VFE. The high-level power supply voltage at the high-level power supply voltage terminal VGH is transmitted to the second output terminal O2, which then outputs a high-level scan-off signal. The presence of the voltage regulator circuit 33 ensures that even if the voltage jump at the frequency conversion enable voltage terminal VFE causes the second circuit R2 to fail to turn on properly, the second output terminal O2 can still output a high-level scan-off signal.

[0208] For example, the second circuit R2 includes a second transistor T2. When the frequency conversion enable voltage terminal VFE is a low-level signal, the second transistor T2 is normally turned on. When the frequency conversion enable voltage terminal VFE becomes a high-level signal, the second transistor T2 cannot be guaranteed to be normally turned on. However, when the frequency conversion enable voltage terminal VFE is a high-level signal, the third transistor T3 is controlled by the high-level signal of the frequency conversion enable voltage terminal VFE to turn on, transmitting the high-level power supply voltage of the high-level power supply voltage terminal VGH to the second output terminal O2, and the second output terminal O2 normally outputs a high-level scan-off signal.

[0209] In some embodiments, the high-level signal of the frequency conversion enable voltage terminal VFE is greater than (Vgh-1)v, where Vgh is the high-level power supply voltage of the high-level power supply voltage terminal VGH.

[0210] By setting the high level signal of the variable frequency enable voltage terminal VFE to be greater than (Vgh-1)v, it can be ensured that when the variable frequency enable voltage terminal VFE is a high level signal, the voltage stabilizing circuit 33 can be normally turned on without a floating state.

[0211] In the three first phases P1 of FIG10C , the first output terminal O1 outputs a low-level signal. Comparing the output of the first output terminal O1 with the output of the second output terminal O2, it can be seen that in the second first phase P1, the signal of the second output terminal O2 is adjusted from a low-level scan-on signal to a high-level scan-off signal, thereby adjusting the frequency of the second scan signal and achieving the purpose of adjusting the refresh rate of the pixel circuit 11. By adjusting the signal of the frequency conversion enable voltage terminal VFE, the signal of the second output terminal O2 can be adjusted, thereby achieving selective output of the second output terminal O2.

[0212] Phase 2 P2:

[0213] In response to the signal at the input terminal I, the node control circuit 31 adjusts the potential of the pull-up node U to a low level and adjusts the potential of the pull-down node D to a high level.

[0214] The pull-up output circuit 321 in the output circuit 32 transmits the high-level power supply voltage of the high-level power supply voltage terminal VGH to the first output terminal O1 in response to the low level of the pull-up node U. The pull-down output circuit 322 in the output circuit 32 is turned off in response to the high level of the pull-down node D. The first output terminal O1 outputs the high-level power supply voltage.

[0215] The first circuit R1 in the variable frequency refresh circuit VFR transmits the high-level power supply voltage of the high-level power supply voltage terminal VGH to the second output terminal O2 in response to a low level at the pull-up node U. The second circuit R2 in the variable frequency refresh circuit VFR is turned off in response to a high level at the pull-down node D. The second output terminal O2 outputs the high-level power supply voltage of the high-level power supply voltage terminal VGH.

[0216] The voltage stabilizing circuit 33 shuts off or transmits the high-level power voltage of the high-level power voltage terminal VGH to the second output terminal O2 in response to the signal of the frequency conversion enabling voltage terminal VFE.

[0217] For example, in the three second phases P2 of FIG. 10C , the signal at the frequency conversion enable voltage terminal VFE is a low-level signal, and the voltage stabilizing circuit 33 is turned off in response to the low-level signal at the frequency conversion enable voltage terminal VFE. The first circuit R1 in the frequency conversion refresh circuit VFR outputs the high-level power supply voltage of the high-level power supply voltage terminal VGH to the second output terminal O2, and the second output terminal O2 outputs the scan-off signal.

[0218] FIG10D is a timing diagram of a first scanning signal and a second scanning signal output by a shift register provided in an embodiment of the present application.

[0219] In some embodiments, as shown in FIG10D , the shift register SR normally outputs a first scanning signal at 120 Hz from the first output terminal O1. However, by regulating the variable voltage of the frequency conversion enable voltage terminal VFE, the scanning signal initially intended to be output by the shift register SR can be frequency-reduced and then output. For example, as shown in FIG10D , the shift register SR outputs a second scanning signal at 30 Hz from the second output terminal O2.

[0220] The scan driver 12 provided in the embodiment of the present application adds a variable frequency refresh circuit VFR to the shift register SR. The power supply voltage output by the shift register SR from the second output terminal O2 is used as the off pulse in the second scan signal, and the variable voltage output by the shift register SR from the second output terminal O2 is used to adjust the number of on pulses in the second scan signal. By adjusting the high and low potential values ​​of the variable voltage, the number of on pulses in the second scan signal can be adjusted, thereby adjusting the frequency of the second scan signal to achieve a display effect with different refresh rates at different positions of the display screen 10. A low refresh rate is used for local positions that do not require a high refresh rate to save the display power consumption of the display screen 10 (for example, the power consumption of the display driver 20 and the drive controller 30). On this basis, the shift register SR also includes a voltage stabilizing circuit 33. When the voltage stabilizing circuit 33 is turned on, it can ensure that the power supply voltage is output to the pixel circuit 11 as the off pulse in the second scan signal, effectively improving the problem of unstable waveform output by the variable frequency refresh circuit VFR to the pixel circuit 11 and the problem of suspended state, reducing display risk, and meeting the driving requirements of large-size display screens 10. Furthermore, because the signals at the variable frequency enable voltage terminals VFE of different shift registers SR are independently controlled, different refresh rates can be achieved at different locations on the same display screen 10, depending on the displayed content. The locations where different refresh rates are divided are not physically restricted, and timing can be set based on the supported gears, allowing for different refresh rates to be achieved that match the user interface (UI). Furthermore, the number of regions with different refresh rates that can be achieved is not physically restricted, allowing for multiple regions with different refresh rates to be matched to the UI.

[0221] FIG11A is an architectural diagram of a shift register provided in an embodiment of the present application, and FIG11B and FIG11C are topological diagrams of a shift register provided in an embodiment of the present application.

[0222] In the second implementation, as shown in FIG11A , the variable frequency refresh circuit VFR no longer transmits the second voltage signal to the second output terminal O2 in response to the signal at the pull-down node D. Instead, the variable frequency refresh circuit VFR transmits the second voltage signal to the second output terminal O2 in response to the signal at the first output terminal O1.

[0223] As shown in FIG. 11B and FIG. 11C , the control electrode of the second transistor T2 is coupled to the first output terminal O1 , and the on / off state of the second transistor T2 is controlled by the signal of the first output terminal O1 .

[0224] In some embodiments, as shown in FIG11B , the first transistor T1 , the second transistor T2 , and the third transistor T3 are transistors of the same type. For example, the first transistor T1 , the second transistor T2 , and the third transistor T3 are all P-type transistors.

[0225] In some embodiments, as shown in FIG11C , the first transistor T1 and the second transistor T2 are of the same type, and the third transistor T3 is of a different type. For example, the first transistor T1 and the second transistor T2 are both P-type transistors, and the third transistor T3 is an N-type transistor.

[0226] As can be seen from Figures 9A and 10C, the first scan signal output by the first output terminal O1 is synchronized with the signal of the pull-down node D. Therefore, when the control electrode of the second transistor T2 is coupled to the first output terminal O1, the working process of the shift register SR is the same as above and will not be repeated here.

[0227] Figures 12A and 12B are architectural diagrams of a shift register provided in an embodiment of the present application, and Figures 12C and 12D are topological diagrams of a shift register provided in an embodiment of the present application.

[0228] In the third implementation, as shown in FIG12A, the difference from the first implementation shown in FIG6 is that the control signal received by the voltage stabilizing circuit 33 is the reverse signal of the variable voltage. It is no longer a variable voltage vfe.

[0229] For example, the voltage stabilizing circuit 33 receives the reverse signal of the variable voltage It can be directly provided by the display driver 20.

[0230] Alternatively, for example, as shown in FIG12B , the shift register SR further includes an inverter, which responds to the variable voltage vfe and outputs a control signal (an inverse signal of the variable voltage). ).

[0231] For example, the inverter is coupled between the variable frequency enable voltage terminal VFE and the control signal terminal C, and converts the variable voltage VFE outputted from the variable frequency enable voltage terminal VFE into an inverse signal of the variable voltage.

[0232] For example, the third transistor T3 in the voltage-stabilizing circuit 33 shown in FIG12C and the third transistor T3 in the voltage-stabilizing circuit 33 shown in FIG7B are transistors of different types. For example, the third transistor T3 in the voltage-stabilizing circuit 33 shown in FIG12C is an N-type transistor, and the third transistor T3 in the voltage-stabilizing circuit 33 shown in FIG7B is a P-type transistor. For example, the first transistor T1 and the second transistor T2 are transistors of the same type, and the third transistor T3 is a transistor of a different type. For example, the first transistor T1 and the second transistor T2 are both P-type transistors, and the third transistor T3 is an N-type transistor.

[0233] For example, the third transistor T3 in the voltage-stabilizing circuit 33 shown in FIG12D and the third transistor T3 in the voltage-stabilizing circuit 33 shown in FIG10B are transistors of different types. For example, the third transistor T3 in the voltage-stabilizing circuit 33 shown in FIG12D is a P-type transistor, and the third transistor T3 in the voltage-stabilizing circuit 33 shown in FIG10B is an N-type transistor. For example, the first transistor T1, the second transistor T2, and the third transistor T3 are transistors of the same type. For example, the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type transistors.

[0234] Figures 13A and 13B are architectural diagrams of a shift register provided in an embodiment of the present application, and Figures 13C and 13D are topological diagrams of a shift register provided in an embodiment of the present application.

[0235] In the fourth implementation, as shown in FIG13A, the difference from the first implementation shown in FIG11A is that the control signal received by the voltage stabilizing circuit 33 is the reverse signal of the variable voltage. It is no longer a variable voltage vfe.

[0236] For example, the voltage stabilizing circuit 33 receives the reverse signal of the variable voltage It can be directly provided by the display driver 20.

[0237] Alternatively, for example, as shown in FIG13B , the scan driver further includes an inverter, which responds to the variable voltage vfe and outputs a control signal (an inverse signal of the variable voltage). ).

[0238] For example, the inverter is coupled between the variable frequency enable voltage terminal VFE and the control signal terminal C, and converts the variable voltage VFE outputted from the variable frequency enable voltage terminal VFE into an inverse signal of the variable voltage.

[0239] For example, the third transistor T3 in the voltage stabilizing circuit 33 shown in FIG13C and the third transistor T3 in the voltage stabilizing circuit 33 shown in FIG11B are transistors of different types. For example, the third transistor T3 in the voltage stabilizing circuit 33 shown in FIG13C is an N-type transistor, and the third transistor T3 in the voltage stabilizing circuit 33 shown in FIG11B is a P-type transistor.

[0240] For example, the third transistor T3 in the voltage stabilizing circuit 33 shown in FIG13D and the third transistor T3 in the voltage stabilizing circuit 33 shown in FIG11C are transistors of different types. For example, the third transistor T3 in the voltage stabilizing circuit 33 shown in FIG13D is a P-type transistor, and the third transistor T3 in the voltage stabilizing circuit 33 shown in FIG11C is an N-type transistor.

[0241] In some embodiments, the structure of each stage of the shift register SR in the scan driver 12 can be any of the above-mentioned shift registers SR including the variable frequency refresh circuit VFR and the voltage stabilizing circuit 33. In this way, the frequency of the scan signal output by each stage of the shift register SR to the pixel circuit 11 can be controlled.

[0242] In other embodiments, the structure of the partial-stage shift register SR in the scan driver 12 may be any of the above-mentioned shift registers SR including the variable frequency refresh circuit VFR and the voltage stabilizing circuit 33. The partial-stage shift register SR may not include the variable frequency refresh circuit VFR and the voltage stabilizing circuit 33. In this way, the frequency of the scan signal output by the partial-stage shift register SR to the pixel circuit 11 can be controlled, and the partial-stage shift register SR may be any one or more scan signals outputting the same frequency, without fixed restrictions.

[0243] FIG14A is a distribution diagram of a display screen provided in an embodiment of the present application.

[0244] As shown in FIG14A , in the scan driver 12 provided in the embodiment of the present application, the shift register SR adds a variable frequency refresh circuit VFR and a voltage stabilizing circuit 33 in addition to the node control circuit 31 and the output circuit 32. By adjusting the high and low potentials of the variable voltage at the variable frequency enable voltage terminal VFE, the number of on-pulses in the second scan signal output by the variable frequency refresh circuit VFR and the voltage stabilizing circuit 33 can be adjusted, thereby adjusting the frequency of the second scan signal to achieve the purpose of adjusting the refresh rate of the display screen 10.

[0245] FIG14B is a schematic diagram of signal output of a scan driver provided in an embodiment of the present application.

[0246] As shown in Figure 14B, the scan driver 12 can be a GOA for controlling a P-type transistor (such as LTPS), the scan driver 12 can also be a GOA for controlling an N-type transistor (such as IGZO), and the scan driver 12 can also be an EOA for controlling the light-emitting control signal terminal EM.

[0247] Figures 15A-15C are display interface diagrams of a display screen provided in an embodiment of the present application.

[0248] Since the signals of the frequency conversion enable voltage terminal VFE received by different shift registers SR in the scan driver 12 of the embodiment of the present application are independently controlled (for example, provided by the display driver DDIC), different refresh rates can be achieved at different locations of the same display screen 10 according to different display contents.

[0249] For example, as shown in FIG15A , in the "Parallel Vision" usage scenario, when no operation is performed and the screen has no dynamic content, the refresh rate of the entire display screen 10 dynamically changes to 1 Hz. When the first-level directory on the left is selected and only the content of the second-level directory on the right is browsed by sliding, the refresh rate of the first-level directory on the left is reduced to 1 Hz, while the refresh rate of the second-level directory on the right is increased to 120 Hz.

[0250] Or, for example, as shown in Figures 15B and 15C, in the "picture-in-picture" usage scenario, when the video is suspended and read, the suspended video is refreshed at 30Hz, and when the background reading is not operated, it is refreshed at 1Hz, and the video can still be refreshed at 30Hz when sliding the background reading.

[0251] The above are only specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A scanning driver, characterized in that: The scan driver includes a plurality of cascaded shift registers; The shift register comprises: an input end, a first output end and a second output end; The input end of the first-stage shift register is used to receive a start signal; except for the first-stage shift register, the input end of each stage of the shift register is coupled to the first output end of the shift register of the previous stage; the second output end of each stage of the shift register is used to output a second scanning signal to the pixel circuit; The shift register further includes: a node control circuit, a pull-up node, a pull-down node, an output circuit, a frequency conversion refresh circuit, and a voltage stabilization circuit; The node control circuit adjusts the potentials of the pull-up node and the pull-down node in response to the signal of the input terminal; The output circuit outputs a first scan signal from the first output terminal in response to signals of the pull-up node and the pull-down node; The variable frequency refresh circuit transmits a first voltage signal to the second output terminal in response to a signal from the pull-up node; the variable frequency refresh circuit also transmits a second voltage signal to the second output terminal in response to a signal from the pull-down node or the first output terminal; one of the first voltage signal and the second voltage signal is a power supply voltage, and the other is a variable voltage; The voltage stabilizing circuit transmits the power supply voltage to the second output terminal in response to a control signal.

2. The scanning driver according to claim 1, wherein: The frequency conversion refresh circuit is coupled to the pull-up node, the pull-down node, the power supply voltage terminal, the frequency conversion enable voltage terminal and the second output terminal; The voltage stabilizing circuit is coupled to the control signal terminal, the power voltage terminal and the second output terminal.

3. The scanning driver according to claim 1 or 2, wherein: The control signal is the variable voltage, or the control signal is an inverse signal of the variable voltage.

4. The scanning driver according to claim 1 or 2, wherein: The shift register further includes an inverter configured to output the control signal in response to the variable voltage.

5. The scanning driver according to any one of claims 2 to 4, characterized in that: The frequency variable refresh circuit includes a first transistor and a second transistor; A control electrode of the first transistor is coupled to the pull-up node, a first electrode of the first transistor is coupled to one of the power supply voltage terminal and the frequency conversion enable voltage terminal, and a second electrode of the first transistor is coupled to the second output terminal; A control electrode of the second transistor is coupled to the pull-down node, a first electrode of the second transistor is coupled to the other of the power supply voltage terminal and the frequency conversion enable voltage terminal, and a second electrode of the second transistor is coupled to the second output terminal.

6. The scanning driver according to any one of claims 2 to 5, characterized in that: The voltage stabilizing circuit includes a third transistor, a control electrode of the third transistor is coupled to the control signal terminal, a first electrode of the third transistor is coupled to the power supply voltage terminal, and a second electrode of the third transistor is coupled to the second output terminal.

7. The scanning driver according to claim 5 or 6, characterized in that: The first electrode of the first transistor is coupled to the frequency conversion enabling voltage terminal, and the first electrode of the second transistor is coupled to the power supply voltage terminal, where the power supply voltage terminal is a low-level power supply voltage terminal.

8. The scan driver according to claim 7, wherein: The low-level signal of the frequency conversion enabling voltage terminal is less than (Vgl-1)v, where Vgl is the low-level power supply voltage of the low-level power supply voltage terminal.

9. The scanning driver according to claim 5 or 6, characterized in that: The first electrode of the first transistor is coupled to the power supply voltage terminal, the first electrode of the second transistor is coupled to the frequency conversion enable voltage terminal, and the power supply voltage terminal is a high-level power supply voltage terminal.

10. The scan driver according to claim 9, wherein: The high-level signal of the frequency conversion enabling voltage terminal is greater than (Vgh-1)v, where Vgh is the high-level power supply voltage of the high-level power supply voltage terminal.

11. The scanning driver according to any one of claims 1 to 10, characterized in that: The output circuit includes a pull-up output circuit and a pull-down output circuit; The pull-up output circuit transmits the high-level power supply voltage of the high-level power supply voltage terminal to the first output terminal in response to a signal of the pull-up node; The pull-down output circuit transmits the low-level power supply voltage of the low-level power supply voltage terminal or the clock signal of the clock signal terminal to the first output terminal in response to the signal of the pull-down node.

12. A display screen, characterized in that: The display screen includes a scan driver and a plurality of pixel circuits arranged in an array; the scan driver includes the scan driver according to any one of claims 1 to 11, and a second output terminal of the scan driver is coupled to the pixel circuit.

13. An electronic device, characterized in that: The electronic device includes a display screen and a middle frame, the display screen is arranged on the middle frame, and the display screen includes the display screen according to claim 12.

14. A driving method of a scanning driver, characterized in that: The scan driver includes a plurality of cascaded shift registers; the shift registers include: an input terminal, a node control circuit, a pull-up node, a pull-down node, an output circuit, a first output terminal, a second output terminal, a frequency conversion refresh circuit, and a voltage stabilization circuit; the input terminal of the first-stage shift register is used to receive a start signal; except for the first-stage shift register, the input terminal of each stage of the shift register is coupled to the first output terminal of the shift register of the previous stage; The driving method of the scanning driver includes: The node control circuit adjusts the potentials of the pull-up node and the pull-down node in response to the signal of the input terminal; The output circuit outputs a first scan signal from the first output terminal in response to signals of the pull-up node and the pull-down node; The variable frequency refresh circuit transmits a first voltage signal to the second output terminal in response to a signal from the pull-up node; the variable frequency refresh circuit also transmits a second voltage signal to the second output terminal in response to a signal from the pull-down node or the first output terminal; one of the first voltage signal and the second voltage signal is a power supply voltage, and the other is a variable voltage; The voltage stabilizing circuit transmits the power supply voltage to the second output terminal in response to a control signal; The second output terminal outputs a second scanning signal to the pixel circuit.

15. The driving method of the scan driver according to claim 14, wherein: The power supply voltage is a low-level power supply voltage; The variable frequency refresh circuit transmits the variable voltage to the second output terminal in response to the signal of the pull-up node; The variable frequency refresh circuit transmits the low-level power supply voltage to the second output terminal in response to the signal of the pull-down node or the first output terminal; after the variable voltage jumps from high to low, the voltage stabilizing circuit transmits the low-level power supply voltage to the second output terminal in response to the control signal.

16. The driving method of the scan driver according to claim 15, wherein: The low-level signal of the variable voltage is less than (Vgl-1)v, where Vgl is the low-level power supply voltage.

17. The driving method of the scan driver according to claim 16, wherein: The power supply voltage is a high-level power supply voltage; The variable frequency refresh circuit transmits the variable voltage to the second output terminal in response to a signal from the pull-down node or the first output terminal; The variable frequency refresh circuit transmits the high-level power supply voltage to the second output terminal in response to the signal of the pull-up node; after the variable voltage jumps from low to high, the voltage stabilizing circuit transmits the high-level power supply voltage to the second output terminal in response to the control signal.

18. The driving method of the scan driver according to claim 17, wherein: The high-level signal of the variable voltage is greater than (Vgh-1)v, where Vgh is the high-level power supply voltage.

Images