Communication apparatus and method

Abstract

The embodiments of the present application relate to the technical field of chips. Disclosed are a communication apparatus and method, which are used for improving the security of chip interconnection. The method comprises: receiving an access command from a master in a first chip; and sending the access command to a secure area or a non-secure area of a second chip on the basis of configuration information, wherein the access command comprises identification information and an access address, the identification information is used for indicating the master in the first chip that sends the access command, the configuration information comprises first information and second information, the first information is used for characterizing the correspondence between the identification information and a security type, the second information is used for characterizing the correspondence between the access address and an address type, the security type comprises a secure master and a non-secure master, and the address type comprises a secure area and a non-secure area.

Description

Communication device and method

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 6, 2024, with application number 202410172718.2 and application name “Communication Device and Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of chip technology, and in particular to communication devices and methods. Background Art

[0003] With technological advancements, electronic devices are entering a period of rapid development. These devices integrate multimedia, the internet, gaming, and online platforms, and their performance is increasing at an exponential rate year after year. Within these devices, chips are like the brain or heart, influencing their processing speed, power consumption, size, and cost.

[0004] As chip sizes increase, in order to cope with challenges such as high integration, multi-core processors, and process technology advancements, the technology of breaking down chips into multiple independent chip components has developed. It is very important to ensure the security of chip interconnection.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a communication device and method for improving the security of chip interconnection. To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a communication method, the method comprising: receiving an access command from a master device (master) of a first chip. Sending the access command to a secure area or a non-secure area of ​​a second chip according to configuration information. The access command comprises identification information and an access address, the identification information being used to indicate the master in the first chip that sends the access command, the configuration information comprising first information and second information, the first information being used to characterize a correspondence between the identification information and a security type, the second information being used to characterize a correspondence between an access address and an address type, the security type comprising a secure master and a non-secure master, and the address type comprising a secure area and a non-secure area.

[0008] In the method provided in the embodiment of the present application, by adding identification information and access address to the access command, the receiving end of the access command can determine the security type corresponding to the access command and the address type corresponding to the access command through the access command and configuration information, and the access command can be authenticated through the security type corresponding to the access command and the address type corresponding to the access command (that is, determine whether the security type corresponding to the access command and the address type corresponding to the access command match). In this way, the access command of the secure master can only be sent to the secure area, and the access command of the non-secure master can only be sent to the non-secure area, so that the secure area and the non-secure area in the chip interconnection are isolated from each other, avoiding the non-secure master from accessing the secure area, thereby improving the security of the chip interconnection.

[0009] In one possible implementation, if the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a secure zone, the access command can be sent to the secure zone of the second chip. This allows the secure master's access command to be sent only to the secure zone, preventing non-secure masters from accessing the secure zone, thereby improving chip interconnect security.

[0010] In one possible implementation, if the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a non-secure zone, the access command can be sent to the non-secure zone of the second chip. This allows the access command of the non-secure master to be sent only to the non-secure zone, preventing the secure master from accessing the non-secure zone, thereby improving the security of chip interconnection.

[0011] In one possible implementation, the secure area includes a secure storage area and a secure peripheral area.

[0012] In one possible implementation, if the access address of the access command corresponds to a secure storage area, the access command can be sent to the secure storage of the second chip. This allows the secure master to send storage access commands only to the secure storage area, preventing non-secure masters from accessing the secure storage area, thereby improving the security of chip interconnection.

[0013] In one possible implementation, if the access address of the access command corresponds to the secure peripheral area, the access command can be sent to the secure peripheral area of ​​the second chip. This allows the secure master to send peripheral access commands only to the secure peripheral area, preventing non-secure masters from accessing the secure peripheral area, thereby improving the security of chip interconnection.

[0014] In a possible implementation, the non-secure area includes a non-secure storage area and a non-secure peripheral area.

[0015] In one possible implementation, if the access address of the access command corresponds to a non-secure storage area, the access command can be sent to the non-secure storage of the second chip. This allows the non-secure master to send storage access commands only to the non-secure storage area, preventing the secure master from accessing the non-secure storage area, thereby improving the security of chip interconnection.

[0016] In one possible implementation, if the access address of the access command corresponds to the non-secure peripheral area, the access command can be sent to the non-secure peripheral area of ​​the second chip. This allows the non-secure master to send peripheral access commands only to the non-secure peripheral area, preventing the secure master from accessing the non-secure peripheral area, thereby improving the security of chip interconnection.

[0017] In a possible implementation, third information may be sent to the first chip according to the configuration information, where the third information is used to indicate that the access command has failed authentication.

[0018] It can be understood that, by sending the third information to the first chip, the first chip can be informed that the master sending the access command does not match the access area.

[0019] In one possible implementation, the third information may be sent to the first chip when the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a non-secure area, or when the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a secure area.

[0020] It can be seen that the method provided in the embodiment of the present application returns the third information when the master of the access command does not match the access area, thereby allowing the access command of the secure master to be sent only to the secure area, and the access command of the non-secure master to be sent only to the non-secure area, thereby isolating the secure area and the non-secure area in the chip interconnection from each other, preventing the non-secure master from accessing the secure area, and thus improving the security of the chip interconnection.

[0021] In a possible implementation, the configuration information may be received from the first chip.

[0022] It can be understood that by receiving the above-mentioned configuration information from the above-mentioned first chip, the receiving end of the access command can determine the security type corresponding to the access command and the address type corresponding to the access command through the access command and the configuration information, and the access command can be authenticated through the security type corresponding to the access command and the address type corresponding to the access command, so that the access command of the secure master can only be sent to the secure area, and the access command of the non-secure master can only be sent to the non-secure area, so that the secure area and the non-secure area in the chip interconnection are isolated from each other, avoiding the non-secure master from accessing the secure area, thereby improving the security of the chip interconnection.

[0023] In a possible implementation, a key may be obtained; encrypted information from the first chip is received; and the encrypted information is decrypted according to the key to obtain the configuration information.

[0024] In a possible implementation, a secure channel is established between the first chip and the second chip.

[0025] It is understandable that a secure channel is established to ensure that the interaction channel between the two chips is safe and reliable, and to prepare for subsequent data transmission.

[0026] In a possible implementation, communication between the first chip and the communication device, the second chip and the communication device, and between the first chip and the second chip may be implemented through the aforementioned secure channel.

[0027] In a possible implementation, the first chip and the second chip may be bound to a key, and the first chip and the second chip may use the key to encrypt and decrypt information (such as configuration information, access commands, etc.) sent to each other.

[0028] In a second aspect, an embodiment of the present application provides a communication device, which includes: a receiving unit and a sending unit. The receiving unit is used to receive an access command from the master of the first chip, the access command including identification information and an access address, and the identification information is used to indicate the master in the first chip that sends the access command. The sending unit is used to send the access command to the secure area or non-secure area of ​​the second chip according to configuration information, the configuration information including first information and second information, the first information being used to characterize the correspondence between the identification information and the security type, the second information being used to characterize the correspondence between the access address and the address type, the security type including a secure master and a non-secure master, and the address type including a secure area and a non-secure area.

[0029] In a possible implementation, the sending unit is specifically configured to: send the access command to the secure area of ​​the second chip when the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a secure area;

[0030] In a possible implementation, the sending unit is specifically configured to send the access command to the non-secure area of ​​the second chip when the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a non-secure area.

[0031] In a possible implementation, the security area includes a secure storage area and a secure peripheral area.

[0032] In a possible implementation, the sending unit is specifically configured to send the access command to the secure storage of the second chip when an access address of the access command corresponds to a secure storage area.

[0033] In a possible implementation, the sending unit is specifically configured to send the access command to the secure peripheral area of ​​the second chip when an access address of the access command corresponds to the secure peripheral area.

[0034] In a possible implementation, the above-mentioned secure area includes a non-secure area including a non-secure storage area and a non-secure peripheral area.

[0035] In a possible implementation, the sending unit is specifically configured to send the access command to the non-secure storage of the second chip when an access address of the access command corresponds to a non-secure storage area.

[0036] In a possible implementation, the sending unit is specifically configured to send the access command to the non-secure peripheral area of ​​the second chip when an access address of the access command corresponds to the non-secure peripheral area.

[0037] In a possible implementation, the sending unit is further configured to send third information to the first chip according to the configuration information, where the third information is used to indicate that the access command has failed authentication.

[0038] In one possible implementation, the sending unit is specifically used to send the third information to the first chip when the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a non-secure area, or when the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a secure area.

[0039] In a possible implementation, the receiving unit is further configured to: receive the configuration information from the first chip.

[0040] In a third aspect, an embodiment of the present application further provides a communication device, which includes: at least one processor, which, when the at least one processor executes program code or instructions, implements the method described in the above first aspect or any possible implementation thereof.

[0041] Optionally, the communication device may further include at least one memory, and the at least one memory is used to store the program code or instruction.

[0042] In a fourth aspect, embodiments of the present application further provide a chip comprising: an input interface, an output interface, and at least one processor. Optionally, the chip further comprises a memory. The at least one processor is configured to execute code in the memory. When the at least one processor executes the code, the chip implements the method described in the first aspect or any possible implementation thereof.

[0043] Optionally, the chip may also be an integrated circuit.

[0044] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program, which includes methods for implementing the above-mentioned first aspect or any possible implementation thereof.

[0045] In a sixth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method described in the first aspect or any possible implementation thereof.

[0046] In the seventh aspect, an embodiment of the present application further provides a chip system, which includes a first chip, a second chip and the communication device described in the above second aspect or any possible implementation thereof.

[0047] Optionally, the communication device may be provided in the first chip and / or the second chip.

[0048] The communication device, computer storage medium, computer program product and chip provided in this embodiment are all used to execute the method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the method provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] FIG1 is a schematic structural diagram of a chip system provided in an embodiment of the present application;

[0051] FIG2 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0052] FIG3 is a schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0053] FIG4 is a schematic structural diagram of another chip provided in an embodiment of the present application;

[0054] FIG5 is a schematic diagram of the structure of another chip provided in an embodiment of the present application;

[0055] FIG6 is a flow chart of a communication method provided in an embodiment of the present application;

[0056] FIG7 is a schematic diagram of an access command transmission process provided by an embodiment of the present application;

[0057] FIG8 is a schematic diagram of another access command transmission process provided in an embodiment of the present application;

[0058] FIG9 is a schematic diagram of another access command transmission process provided in an embodiment of the present application;

[0059] FIG10 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0060] FIG11 is a schematic structural diagram of another communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of this application.

[0062] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0063] The terms "first" and "second" and so on in the description and drawings of the embodiments of this application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.

[0064] Furthermore, the terms "including," "having," and any variations thereof, mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or apparatus.

[0065] It should be noted that in the description of the embodiments of this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be interpreted as having priority or advantage over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0066] With technological advancements, electronic devices are entering a period of rapid development. These devices integrate multimedia, the internet, gaming, and online platforms, and their performance is increasing at an exponential rate year after year. Within these devices, chips are like the brain or heart, influencing their processing speed, power consumption, size, and cost.

[0067] As chip sizes increase, in order to cope with challenges such as high integration, multi-core processors, and process technology advancements, the technology of breaking down chips into multiple independent chip components has developed. It is very important to ensure the security of chip interconnection.

[0068] To this end, an embodiment of the present application provides a communication method for improving the security of chip interconnection. The communication method can be applied to a chip system. Figure 1 shows a possible, non-limiting schematic diagram of the above-mentioned chip system. As shown in Figure 1, the chip system 10 includes N chips and M communication devices. The above-mentioned communication device is used to execute the communication method provided in the embodiment of the present application.

[0069] What is not shown in FIG1 is that the N chips mentioned above can be interconnected via a bus.

[0070] Exemplarily, the communication device may be a through-silicon via (TSV) interface, a microbump interface, an interposer interface, a serializer and deserializer (serdes) interface (such as PCIE or USB).

[0071] It should be understood that the structure of the chip system 10 shown in FIG1 does not constitute a specific limitation on the chip system 10. In other embodiments of the present application, the chip system 10 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0072] Figure 2 shows a possible, non-limiting schematic diagram of the chip. As shown in Figure 2, the chip may include multiple processor cores, memories, and multiple peripherals.

[0073] Exemplarily, the aforementioned multiple processor cores may be configured as a master or a non-master (eg, a slave device).

[0074] Exemplarily, the above-mentioned processor core can be a central processing unit (CPU) core, an application processor (AP) core, a modem processor core, a graphics processing unit (GPU) core, an image signal processor (ISP) core, a video codec core, a digital signal processor (DSP) core, a baseband processor core, a neural-network processing unit (NPU) core or other processor cores.

[0075] Exemplarily, the above-mentioned multiple peripherals may include peripheral component interconnect express (PCIE), universal serial bus (USB), high definition multimedia interface (HDMI), display port (DP) or registered jack 45 (RJ45) or other peripherals.

[0076] It is understood that the structure of the chip shown in FIG2 does not constitute a specific limitation on the chip. In other embodiments of the present application, the chip may include more or fewer components than shown, or combine or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware. For example, the above chip may also include one or more firewall modules.

[0077] In combination with FIG2 , as shown in FIG3 , in a possible implementation, the communication device may be provided in the chip.

[0078] For example, each chip may be provided with one or more communication devices.

[0079] As shown in FIG4 in combination with FIG2 , in a possible implementation, the multiple processor cores may be configured as a secure master (trust execution environment master, TEE master) and a non-secure master (rich execution environment master, REE master).

[0080] The secure master and the non-secure master may be set by the user or determined in other ways, which is not limited in the embodiments of the present application.

[0081] In combination with FIG2 , as shown in FIG4 , in a possible implementation, the storage space of the above-mentioned memory may be configured as a secure storage area (TEE Storage) and a non-secure storage area (REE Storage).

[0082] Among them, the secure storage area and the non-secure storage area can be set by the user or determined according to other methods, and the embodiments of the present application are not limited to this.

[0083] In combination with FIG2 , as shown in FIG4 , in a possible implementation, the plurality of peripherals may be configured as secure peripherals (TEE Peri) and non-secure peripherals (REE Peri).

[0084] Among them, the secure peripheral area and the non-secure peripheral area can be set by the user or determined according to other methods, and the embodiments of the present application do not limit this.

[0085] In combination with FIG4 , as shown in FIG5 , the above-mentioned secure peripherals may constitute a secure peripheral area.

[0086] In combination with FIG4 , as shown in FIG5 , the above-mentioned non-secure peripherals may constitute a non-secure peripheral area.

[0087] 4 , as shown in FIG5 , the secure peripheral area and the secure storage area may constitute a secure area.

[0088] In combination with FIG4 , as shown in FIG5 , the non-secure peripheral area and the non-secure storage area may constitute a non-secure area.

[0089] FIG6 shows a communication method provided by an embodiment of the present application. As shown in FIG6 , the method includes:

[0090] S501: Receive an access command from a master of a first chip.

[0091] Exemplarily, the master of the first chip may send an access command to the communication device, and correspondingly, the communication device receives the access command from the master of the first chip.

[0092] For example, the security master of the first chip may send an access command to the communication device.

[0093] For another example, the non-secure master of the first chip may send an access command to the communication device.

[0094] It can be understood that in the embodiments of the present application, "sending information to... (e.g., a communication device)" or the related illustrations in the accompanying drawings can be understood as the destination end of the information being the communication device. It can include sending information directly or indirectly to the communication device. "Receiving information from... (e.g., a communication device)" or "receiving information from... (e.g., a communication device)", or the related illustrations in the accompanying drawings can be understood as the source end of the information being the communication device, which can include receiving information directly or indirectly from the communication device. The information may be processed as necessary between the source end and the destination end of the information transmission, such as format changes, etc., but the destination end can understand the valid information from the source end. Similar expressions in the embodiments of the present application can be understood similarly and will not be repeated here.

[0095] The access command may include identification information and an access address. The first chip is any chip in the chip system, and the second chip is a chip connected to the first chip.

[0096] Exemplarily, the identification information may be a master identity document (master ID).

[0097] The identification information is used to indicate the master in the first chip that sends the access command, that is, to indicate which master in the first chip sends the access command.

[0098] In a possible implementation, the communication device may be provided at the source end, that is, the communication device may be provided in the first chip.

[0099] Exemplarily, the master of the first chip may send an access command to the communication device of the first chip, and correspondingly, the communication device of the first chip receives the access command from the master of the first chip.

[0100] In a possible implementation, the communication device may also be provided at the destination end, that is, the communication device may be provided in the second chip.

[0101] For example, the master of the first chip may send an access command to the communication device of the second chip, and correspondingly, the communication device of the second chip receives the access command from the master of the first chip.

[0102] In a possible implementation, the communication device may also obtain a key.

[0103] In a possible implementation, the communication device may receive an encrypted access command, and decrypt the encrypted access command according to a key to obtain the above access command.

[0104] The encryption method of the access command may adopt any encryption method that can be thought of by a person skilled in the art, and the embodiment of the present application does not limit this.

[0105] S502: Send an access command to the secure area or the non-secure area of ​​the second chip according to the configuration information.

[0106] Exemplarily, the communication device of the first chip sends the access command to the secure area or the non-secure area of ​​the second chip according to the configuration information of the second chip.

[0107] As another example, the communication device of the first chip sends the access command to the secure area or the non-secure area of ​​the second chip according to the configuration information of the second chip.

[0108] Among them, the above-mentioned configuration information includes first information and second information. The above-mentioned first information is used to characterize the correspondence between identification information and security type, and the above-mentioned second information is used to characterize the correspondence between access address and address type. The above-mentioned security type includes secure master and non-secure master, and the above-mentioned address type includes secure area and non-secure area.

[0109] For example, as shown in Table 1, the identification information corresponding to the secure master is A1 to A4, and the identification information corresponding to the non-secure master is B1 to B4. That is, access commands with identification information A1 to A4 are access commands from the secure master, and access commands with identification information B1 to B4 are access commands from the non-secure master.

[0110] Table 1

[0111] For example, as shown in Table 2, the access addresses corresponding to the secure area are C1 to C4, and the identification information corresponding to the non-secure area is D1 to D4. That is, the access commands with access addresses C1 to C4 are used to access the secure area, and the access commands with access addresses D1 to D4 are used to access the non-secure area.

[0112] Table 2

[0113] In a possible implementation, the access command may be sent to the secure area of ​​the second chip when the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a secure area.

[0114] Exemplarily, as shown in FIG7 , when the identification information of the access command 1 corresponds to the secure master and the access address of the access command 1 corresponds to the secure zone, the communication device sends the access command 1 to the secure zone of the second chip.

[0115] For example, if the access command's identification information is A1 and the access address is C2, Table 1 shows that identification information A1 corresponds to the secure master, and Table 2 shows that access address C2 corresponds to the secure zone. Because identification information A1 corresponds to the secure master and access address C2 corresponds to the secure zone, the access command can be sent to the secure zone of the second chip.

[0116] In a possible implementation, the access command may be sent to the non-secure area of ​​the second chip when the identification information of the access command corresponds to the non-secure master and the access address of the access command corresponds to the non-secure area.

[0117] Exemplarily, as shown in FIG8 , the communication device sends access command 2 to the non-secure area of ​​the second chip when the identification information of access command 2 corresponds to the non-secure master and the access address of access command 2 corresponds to the non-secure area.

[0118] For example, if the identification information of the access command is B2 and the access address of the access command is D1, Table 1 shows that the identification information B2 corresponds to the non-secure master, and Table 2 shows that the access address D1 corresponds to the non-secure area. Because the identification information B2 corresponds to the non-secure master and the access address D1 corresponds to the non-secure area, the access command can be sent to the non-secure area of ​​the second chip.

[0119] In a possible implementation, third information may be sent to the first chip according to the configuration information, where the third information is used to indicate that the access command has failed authentication.

[0120] Exemplarily, the third information may be sent to the first chip when the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a non-secure area, or when the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a secure area.

[0121] As shown in Figure 9, the communication device sends the above-mentioned third information to the above-mentioned first chip when the identification information of the access command 3 corresponds to the secure master and the access address of the access command 3 corresponds to the non-secure area, or when the identification information of the access command 3 corresponds to the non-secure master and the access address of the access command 3 corresponds to the secure area.

[0122] For example, if the access command's identification information is A1 and the access address is D2, Table 1 shows that identification information A1 corresponds to the secure master, and Table 2 shows that access address D2 corresponds to the non-secure area. Because identification information A1 corresponds to the secure master and access address D2 corresponds to the non-secure area, a third message can be sent to the first chip to inform it that the access command failed authentication, meaning that the secure master does not have access to the non-secure area.

[0123] For another example, the identification information of the access command is B2, and the access address of the access command is C1. Table 1 shows that identification information B2 corresponds to the non-secure master, and Table 2 shows that access address C1 corresponds to the secure zone. Because identification information B2 corresponds to the non-secure master and access address C1 corresponds to the secure zone, a third message can be sent to the first chip to inform it that the access command failed authentication, meaning that the non-secure master does not have access to the secure zone.

[0124] It is understandable that the above authentication refers to determining whether the security type matches the address type.

[0125] For example, a security master has access rights to the security zone but not to the non-security zone. If the security type in the access command is security master, authentication is successful if the address type in the access command is in the security zone. However, authentication fails if the address type in the access command is in the non-security zone.

[0126] For example, a non-secure master has access rights to the non-secure zone but not to the secure zone. If the security type in the access command is non-secure master, authentication is successful if the address type in the access command is in the non-secure zone. However, authentication fails if the address type in the access command is in the secure zone.

[0127] In a possible implementation, the secure area may include a secure storage area and a secure peripheral area.

[0128] In one possible implementation, the non-secure area includes a non-secure storage area and a non-secure peripheral area.

[0129] For example, as shown in Table 3, it can be seen that the access addresses corresponding to the secure storage area are C1-C2, the access addresses corresponding to the secure peripheral area are C3-C4, the identification information corresponding to the non-secure storage area is D1-D2, and the identification information corresponding to the non-secure peripheral area is D3-D4. That is, the access commands with access addresses C1-C2 are used to access the secure storage area, the access commands with access addresses C3-C4 are used to access the secure peripheral area, the access commands with access addresses D1-D2 are used to access the non-secure storage area, and the access commands with access addresses D3-D4 are used to access the non-secure peripheral area.

[0130] Table 3

[0131] In a possible implementation, when the access address of the access command corresponds to a secure storage area, the access command may be sent to the secure storage of the second chip.

[0132] For example, if the identification information of the access command is A1 and the access address of the access command is C2, Table 1 shows that identification information A1 corresponds to the secure master, and Table 3 shows that access address C2 corresponds to the secure storage area. Because identification information A1 corresponds to the secure master and access address C2 corresponds to the secure storage area, the access command can be sent to the secure storage area of ​​the second chip. Accordingly, the secure storage area of ​​the second chip can execute the access command.

[0133] In a possible implementation, when the access address of the access command corresponds to the secure peripheral area, the access command may be sent to the secure peripheral area of ​​the second chip.

[0134] For example, if the access command's identification information is A1 and its access address is C3, Table 1 shows that identification information A1 corresponds to the secure master, and Table 3 shows that access address C3 corresponds to the secure peripheral area. Because identification information A1 corresponds to the secure master and access address C3 corresponds to the secure peripheral area, the access command can be sent to the secure peripheral area of ​​the second chip. Accordingly, the secure peripheral area of ​​the second chip can execute the access command.

[0135] In a possible implementation, when the access address of the access command corresponds to a non-secure storage area, the access command may be sent to the non-secure storage of the second chip.

[0136] For example, if the identification information of the access command is B2 and the access address of the access command is D1, Table 1 shows that the identification information B2 corresponds to the non-secure master, and Table 3 shows that the access address D1 corresponds to the non-secure storage area. Because the identification information B2 corresponds to the non-secure master and the access address D1 corresponds to the non-secure storage area, the access command can be sent to the non-secure storage area of ​​the second chip. Accordingly, the non-secure storage area of ​​the second chip can execute the access command.

[0137] In a possible implementation, when the access address of the access command corresponds to the non-secure peripheral area, the access command may be sent to the non-secure peripheral area of ​​the second chip.

[0138] For example, if the identification information of the access command is B2 and the access address of the access command is D3, comparing Table 1 shows that the identification information B2 corresponds to the non-secure master, and comparing Table 3 shows that the access address D3 corresponds to the non-secure peripheral area. Because the identification information B2 corresponds to the non-secure master and the access address D1 corresponds to the non-secure peripheral area, the access command can be sent to the non-secure peripheral area of ​​the second chip. Accordingly, the non-secure peripheral area of ​​the second chip can execute the access command.

[0139] In a possible implementation, the first information is further used to characterize the correspondence between the identification information and the access device.

[0140] For example, as shown in Table 4, it can be seen that the identification information of secure master 1 is A1, the identification information of secure master 2 is A2, the identification information of secure master 3 is A3, the identification information of secure master 4 is A4, the identification information of non-secure master 1 is B1, the identification information of non-secure master 2 is B2, the identification information of non-secure master 3 is B3, and the identification information of non-secure master 4 is B4. That is, the access command with identification information A1 comes from secure master 1, the access command with identification information A2 comes from secure master 2, the access command with identification information A3 comes from secure master 3, the access command with identification information A4 comes from secure master 4, the access command with identification information B1 comes from non-secure master 1, the access command with identification information B2 comes from non-secure master 2, the access command with identification information B3 comes from non-secure master 3, and the access command with identification information B4 comes from non-secure master 4.

[0141] Table 4

[0142] In a possible implementation, the second information is further used to represent the correspondence between the access address and the access object.

[0143] For example, as shown in Table 5, it can be seen that the access address corresponding to the secure storage area 1 is C1, the access address corresponding to the secure storage area 2 is C2, the access address corresponding to the secure peripheral area 1 is C3, the access address corresponding to the secure peripheral area 2 is C4, the access address corresponding to the non-secure storage area 1 is D1, the access address corresponding to the non-secure storage area 2 is D2, the access address corresponding to the non-secure peripheral area 1 is D3, and the access address corresponding to the non-secure peripheral area 2 is D4. That is, the access command with the access address C1 is used to access the secure storage area 1, the access command with the access address C2 is used to access the secure storage area 2, the access command with the access address C3 is used to access the secure peripheral area 1, the access command with the access address C4 is used to access the secure peripheral area 2, the access command with the access address D1 is used to access the non-secure storage area 1, the access command with the access address D2 is used to access the non-secure storage area 2, the access command with the access address D3 is used to access the non-secure peripheral area 1, and the access command with the access address D4 is used to access the non-secure peripheral area 2.

[0144] Table 5

[0145] In a possible implementation, the second information is further used to characterize the correspondence between the access object and the access device, wherein the access object can only be accessed by the corresponding access device.

[0146] For example, as shown in Table 6, it can be seen that the access device corresponding to the secure storage area 1 is secure master 1, the access device corresponding to the secure storage area 2 is secure master 2, the access device corresponding to the secure peripheral area 1 is secure master 3, and the access device corresponding to the secure peripheral area 2 is secure master 4. The access device corresponding to the non-secure storage area 1 is non-secure master 1, the access device corresponding to the non-secure storage area 2 is non-secure master 2, the access device corresponding to the non-secure peripheral area 1 is non-secure master 3, and the access device corresponding to the non-secure peripheral area 2 is non-secure master 4. In other words, the secure storage area 1 can only be accessed by the secure master 1, the secure storage area 2 can only be accessed by the secure master 2, the secure peripheral area 1 can only be accessed by the secure master 3, and the secure peripheral area 2 can only be accessed by the secure master 4. The non-secure storage area 1 can only be accessed by the non-secure master 1, the non-secure storage area 2 can only be accessed by the non-secure master 2, the non-secure peripheral area 1 can only be accessed by the non-secure master 3, and the non-secure peripheral area 2 can only be accessed by the non-secure master 4.

[0147] Table 6

[0148] It should be understood that the one-to-one correspondence between access objects and access devices in Table 6 is merely illustrative; a single access object can correspond to multiple access devices. For example, secure storage area 1 can correspond to secure master 1 and secure master 2. Secure storage area 1 can only be accessed by secure master 1 and secure master 2. Even though secure master 3 and secure master 4 are also secure masters, they cannot access secure storage area 1 because they do not correspond to secure storage area 1.

[0149] In a possible implementation, the configuration information may be received from the first chip.

[0150] Exemplarily, the first chip may send the configuration information to the communication device, and correspondingly, the communication device receives the configuration information from the first chip.

[0151] In a possible implementation, the first chip and the second chip may exchange their respective configuration information so that the two chips can recognize each other's storage, peripheral address space and other information and prepare for subsequent access.

[0152] In a possible implementation, a secure channel is established between the first chip and the second chip.

[0153] It is understandable that a secure channel is established to ensure that the interaction channel between the two chips is safe and reliable, and to prepare for subsequent data transmission.

[0154] In a possible implementation, communication between the first chip and the communication device, the second chip and the communication device, and between the first chip and the second chip may be implemented through the aforementioned secure channel.

[0155] In a possible implementation, the first chip and the second chip may be bound to a key, and the first chip and the second chip may use the key to encrypt and decrypt information (such as configuration information, access commands, etc.) sent to each other.

[0156] The following will introduce a communication device for executing the above communication method with reference to FIG10 and FIG11.

[0157] It is understandable that, in order to implement the above functions, the communication device includes hardware and / or software modules that perform the corresponding functions. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0158] In the embodiment of the present application, the communication device can be divided into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. In actual implementation, other division methods may be used.

[0159] In the case of dividing each functional module according to each function, Figure 10 shows a possible schematic diagram of the composition of the communication device involved in the above embodiment. As shown in Figure 10, the communication device 900 may include: a receiving unit 901 and a sending unit 902.

[0160] The receiving unit 901 is configured to receive an access command from a master of a first chip, wherein the access command includes identification information and an access address. The identification information is used to indicate the master in the first chip that sends the access command.

[0161] The sending unit 902 is used to send the above-mentioned access command to the secure area or non-secure area of ​​the second chip according to the configuration information. The above-mentioned configuration information includes first information and second information. The above-mentioned first information is used to characterize the correspondence between the identification information and the security type. The above-mentioned second information is used to characterize the correspondence between the access address and the address type. The above-mentioned security type includes a secure master and a non-secure master. The above-mentioned address type includes a secure area and a non-secure area.

[0162] In a possible implementation, the sending unit 902 is specifically configured to: send the access command to the secure area of ​​the second chip when the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a secure area;

[0163] In a possible implementation, the sending unit 902 is specifically configured to send the access command to the non-secure area of ​​the second chip when the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a non-secure area.

[0164] In a possible implementation, the security area includes a secure storage area and a secure peripheral area.

[0165] In a possible implementation, the sending unit 902 is specifically configured to send the access command to the secure storage of the second chip when the access address of the access command corresponds to a secure storage area.

[0166] In a possible implementation, the sending unit 902 is specifically configured to send the access command to the secure peripheral area of ​​the second chip when the access address of the access command corresponds to the secure peripheral area.

[0167] In a possible implementation, the above-mentioned secure area includes a non-secure area including a non-secure storage area and a non-secure peripheral area.

[0168] In a possible implementation, the sending unit 902 is specifically configured to send the access command to the non-secure storage of the second chip when the access address of the access command corresponds to a non-secure storage area.

[0169] In a possible implementation, the sending unit 902 is specifically configured to send the access command to the non-secure peripheral area of ​​the second chip when the access address of the access command corresponds to the non-secure peripheral area.

[0170] In a possible implementation, the sending unit 902 is further configured to send third information to the first chip according to the configuration information, where the third information is used to indicate that the access command has failed authentication.

[0171] In one possible implementation, the sending unit 902 is specifically used to send the third information to the first chip when the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a non-secure area, or when the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a secure area.

[0172] In a possible implementation, the receiving unit 901 is further configured to receive the configuration information from the first chip.

[0173] 11 shows another schematic structural diagram of a communication device 1000. The communication device 1000 includes one or more processors 1001 and an interface circuit 1002. Optionally, the communication device 1000 may further include a bus 1003.

[0174] The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above communication method can be completed by a hardware integrated logic circuit in the processor 1001 or by software instructions.

[0175] Optionally, the processor 1001 may be a general-purpose processor, a digital signal processing (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods and steps disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor.

[0176] The interface circuit 1002 can be used to send or receive data, instructions or information. The processor 1001 can use the data, instructions or other information received by the interface circuit 1002 to process it, and can send the processing completion information through the interface circuit 1002.

[0177] Optionally, the chip also includes a memory, which may include a read-only memory and a random access memory, and provides operating instructions and data to the processor. Part of the memory may also include a non-volatile random access memory (NVRAM).

[0178] Optionally, the memory stores an executable software module or a data structure, and the processor can perform corresponding operations by calling an operation instruction stored in the memory (the operation instruction may be stored in an operating system).

[0179] Optionally, the chip can be used in the communication device involved in the embodiments of the present application. Optionally, the interface circuit 1002 can be used to output the execution result of the processor 1001. Regarding the communication method provided in one or more embodiments of the present application, reference can be made to the aforementioned embodiments and will not be repeated here.

[0180] It should be noted that the corresponding functions of the processor 1001 and the interface circuit 1002 can be implemented through hardware design, software design, or a combination of hardware and software, and there is no limitation here.

[0181] An embodiment of the present application also provides a computer storage medium, which stores computer instructions. When the computer instructions are executed on a communication device, the communication device executes the above-mentioned related method steps to implement the communication method in the above-mentioned embodiment.

[0182] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, it enables the computer to execute the above-mentioned related steps to implement the communication method in the above-mentioned embodiment.

[0183] Embodiments of the present application also provide a communication device, which may specifically be a chip, integrated circuit, component, or module. Specifically, the device may include a connected processor and a memory for storing instructions, or the device may include at least one processor configured to retrieve instructions from an external memory. When the device is in operation, the processor may execute the instructions, causing the chip to perform the communication methods described in the aforementioned method embodiments.

[0184] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0185] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0186] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0187] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0188] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, and may be located in one place or distributed across multiple network units. Some or all of these units may be selected based on actual needs to achieve the objectives of this embodiment.

[0189] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0190] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the above methods of each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0191] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A communication method, characterized in that: include: receiving an access command from a master device of the first chip, the access command including identification information and an access address, the identification information being used to indicate the master in the first chip that sends the access command; The access command is sent to the secure area or non-secure area of the second chip according to the configuration information, and the configuration information includes first information and second information. The first information is used to characterize the correspondence between the identification information and the security type, and the second information is used to characterize the correspondence between the access address and the address type. The security type includes a secure master and a non-secure master, and the address type includes a secure area and a non-secure area.

2. The method according to claim 1, characterized in that The sending the access command to the secure area or the non-secure area of the second chip according to the configuration information includes: When the identification information of the access command corresponds to a security master and the access address of the access command corresponds to a security zone, sending the access command to the security zone of the second chip; In a case where the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a non-secure area, the access command is sent to the non-secure area of the second chip.

3. The method according to claim 2, characterized in that The security area includes a secure storage area and a secure peripheral area, and sending the access command to the security area of the second chip includes: When the access address of the access command corresponds to a secure storage area, sending the access command to the secure storage of the second chip; In a case where the access address of the access command corresponds to the secure peripheral area, the access command is sent to the secure peripheral area of the second chip.

4. The method according to claim 2 or 3, characterized in that The non-secure area includes a non-secure storage area and a non-secure peripheral area, and sending the access command to the non-secure area of the second chip includes: When the access address of the access command corresponds to the non-secure storage area, sending the access command to the non-secure storage of the second chip; In a case where the access address of the access command corresponds to the non-secure peripheral area, the access command is sent to the non-secure peripheral area of the second chip.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: Sending third information to the first chip according to the configuration information, where the third information is used to indicate that the access command has failed authentication.

6. The method according to claim 5, characterized in that The sending third information to the first chip according to the configuration information includes: When the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a non-secure area, or when the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a secure area, the third information is sent to the first chip.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: The configuration information is received from the first chip.

8. A communication device, characterized in that: include: a receiving unit and a sending unit; The receiving unit is configured to receive an access command from a master of the first chip, wherein the access command includes identification information and an access address, and the identification information is used to indicate the master in the first chip that sends the access command; The sending unit is used to send the access command to the secure area or non-secure area of the second chip according to the configuration information, the configuration information includes first information and second information, the first information is used to characterize the correspondence between the identification information and the security type, and the second information is used to characterize the correspondence between the access address and the address type, the security type includes a secure master and a non-secure master, and the address type includes a secure area and a non-secure area.

9. The device according to claim 8, characterized in that The sending unit is specifically configured to: When the identification information of the access command corresponds to a security master and the access address of the access command corresponds to a security zone, sending the access command to the security zone of the second chip; In a case where the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a non-secure area, the access command is sent to the non-secure area of the second chip.

10. The device according to claim 9, characterized in that The security area includes a security storage area and a security peripheral area, and the sending unit is specifically used to: When the access address of the access command corresponds to a secure storage area, sending the access command to the secure storage of the second chip; In a case where the access address of the access command corresponds to the secure peripheral area, the access command is sent to the secure peripheral area of the second chip.

11. The device according to claim 9 or 10, characterized in that The secure area includes a non-secure area including a non-secure storage area and a non-secure peripheral area, and the sending unit is specifically configured to: When the access address of the access command corresponds to the non-secure storage area, sending the access command to the non-secure storage of the second chip; In a case where the access address of the access command corresponds to the non-secure peripheral area, the access command is sent to the non-secure peripheral area of the second chip.

12. The device according to any one of claims 8 to 11, characterized in that The sending unit is further configured to: Sending third information to the first chip according to the configuration information, where the third information is used to indicate that the access command has failed authentication.

13. The device according to claim 12, characterized in that The sending unit is specifically configured to: When the identification information of the access command corresponds to a secure master and the access address of the access command corresponds to a non-secure area, or when the identification information of the access command corresponds to a non-secure master and the access address of the access command corresponds to a secure area, the third information is sent to the first chip.

14. The device according to any one of claims 8 to 13, characterized in that The receiving unit is further configured to: The configuration information is received from the first chip.

15. A communication device comprising at least one processor and a memory, characterized in that: The at least one processor executes a program or instruction stored in the memory, so that the communication device implements the method according to any one of claims 1 to 7.

16. A chip system, characterized in that: The chip system includes a first chip, a second chip, and the communication device according to any one of claims 8 to 15.

17. A chip system, characterized in that: The chip system includes a first chip and a second chip, and the first chip and / or the second chip includes the communication device according to any one of claims 8 to 15.

18. A computer-readable storage medium for storing a computer program, characterized in that: When the computer program is executed on a computer or a processor, the computer or the processor is caused to implement the method according to any one of claims 1 to 7.

19. A computer program product comprising instructions, characterized in that: When the instructions are executed on a computer or a processor, the computer or the processor is caused to implement the method according to any one of claims 1 to 7.

Images