Chip and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and provides a chip and a manufacturing method therefor, and an electronic device. A first gate dielectric layer can be used to suppress a positive drift component of a threshold voltage without affecting the gate control capability, thereby improving the BTI of a transistor. The chip comprises a transistor, and the transistor comprises a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate which are sequentially stacked. The material of the channel layer comprises an oxide semiconductor, and the channel layer is in contact with the first gate dielectric layer; the defect concentration of the material of the first gate dielectric layer is lower than the defect concentration of the material of the second gate dielectric layer, and the dielectric constant of the material of the second gate dielectric layer is greater than the dielectric constant of the material of the first gate dielectric layer.

Description

Chip and preparation method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 7, 2024, with application number 202410174392.7 and application name “Chip and its preparation method, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a chip and a preparation method thereof, and an electronic device. Background Art

[0003] With the development of advanced integrated circuit technology, new transistors that can be fabricated in back-end processes are an effective way to achieve chip miniaturization and improve chip performance. Oxide semiconductor transistors, whose channel layers include an oxide semiconductor, are a candidate for next-generation transistor technology due to their advantages such as low leakage, high mobility, high on-off ratio, low processing temperature, and ease of back-end integration.

[0004] However, reliability issues, represented by bias-temperature instability (BTI), are currently the main problems faced by oxide semiconductor transistors.

[0005] Summary of the Invention

[0006] In order to solve the above technical problems, the present application provides a chip and its preparation method, and an electronic device, which can use the first gate dielectric layer to suppress the positive drift component of the threshold voltage without affecting the gate control capability, thereby improving the BTI of the transistor.

[0007] In a first aspect, the present application provides a chip comprising a transistor, wherein the transistor comprises a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate layer stacked in sequence. The channel layer comprises an oxide semiconductor and is in contact with the first gate dielectric layer. The first gate dielectric layer has a lower defect concentration than the second gate dielectric layer, and the second gate dielectric layer has a higher dielectric constant than the first gate dielectric layer.

[0008] In the present application, on one hand, the channel layer contacts the first gate dielectric layer, and the defect concentration of the material of the first gate dielectric layer is lower than the defect concentration of the material of the second gate dielectric layer. That is, the number of defects in the first gate dielectric layer is lower than the number of defects in the second gate dielectric layer. This allows the first gate dielectric layer to suppress the positive drift component of the threshold voltage, thereby improving the BTI of the transistor. On the other hand, in addition to the first gate dielectric layer, embodiments of the present application also include a second gate dielectric layer in contact with the gate. The dielectric constant of the material of the second gate dielectric layer is greater than the dielectric constant of the material of the first gate dielectric layer. This allows the second gate dielectric layer to ensure the gate control capability of the gate.

[0009] In some possible implementations, the gap between the defect energy level of the material of the first gate dielectric layer and the conduction band electrons of the channel layer can be larger than the gap between the defect energy level of the material of the second gate dielectric layer and the conduction band electrons of the channel layer, so that the first gate dielectric layer can suppress the positive drift component of the threshold voltage, thereby improving the transistor's BTI. Alternatively, the hydrogen content of the material of the first gate dielectric layer can be lower than that of the material of the second gate dielectric layer. Due to the low hydrogen content of the first gate dielectric layer, only a small amount of hydrogen in the first gate dielectric layer in contact with the channel layer enters the channel layer as a donor and dopes with electrons in the channel layer, thereby effectively suppressing the negative drift component of the threshold voltage and improving the transistor's BTI.

[0010] The present application does not limit the hydrogen content of the material of the first gate dielectric layer, as long as the hydrogen content of the material of the first gate dielectric layer is lower than the hydrogen content of the material of the second gate dielectric layer. 20 atoms / cc.

[0011] Based on the above conditions, the material of the first gate dielectric layer includes hafnium aluminum oxide and aluminum oxide; and / or the dielectric constant of the material of the second gate dielectric layer is greater than 15, for example, the material of the second gate dielectric layer includes at least one of lanthanum oxide and hafnium dioxide.

[0012] In some possible implementations, given the high defect concentration of the second gate dielectric layer, the small gap between the conduction band electrons in the channel layer and the high hydrogen content, i.e., the second gate dielectric layer still contains significant defects that may affect the transistor's BTI, the thickness of the first gate dielectric layer can be greater than that of the second gate dielectric layer in the direction from the first gate dielectric layer to the second gate dielectric layer. This ensures that the thickness of the first gate dielectric layer is sufficient to block the second gate dielectric layer, preventing the second gate dielectric layer from capturing electrons in the channel layer, thereby improving the transistor's BTI.

[0013] For example, the thickness of the first gate dielectric layer may range from 2 nm to 50 nm, and the thickness of the second gate dielectric layer is less than that of the first gate dielectric layer. For example, the thickness of the first gate dielectric layer is 3 nm, and the thickness of the second gate dielectric layer is 2 nm.

[0014] In some possible implementations, the chip further includes a substrate, on which the transistor is disposed. The transistor further includes a first electrode and a second electrode, both of which are in contact with the channel. The first electrode is a source electrode, and the second electrode is a drain electrode; alternatively, the first electrode is a drain electrode, and the second electrode is a source electrode.

[0015] For transistors with different structures, the stacking positions of the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are different.

[0016] For example, the transistor is a bottom-gate transistor. Along the direction from the substrate toward the transistor, the gate, second gate dielectric layer, first gate dielectric layer, and channel layer are stacked in sequence. The transistor also includes a first protective layer. The first protective layer, first electrode, and second electrode are all disposed on the side of the channel layer facing away from the substrate. The first protective layer is disposed between the channel layer and the first electrode and the second electrode. The first protective layer includes first and second through-holes spaced apart. The first electrode contacts the channel layer through the first through-hole, and the second electrode contacts the channel layer through the second through-hole.

[0017] For example, the transistor is a top-gate transistor. Along the direction from the substrate toward the transistor, a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate are stacked in this order. The first and second gate dielectric layers are recessed, with the gate disposed within the recess. A first electrode and a second electrode are disposed on the channel layer and on opposite sides of the recess's sidewalls.

[0018] In another example, the transistor is a vertical transistor. A first electrode and a gate are stacked in sequence along the direction from the substrate toward the transistor. The gate includes a hollow portion, and along the sidewall away from the hollow portion, a second gate dielectric layer, a first gate dielectric layer, and a channel layer are stacked in sequence. The second electrode is disposed on the side of the channel layer facing away from the first electrode.

[0019] In this case, the chip further includes an insulating layer, and along the sidewalls away from the hollow portion, a second gate dielectric layer, a first gate dielectric layer, a channel layer, and an insulating layer are stacked in this order. That is, the insulating layer is disposed within the region enclosed by the channel. Thus, without changing the outer dimensions of the channel layer, the embodiment of the present application can reduce the thickness of the channel layer by filling the channel layer with the insulating layer, thereby improving the gate control capability of the vertical transistor.

[0020] Furthermore, the first gate dielectric layer and the second gate dielectric layer include sidewalls and a bottom, the bottom of the second gate dielectric layer contacts the first electrode, and a third through hole is opened at the bottom of the second gate dielectric layer and the first gate dielectric layer, and the channel layer contacts the first electrode through the third through hole.

[0021] In a second aspect, the present application provides an electronic device, comprising a circuit board and the chip described in the first aspect, wherein the chip is arranged on the circuit board.

[0022] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0023] In a third aspect, the present application provides a method for preparing a chip, the chip including a transistor, and the method for preparing the transistor including: forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on a substrate; the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are stacked in sequence, and the channel layer is in contact with the first gate dielectric layer; wherein the material of the channel layer includes an oxide semiconductor; the defect concentration of the material of the first gate dielectric layer is lower than the defect concentration of the material of the second gate dielectric layer, and the dielectric constant of the material of the second gate dielectric layer is greater than the dielectric constant of the material of the first gate dielectric layer.

[0024] In some possible implementations, the gap between the defect energy level of the material of the first gate dielectric layer and the conduction band electrons of the channel layer is greater than the gap between the defect energy level of the material of the second gate dielectric layer and the conduction band electrons of the channel layer; and / or, the hydrogen content in the material of the first gate dielectric layer is lower than the hydrogen content in the material of the second gate dielectric layer.

[0025] In some possible implementations, forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on a substrate includes: sequentially forming the gate, the second gate dielectric layer, the first gate dielectric layer, and the channel layer on the substrate. After forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the preparation method further includes: forming a first protective layer on the channel layer, the first protective layer including first and second through-holes spaced apart; and forming a first electrode and a second electrode on the first protective layer, the first electrode contacting the channel layer through the first through-hole, and the second electrode contacting the channel layer through the second through-hole.

[0026] In some possible implementations, a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate are formed on a substrate, including: forming a channel layer, a conductive layer, and a second protective layer on the substrate in sequence; the second protective layer includes a fourth through hole; under the protection of the second protective layer, a fifth through hole is formed in the conductive layer to obtain a first pole and a second pole, and expose the surface of the channel layer facing away from the substrate; and forming a first gate dielectric layer, a second gate dielectric layer, and a gate in sequence in the fourth through hole and the fifth through hole.

[0027] In some possible implementations, before forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on a substrate, the preparation method includes: forming a first electrode on the substrate. Forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate includes: forming the gate on the first electrode, the gate including a hollow portion, the hollow portion exposing the surface of the first electrode facing away from the substrate; sequentially forming a second gate dielectric layer, a first gate dielectric layer, and a channel layer in the hollow portion along a sidewall direction away from the hollow portion; the channel layer contacts the surface of the first electrode facing away from the substrate. After forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the preparation method further includes: forming a second electrode on the side of the channel layer facing away from the first electrode.

[0028] In some possible implementation methods, after forming a second gate dielectric layer, a first gate dielectric layer, and a channel layer in the hollow portion in sequence along the side wall direction away from the hollow portion, the preparation method also includes: filling an insulating layer in the hollow portion, and the insulating layer is located on the side of the channel layer away from the first gate dielectric layer.

[0029] In some possible implementations, a second gate dielectric layer, a first gate dielectric layer, and a channel layer are sequentially formed in the hollow portion along a side wall direction away from the hollow portion, including: a second gate dielectric layer, a first gate dielectric layer, and a sacrificial layer are sequentially formed in the hollow portion along a side wall direction away from the hollow portion, so as to protect the side wall of the first gate dielectric layer with the sacrificial layer; the first gate dielectric layer and the second gate dielectric layer include side walls and a bottom, and the bottom of the second gate dielectric layer is in contact with the first pole; the sacrificial layer covers the side walls and the bottom of the first gate dielectric layer and exposes a third through hole at the bottom of the second gate dielectric layer and the first gate dielectric layer; the sacrificial layer is removed, and the channel layer is filled in the hollow portion, and the channel layer is in contact with the first pole through the third through hole.

[0030] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic structural diagram of a transistor provided in an embodiment of the present application;

[0032] FIG2 is a schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0033] FIG3 is a schematic structural diagram of a transistor provided in an embodiment of the present application;

[0034] FIG4 a is a schematic structural diagram of a transistor provided in an embodiment of the present application;

[0035] FIG4 b is a top view of a portion of the structure of a transistor provided in an embodiment of the present application;

[0036] FIG5 is a schematic diagram of the structure of a transistor provided in an embodiment of the present application;

[0037] FIG6 is a flow chart of the preparation of a transistor provided in an embodiment of the present application;

[0038] FIG7 a is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0039] FIG7 b is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0040] FIG7 c is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0041] FIG8 is a flow chart of manufacturing a transistor according to an embodiment of the present application;

[0042] FIG9 a is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0043] FIG9 b is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0044] FIG9 c is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0045] FIG9 d is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0046] FIG10 is a flow chart of manufacturing a transistor according to an embodiment of the present application;

[0047] FIG11a is a diagram showing a process for manufacturing a transistor according to an embodiment of the present application;

[0048] FIG11 b is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0049] FIG11c is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0050] FIG11d is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0051] FIG12 is a diagram showing a process for manufacturing a transistor according to an embodiment of the present application;

[0052] FIG13a is a diagram showing the manufacturing process of a transistor provided in an embodiment of the present application;

[0053] FIG13 b is a diagram showing the preparation process of the transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0056] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0057] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0058] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0059] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a memory.

[0060] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain transistors.

[0061] For ease of explanation, the following uses a mobile phone as an example electronic device. The mobile phone may include a processor, which includes logic circuits and memory. The memory includes a storage array, a storage controller, a decoder, etc. The logic circuit can read and write data to the storage array through the storage controller and decoder. The memory includes a storage array, which includes storage cells, and the storage cells include transistors and capacitors. Of course, other devices may also include transistors, and this is not limited to this embodiment of the present application.

[0062] As mentioned in the background, with the development of advanced integrated circuit technology, new transistors that can be fabricated in back-end processes are an effective way to achieve chip miniaturization and improve chip performance. Oxide semiconductor transistors, whose channel layers include an oxide semiconductor, are a candidate for next-generation transistor technology due to their advantages such as low leakage, high mobility, high on / off ratio, low processing temperature, and ease of back-end integration.

[0063] However, reliability issues represented by BTI are the main problems currently facing oxide semiconductor transistors.

[0064] For traditional silicon-based transistors, interface defects between the channel layer and the gate dielectric layer cause the threshold voltage of the transistor to drift, which is the main reason for the BTI degradation of traditional silicon-based transistors.

[0065] For N-type oxide semiconductor transistors, gate dielectric layer and interface defects will cause the threshold voltage of the oxide semiconductor transistor to shift positively. Hydrogen (H) diffusion from the chip into the oxide semiconductor transistor for electron doping will also cause the threshold voltage of the oxide semiconductor transistor to shift negatively. These positive and negative threshold voltage shifts are the main causes of BTI degradation in oxide semiconductor transistors.

[0066] To address this issue, related technologies insert an ultrathin layer of silicon dioxide (SiO2) between the channel layer and the gate dielectric layer as a barrier layer to prevent the gate dielectric from capturing electrons in the channel layer. However, this technology does not directly reduce the number of defects in the gate dielectric layer. Therefore, relying solely on the barrier layer to block defects does not significantly improve device reliability.

[0067] Based on this, an embodiment of the present application provides a chip comprising a transistor disposed on a substrate, wherein the transistor comprises a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate. The material of the channel layer comprises an oxide semiconductor, making the transistor an oxide semiconductor transistor (hereinafter collectively referred to as a transistor). The present application suppresses the positive drift component of the threshold voltage by adding a first gate dielectric layer with a lower defect concentration, thereby improving the BTI of the transistor.

[0068] Specifically, as shown in Figures 1 to 3, the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the gate 13 are stacked in sequence. On the one hand, the channel layer 11 is in contact with the first gate dielectric layer 121, and the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 122, that is, the number of defects in the first gate dielectric layer 121 is lower than the number of defects in the second gate dielectric layer 122, so that the first gate dielectric layer 121 can be used to suppress the positive drift component of the threshold voltage, thereby improving the BTI of the transistor. On the other hand, in addition to the first gate dielectric layer 121, the embodiment of the present application also includes a second gate dielectric layer 122 in contact with the gate 13, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121, so that the second gate dielectric layer 122 can be used to ensure the gate control capability of the gate 13.

[0069] In some possible implementations, the embodiments of the present application do not limit the materials of the first gate dielectric layer 121 and the second gate dielectric layer 122. As long as the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 122, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121, it can be sufficient.

[0070] Regarding the selection of materials for the first gate dielectric layer 121 and the second gate dielectric layer 122, in addition to satisfying that the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 122, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121, the following conditions may also be met:

[0071] For example, the gap between the defect energy level of the material of the first gate dielectric layer 121 and the conduction band electrons of the channel layer 11 can be larger than the gap between the defect energy level of the material of the second gate dielectric layer 122 and the conduction band electrons of the channel layer 11, so that the first gate dielectric layer 121 can be used to suppress the positive drift component of the threshold voltage, thereby improving the transistor's BTI. Alternatively, the hydrogen content in the material of the first gate dielectric layer 121 can be lower than the hydrogen content in the material of the second gate dielectric layer 122. Due to the low hydrogen content of the first gate dielectric layer 121, only a small amount of hydrogen in the first gate dielectric layer 121 in contact with the channel layer 11 enters the channel layer 11 as a donor and dopes with electrons in the channel layer 11, thereby effectively suppressing the negative drift component of the threshold voltage and improving the transistor's BTI.

[0072] The present embodiment does not limit the hydrogen content of the material of the first gate dielectric layer 121, as long as the hydrogen content of the material of the first gate dielectric layer 121 is lower than the hydrogen content of the material of the second gate dielectric layer 122. Optionally, the hydrogen content of the material of the first gate dielectric layer 121 can be less than 1e 20 atoms / cc (number of atoms per unit volume).

[0073] Optionally, the embodiment of the present application does not limit the dielectric constant of the material of the second gate dielectric layer 122, as long as the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121. Optionally, the dielectric constant of the material of the second gate dielectric layer 122 is greater than 15.

[0074] Based on the above conditions, the material of the first gate dielectric layer 121 may include at least one of aluminum oxide (Al2O3) and hafnium aluminum oxide (HfAlO). The material of the second gate dielectric layer 122 may include at least one of lanthanum oxide (La2O3) and hafnium dioxide (HfO2).

[0075] In some possible implementations, as shown in FIG1 , given the high defect concentration of the second gate dielectric layer 122, the small gap between the conduction band electrons of the channel layer 11, and the high hydrogen content, that is, the second gate dielectric layer 122 still contains significant defects, which may affect the transistor's BTI. Therefore, along the direction from the first gate dielectric layer 121 to the second gate dielectric layer 122, the thickness of the first gate dielectric layer 121 can be greater than the thickness of the second gate dielectric layer 122, so that the thickness of the first gate dielectric layer 121 is sufficient to block the second gate dielectric layer 122, preventing the second gate dielectric layer 122 from capturing electrons in the channel layer 11, thereby improving the transistor's BTI.

[0076] For example, the thickness of the first gate dielectric layer 121 may range from 2 nm to 50 nm, and the thickness of the second gate dielectric layer 122 is less than that of the first gate dielectric layer 121. For example, the thickness of the first gate dielectric layer 121 is 3 nm, and the thickness of the second gate dielectric layer 122 is 2 nm.

[0077] In some possible implementations, the present invention does not limit the material of the channel layer 11, as long as the material of the channel layer 11 includes an oxide semiconductor. For example, the material of the channel layer 11 includes an oxide semiconductor material such as indium gallium zinc oxide (IGZO), indium gallium oxide, or indium zinc oxide.

[0078] In some possible implementations, as shown in Figures 1 to 3, in addition to the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the gate 13, the transistor also includes a first electrode 14 and a second electrode 15 in contact with the channel layer 11. The first electrode 14 is a source electrode and the second electrode 15 is a drain electrode; alternatively, the first electrode 14 is a drain electrode and the second electrode 15 is a source electrode.

[0079] For transistors with different structures, the channel layer 11 , the first gate dielectric layer 121 , the second gate dielectric layer 122 , and the gate 13 are stacked at different positions.

[0080] For example, the transistor shown in FIG1 is a bottom-gate transistor. The transistor also includes a first protective layer 21. Along the direction of the substrate 10 toward the transistor, the gate 13, the second gate dielectric layer 122, the first gate dielectric layer 121, the channel layer 11, and the first protective layer 21 are stacked in sequence. The first electrode and the second electrode are both arranged on the side of the first protective layer 21 facing away from the substrate 10. The first protective layer 21 includes a first through hole and a second through hole arranged at intervals. The first electrode 14 contacts the channel layer 11 through the first through hole, and the second electrode 15 contacts the channel layer 11 through the second through hole.

[0081] For another example, the transistor shown in FIG2 is a top-gate transistor. Along the direction of the substrate 10 toward the transistor, the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the gate 13 are stacked in sequence. The first gate dielectric layer 121 and the second gate dielectric layer 122 are groove-shaped, and the gate 13 is disposed in the groove. The first electrode 14 and the second electrode 15 are disposed on the channel layer 11 and in contact with the channel layer 11, and are located on opposite sides of the groove sidewalls, so that the first gate dielectric layer 121 and the second gate dielectric layer 122 are used to electrically isolate the first electrode 14 and the second electrode 15 from the gate 13.

[0082] For another example, the transistor shown in Figure 3 is a vertical transistor. Along the direction from the substrate 10 toward the transistor, the first electrode 14 and the gate 13 are stacked in sequence. The gate 13 includes a hollow portion, and along the sidewalls away from the hollow portion, the second gate dielectric layer 122, the first gate dielectric layer 121, and the channel layer 11 are stacked in sequence. Furthermore, the second electrode 15 is disposed on the side of the channel layer 11 facing away from the first electrode 14. That is, along the direction from the substrate 10 toward the transistor, the first electrode 14 and the second electrode 15 are disposed on opposite sides of the channel layer 11.

[0083] A first dielectric layer 31 is disposed between the first electrode 14 and the gate 13, and a second dielectric layer 32 is disposed between the second electrode 15 and the gate 13. The first dielectric layer 31 electrically isolates the first electrode 14 from the gate 13, while the second dielectric layer 32 electrically isolates the second electrode 15 from the gate 13. Furthermore, the first and second dielectric layers 31, 32 define the gate length of the gate 13. It should be understood that, in this application, the gate length of the gate 13 is defined as the direction from the first electrode 14 to the second electrode 15.

[0084] Based on the vertical transistor shown in FIG3 , as shown in FIG4 a and FIG4 b , the chip may further include an insulating layer 16. Along the sidewalls away from the hollow portion, a second gate dielectric layer 122, a first gate dielectric layer 121, a channel layer 11, and an insulating layer 16 are stacked in sequence. Specifically, the insulating layer 16 is disposed within the region enclosed by the channel 11. Thus, without changing the outer dimensions of the channel layer 11, the embodiment of the present application can reduce the thickness of the channel layer 11 by filling the channel layer 11 with the insulating layer 16, thereby improving the gate control capability of the vertical transistor.

[0085] It should be understood that the thickness direction of the channel layer 11 is the direction from the sidewall of the first gate dielectric layer 121 to the sidewall of the second gate dielectric layer 122 .

[0086] [Corrected 09.01.2025 according to Rule 91] Furthermore, based on the vertical transistor shown in FIG. 3 or FIG. 4a , as shown in FIG. 5 , the first gate dielectric layer 121 and the second gate dielectric layer 122 further include a bottom portion adjacent to the sidewalls, and the bottom portion of the second gate dielectric layer 122 contacts the first electrode 11. A third through-hole is defined in the bottom portions of the second gate dielectric layer 122 and the first gate dielectric layer 121, and the channel layer 11 contacts the first electrode 14 through the third through-hole.

[0087] Of course, the structure of the transistor can also be other, and the embodiments of the present application are not limited to this, as long as the first gate dielectric layer 121 and the second gate dielectric layer 122 are arranged between the channel layer 11 and the gate 13, and the first gate dielectric layer 121 is arranged on the side of the second gate dielectric layer 122 facing the channel layer 11, and the second gate dielectric layer 122 is arranged on the side of the first gate dielectric layer 121 facing the gate 13.

[0088] In another embodiment, the present application also provides a method for preparing a chip, the chip including a transistor, and the method for preparing the transistor including: forming a channel layer 11, a first gate dielectric layer 121, a second gate dielectric layer 122, and a first gate dielectric layer gate 13 on a substrate 10; the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the first gate dielectric layer gate 13 are stacked in sequence; wherein the material of the channel layer 11 includes an oxide semiconductor; the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 11, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121.

[0089] On the one hand, the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 122, that is, the number of defects in the first gate dielectric layer 121 in contact with the channel layer 11 is lower than the number of defects in the second gate dielectric layer 122, so that the first gate dielectric layer 121 can be used to suppress the positive drift component of the threshold voltage, thereby improving the BTI of the transistor. On the other hand, because the material of the first gate dielectric layer 121 has a lower defect concentration, its dielectric constant is generally also lower. If the dielectric constant of the first gate dielectric layer 121 is reduced, the gate control capability of the gate 13 will be affected. Therefore, in addition to the first gate dielectric layer 121, the embodiment of the present application also includes a second gate dielectric layer 122 in contact with the gate 13, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121, so that the second gate dielectric layer 122 can be used to ensure the gate control capability of the gate 13.

[0090] In some possible implementations, the embodiments of the present application do not limit the materials of the first gate dielectric layer 121 and the second gate dielectric layer 122. As long as the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 122, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121, it can be sufficient.

[0091] Regarding the selection of materials for the first gate dielectric layer 121 and the second gate dielectric layer 122, in addition to satisfying that the defect concentration of the material of the first gate dielectric layer 121 is lower than the defect concentration of the material of the second gate dielectric layer 122, and the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121, the following conditions may also be met:

[0092] For example, the gap between the defect energy level of the material of the first gate dielectric layer 121 and the conduction band electrons of the channel layer 11 can be larger than the gap between the defect energy level of the material of the second gate dielectric layer 122 and the conduction band electrons of the channel layer 11, so that the first gate dielectric layer 121 can be used to suppress the positive drift component of the threshold voltage, thereby improving the transistor's BTI. Alternatively, the hydrogen content in the material of the first gate dielectric layer 121 can be lower than the hydrogen content in the material of the second gate dielectric layer 122. Due to the low hydrogen content of the first gate dielectric layer 121, only a small amount of hydrogen in the first gate dielectric layer 121 in contact with the channel layer 11 enters the channel layer 11 as a donor and dopes with electrons in the channel layer 11, thereby effectively suppressing the negative drift component of the threshold voltage and improving the transistor's BTI.

[0093] The present embodiment does not limit the hydrogen content of the material of the first gate dielectric layer 121, as long as the hydrogen content of the material of the first gate dielectric layer 121 is lower than the hydrogen content of the material of the second gate dielectric layer 122. Optionally, the hydrogen content of the material of the first gate dielectric layer 121 can be less than 1e 20 atoms / cc (number of atoms per unit volume).

[0094] Optionally, the embodiment of the present application does not limit the dielectric constant of the material of the second gate dielectric layer 122, as long as the dielectric constant of the material of the second gate dielectric layer 122 is greater than the dielectric constant of the material of the first gate dielectric layer 121. Optionally, the dielectric constant of the second gate dielectric layer 122 is greater than 15.

[0095] Based on the above conditions, the material of the first gate dielectric layer 121 may include at least one of Al 2 O 3 and HfAlO, and the material of the second gate dielectric layer 122 may include at least one of La 2 O 3 and HfO 2 .

[0096] In some possible implementations, as shown in FIG1 , given the high defect concentration of the second gate dielectric layer 122, the small gap between the conduction band electrons of the channel layer 11, and the high hydrogen content, that is, the second gate dielectric layer 122 still contains significant defects, which may affect the transistor's BTI. Therefore, along the direction from the first gate dielectric layer 121 to the second gate dielectric layer 122, the thickness of the first gate dielectric layer 121 can be greater than the thickness of the second gate dielectric layer 122, so that the thickness of the first gate dielectric layer 121 is sufficient to block the second gate dielectric layer 122, preventing the second gate dielectric layer 122 from capturing electrons in the channel layer 11, thereby improving the transistor's BTI.

[0097] For example, the thickness of the first gate dielectric layer 121 may range from 2 nm to 50 nm, and the thickness of the second gate dielectric layer 122 is less than that of the first gate dielectric layer 121. For example, the thickness of the first gate dielectric layer 121 is 3 nm, and the thickness of the second gate dielectric layer 122 is 2 nm.

[0098] In some possible implementations, as shown in Figures 1 to 3, in addition to the channel layer 11, the first gate dielectric layer 121, the second gate dielectric layer 122, and the gate 13, the transistor also includes a first electrode 14 and a second electrode 15 in contact with the channel layer 11. The first electrode 14 is a source electrode and the second electrode 15 is a drain electrode; alternatively, the first electrode 14 is a drain electrode and the second electrode 15 is a source electrode.

[0099] For transistors with different structures, the manufacturing processes of the transistors are different. The manufacturing processes of the following three transistors are described below with reference to the accompanying drawings.

[0100] The first type is a bottom-gate transistor, as shown in Figure 6, which can be implemented by the following steps:

[0101] S110 , as shown in FIG. 7 a - FIG. 7 b , a gate 13 , a second gate dielectric layer 122 , a first gate dielectric layer 121 , and a channel layer 11 are sequentially formed on the substrate 10 .

[0102] In some possible implementations, the embodiments of the present application do not limit the material of the substrate 10. Optionally, a stack of silicon and silicon dioxide can be used as the substrate 10. Of course, the material of the substrate 10 can also include other materials such as glass that can be used for oxide semiconductor deposition.

[0103] In some possible implementations, the present embodiment does not limit the material of the gate 13, as long as the gate 13 is conductive. Optionally, the gate 13 may include tungsten, titanium nitride, nickel, indium tin oxide, etc.

[0104] S120 , as shown in FIG7 c , a first protection layer 21 is formed on the channel layer 11 , wherein the first protection layer 21 includes first through holes and second through holes that are spaced apart.

[0105] In some possible implementations, the material of the first protective layer 21 may include silicon dioxide, aluminum oxide, hafnium oxide, and other materials with an insulating effect.

[0106] S130 , as shown in FIG1 , a first electrode 14 and a second electrode 15 are formed on the first protection layer 21 , wherein the first electrode 14 contacts the channel layer 11 through the first through hole, and the second electrode 15 contacts the channel layer 11 through the second through hole.

[0107] In some possible implementations, the materials of the first electrode 14 and the second electrode 15 may be the same, both including conductive materials such as tungsten, titanium nitride, nickel, and indium tin oxide.

[0108] The second type is a top-gate transistor, as shown in FIG8 , which can be implemented by the following steps:

[0109] S210, as shown in FIG9a-FIG9b, a channel layer 11, a conductive layer 141, and a second protective layer 22 are sequentially formed on the substrate 10. The second protective layer 22 includes a fourth through hole.

[0110] In some possible implementations, the embodiments of the present application do not limit the material of the substrate 10. Optionally, a stack of silicon and silicon dioxide can be used as the substrate 10. Of course, the material of the substrate 10 can also include other materials such as glass that can be used for oxide semiconductor deposition.

[0111] In some possible implementations, the embodiment of the present application does not limit the material of the conductive layer 141. Optionally, the material of the conductive layer 141 may include conductive materials such as tungsten, titanium nitride, nickel, and indium tin oxide.

[0112] S220 , as shown in FIG9 c , under the protection of the second protection layer 22 , a fifth through hole is formed in the conductive layer 141 to obtain the first electrode 14 and the second electrode 15 , and to expose the surface of the channel layer 11 facing away from the substrate 10 .

[0113] In some possible implementations, the material of the second protective layer 22 may include silicon dioxide, aluminum oxide, hafnium oxide, and other materials with an insulating effect.

[0114] S230 , as shown in FIG2 , sequentially forming a first gate dielectric layer 121 , a second gate dielectric layer 122 , and a gate electrode 13 in the fourth through hole and the fifth through hole so that the first gate dielectric layer 121 can contact the channel layer 11 .

[0115] In some possible implementations, the present embodiment does not limit the material of the gate 13, as long as the gate 13 is conductive. Optionally, the gate 13 may include tungsten, titanium nitride, nickel, indium tin oxide, etc.

[0116] In addition, as shown in Figure 9d, after forming the gate 13, the method for preparing the transistor may further include: sequentially forming a third protective layer 23 and a conductive lead 40 on the side of the gate 13 facing away from the substrate 10, and the conductive lead 40 is electrically connected to the first electrode 14 and the second electrode 15 respectively through through holes in the third protective layer 23, the second protective layer 22, etc.

[0117] The third method is to use a vertical transistor. As shown in Figure 10, this can be achieved by the following steps:

[0118] S310 , as shown in FIG. 11 a , a first electrode 14 is formed on the substrate 10 .

[0119] In some possible implementations, the embodiments of the present application do not limit the material of the substrate 10. Optionally, a stack of silicon and silicon dioxide can be used as the substrate 10. Of course, the material of the substrate 10 can also include other materials such as glass that can be used for oxide semiconductor deposition.

[0120] S320 , as shown in FIG11 b , a gate electrode 13 is formed on the first electrode 14 . The gate electrode 13 includes a hollow portion, and the hollow portion exposes a surface of the first electrode 14 facing away from the substrate 10 .

[0121] In some possible implementations, a first dielectric layer 31 is further provided between the first electrode 14 and the gate 13 . On the one hand, the first dielectric layer 31 is used to electrically isolate the first electrode 14 from the gate 13 ; on the other hand, the first dielectric layer 31 is also used to define the gate length of the gate 13 .

[0122] In some possible implementations, the present embodiment does not limit the material of the gate 13, as long as the gate 13 is conductive. Optionally, the gate 13 may include tungsten, titanium nitride, nickel, indium tin oxide, etc.

[0123] S330 , as shown in FIG11 c - FIG11 d , a second gate dielectric layer 122 , a first gate dielectric layer 121 , and a channel layer 11 are sequentially formed in the hollow portion along the sidewall direction away from the hollow portion.

[0124] S340 , as shown in FIG3 , forming the second electrode 15 on the side of the channel layer 11 away from the first electrode 14 .

[0125] In some possible implementations, a second dielectric layer 32 is further provided between the second electrode 15 and the gate 13 . On the one hand, the second dielectric layer 32 is used to electrically isolate the second electrode 15 from the gate 13 ; on the other hand, the second dielectric layer 32 is also used to define the gate length of the gate 13 .

[0126] In some possible implementations, the materials of the first electrode 14 and the second electrode 15 may be the same, both including conductive materials such as tungsten, titanium nitride, nickel, and indium tin oxide.

[0127] In some embodiments, for the third case, there are other structural deformations.

[0128] The first deformation structure, its preparation process includes:

[0129] S310 , as shown in FIG. 11 a , a first electrode 14 is formed on the substrate 10 .

[0130] S320 , as shown in FIG11 b , a gate electrode 13 is formed on the first electrode 14 . The gate electrode 13 includes a hollow portion, and the hollow portion exposes a surface of the first electrode 14 facing away from the substrate 10 .

[0131] S331, as shown in FIG12, forms a second gate dielectric layer 122, a first gate dielectric layer 121, a channel layer 11, and an insulating layer 16 in the hollow portion in sequence along the sidewall direction away from the hollow portion. Specifically, the insulating layer 16 is disposed within the region enclosed by the channel 11. Thus, without changing the outer dimensions of the channel layer 11, the embodiment of the present application can reduce the thickness of the channel layer 11 by filling the channel layer 11 with the insulating layer 16, thereby improving the gate control capability of the vertical transistor. The channel layer 11 is in contact with the first electrode 14.

[0132] S340 , as shown in FIG4 a , forming a second electrode 15 on a side of the channel layer 11 away from the first electrode 14 .

[0133] The second deformation structure, its preparation process includes:

[0134] S310 , as shown in FIG. 11 a , a first electrode 14 is formed on the substrate 10 .

[0135] S320 , as shown in FIG11 b , a gate electrode 13 is formed on the first electrode 14 . The gate electrode 13 includes a hollow portion, and the hollow portion exposes a surface of the first electrode 14 facing away from the substrate 10 .

[0136] S332, as shown in FIG13a, a second gate dielectric layer 122, a first gate dielectric layer 121, and a sacrificial layer 50 are sequentially formed in the hollow portion along the sidewall direction away from the hollow portion, so that the sidewall of the first gate dielectric layer 121 is protected by the sacrificial layer 50. The first gate dielectric layer 121 and the second gate dielectric layer 122 include sidewalls and a bottom, and the bottom of the second gate dielectric layer 122 is in contact with the first electrode 14. The sacrificial layer 50 covers the sidewalls and bottom of the first gate dielectric layer 121 and the second gate dielectric layer 122, and exposes the third through hole at the bottom of the second gate dielectric layer 122 and the first gate dielectric layer 121.

[0137] S333 , as shown in FIG13 b , the sacrificial layer 50 is removed, and the channel layer 11 is filled in the hollow portion, and the channel layer 11 is in contact with the first electrode 14 through the third through hole.

[0138] On this basis, as shown in FIG13b , after forming the channel layer 11, an insulating layer 16 may be further filled in the hollowed portion. That is, the insulating layer 16 is disposed within the region enclosed by the channel 11. Thus, without changing the outer dimensions of the channel layer 11, the embodiment of the present application can reduce the thickness of the channel layer 11 by filling the channel layer 11 with the insulating layer 16, thereby improving the gate control capability of the vertical transistor.

[0139] S340 , as shown in FIG5 , forming the second electrode 15 on the side of the channel layer 11 away from the first electrode 14 .

[0140] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as those of the previous embodiment and will not be repeated here.

[0141] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip, characterized in that: A transistor comprising a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate layer stacked in sequence; The material of the channel layer includes an oxide semiconductor, and the channel layer is in contact with the first gate dielectric layer; the defect concentration of the material of the first gate dielectric layer is lower than the defect concentration of the material of the second gate dielectric layer, and the dielectric constant of the material of the second gate dielectric layer is greater than the dielectric constant of the material of the first gate dielectric layer.

2. The chip according to claim 1, characterized in that The gap between the defect energy level of the material of the first gate dielectric layer and the conduction band electrons of the channel layer is greater than the gap between the defect energy level of the material of the second gate dielectric layer and the conduction band electrons of the channel layer; and / or the hydrogen content in the material of the first gate dielectric layer is lower than the hydrogen content in the material of the second gate dielectric layer.

3. The chip according to claim 2, characterized in that The hydrogen content in the material of the first gate dielectric layer is less than 1e 20 atoms / cc.

4. The chip according to any one of claims 1 to 3, characterized in that The material of the first gate dielectric layer includes hafnium aluminum oxide and aluminum oxide; and / or the dielectric constant of the second gate dielectric layer is greater than 15.

5. The chip according to any one of claims 1 to 4, characterized in that: Along a direction from the first gate dielectric layer to the second gate dielectric layer, a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.

6. The chip according to any one of claims 1 to 5, characterized in that: The chip further includes a substrate, and the transistor is arranged on the substrate; The transistor further includes a first electrode and a second electrode, wherein both the first electrode and the second electrode are in contact with the channel.

7. The chip according to claim 6, characterized in that Along the direction from the substrate to the transistor, the gate, the second gate dielectric layer, the first gate dielectric layer, and the channel layer are stacked in sequence; The transistor further includes a first protective layer, wherein the first protective layer, the first electrode, and the second electrode are all arranged on a side of the channel layer away from the substrate, and the first protective layer is arranged between the channel layer and the first electrode and the second electrode; The first protection layer includes a first through hole and a second through hole that are spaced apart. The first electrode contacts the channel layer through the first through hole, and the second electrode contacts the channel layer through the second through hole.

8. The chip according to claim 6, characterized in that Along the direction from the substrate to the transistor, the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are stacked in sequence; The first gate dielectric layer and the second gate dielectric layer are in a groove shape, and the gate is arranged in the groove; the first electrode and the second electrode are arranged on the channel layer and are located on opposite sides of the groove sidewalls.

9. The chip according to claim 6, characterized in that Along the direction from the substrate to the transistor, the first electrode and the gate are stacked in sequence; The gate includes a hollow portion, and along a sidewall direction away from the hollow portion, the second gate dielectric layer, the first gate dielectric layer, and the channel layer are stacked in sequence; the second electrode is arranged on a side of the channel layer away from the first electrode.

10. The chip according to claim 6, characterized in that The chip further includes an insulating layer. Along a sidewall direction away from the hollow portion, the second gate dielectric layer, the first gate dielectric layer, the channel layer, and the insulating layer are stacked in sequence.

11. The chip according to claim 9 or 10, characterized in that: The first gate dielectric layer and the second gate dielectric layer include sidewalls and a bottom, and the bottom of the second gate dielectric layer is in contact with the first electrode; A third through hole is formed at the bottom of the second gate dielectric layer and the first gate dielectric layer, and the channel layer is in contact with the first electrode through the third through hole.

12. An electronic device, characterized in that: The device comprises a circuit board and the chip according to any one of claims 1 to 11, wherein the chip is arranged on the circuit board.

13. A method for preparing a chip, characterized in that: The chip includes a transistor, and a method for preparing the transistor includes: A channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate are formed on a substrate; the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate are stacked in sequence, and the channel layer is in contact with the first gate dielectric layer; wherein the material of the channel layer includes an oxide semiconductor; the defect concentration of the material of the first gate dielectric layer is lower than the defect concentration of the material of the second gate dielectric layer, and the dielectric constant of the material of the second gate dielectric layer is greater than the dielectric constant of the material of the first gate dielectric layer.

14. The preparation method according to claim 13, characterized in that The gap between the defect energy level of the material of the first gate dielectric layer and the conduction band electrons of the channel layer is greater than the gap between the defect energy level of the material of the second gate dielectric layer and the conduction band electrons of the channel layer; and / or, The hydrogen content in the material of the first gate dielectric layer is lower than the hydrogen content in the material of the second gate dielectric layer.

15. The preparation method according to claim 13 or 14, characterized in that: The step of forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on a substrate includes: forming the gate, the second gate dielectric layer, the first gate dielectric layer, and the channel layer on the substrate in sequence; After forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the preparation method further includes: forming a first protective layer on the channel layer, wherein the first protective layer includes a first through hole and a second through hole that are spaced apart; A first electrode and a second electrode are formed on the first protection layer, wherein the first electrode contacts the channel layer through the first through-hole, and the second electrode contacts the channel layer through the second through-hole.

16. The preparation method according to claim 13 or 14, characterized in that: The step of forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on a substrate includes: forming the channel layer, the conductive layer, and the second protective layer on the substrate in sequence; wherein the second protective layer includes a fourth through hole; Under the protection of the second protective layer, forming a fifth through hole in the conductive layer to obtain a first electrode and a second electrode, and exposing a surface of the channel layer facing away from the substrate; The first gate dielectric layer, the second gate dielectric layer, and the gate are sequentially formed in the fourth through hole and the fifth through hole.

17. The preparation method according to claim 13 or 14, characterized in that: Before forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the preparation method includes: forming a first electrode on the substrate; The step of forming a channel layer, a first gate dielectric layer, a second gate dielectric layer, and a gate on a substrate includes: forming a gate on the first electrode, wherein the gate includes a hollow portion, and the hollow portion exposes a surface of the first electrode facing away from the substrate; forming a second gate dielectric layer, a first gate dielectric layer, and a channel layer in the hollow portion in sequence along a sidewall direction away from the hollow portion; the channel layer is in contact with a surface of the first electrode facing away from the substrate; After forming the channel layer, the first gate dielectric layer, the second gate dielectric layer, and the gate on the substrate, the preparation method further includes: A second electrode is formed on a side of the channel layer away from the first electrode.

18. The preparation method according to claim 17, characterized in that: After sequentially forming the second gate dielectric layer, the first gate dielectric layer, and the channel layer in the hollow portion along the sidewall direction away from the hollow portion, the preparation method further includes: An insulating layer is filled in the hollow portion, and the insulating layer is located on a side of the channel layer away from the first gate dielectric layer.

19. The preparation method according to claim 17 or 18, characterized in that: The method of sequentially forming a second gate dielectric layer, a first gate dielectric layer, and a channel layer in the hollow portion along a sidewall direction away from the hollow portion includes: A second gate dielectric layer, a first gate dielectric layer, and a sacrificial layer are sequentially formed in the hollow portion along a sidewall direction away from the hollow portion; the first gate dielectric layer and the second gate dielectric layer include sidewalls and a bottom, and the bottom of the second gate dielectric layer is in contact with the first electrode; the sacrificial layer covers the sidewalls and the bottom of the first gate dielectric layer and the second gate dielectric layer, and exposes a third through hole at the bottom of the second gate dielectric layer and the first gate dielectric layer; The sacrificial layer is removed, and a channel layer is filled in the hollow portion, wherein the channel layer is in contact with the first electrode through the third through hole.

Images