Level shift circuit and level shift device

Abstract

The present application relates to a level shift circuit and a level shift device. The level shift circuit comprises a signal output module and a control module; the signal output module comprises a triode; a high-voltage end of the triode is used for receiving a power supply voltage; a low-voltage end of the triode is used for outputting a shift signal; a base of the triode is used for receiving a first control signal; the control module comprises a junction field-effect transistor and an insulated-gate field-effect transistor; a drain of the junction field-effect transistor is connected to the base of the triode and used for outputting the first control signal; the gate of the junction field-effect transistor is grounded; a source of the junction field-effect transistor is connected to a drain of the insulated-gate field-effect transistor; a gate of the insulated-gate field-effect transistor is used for receiving a second control signal; and a source of the insulated-gate field-effect transistor is grounded. According to the level shift circuit of the present application, the power consumption of the level shift circuit during working can be reduced.

Description

Level shift circuit and level shift device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to application number 202410172934.7, filed on February 6, 2024, entitled “LEVEL SHIFT CIRCUIT AND LEVEL SHIFT DEVICE,” and the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] The present application relates to the technical field of electronic circuits, and in particular to a level shift circuit and a level shift device. Background Art

[0004] The level shift circuit can shift the input control signal with a relatively low voltage and output a control signal with a relatively high voltage. In the related art, a level shift circuit using a high-voltage gate driver is disclosed, but its power consumption is relatively high. Summary of the Invention

[0005] Based on this, it is necessary to provide a level shift circuit and a level shift device that can reduce power consumption in order to solve the above technical problems.

[0006] In the first aspect, the present application provides a level shift circuit, comprising: a signal output module, the signal output module comprising a transistor, the high-voltage end of the transistor being used to receive a power supply voltage, the low-voltage end of the transistor being used to output a shift signal, and the base of the transistor being used to receive a first control signal; a control module, the control module comprising a junction field-effect transistor and an insulated gate field-effect transistor, the drain of the junction field-effect transistor being connected to the base of the transistor and being used to output the first control signal, the gate of the junction field-effect transistor being grounded, the source of the junction field-effect transistor being connected to the drain of the insulated gate field-effect transistor, the gate of the insulated gate field-effect transistor being used to receive a second control signal, the source of the insulated gate field-effect transistor being grounded, the control module being used to send the first control signal to the signal output module according to the second control signal, and the signal output module being used to output the shift signal according to the first control signal.

[0007] In one embodiment, the level shift circuit further includes: a bootstrap module, wherein the input end of the bootstrap module is used to receive the operating voltage, and the first power supply end of the bootstrap module is used to output the power supply voltage according to the operating voltage and the bootstrap voltage of the second power supply end of the bootstrap module.

[0008] In one embodiment, the bootstrap module includes a diode and a capacitor, the positive electrode of the diode is used to receive the operating voltage, the negative electrode of the diode is connected to the first end of the capacitor, the first end of the capacitor is the first power supply end of the bootstrap module, and the second end of the capacitor is the second power supply end of the bootstrap module.

[0009] In one embodiment, the number of the signal output module and the number of the control module are both two.

[0010] In one embodiment, the level shift circuit further includes: a trigger, wherein the input end of the trigger is respectively connected to the two signal output modules, and the output end of the trigger is used to output a level signal according to the two shift signals.

[0011] In the second aspect, the present application also provides a level shifter device, including the level shifter circuit described in the embodiment of the first aspect above, and the level shifter device also includes: a high-voltage region, the signal output module is arranged in the high-voltage region, and the transistor is arranged in the high-voltage region; a high-voltage N-well region, the high-voltage N-well region is arranged around the high-voltage region; and a low-voltage region, the low-voltage region is arranged around the high-voltage N-well region, and at least part of the control module is arranged in the low-voltage region.

[0012] In one embodiment, at least part of the bootstrap module is further provided in the high voltage region.

[0013] In one embodiment, a PN junction isolation ring is provided in the high-voltage N-well region, the PN junction isolation ring contacts the low-voltage region, the drain of the junction field-effect transistor is provided in the PN junction isolation ring, the low-voltage region is used to provide the channel region of the junction field-effect transistor, and the insulated gate field-effect transistor is provided in the low-voltage region.

[0014] In one embodiment, the channel region of the junction field effect transistor includes a plurality of high-voltage N-well units arranged at intervals.

[0015] In one embodiment, the transistor is a fully isolated longitudinal PNP transistor, the high-voltage end is the emitter, and the low-voltage end is the collector.

[0016] The aforementioned level shift circuit and level shift device utilize a transistor, a junction field-effect transistor, and an insulated-gate field-effect transistor. When the gate of the insulated-gate field-effect transistor receives a second control signal, the insulated-gate field-effect transistor turns on. Correspondingly, the voltage level at the source of the junction field-effect transistor drops, causing the junction field-effect transistor to also enter a conducting state. At this point, the base of the transistor receives the corresponding first control signal, turning it on and outputting a shift signal from the low-voltage terminal of the transistor, thereby completing the level shift. Because the transistor amplifies current, the drain of the junction field-effect transistor only needs to provide a very small current to the base of the transistor to turn it on, reducing the power consumption of the level shift circuit during operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] FIG1 is a circuit diagram of a level shift circuit in one embodiment;

[0019] FIG2 is a circuit diagram of a level shift circuit in another embodiment;

[0020] FIG3 is a circuit diagram of a bootstrap module according to an embodiment;

[0021] FIG4 is a circuit diagram of a level shift circuit in yet another embodiment;

[0022] FIG5 is a schematic diagram of a layout of a level shift device in one embodiment;

[0023] FIG6 is a schematic diagram of a layout of a level shift device in another embodiment;

[0024] FIG7 is a schematic cross-sectional view of the line AA′ in FIG6 ;

[0025] FIG8 is a schematic cross-sectional view of the line BB' in FIG6;

[0026] FIG9 is a schematic cross-sectional view of the line CC' in FIG6;

[0027] FIG10 is a schematic diagram of the structure of a transistor in one embodiment;

[0028] Description of the accompanying drawings: Signal output module 110, control module 120, bootstrap module 130, high voltage region 210, high voltage N-well region 220, low voltage region 230, PN junction isolation ring 240, high voltage N-well unit 250, P-type substrate 201, first P-type buried layer 202a, second P-type buried layer 202b, first N-type buried layer 203, first high voltage N-well 204a, second high voltage N-well 204b, first P-well 205a, second P-well 205b, third P-well 205c, fourth P-well 205d, first N-well 206a, second N-well 206b, third N-well 206c, field oxide region 207, upper gate 208, first metal layer 209, first P-type terminal 211, second metal layer 212, first N-type terminal 213, third metal layer 214, second N-type terminal 215, fourth metal layer 216, third N-type terminal 217, fifth metal layer 218, second N-type buried layer 219, low-voltage N-well 221, second P-type terminal 222, sixth metal layer 223, fourth N-type terminal 224, seventh metal layer 225, fifth N-type terminal 226, and eighth metal layer 227. DETAILED DESCRIPTION

[0029] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0031] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0032] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0033] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc., if there is transmission of electrical signals or data between the connected objects.

[0034] It should also be understood that the terms "include / comprising" or "having" etc. specify the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0035] As described in the background, when a conventional high-voltage gate-driven level-shift circuit is operating, the drain current of its high-voltage lateral field-effect transistor is approximately 2 to 20 mA. Because the operating voltage of the high-voltage gate driver chip is very high, ranging from 150 to 1200V or even higher for different chip types, the high-voltage gate driver chip must conduct and operate in the saturation region under high-voltage conditions at the drain terminal. Although its gate is controlled by short pulses, the high voltage still results in significant power consumption.

[0036] Based on the above reasons, the present application provides a level shift circuit and a level shift device suitable for ultra-high voltage gate drive applications, which can reduce the power consumption of the level shift circuit.

[0037] In one embodiment, as shown in FIG1 , a level shift circuit is provided, including: a signal output module 110 and a control module 120, wherein the signal output module 110 includes a transistor Q1, wherein the high-voltage end of the transistor Q1 is used to receive a power supply voltage, the low-voltage end of the transistor Q1 is used to output a shift signal, and the base of the transistor Q1 is used to receive a first control signal; the control module 120 includes a junction field-effect transistor J1 and an insulated-gate field-effect transistor M1, wherein the drain of the junction field-effect transistor J1 is connected to the base of the transistor Q1 and is used to output the first control signal, the gate of the junction field-effect transistor J1 is grounded, the source of the junction field-effect transistor J1 is connected to the drain of the insulated-gate field-effect transistor M1, the gate of the insulated-gate field-effect transistor M1 is used to receive a second control signal, and the source of the insulated-gate field-effect transistor M1 is grounded, the control module 120 is used to send a first control signal to the signal output module 110 according to the second control signal, and the signal output module 110 is used to output a shift signal according to the first control signal.

[0038] Specifically, the signal output module 110 includes a transistor Q1, and the high-voltage end of the transistor Q1 is used to receive the power supply voltage. In some embodiments, the level shift circuit is an ultra-high voltage level shift circuit. In this case, the power supply voltage is 150V to 1200V, or even higher. The low-voltage end of the transistor Q1 is used to output the shift signal, and the magnitude of the power supply voltage can affect the voltage magnitude of the shift signal. The base of the transistor Q1 is connected to the drain of the junction field effect transistor J1 and is used to receive the first control signal. It is understandable that when the transistor Q1 is a PNP transistor, the emitter of the transistor Q1 is the high-voltage end, and the collector of the transistor Q1 is the low-voltage end. In other embodiments, the transistor Q1 can also be an NPN transistor, in which case the collector is the high-voltage end and the emitter is the low-voltage end.

[0039] Because the power supply voltage received by transistor Q1 is relatively high, junction field-effect transistor J1 connected to transistor Q1 is a high-voltage-resistant field-effect transistor. The drain of junction field-effect transistor J1 is located on the high-voltage side, and the source of junction field-effect transistor J1 is located on the low-voltage side. Insulated-gate field-effect transistor M1 can be a common low-voltage field-effect transistor. When the gate of insulated-gate field-effect transistor M1 does not receive the second control signal, the gate of insulated-gate field-effect transistor M1 has no input and is at a low level, and insulated-gate field-effect transistor M1 is in the off state. At the same time, junction field-effect transistor J1 is turned off and no current flows. The base of transistor Q1 also has no current and is in the off state. When the gate of the insulated gate field effect transistor M1 receives the second control signal (for example, a short pulse signal), the insulated gate field effect transistor M1 is turned on, the voltage levels of the drain of the insulated gate field effect transistor M1 and the source of the junction field effect transistor J1 decrease, and the junction field effect transistor J1 enters the on state. Since the drain of the junction field effect transistor J1 is connected to the base of the transistor Q1, the transistor Q1 is also turned on at this time, so that the low-voltage end of the transistor Q1 outputs a shift signal. The voltage of the shift signal is related to the power supply voltage. The power supply voltage can be adjusted according to circuit requirements to achieve the level shifting function.

[0040] The transistor Q1 in the level shift circuit of this embodiment has a large current amplification effect. The drain of the junction field effect transistor J1 only needs to provide a very small base current to the transistor Q1 to complete the level shift. Compared with the traditional high-voltage gate drive level shift circuit, the operating current of the drain of the junction field effect transistor J1 is reduced by 1 to 2 orders of magnitude. Typically, a current of 20 to 200 μA is sufficient to ensure the normal operation of the level shift circuit, thereby reducing the power consumption of the level shift circuit during operation.

[0041] In one embodiment, as shown in FIG2 , the level shift circuit further includes: a bootstrap module 130 , wherein the input terminal of the bootstrap module 130 is used to receive an operating voltage, and the first power supply terminal of the bootstrap module 130 is used to output a power supply voltage according to the operating voltage and a bootstrap voltage of the second power supply terminal of the bootstrap module 130 .

[0042] Specifically, the bootstrap module 130 mainly utilizes electronic components such as bootstrap boost diodes and bootstrap boost capacitors to superimpose the capacitor discharge voltage and the power supply voltage, thereby increasing the voltage. The increased voltage can reach several times the power supply voltage. The input terminal of the bootstrap module 130 is used to receive the operating voltage. VCC in Figure 2 is the operating voltage. The operating voltage is generally 5V to 25V, and its voltage magnitude is determined by the design requirements of the level shift circuit. The first power supply terminal of the bootstrap module 130 is used to output the supply voltage. VB in Figure 2 is the supply voltage. The second power supply terminal of the bootstrap module 130 is used to output the bootstrap voltage. VS in the figure is the bootstrap voltage. The bootstrap voltage is a floating voltage terminal, and its voltage floating range can be 0 to 1200V. Correspondingly, the magnitude of the supply voltage is the sum of the bootstrap voltage and the operating voltage. In some embodiments, the low voltage terminal of the transistor Q1 is connected to the second power supply terminal of the bootstrap module 130.

[0043] In one embodiment, as shown in FIG3 , the signal output module 110 further includes a first resistor R1, one end of the first resistor R1 being connected to the low-voltage terminal of the transistor Q1, and the other end of the first resistor R1 being connected to the second power supply terminal of the bootstrap module 130. Specifically, by configuring the first resistor R1, when the transistor Q1 is turned on, the first resistor R1 generates a voltage drop due to the current output from the low-voltage terminal of the transistor Q1, thereby adjusting the voltage of the shift signal output from the low-voltage terminal of the transistor Q1.

[0044] In one embodiment, as shown in FIG3 , the bootstrap module 130 includes a diode D1 and a capacitor C1. The anode of the diode D1 is used to receive the operating voltage, and the cathode of the diode D1 is connected to the first end of the capacitor C1. The first end of the capacitor C1 serves as the first power supply end of the bootstrap module 130, and the second end of the capacitor C1 serves as the second power supply end of the bootstrap module 130. Specifically, when the second power supply end is at a low level and the operating voltage is present, the operating voltage charges the capacitor C1 through the diode D1, causing the voltage on the capacitor C1 to approach the operating voltage. When the second power supply end floats to a high voltage (e.g., 1200V), the voltage on the first power supply end rises to the sum of the floating voltage and the operating voltage. The charge stored on the capacitor C1 is used to support the operation of the high-side circuit. The supply voltage is determined by the floating voltage and the operating voltage.

[0045] In one embodiment, as shown in FIG3 , the control module 120 further includes a second resistor R2 , one end of which is connected to the source of the insulated gate field effect transistor M1 , and the other end of which is grounded. Specifically, by setting the resistance value of the second resistor R2 , the operating current of the junction field effect transistor J1 can be controlled, thereby facilitating adjustment of the power consumption of the level shift circuit during operation.

[0046] In one embodiment, as shown in FIG4 , the signal output module 110 and the control module 120 are each configured as two. Specifically, in this embodiment, the signal output module 110 and the control module 120 are each configured as two, the structural parameters of the two signal output modules 110 are the same, the structural parameters of the two control modules 120 are the same, and the specific structures of the signal output module 110 and the control module 120 are the same as those in the above-mentioned embodiment, and are not described in detail here. The two signal output modules 110 can respectively output two shift signals, and the two signals can be synchronized by an externally set trigger, thereby converting the two shift signals into a more stable signal. In some other embodiments, the signal output module 110 and the control module 120 can each be configured as multiple.

[0047] In one embodiment, as shown in FIG4 , the level shift circuit further includes: a trigger U1, wherein the input end of the trigger U1 is respectively connected to two signal output modules 110, and the output end of the trigger U1 is used to output a level signal according to the two shift signals. Specifically, when both the signal output module 110 and the control module 120 are set to two, the two signal output modules 110 will respectively input a shift signal to the trigger U1. The trigger U1 synchronizes the two input shift signals to obtain a more stable level signal and outputs it from the output end of the trigger U1, thereby making the signal ultimately output by the level shift circuit more stable. In some embodiments, the trigger U1 is an RS (Reset-Set) trigger, wherein its input end R and input end S are each connected to a signal output module 110, and a more stable level signal is output through the output end Q.

[0048] In one embodiment, the present application further provides a level shift device, which includes the level shift circuit in the above embodiment.

[0049] In one embodiment, as shown in Figure 5, the device structure of the level shift device in the chip includes: a high-voltage region 210, a high-voltage N-well region 220 and a low-voltage region 230. The signal output module 110 is provided in the high-voltage region 210, the transistor Q1 is provided in the high-voltage region 210, the high-voltage N-well region 220 is provided around the high-voltage region 210, the low-voltage region 230 is provided around the high-voltage N-well region 220, and at least part of the control module 120 is provided in the low-voltage region 230.

[0050] Specifically, the high-voltage region 210 and the high-voltage N-well region 220 in this embodiment form a high-voltage island. The high-voltage region 210 is used to layout the high-voltage side circuitry, namely, the signal output module 110 in the level shift circuit in the above-described embodiment. Therefore, the transistor Q1 in the signal output module 110 is disposed in the high-voltage region 210. In some embodiments, the first resistor R1 in the signal output module 110 is also disposed in the high-voltage region 210. The high-voltage N-well region 220 is an N-type doped region formed in a semiconductor wafer. It serves as the high-voltage junction terminal of the high-voltage island, also known as the drift region. The high-voltage N-well region 220 is disposed around the high-voltage region 210. A low-voltage region 230 is disposed around the high-voltage N-well region 220. The low-voltage region 230 is used to house at least a portion of the control module 120. For example, both the junction field-effect transistor J1 and the insulated-gate field-effect transistor M1 in the control module 120 are disposed in the low-voltage region 230, or only a portion of the junction field-effect transistor J1 is disposed in the low-voltage region 230. In some embodiments, the second resistor R2 of the control module 120 is also disposed in the low-voltage region 230. It is understood that, in subsequent use, the outer periphery of the low-voltage region 230 of the level shifting device is used to connect to the ground line.

[0051] In one embodiment, at least a portion of the bootstrap module 130 is further disposed in the high-voltage region 210 to boost the operating voltage to the supply voltage. In some other embodiments, when the bootstrap module 130 includes a diode D1 and a capacitor C1, for ease of integration, only the diode D1 may be disposed in the high-voltage region 210.

[0052] In one embodiment, as shown in FIG6 , a PN junction isolation ring 240 is provided in the high-voltage N-well region 220 . The PN junction isolation ring 240 contacts the low-voltage region 230 . The drain of the junction field-effect transistor J1 is provided in the PN junction isolation ring 240 . The low-voltage region 230 is used to provide the channel region of the junction field-effect transistor J1 . The insulated gate field-effect transistor M1 is provided in the low-voltage region 230 .

[0053] Specifically, the drain of the junction field effect transistor J1 in this embodiment is formed in the high-voltage N-well region 220, and the channel region of the junction field effect transistor J1 is formed in the low-voltage region 230. The PN junction isolation ring 240 is composed of a P-well formed in the high-voltage N-well region 220, and is used to isolate the drain of the junction field effect transistor J1 from the high-voltage N-well region 220. Figure 6 shows a schematic diagram of a layout including one junction field effect transistor J1 (in the dashed box). In some other embodiments, the number of junction field effect transistors J1 can also be two or more.

[0054] In one embodiment, the channel region of the junction field effect transistor J1 includes a plurality of spaced-apart high-voltage N-well units 250. Specifically, as shown in FIG6 , the channel region of the junction field effect transistor J1 is provided with three high-voltage N-well units 250. The high-voltage N-well units 250 are arranged in a rectangular shape in the cross-sectional position shown in FIG6 . The pinch-off voltage of the junction field effect transistor J1 can be adjusted by adjusting the shape and size of the rectangle.

[0055] The following describes in detail the manufacturing process and structure of the junction field effect transistor J1 in the embodiment of the present application. As shown in Figure 7, it is a schematic diagram of the cross-sectional structure along line A-A' in Figure 6. The junction field effect transistor J1 is manufactured using a P-type substrate 201. A first P-type buried layer 202a, a second P-type buried layer 202b, and a first N-type buried layer 203 are then formed in the P-type substrate 201. A P-type epitaxial layer is then grown, and a first high-voltage N-well 204a and a second high-voltage N-well 204b are formed in the P-type epitaxial layer by ion implantation. Furthermore, a first P-well 205a, a second P-well 205b, a third P-well 205c, a first N-well 206a, and a second N-well 206b are formed by ion implantation. After well pushing, the structure shown in Figure 7 is obtained. The first high-voltage N-well 204a is the high-voltage N-well unit 250 extending from the high-voltage N-well region 220 in FIG6 , which is also the channel region of the junction field-effect transistor J1. By adjusting the width of the first high-voltage N-well 204a, the pinch-off voltage of the junction field-effect transistor J1 can be changed. The first P-well 205a represents the P-well in the low-voltage region 230. The second P-well 205b and the second P-type buried layer 202b form a PN junction isolation ring 240. The third P-well 205c is surrounded by the first N-type buried layer 203 and the second N-well 206b, thereby isolating it from the P-type substrate 201 and forming a P-well. The third P-well 205c is connected to a floating potential, namely the VS terminal shown in FIG3 . After the N-well and P-well are fabricated, photolithography and field oxidation are performed on the active region to form the active region, namely the field oxide region 207 shown in the figure. The area outside the field oxide region 207 is the active region.

[0056] Gate oxidation and polysilicon patterning are then performed to form the field plate of the junction field effect transistor J1 made of polysilicon, namely the upper gate 208 of the junction field effect transistor J1. The polysilicon of the upper gate 208 is led out through the first metal layer 209 and can be directly connected to ground or a control potential. The first P-type lead terminal 211 is used to connect the first P-well 205a and the first P-type buried layer 202a. The first P-type lead terminal 211 is connected to the P-type substrate 201 through the second metal layer 212, thereby forming a substrate contact. The P-type substrate 201 is the gate of the junction field effect transistor J1. The first N-type lead terminal 213 is used to connect to the first high-voltage N-well 204a. The first N-type lead terminal 213 is led out through the third metal layer 214 and connected to the source of the junction field effect transistor J1. The second N-type lead-out terminal 215 is connected to the first N-well 206a. The second N-type lead-out terminal 215 is led out through the fourth metal layer 216 and connected to the drain of the junction field-effect transistor J1. The junction field-effect transistor J1 in the embodiment of the present application is actually a parasitic device, and the P-type substrate 201 of the junction field-effect transistor J1 is fixedly grounded. The third N-type lead-out terminal 217 is connected to the second N-well 206b. The third N-type lead-out terminal 217 is led out through the fifth metal layer 218. The fifth metal layer 218 is the island potential of the high-voltage island and is used to connect to the VB terminal shown in Figure 3.

[0057] FIG8 is a schematic diagram of the cross-sectional structure taken along line BB' in FIG6 , i.e., the cross-sectional structure of the location between the high-voltage N-well unit 250 of the junction field effect transistor J1. Compared to FIG7 , FIG8 lacks the first high-voltage N-well 204a in FIG7 . FIG9 is a schematic diagram of the cross-sectional structure taken along line C-C' in FIG6 . FIG9 shows a location without a high-voltage junction terminal of the device, lacking the junction field effect transistor J1 (the first high-voltage N-well 204a in FIG7 ), and lacking the PN junction isolation ring 240 structure (the second P-well 205b and the second P-type buried layer 202b in FIG7 and FIG8 ).

[0058] In one embodiment, transistor Q1 is a fully isolated vertical PNP transistor, with the high-voltage end serving as the emitter and the low-voltage end serving as the collector. Specifically, FIG10 shows a schematic structural diagram of the vertical PNP transistor. A second N-type buried layer 219 is provided on the P-type substrate 201 of the vertical PNP transistor. A low-voltage N-well 221 is provided on the second N-type buried layer 219. A fourth P-well 205d, isolated and surrounded by the second N-type buried layer 219 and the low-voltage N-well 221, serves as the collector of the vertical PNP transistor. A third N-well 206c is provided on the fourth P-well 205d, serving as the base region of the vertical PNP transistor. A second P-type lead 222 is connected to the fourth P-well 205d. The second P-type lead 222 is led out through a sixth metal layer 223 to serve as the collector of the vertical PNP transistor. In some embodiments, the collector lead is formed in a ring shape. A fourth N-type lead terminal 224 is connected to the third N-well 206c and is led out through the seventh metal layer 225 to serve as the base of the vertical PNP transistor. In some embodiments, the base lead terminal is in a ring shape. A fifth N-type lead terminal 226 is connected to the third N-well 206c and is led out through the eighth metal layer 227 to serve as the emitter of the vertical PNP transistor.

[0059] In the description of this specification, reference to the terms "one embodiment," "some embodiments," "specific embodiments," etc., means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0060] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0061] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A level shift circuit, characterized in that: include: A signal output module, the signal output module comprising a transistor, a high-voltage end of the transistor being used to receive a power supply voltage, a low-voltage end of the transistor being used to output a shift signal, and a base of the transistor being used to receive a first control signal; A control module, the control module including a junction field-effect transistor and an insulated gate field-effect transistor, the drain of the junction field-effect transistor being connected to the base of the transistor and being used to output the first control signal, the gate of the junction field-effect transistor being grounded, the source of the junction field-effect transistor being connected to the drain of the insulated gate field-effect transistor, the gate of the insulated gate field-effect transistor being used to receive a second control signal, the source of the insulated gate field-effect transistor being grounded, the control module being used to send the first control signal to the signal output module according to the second control signal, and the signal output module being used to output the shift signal according to the first control signal.

2. The level shift circuit according to claim 1, wherein: Also includes: A bootstrap module, wherein the input terminal of the bootstrap module is used to receive an operating voltage, and the first power supply terminal of the bootstrap module is used to output the power supply voltage according to the operating voltage and the bootstrap voltage of the second power supply terminal of the bootstrap module.

3. The level shift circuit according to claim 2, wherein: The bootstrap module includes a diode and a capacitor, the positive electrode of the diode is used to receive the working voltage, the negative electrode of the diode is connected to the first end of the capacitor, the first end of the capacitor is the first power supply end of the bootstrap module, and the second end of the capacitor is the second power supply end of the bootstrap module.

4. The level shift circuit according to any one of claims 1 to 3, wherein: The number of the signal output module and the number of the control module are both two.

5. The level shift circuit according to claim 4, wherein: Also includes: A trigger, wherein the input end of the trigger is respectively connected to the two signal output modules, and the output end of the trigger is used to output a level signal according to the two shift signals.

6. The level shift circuit according to claim 2, wherein: The signal output module further includes a first resistor, one end of the first resistor is connected to the low voltage end of the transistor, and the other end of the first resistor is connected to the second power supply end of the bootstrap module.

7. The level shift circuit according to claim 1, wherein: The control module further includes a second resistor, one end of the second resistor is connected to the source of the insulated gate field effect transistor, and the other end of the second resistor is grounded.

8. A level shift device, characterized in that: The level shift circuit according to any one of claims 1 to 7, wherein the level shift device further comprises: a high-voltage region, wherein the signal output module is provided in the high-voltage region, and the triode is provided in the high-voltage region; a high-voltage N-well region, the high-voltage N-well region being arranged around the high-voltage region; A low-voltage region is provided around the high-voltage N-well region, and at least a portion of the control module is provided in the low-voltage region.

9. The level shift device according to claim 8, wherein: The level shift circuit further includes: a bootstrap module, wherein an input terminal of the bootstrap module is used to receive an operating voltage, and a first power supply terminal of the bootstrap module is used to output the supply voltage based on the operating voltage and a bootstrap voltage of a second power supply terminal of the bootstrap module, wherein at least a portion of the bootstrap module is also provided in the high-voltage region of the level shift device.

10. The level shift device according to claim 9, wherein: The bootstrap module includes a diode and a capacitor, the positive electrode of the diode is used to receive the operating voltage, the negative electrode of the diode is connected to the first end of the capacitor, the first end of the capacitor is the first power supply end of the bootstrap module, and the second end of the capacitor is the second power supply end of the bootstrap module, wherein only the diode is arranged in the high-voltage area.

11. The level shift device according to claim 8, wherein: A PN junction isolation ring is provided in the high-voltage N-well region, and the PN junction isolation ring contacts the low-voltage region. The drain of the junction field-effect transistor is provided in the PN junction isolation ring, and the low-voltage region is used to provide the channel region of the junction field-effect transistor. The insulated gate field-effect transistor is provided in the low-voltage region.

12. The level shift device according to claim 11, wherein: The channel region of the junction field effect transistor includes a plurality of high-voltage N-well units arranged at intervals.

13. The level shift device according to claim 8, wherein: The triode is a fully isolated longitudinal PNP tube, the high voltage end of the triode is the emitter, and the low voltage end of the triode is the collector.

14. The level shift device according to claim 8, wherein: The control module further includes a second resistor, one end of the second resistor is connected to the source of the insulated gate field effect transistor, and the other end of the second resistor is grounded, wherein the second resistor of the control module is arranged in the low voltage area.

15. The level shift device according to claim 9, wherein: The signal output module also includes a first resistor, one end of the first resistor is connected to the low voltage end of the transistor, and the other end of the first resistor is connected to the second power supply end of the bootstrap module, wherein the first resistor of the signal output module is arranged in the high voltage area.

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