Data processing method, apparatus, and system

Abstract

Disclosed in embodiments of the present application are a data processing method, apparatus, and system. It is ensured that the overall data processing operation is simple, the complexity is low, the power consumption is low, the spectrum efficiency is improved, and the system transmission performance is improved. Specifically, PCS processing is performed on a first bit set among a plurality of bits to obtain a second bit set. Further, first interleaving is performed on the second bit set and a third bit set other than the first bit set among the plurality of bits to obtain a fourth bit set 1 and a fourth bit set 2. Then, FEC coding is performed at the granularity of a fifth bit set, for example, a fifth bit set 1 comprises at least one fourth bit set 1, a fifth bit set 2 comprises at least one fourth bit set 2, and FEC coding is separately performed on the two fifth bit sets to obtain two sixth bit sets. Second interleaving is separately performed on the two sixth bit sets to obtain two seventh bit sets. Third interleaving is performed on two seventh bit sets to obtain an eighth bit set.

Description

Data processing method, device and system

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 8, 2024, with application number 202410178324.8 and application name “A Data Processing Method, Device and System”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a data processing method, device and system. Background Art

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards large capacity, packetization, and intelligence. Coherent optical communication systems use the amplitude, phase, polarization, and frequency of light waves to carry information. To combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and maintain long-distance transmission, coherent optical communication systems typically require the use of efficient forward error correction (FEC) codes to combat optical impairments during optical transmission and maintain a sufficiently low bit error rate over long distances. For example, the open FEC code (OpenFEC), also referred to as OFEC code, currently adopted by 400ZR+ and 800ZR, has an overhead (OH) of 15.3%. When soft-decision decoding is used, the performance is approximately 2.0E-2 before correction.

[0004] In order to improve spectrum efficiency, multi-level Quadrature Amplitude Modulation (QAM) is usually used, such as 16QAM, 32QAM, 64QAM and even higher-order QAM. Each constellation point on the signal constellation diagram corresponding to traditional QAM modulation appears with the same probability. Probabilistic Constellation Shaping (PCS) processing technology changes the probability of constellation points appearing while keeping the constellation point positions unchanged, making them non-uniformly distributed, thereby improving system transmission performance. As a modulation format optimization technology, PCS processing technology has the advantages of approaching the Shannon limit and being flexible and variable, and has been widely studied and applied. The existing data processing and transmission methods using OFEC coding mainly use traditional QAM modulation, which cannot be applied to scenarios where PCS processing technology will be used in the future. This is a problem that needs to be solved urgently in the future. Summary of the Invention

[0005] The embodiments of the present application provide a data processing method, device, and system. In scenarios using DP-64QAM modulation, combined with FEC coding, interleaving, and PCS processing technologies, these methods ensure simple overall data processing operations, low complexity, and low power consumption, while improving spectrum utilization and enhancing system transmission performance. This facilitates application in future metropolitan area telecommunications transmission and metropolitan area Data Center Interconnect (DCI) interconnection scenarios.

[0006] In a first aspect, embodiments of the present application provide a data processing method. Specifically, PCS processing is performed on a first bit set from a plurality of bits to obtain a second bit set. A first interleaving is performed on the second bit set and a third bit set from the plurality of bits, excluding the first bit set, to obtain two fourth bit sets. The bit distribution of the two fourth bit sets differs. For ease of distinction, they are referred to herein as fourth bit set 1 and fourth bit set 2. Fourth bit set 1 may correspond to fourth bit set 2i in later embodiments, and fourth bit set 2 may correspond to fourth bit set 2i+1 in later embodiments. Subsequently, FEC encoding is performed using a fifth bit set as the granularity. For example, fifth bit set 1 includes at least one fourth bit set 1, and fifth bit set 2 includes at least one fourth bit set 2. FEC encoding is performed on each of the two fifth bit sets to obtain two sixth bit sets, each of which includes parity bits generated by the FEC encoding. Next, a second interleaving is performed on each of the two sixth bit sets to obtain two seventh bit sets. Furthermore, a third interleaving is performed on the two seventh bit sets to obtain an eighth bit set. In a specific scenario, the fifth bit set includes 42 rows and 7 columns, totaling 294 bit subsets, wherein each bit subset in the 42 rows and 6 columns, totaling 252 bit subsets includes 16 rows and 16 columns, totaling 256 bits, and each bit subset in the 42 rows and 1 column, totaling 42 bit subsets includes 16 rows and 15 columns, totaling 240 bits. The sixth bit set and the seventh bit set each include 42 rows and 8 columns, totaling 336 bit subsets, and each bit subset includes 16 rows and 16 columns, totaling 256 bits.

[0007] It should be noted that the 12 consecutive bits in the eighth bit set are used to map to obtain a dual-polarization symbol, which includes a first polarization symbol and a second polarization symbol. The first polarization symbol can also be recorded as the X polarization symbol, and the second polarization symbol can also be recorded as the Y polarization symbol. Bits 0, 2, 4, 6, 8, and 10 of the 12 bits are used to map to the first polarization symbol, and bits 1, 3, 5, 7, 9, and 11 of the 12 bits are used to map to the second polarization symbol. Four of the 12 bits used to map to the first polarization symbol come from the second bit set, and the other two of the 12 bits used to map to the first polarization symbol come from the third bit set and / or FEC-encoded parity bits. Four of the 12 bits used to map to the second polarization symbol come from the second bit set, and the other two of the 12 bits used to map to the second polarization symbol come from the third bit set and / or FEC-encoded parity bits.

[0008] In this embodiment, the present application designs a data processing method that combines PCS processing, FEC encoding and interleaving. After the data processing, every 12 consecutive bits in the bit data are used to map to obtain a dual-polarization symbol. The dual-polarization symbol includes a first polarization symbol and a second polarization symbol. The bits located at odd and even positions in the 12 bits are respectively mapped to different polarization symbols. Moreover, among the 6 bits mapped to each polarization symbol, 4 bits are from the bit set processed by PCS, and the other 2 bits are from the bit set not processed by PCS and / or the check bits of FEC encoding. The data processing method designed in this way can better match the DP-64QAM modulation scenario, ensure that the overall data processing operation is simple, the complexity is low, and the power consumption is low, while improving the spectrum utilization and enhancing the system transmission performance, so as to facilitate application in future metropolitan area telecommunication transmission and metropolitan area DCI interconnection scenarios.

[0009] In some possible implementations, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, and the seventh bit set 1 and the seventh bit set 2 each include 42 rows and 8 columns, totaling 336 first bit subsets, and the first bit subset includes 16 rows and 16 columns, totaling 256 bits. It should be understood that the bit distribution pattern of the first bit subset is used to indicate the position of the bits from the second bit set in the first bit subset and the position of the bits from the third bit set and / or the FEC-coded check bits in the first bit subset. The bit distribution patterns of the first bit subsets in different rows of the two seventh bit sets are introduced below. This design method can match the inter-matrix interleaving method with an 8-bit granularity, and is conducive to ensuring that the overall data processing operation is simple, the complexity is low, and the power consumption is low.

[0010] The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 1 is the first bit distribution pattern.

[0011] The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 1 is the second bit distribution pattern.

[0012] The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 1 is the third bit distribution pattern.

[0013] The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 2 is the third bit distribution pattern.

[0014] The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 2 is the first bit distribution pattern.

[0015] The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 2 is the second bit distribution pattern.

[0016] In some possible implementations, performing a second interleaving on two sixth bit sets to obtain two seventh bit sets includes: performing a fourth interleaving on the two sixth bit sets to obtain two ninth bit sets. The two ninth bit sets include a ninth bit set 1 and a ninth bit set 2, and the ninth bit set 1 and the ninth bit set 2 each include 42 rows and 8 columns, totaling 336 second bit subsets, and the second bit subset includes 16 rows and 16 columns, totaling 256 bits. Performing a fifth interleaving on the two ninth bit sets to obtain two seventh bit sets, wherein the fifth interleaving is used to interleave the 16 bits in each row of each second bit subset in the ninth bit set. In other words, the second interleaving operation can be implemented in two steps, namely the fourth interleaving and the fifth interleaving, wherein the fifth interleaving can be understood as a method of intra-row interleaving of the bits in each row of the second bit subset. This design improves the flexibility of the implementation of this solution.

[0017] In some possible implementations, the bit distribution pattern of the second bit subset is used to indicate the positions of bits from the second bit set and the positions of bits from the third bit set and / or FEC-coded parity bits within the second bit subset. The following describes the bit distribution patterns of the second bit subsets in different rows of the two ninth bit sets. This design approach matches the inter-matrix interleaving method with an 8-bit granularity, and helps ensure simple overall data processing operations, low complexity, and low power consumption.

[0018] The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 1 is the fourth bit distribution pattern.

[0019] The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 1 is the fifth bit distribution pattern.

[0020] The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 1 is the sixth bit distribution pattern.

[0021] The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 2 is the sixth bit distribution pattern.

[0022] The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 2 is the fourth bit distribution pattern.

[0023] The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 2 is the fifth bit distribution pattern.

[0024] In some possible implementations, the two sixth bit sets include sixth bit set 1 and sixth bit set 2. Sixth bit set 1 and sixth bit set 2 each include 42 rows and 8 columns, totaling 336 third bit subsets. The third bit subset includes 16 rows and 16 columns, totaling 256 bits. In the 42 rows and 8 columns, totaling 336 third bit subsets, the bits in the third bit subset from columns 0 to 4 come from the second bit set and the third bit set. The bits in the third bit subset from column 5 and the bits from columns 0 to 14 in the third bit subset from column 6 come from the second bit set. The bits in column 15 of the third bit subset from column 6 and the bits in the third bit subset from column 7 are parity bits for FEC encoding. This implementation provides a bit distribution method in the sixth bit set, namely, where each portion of the bits in the sixth bit set comes from, ensuring the effectiveness of this solution.

[0025] In some possible implementations, the bit distribution pattern of the third bit subset is used to indicate the positions of bits from the second bit set within the third bit subset, as well as the positions of bits from the third bit set and / or FEC-coded parity bits within the third bit subset. The following describes the bit distribution patterns of the third bit subsets in different rows of the two sixth bit sets. This design approach matches the 8-bit granularity of inter-matrix interleaving and helps ensure simple overall data processing operations, low complexity, and low power consumption.

[0026] The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 1 is the fourth bit distribution pattern.

[0027] The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 1 is the fifth bit distribution pattern.

[0028] The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 1 is the sixth bit distribution pattern.

[0029] The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 2 is the sixth bit distribution pattern.

[0030] The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 2 is the fourth bit distribution pattern.

[0031] The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 2 is the fifth bit distribution pattern.

[0032] In some possible implementations, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, and the seventh bit set 1 and the seventh bit set 2 each include 42 rows and 8 columns, totaling 336 first bit subsets, and the first bit subset includes 16 rows and 16 columns, totaling 256 bits. The bit distribution pattern of the first bit subset is used to indicate the position of the bits from the second bit set in the first bit subset and the position of the bits from the third bit set and / or the FEC-coded check bits in the first bit subset. The bit distribution patterns of the first bit subsets in different rows of the two seventh bit sets are introduced below. This design method can match the inter-matrix interleaving processing method with a granularity of 16 bits, and is conducive to ensuring that the overall data processing operation is simple, low in complexity, and low in power consumption.

[0033] The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 1 is the first bit distribution pattern.

[0034] The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 1 is the second bit distribution pattern.

[0035] The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 1 is the third bit distribution pattern.

[0036] The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 2 is the second bit distribution pattern.

[0037] The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 2 is the third bit distribution pattern.

[0038] The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 2 is the first bit distribution pattern.

[0039] In some possible implementations, performing a second interleaving on the two sixth bit sets to obtain the two seventh bit sets includes performing a fourth interleaving on the two sixth bit sets to obtain the two ninth bit sets. The two ninth bit sets include a ninth bit set 1 and a ninth bit set 2, each of which includes 42 rows and 8 columns, totaling 336 second bit subsets, and the second bit subsets include 16 rows and 16 columns, totaling 256 bits. Performing a fifth interleaving on the two ninth bit sets to obtain the two seventh bit sets, wherein the fifth interleaving is used to interleave 16 bits in each row of each second bit subset in the ninth bit set.

[0040] In some possible implementations, the bit distribution pattern of the second bit subset is used to indicate the positions of bits from the second bit set and the positions of bits from the third bit set and / or FEC-coded parity bits within the second bit subset. The following describes the bit distribution patterns of the second bit subsets in different rows of two ninth bit sets. This design approach matches the 16-bit granularity of interleaving between matrices and helps ensure simple overall data processing operations, low complexity, and low power consumption.

[0041] The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 1 is the fourth bit distribution pattern.

[0042] The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 1 is the fifth bit distribution pattern.

[0043] The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 1 is the sixth bit distribution pattern.

[0044] The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 2 is the fifth bit distribution pattern.

[0045] The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 2 is the sixth bit distribution pattern.

[0046] The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 2 is the fourth bit distribution pattern.

[0047] In some possible implementations, the two sixth bit sets include a sixth bit set 1 and a sixth bit set 2. The sixth bit set 1 and the sixth bit set 2 each include 42 rows and 8 columns, totaling 336 third bit subsets. The third bit subset includes 16 rows and 16 columns, totaling 256 bits. In the 42 rows and 8 columns, totaling 336 third bit subsets, the bits in the third bit subset from columns 0 to 4 are from the second bit set and the third bit set, the bits in the third bit subset from column 5 and the bits from columns 0 to 14 in the third bit subset from column 6 are from the second bit set, and the bits in column 15 of the third bit subset from column 6 and the bits in the third bit subset from column 7 are parity bits for FEC coding.

[0048] In some possible implementations, the bit distribution pattern of the third bit subset is used to indicate the positions of bits from the second bit set within the third bit subset, as well as the positions of bits from the third bit set and / or FEC-coded parity bits within the third bit subset. The following describes the bit distribution patterns of the third bit subsets in different rows of the two sixth bit sets. This design approach matches the 16-bit granularity of interleaving between matrices, and helps ensure simple overall data processing operations, low complexity, and low power consumption.

[0049] The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 1 is the fourth bit distribution pattern.

[0050] The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 1 is the fifth bit distribution pattern.

[0051] The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 1 is the sixth bit distribution pattern.

[0052] The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 2 is the fifth bit distribution pattern.

[0053] The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 2 is the sixth bit distribution pattern.

[0054] The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 2 is the fourth bit distribution pattern.

[0055] In some possible implementations, the 0th, 2nd, and 4th bits of the 12 bits are used to map to the first component of the first polarization symbol, the 6th, 8th, and 10th bits of the 12 bits are used to map to the second component of the first polarization symbol, the 1st, 3rd, and 5th bits of the 12 bits are used to map to the first component of the second polarization symbol, and the 7th, 9th, and 11th bits of the 12 bits are used to map to the second component of the second polarization symbol. A specific mapping rule 1 for mapping 12 bits to obtain a dual polarization symbol is provided herein, which has good practical effects.

[0056] In some possible implementations, based on the above-mentioned mapping rule 1, the first bit distribution pattern is shown in Figure 22(a), the second bit distribution pattern is shown in Figure 22(b), the third bit distribution pattern is shown in Figure 22(c), the fourth bit distribution pattern is shown in Figure 11(a), the fifth bit distribution pattern is shown in Figure 11(b), and the sixth bit distribution pattern is shown in Figure 11(c).

[0057] In some possible implementations, the 0th, 4th, and 6th bits of the 12 bits are used to map to the first component of the first polarization symbol, the 2nd, 8th, and 10th bits of the 12 bits are used to map to the second component of the first polarization symbol, the 1st, 5th, and 7th bits of the 12 bits are used to map to the first component of the second polarization symbol, and the 3rd, 9th, and 11th bits of the 12 bits are used to map to the second component of the second polarization symbol. Another specific mapping rule 2 for mapping 12 bits to obtain a dual polarization symbol is provided herein, enriching the implementation of this solution.

[0058] In some possible implementations, based on the above-mentioned mapping rule 2, the first bit distribution pattern is shown in Figure 30(a), the second bit distribution pattern is shown in Figure 30(b), the third bit distribution pattern is shown in Figure 30(c), the fourth bit distribution pattern is shown in Figure 28(a), the fifth bit distribution pattern is shown in Figure 28(b), and the sixth bit distribution pattern is shown in Figure 28(c).

[0059] In some possible implementations, the 8th bit, the 0th bit, and the 2nd bit of the 12 bits are used to map to the first component of the first polarization symbol, the 10th bit, the 4th bit, and the 6th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 9th bit, the 1st bit, and the 3rd bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 11th bit, the 5th bit, and the 7th bit of the 12 bits are used to map to the second component of the second polarization symbol. Here, another specific mapping rule 3 for mapping 12 bits to obtain a dual polarization symbol is provided, enriching the implementation of this solution.

[0060] In some possible implementations, based on the above-mentioned mapping rule 3, the first bit distribution pattern is shown in Figure 30(b), the second bit distribution pattern is shown in Figure 30(c), the third bit distribution pattern is shown in Figure 30(a), the fourth bit distribution pattern is shown in Figure 28(b), the fifth bit distribution pattern is shown in Figure 28(c), and the sixth bit distribution pattern is shown in Figure 28(a).

[0061] In some possible implementations, the 4th bit, the 0th bit, and the 2nd bit of the 12 bits are used to map to the first component of the first polarization symbol, the 6th bit, the 8th bit, and the 10th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 5th bit, the 1st bit, and the 3rd bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 7th bit, the 9th bit, and the 11th bit of the 12 bits are used to map to the second component of the second polarization symbol. Here, another specific mapping rule 4 for mapping 12 bits to obtain a dual polarization symbol is provided, enriching the implementation of this solution.

[0062] In some possible implementations, based on the above-mentioned mapping rule 4, the first bit distribution pattern is shown in Figure 30(c), the second bit distribution pattern is shown in Figure 30(a), the third bit distribution pattern is shown in Figure 30(b), the fourth bit distribution pattern is shown in Figure 28(c), the fifth bit distribution pattern is shown in Figure 28(a), and the sixth bit distribution pattern is shown in Figure 28(b).

[0063] In some possible implementations, the polarization direction of the first polarization symbol is orthogonal to the deflection direction of the second polarization symbol. The first component is an I-path component and the second component is a Q-path component; or the first component is a Q-path component and the second component is an I-path component.

[0064] In some possible implementations, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2. Performing a third interleaving on the two seventh bit sets to obtain an eighth bit set includes: performing intra-matrix interleaving on the seventh bit set 1 to obtain a tenth bit set 1, and performing intra-matrix interleaving on the seventh bit set 2 to obtain a tenth bit set 2. Wherein, the tenth bit set 1 and the tenth bit set 2 each include 42 rows and 8 columns, totaling 336 fourth bit subsets, and the fourth bit subset includes 16 rows and 16 columns, totaling 256 bits. Performing inter-matrix interleaving on the tenth bit set 1 and the tenth bit set 2 to obtain an eighth bit set, and the eighth bit set includes 84 rows and 8 columns, totaling 672 fourth bit subsets. A specific implementation method of the third interleaving is provided herein, that is, the third interleaving includes intra-matrix interleaving and inter-matrix interleaving, which improves the practicality of this solution.

[0065] In some possible implementations, the first bit set includes a first bit set 1 and a first bit set 2, and performing PCS processing on the first bit set among the multiple bits to obtain the second bit set includes: performing PCS processing on the first bit set 1 to obtain the second bit set 1, and performing PCS processing on the first bit set 2 to obtain the second bit set 2, wherein the second bit set includes the second bit set 1 and the second bit set 2. It should be understood that implementing the two PCS processes helps reduce the complexity of a single PCS process, and simplifies hardware implementation of the single PCS process.

[0066] In some possible implementations, the third bit set includes a third bit set 1 and a third bit set 2. Performing a first interleaving on the second bit set and a third bit set excluding the first bit set in the plurality of bits to obtain two fourth bit sets includes performing a first interleaving on the second bit set 1, the second bit set 2, the third bit set 1, and the third bit set 2 to obtain a fourth bit set 1 and a fourth bit set 2.

[0067] In some possible implementations, the third bit set includes a third bit set 1 and a third bit set 2. Performing a first interleaving on the second bit set and a third bit set excluding the first bit set from the plurality of bits to obtain two fourth bit sets includes: performing a first interleaving on the second bit set 1 and the third bit set 1 to obtain fourth bit set 1, and performing a first interleaving on the second bit set 2 and the third bit set 2 to obtain fourth bit set 2. It should be understood that implementing the first interleaving as two steps helps reduce the complexity of a single first interleaving, and simplifies hardware implementation of the single first interleaving.

[0068] In some possible implementations, performing a first interleaving on the second bit set and a third bit set in multiple bits excluding the first bit set to obtain two fourth bit sets includes: performing a first interleaving on the second bit set 1, the second bit set 2, and the third bit set to obtain fourth bit set 1 and fourth bit set 2.

[0069] In some possible implementations, the amplitude bits mapped to the dual-polarization symbols come from the second bit set, and the sign bits mapped to the dual-polarization symbols come from the third bit set and / or FEC-coded parity bits.

[0070] In some possible implementations, before performing PCS processing on the first bit set of e bits to obtain the second bit set, the method further includes: obtaining first data from a data frame, the first data including r rows and q columns of bits, where r is an integer greater than 0, and q is an integer greater than 0. Performing a cyclic redundancy check (CRC) on the first data and / or inserting padding bits to obtain second data, the second data including d bits to which the CRC is inserted.CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0. The second data is scrambled to obtain the third data, and the number of bits of the third data is d scr =r×q+d CP , d CP =d CRC +d PAD e×L bits are obtained from the third data, and the e×L bits are divided into L groups of bits, each of the L groups of bits including e bits.

[0071] In some possible implementations, d scr =168×e.

[0072] In some possible implementations, d scr =84×e.

[0073] In some possible implementations, d scr =12×e.

[0074] In some possible implementations, after performing a third interleaving on two seventh bit sets to obtain an eighth bit set, the method further includes: combining L eighth bit sets to obtain fourth data; performing symbol mapping and polarization division on the fourth data to obtain a dual-polarization symbol stream, wherein every 12 consecutive bits in the fourth data are mapped to obtain one dual-polarization symbol; and performing DSP framing on the dual-polarization symbol stream.

[0075] In a second aspect, an embodiment of the present application provides a data processing device. The data processing device includes: a PCS unit, a first interleaving unit, an FEC encoding unit, a second interleaving unit, and a third interleaving unit. The PCS unit is configured to perform PCS processing on a first bit set among a plurality of bits to obtain a second bit set. The first interleaving unit is configured to perform a first interleaving on the second bit set and a third bit set among the plurality of bits, excluding the first bit set, to obtain two fourth bit sets, wherein the two fourth bit sets include a fourth bit set 1 and a fourth bit set 2. The FEC encoding unit is configured to perform FEC encoding on two fifth bit sets to obtain two sixth bit sets, wherein the fifth bit set 1 among the two fifth bit sets includes at least one fourth bit set 1, and the fifth bit set 2 among the two fifth bit sets includes at least one fourth bit set 2. The second interleaving unit is configured to perform a second interleaving on the two sixth bit sets to obtain two seventh bit sets. The third interleaving unit is configured to perform a third interleaving on the two seventh bit sets to obtain an eighth bit set.

[0076] Among them, 12 consecutive bits in the eighth bit set are used to map to obtain a dual polarization symbol, the dual polarization symbol includes a first polarization symbol and a second polarization symbol, the 0th bit, the 2nd bit, the 4th bit, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used to map to the first polarization symbol, the 1st bit, the 3rd bit, the 5th bit, the 7th bit, the 9th bit and the 11th bit of the 12 bits are used to map to the second polarization symbol, 4 bits of the 12 bits used to map to the first polarization symbol come from the second bit set, the other 2 bits of the 12 bits used to map to the first polarization symbol come from the third bit set and / or FEC-encoded check bits, 4 bits of the 12 bits used to map to the second polarization symbol come from the second bit set, and the other 2 bits of the 12 bits used to map to the second polarization symbol come from the third bit set and / or FEC-encoded check bits.

[0077] In some possible implementations, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2. Each of the seventh bit set 1 and the seventh bit set 2 includes 42 rows and 8 columns, totaling 336 first bit subsets. The first bit subset includes 16 rows and 16 columns, totaling 256 bits. It should be understood that the bit distribution pattern of the first bit subset is used to indicate the positions of bits from the second bit set in the first bit subset and the positions of bits from the third bit set and / or FEC-coded parity bits in the first bit subset. The bit distribution patterns of the first bit subsets in different rows of the two seventh bit sets are described below.

[0078] The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 1 is the first bit distribution pattern.

[0079] The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 1 is the second bit distribution pattern.

[0080] The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 1 is the third bit distribution pattern.

[0081] The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 2 is the third bit distribution pattern.

[0082] The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 2 is the first bit distribution pattern.

[0083] The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 2 is the second bit distribution pattern.

[0084] In some possible implementations, the second interleaving unit includes a fourth interleaving unit and a fifth interleaving unit. The fourth interleaving unit is configured to perform a fourth interleaving on each of the two sixth bit sets to obtain two ninth bit sets. The two ninth bit sets include a ninth bit set 1 and a ninth bit set 2, each of which includes 42 rows and 8 columns, totaling 336 second bit subsets, and the second bit subset includes 16 rows and 16 columns, totaling 256 bits. The fifth interleaving unit is configured to perform a fifth interleaving on each of the two ninth bit sets to obtain two seventh bit sets, wherein the fifth interleaving is used to interleave the 16 bits in each row of each second bit subset in the ninth bit set.

[0085] In some possible implementations, the bit distribution pattern of the second bit subset is used to indicate positions of bits from the second bit set and positions of bits from the third bit set and / or FEC-coded parity bits within the second bit subset. The bit distribution patterns of the second bit subsets in different rows of the two ninth bit sets are described below.

[0086] The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 1 is the fourth bit distribution pattern.

[0087] The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 1 is the fifth bit distribution pattern.

[0088] The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 1 is the sixth bit distribution pattern.

[0089] The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 2 is the sixth bit distribution pattern.

[0090] The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 2 is the fourth bit distribution pattern.

[0091] The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 2 is the fifth bit distribution pattern.

[0092] In some possible implementations, the two sixth bit sets include a sixth bit set 1 and a sixth bit set 2. The sixth bit set 1 and the sixth bit set 2 each include 42 rows and 8 columns, totaling 336 third bit subsets. The third bit subset includes 16 rows and 16 columns, totaling 256 bits. In the 42 rows and 8 columns, totaling 336 third bit subsets, the bits in the third bit subset from columns 0 to 4 are from the second bit set and the third bit set, the bits in the third bit subset from column 5 and the bits from columns 0 to 14 in the third bit subset from column 6 are from the second bit set, and the bits in column 15 of the third bit subset from column 6 and the bits in the third bit subset from column 7 are parity bits for FEC coding.

[0093] In some possible implementations, the bit distribution pattern of the third bit subset is used to indicate the positions of bits from the second bit set in the third bit subset and the positions of bits from the third bit set and / or FEC-coded parity bits in the third bit subset. The bit distribution patterns of the third bit subset in different rows of the two sixth bit sets are described below.

[0094] The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 1 is the fourth bit distribution pattern.

[0095] The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 1 is the fifth bit distribution pattern.

[0096] The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 1 is the sixth bit distribution pattern.

[0097] The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 2 is the sixth bit distribution pattern.

[0098] The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 2 is the fourth bit distribution pattern.

[0099] The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 2 is the fifth bit distribution pattern.

[0100] In some possible implementations, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2. The seventh bit set 1 and the seventh bit set 2 each include 42 rows and 8 columns, totaling 336 first bit subsets. The first bit subset includes 16 rows and 16 columns, totaling 256 bits. The bit distribution pattern of the first bit subset is used to indicate the positions of bits from the second bit set in the first bit subset and the positions of bits from the third bit set and / or FEC-coded parity bits in the first bit subset. The bit distribution patterns of the first bit subsets in different rows of the two seventh bit sets are described below.

[0101] The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 1 is the first bit distribution pattern.

[0102] The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 1 is the second bit distribution pattern.

[0103] The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 1 is the third bit distribution pattern.

[0104] The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 2 is the second bit distribution pattern.

[0105] The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 2 is the third bit distribution pattern.

[0106] The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 2 is the first bit distribution pattern.

[0107] In some possible implementations, the second interleaving unit includes a fourth interleaving unit and a fifth interleaving unit. The fourth interleaving unit is configured to perform a fourth interleaving on each of the two sixth bit sets to obtain two ninth bit sets. The two ninth bit sets include a ninth bit set 1 and a ninth bit set 2, each of which includes 42 rows and 8 columns, totaling 336 second bit subsets, and the second bit subset includes 16 rows and 16 columns, totaling 256 bits. The fifth interleaving unit is configured to perform a fifth interleaving on each of the two ninth bit sets to obtain two seventh bit sets, wherein the fifth interleaving is used to interleave the 16 bits in each row of each second bit subset in the ninth bit set.

[0108] In some possible implementations, the bit distribution pattern of the second bit subset is used to indicate positions of bits from the second bit set and positions of bits from the third bit set and / or FEC-coded parity bits within the second bit subset. The bit distribution patterns of the second bit subsets in different rows of the two ninth bit sets are described below.

[0109] The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 1 is the fourth bit distribution pattern.

[0110] The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 1 is the fifth bit distribution pattern.

[0111] The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 1 is the sixth bit distribution pattern.

[0112] The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 2 is the fifth bit distribution pattern.

[0113] The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 2 is the sixth bit distribution pattern.

[0114] The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 2 is the fourth bit distribution pattern.

[0115] In some possible implementations, the two sixth bit sets include a sixth bit set 1 and a sixth bit set 2. The sixth bit set 1 and the sixth bit set 2 each include 42 rows and 8 columns, totaling 336 third bit subsets. The third bit subset includes 16 rows and 16 columns, totaling 256 bits. In the 42 rows and 8 columns, totaling 336 third bit subsets, the bits in the third bit subset from columns 0 to 4 are from the second bit set and the third bit set, the bits in the third bit subset from column 5 and the bits from columns 0 to 14 in the third bit subset from column 6 are from the second bit set, and the bits in column 15 of the third bit subset from column 6 and the bits in the third bit subset from column 7 are parity bits for FEC coding.

[0116] In some possible implementations, the bit distribution pattern of the third bit subset is used to indicate the positions of bits from the second bit set in the third bit subset and the positions of bits from the third bit set and / or FEC-coded parity bits in the third bit subset. The bit distribution patterns of the third bit subset in different rows of the two sixth bit sets are described below.

[0117] The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 1 is the fourth bit distribution pattern.

[0118] The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 1 is the fifth bit distribution pattern.

[0119] The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 1 is the sixth bit distribution pattern.

[0120] The bit distribution pattern of the third bit subset of rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 2 is the fifth bit distribution pattern.

[0121] The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 2 is the sixth bit distribution pattern.

[0122] The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 2 is the fourth bit distribution pattern.

[0123] In some possible implementations, the 0th, 2nd, and 4th bits of the 12 bits are used to map to the first component of the first polarization symbol, the 6th, 8th, and 10th bits of the 12 bits are used to map to the second component of the first polarization symbol, the 1st, 3rd, and 5th bits of the 12 bits are used to map to the first component of the second polarization symbol, and the 7th, 9th, and 11th bits of the 12 bits are used to map to the second component of the second polarization symbol. A specific mapping rule 1 for mapping 12 bits to obtain a dual polarization symbol is provided herein, which has good practical effects.

[0124] In some possible implementations, based on the above-mentioned mapping rule 1, the first bit distribution pattern is shown in Figure 22(a), the second bit distribution pattern is shown in Figure 22(b), the third bit distribution pattern is shown in Figure 22(c), the fourth bit distribution pattern is shown in Figure 11(a), the fifth bit distribution pattern is shown in Figure 11(b), and the sixth bit distribution pattern is shown in Figure 11(c).

[0125] In some possible implementations, the 0th, 4th, and 6th bits of the 12 bits are used to map to the first component of the first polarization symbol, the 2nd, 8th, and 10th bits of the 12 bits are used to map to the second component of the first polarization symbol, the 1st, 5th, and 7th bits of the 12 bits are used to map to the first component of the second polarization symbol, and the 3rd, 9th, and 11th bits of the 12 bits are used to map to the second component of the second polarization symbol. Another specific mapping rule 2 for mapping 12 bits to obtain a dual polarization symbol is provided herein, enriching the implementation of this solution.

[0126] In some possible implementations, based on the above-mentioned mapping rule 2, the first bit distribution pattern is shown in Figure 30(a), the second bit distribution pattern is shown in Figure 30(b), the third bit distribution pattern is shown in Figure 30(c), the fourth bit distribution pattern is shown in Figure 28(a), the fifth bit distribution pattern is shown in Figure 28(b), and the sixth bit distribution pattern is shown in Figure 28(c).

[0127] In some possible implementations, the 8th bit, the 0th bit, and the 2nd bit of the 12 bits are used to map to the first component of the first polarization symbol, the 10th bit, the 4th bit, and the 6th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 9th bit, the 1st bit, and the 3rd bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 11th bit, the 5th bit, and the 7th bit of the 12 bits are used to map to the second component of the second polarization symbol. Here, another specific mapping rule 3 for mapping 12 bits to obtain a dual polarization symbol is provided, enriching the implementation of this solution.

[0128] In some possible implementations, based on the above-mentioned mapping rule 3, the first bit distribution pattern is shown in Figure 30(b), the second bit distribution pattern is shown in Figure 30(c), the third bit distribution pattern is shown in Figure 30(a), the fourth bit distribution pattern is shown in Figure 28(b), the fifth bit distribution pattern is shown in Figure 28(c), and the sixth bit distribution pattern is shown in Figure 28(a).

[0129] In some possible implementations, the 4th bit, the 0th bit, and the 2nd bit of the 12 bits are used to map to the first component of the first polarization symbol, the 6th bit, the 8th bit, and the 10th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 5th bit, the 1st bit, and the 3rd bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 7th bit, the 9th bit, and the 11th bit of the 12 bits are used to map to the second component of the second polarization symbol. Here, another specific mapping rule 4 for mapping 12 bits to obtain a dual polarization symbol is provided, enriching the implementation of this solution.

[0130] In some possible implementations, based on the above-mentioned mapping rule 4, the first bit distribution pattern is shown in Figure 30(c), the second bit distribution pattern is shown in Figure 30(a), the third bit distribution pattern is shown in Figure 30(b), the fourth bit distribution pattern is shown in Figure 28(c), the fifth bit distribution pattern is shown in Figure 28(a), and the sixth bit distribution pattern is shown in Figure 28(b).

[0131] In some possible implementations, the polarization direction of the first polarization symbol is orthogonal to the deflection direction of the second polarization symbol. The first component is an I-path component and the second component is a Q-path component; or the first component is a Q-path component and the second component is an I-path component.

[0132] In some possible implementations, the two seventh bit sets include a seventh bit set 1 and a seventh bit set 2. The third interleaving unit includes an intra-matrix interleaving unit 1, an intra-matrix interleaving unit 2, and an inter-matrix interleaving unit. The intra-matrix interleaving unit 1 is configured to perform intra-matrix interleaving on the seventh bit set 1 to obtain a tenth bit set 1. The intra-matrix interleaving unit 2 is configured to perform intra-matrix interleaving on the seventh bit set 2 to obtain a tenth bit set 2. The inter-matrix interleaving unit performs inter-matrix interleaving on the tenth bit set 1 and the tenth bit set 2 to obtain an eighth bit set, which includes 84 rows and 8 columns, totaling 672 fourth bit subsets.

[0133] In some possible implementations, the first bit set includes a first bit set 1 and a first bit set 2. The PCS unit includes a first PCS subunit and a second PCS subunit. The first PCS subunit is configured to perform PCS processing on the first bit set 1 to obtain the second bit set 1. The second PCS subunit is configured to perform PCS processing on the first bit set 2 to obtain the second bit set 2. The second bit set includes the second bit set 1 and the second bit set 2.

[0134] In some possible implementations, the third bit set includes a third bit set 1 and a third bit set 2. The first interleaving unit is specifically configured to perform a first interleaving on the second bit set 1, the second bit set 2, the third bit set 1, and the third bit set 2 to obtain a fourth bit set 1 and a fourth bit set 2.

[0135] In some possible implementations, the third bit set includes a third bit set 1 and a third bit set 2. The first interleaving unit includes a first interleaving subunit and a second interleaving subunit. The first interleaving subunit is configured to perform a first interleaving on the second bit set 1 and the third bit set 1 to obtain a fourth bit set 1. The second interleaving subunit is configured to perform a first interleaving on the second bit set 2 and the third bit set 2 to obtain a fourth bit set 2.

[0136] In some possible implementations, the first interleaving unit is specifically configured to perform a first interleaving on the second bit set 1 , the second bit set 2 , and the third bit set to obtain the fourth bit set 1 and the fourth bit set 2 .

[0137] In some possible implementations, the amplitude bits mapped to the dual-polarization symbols come from the second bit set, and the sign bits mapped to the dual-polarization symbols come from the third bit set and / or FEC-coded parity bits.

[0138] In some possible implementations, the data processing device further includes a first processing unit. Specifically, before performing PCS processing on the first bit set of e bits to obtain the second bit set, the first processing unit is configured to: obtain first data from a data frame, where the first data includes r rows and q columns of bits, where r is an integer greater than 0, and q is an integer greater than 0. Perform CRC on the first data and / or insert padding bits to obtain second data, where the second data includes d bits for which CRC insertion is performed. CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0. The second data is scrambled to obtain the third data, and the number of bits of the third data is d scr =r×q+d CP , d CP =d CRC +d PAD e×L bits are obtained from the third data, and the e×L bits are divided into L groups of bits, each of the L groups of bits including e bits.

[0139] In some possible implementations, d scr =168×e.

[0140] In some possible implementations, d scr =84×e.

[0141] In some possible implementations, d scr =12×e.

[0142] In some possible implementations, the data processing apparatus further includes a second processing unit. After performing a third interleaving on the two seventh bit sets to obtain an eighth bit set, the second processing unit is configured to: combine L eighth bit sets to obtain fourth data; perform symbol mapping and polarization division on the fourth data to obtain a dual-polarization symbol stream, wherein each 12 consecutive bits in the fourth data are mapped to obtain a dual-polarization symbol; and perform DSP framing on the dual-polarization symbol stream.

[0143] In a third aspect, the present application provides a chip comprising a processor configured to execute the method described in any embodiment of the first aspect.

[0144] In a fourth aspect, embodiments of the present application provide an optical module. The optical module includes a processor and an interface, wherein the processor is configured to execute the method described in any embodiment of the first aspect and to send signals through the interface. For example, the interface is configured to send signals from the processor or transmit received signals to the processor.

[0145] In some possible implementations, the interface is specifically an electrical interface, and the processor is configured to send electrical signals via the interface. For example, the processor executes the method described in any implementation of the first aspect and performs data processing on the eighth bit set to obtain a DSP superframe, and then sends the DSP superframe via the interface. The data processing herein includes symbol mapping, polarization division, and DSP framing.

[0146] In some possible implementations, the interface is specifically an optical interface, and the optical module further includes a modulator. For example, the processor executes the method described in any implementation of the first aspect and performs data processing on the eighth bit set to obtain a DSP superframe. The modulator then performs signal processing such as electro-optical conversion based on the DSP superframe to obtain an optical signal, which is then transmitted via the interface. The data processing herein includes symbol mapping, polarization division, and DSP framing.

[0147] In a fifth aspect, an embodiment of the present application provides a sending device, which includes a host-side device and an optical module as described in any embodiment of the fourth aspect, wherein the optical module is configured to generate an optical signal based on data from the host-side device and send the optical signal.

[0148] In a sixth aspect, an embodiment of the present application provides a communication system, which includes the sending device and receiving device introduced in the fifth aspect, and the sending device is used to send an optical signal to the receiving device.

[0149] In a seventh aspect, the present application provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed by a computer, the method described in any embodiment of the first aspect is implemented.

[0150] In an eighth aspect, the present application provides a computer program product, which includes program instructions. When the computer program product is executed, it is used to implement the method introduced in any embodiment of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0151] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application;

[0152] FIG2 is a schematic diagram of the structure of a data frame;

[0153] FIG3 is a schematic diagram of an embodiment of the first data processing in an embodiment of the present application;

[0154] FIG4( a ) is a schematic diagram of an embodiment of the second data processing in an embodiment of the present application;

[0155] FIG4( b ) is a schematic diagram of an embodiment of the second data sub-processing in an embodiment of the present application;

[0156] FIG5( a ) is a schematic diagram of an embodiment of the third data processing in an embodiment of the present application;

[0157] FIG5( b ) is a schematic diagram of another embodiment of the third data processing in the embodiment of the present application;

[0158] FIG5( c ) is a schematic diagram of another embodiment of the third data processing in the embodiment of the present application;

[0159] FIG6( a ) is a schematic diagram of an embodiment of PCS processing and first interleaving in an embodiment of the present application;

[0160] FIG6( b ) is a schematic diagram of another embodiment of PCS processing and first interleaving in an embodiment of the present application;

[0161] FIG6( c ) is a schematic diagram of another embodiment of PCS processing and first interleaving in an embodiment of the present application;

[0162] FIG6( d ) is a schematic diagram of another embodiment of PCS processing and first interleaving in an embodiment of the present application;

[0163] FIG7 is a schematic diagram of a bit block with 7 columns per row in an embodiment of the present application;

[0164] FIG8 is a schematic diagram of a fifth bit set in an embodiment of the present application;

[0165] FIG9 is a schematic diagram of a 16×16 bit block in an embodiment of the present application;

[0166] FIG10 is a schematic diagram of a 16×15 bit block in an embodiment of the present application;

[0167] FIG11( a ) is a schematic diagram of a first bit pattern in an embodiment of the present application;

[0168] FIG11( b ) is a schematic diagram of a second bit pattern in an embodiment of the present application;

[0169] FIG11( c ) is a schematic diagram of a third bit pattern in an embodiment of the present application;

[0170] FIG12( a ) is a schematic diagram of a fourth bit pattern in an embodiment of the present application;

[0171] FIG12( b ) is a schematic diagram of a fifth bit pattern in an embodiment of the present application;

[0172] FIG12( c ) is a schematic diagram of a sixth bit pattern in an embodiment of the present application;

[0173] FIG12( d ) is a schematic diagram of another fourth bit pattern in an embodiment of the present application;

[0174] FIG12( e ) is a schematic diagram of another fifth bit pattern in an embodiment of the present application;

[0175] FIG12( f ) is a schematic diagram of another sixth bit pattern in an embodiment of the present application;

[0176] FIG13 is a schematic diagram of a seventh bit pattern in an embodiment of the present application;

[0177] FIG14 is a schematic diagram of an eighth bit pattern in an embodiment of the present application;

[0178] FIG15 is a schematic diagram of an implementation method of data processing of two first bit streams in an embodiment of the present application;

[0179] FIG16 is a schematic diagram of a bit block with 8 columns per row according to an embodiment of the present application;

[0180] FIG17 is a schematic diagram of a sixth bit set in an embodiment of the present application;

[0181] FIG18( a ) is a schematic diagram of a ninth bit pattern in an embodiment of the present application;

[0182] FIG18( b ) is a schematic diagram of a tenth bit pattern in an embodiment of the present application;

[0183] FIG19 is a schematic diagram of a ninth bit set according to an embodiment of the present application;

[0184] FIG20 is a schematic diagram of a seventh bit set in an embodiment of the present application;

[0185] FIG21 is a schematic diagram of an implementation of the fifth interweaving in an embodiment of the present application;

[0186] FIG22( a ) is a schematic diagram of an eleventh bit pattern in an embodiment of the present application;

[0187] FIG22( b ) is a schematic diagram of a twelfth bit pattern in an embodiment of the present application;

[0188] FIG22( c ) is a schematic diagram of a thirteenth bit pattern in an embodiment of the present application;

[0189] FIG23 is a schematic diagram of an implementation method of interweaving within a square matrix according to an embodiment of the present application;

[0190] FIG24( a ) is a schematic diagram of a fourteenth bit pattern in an embodiment of the present application;

[0191] FIG24( b ) is a schematic diagram of a fifteenth bit pattern in an embodiment of the present application;

[0192] FIG24( c ) is a schematic diagram of a sixteenth bit pattern in an embodiment of the present application;

[0193] FIG25 is a schematic diagram of an embodiment of inter-matrix interleaving in an embodiment of the present application;

[0194] FIG26 is a schematic diagram of a bit set after interleaving between square matrices in an embodiment of the present application;

[0195] FIG27 is a schematic diagram of a constellation diagram in a polarization direction according to an embodiment of the present application;

[0196] FIG28( a ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0197] FIG28( b ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0198] FIG28( c ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0199] FIG29( a ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0200] FIG29( b ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0201] FIG29( c ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0202] FIG30( a ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0203] FIG30( b ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0204] FIG30( c ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0205] FIG31( a ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0206] FIG31( b ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0207] FIG31( c ) is a schematic diagram of another bit pattern in an embodiment of the present application;

[0208] FIG32 is a schematic diagram of an application scenario of the second data processing in an embodiment of the present application;

[0209] FIG33 is a schematic diagram of another application scenario of the second data processing in an embodiment of the present application;

[0210] FIG34( a ) is a schematic diagram showing a bit distribution of the last 51 bit columns in the sixth bit set 2i and the sixth bit set 2i+1 according to an embodiment of the present application;

[0211] FIG34( b ) is a schematic diagram of a bit distribution of a ninth bit set 2i in an embodiment of the present application;

[0212] FIG34( c ) is a schematic diagram of a bit distribution of the ninth bit set 2i+1 according to an embodiment of the present application;

[0213] FIG35( a ) is a schematic diagram showing a bit distribution of the last 54-bit columns in the sixth bit set 2i and the sixth bit set 2i+1 according to an embodiment of the present application;

[0214] FIG35( b ) is a schematic diagram of a bit distribution of a ninth bit set 2i in an embodiment of the present application;

[0215] FIG35( c ) is a schematic diagram of a bit distribution of the ninth bit set 2i+1 according to an embodiment of the present application;

[0216] FIG36 is a schematic diagram of another application scenario of the second data processing in an embodiment of the present application;

[0217] FIG37 is a schematic diagram of another embodiment of inter-matrix interleaving according to an embodiment of the present application;

[0218] FIG38 is a schematic diagram of another application scenario of the second data processing in an embodiment of the present application;

[0219] FIG39 is a schematic structural diagram of a data processing device according to an embodiment of the present application;

[0220] FIG40 is a schematic structural diagram of an optical module according to an embodiment of the present application;

[0221] Figure 41 is a structural diagram of a sending device in an embodiment of the present application. DETAILED DESCRIPTION

[0222] The embodiments of the present application provide a data processing method and a data processing device, which will adopt DP-64QAM modulation and combine FEC coding, interleaving and PCS technology to ensure that the overall data processing operation is simple, low in complexity and low in power consumption, while improving spectrum utilization and enhancing system transmission performance to meet the needs of future metropolitan area telecommunications transmission and metropolitan area DCI interconnection scenarios.

[0223] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or precedence. It should be understood that the above terms can be interchangeable where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0224] FIG1 is a schematic diagram of a communication system used in an embodiment of the present application. As shown in FIG1 , at the transmitting end, a signal source provides a data stream to be transmitted, and a transmitting data processor receives the data stream. The transmitting data processor first performs data processing including PCS processing, encoding, interleaving, modulation, and DSP framing to obtain a symbol data stream, which is then sent to the transmitting signal processor for signal processing, and then transmitted through the channel to the receiving device. After the receiving device receives the distorted signal caused by noise or other damage in the channel, it is sent to the receiving signal processor for dispersion compensation, synchronization, phase recovery, and other operations. The signal is then sent to the receiving data processor for operations including demodulation, deinterleaving, decoding, etc. to recover the original data, and the recovered data is sent to the destination.

[0225] It should be noted that some of the operation symbols appearing in the formulas involved in the embodiments of this application, Operation, which means rounding a down to an integer. For example, The b%c operation in the embodiments of the present application represents the modulus of b with respect to c. When b is non-negative, the value of b%c is the remainder of b divided by c. For example, 8%3=2, 2%3=3. When b is negative, the value of b%c is the modulus of b plus an integer multiple of c to obtain a positive integer. For example, -9%16=7, -10%3=2.

[0226] It should be noted that the concepts of bit sets and bit subsets in this specification and claims are merely introduced for ease of description. In practical applications, the data stream is a whole and not divided. Each bit set or bit subset can be considered as one or more bits in the data stream. It should be understood that bit sets and bit subsets can also be presented in the form of matrices, arrays, sequences, etc., which are not specifically limited here.

[0227] Figure 2 is a schematic diagram of the structure of a data frame. As shown in Figure 2, the data frame includes multiple rows of bits, and each row includes q bits. It should be understood that this application does not limit the specific type of data frame. As an example, an 800ZR frame, a FlexO-8 frame, or a FlexO-8e frame includes 512 rows, each row including 10280 bits. As another example, to better adapt to PCS processing, an 800ZR frame, a FlexO-8 frame, or a FlexO-8e frame can be represented by including 2560 rows, each row including 2056 bits. As another example, a 1.6T data frame includes 5120 rows, each row including 2056 bits. As another example, a 1.2T data frame includes 3840 rows, each row including 2056 bits. In some specific applications, the integer q is an integer multiple of 257; typically, q is 10280, 8224, 4112, or 2056, etc.

[0228] It should be noted that the data processing method provided in this application can be divided into three parts, respectively referred to as "first data processing," "second data processing," and "third data processing." The following details each of the "first data processing," "second data processing," and "third data processing."

[0229] FIG3 is a schematic diagram of an embodiment of the first data processing in an embodiment of the present application. As shown in FIG3, the first data processing includes a cyclic redundancy check (CRC), pad insertion, and scrambling. In practical applications, at least one of the CRC and pad insertion operations can be performed. Specifically, the first bit data is obtained from the data frame. The first bit data includes r rows and q columns of bits, where r is an integer greater than 0, q is an integer greater than 0, and r is used uniformly thereafter. Frame To indicate the r rows that the first bit of data includes.

[0230] As an example, the first bit of data is d in =q×r Frame bits. Then, the first bit data is CRCed and / or filled with padding bits to obtain the second bit data. In the CRC operation, d CRCCRC check bits are inserted during the padding operation. PAD Then, the second bit data is scrambled to obtain the third bit data. The number of bits of the third bit data is d scr =q×r Frame +d CRC +d PAD scrambled bits. CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0, which can be expressed as d CP =d CRC +d PAD At this time, the redundancy corresponding to the CRC checksum and inserted padding bits is OH CP =d scr / d in -1=(d CRC +d PAD ) / (q×r Frame ).

[0231] As an example, when d PAD = 0, the q×r after CRC check Frame +d CRC As another example, in order to achieve lower latency and lower complexity, the CRC check is bypassed and replaced with padding bits, that is, d CRC =0.

[0232] It should be noted that in some specific application scenarios, CRC check uses CRC-32. As an example, a total of p CRC-32 operations are performed on the first bit of data, where p is an integer greater than 1 and the integer r Frame can be divided by p. At this time, d CRC =32×p. More specifically, for r obtained from the data frame Frame Row data, each r Frame / p rows total q×r Frame / p bits perform CRC-32 operation to add 32-bit check bits, repeat the CRC-32 operation p times to add a total of d CRC =32×p bits of CRC-32 check bits.

[0233] It should be noted that, in some other specific application scenarios, a total of p CRC-32 operations are performed on the first bit of data, where p is an integer greater than 1 but the integer r Frame cannot be divided by p. At this time, consider r F0 ×(p-1)+r F1 =r Frame , where the integer rF0 Greater than an integer r F1 In some implementations, the integer integer r F1 =r Frame -r F0 ×(p-1), and r F0 >r F1 The following is a specific implementation method for obtaining r from the data frame. Frame Row data, for r Frame The first row of data F0 ×(p-1) rows of each r F0 Rows total q×r F0 The bits are CRC-32 added with 32-bit check bits, and a total of 32×(p-1) CRC check bits are obtained; the last r F1 Rows total q×r F1 Perform a CRC-32 operation on each bit and add a 32-bit check bit. The total number of bits is d CRC =32×(p-1)+32=32×p CRC-32 check bits. It should be noted that in some specific implementations, q×r F0 =41120, then the CRC-32 encoding and corresponding CRC check operation can directly use the CRC-32 operation in the existing 800G-ZR, where the existing 800GZR performs a CRC-32 operation on 4 rows and 10280 columns of 4×10280=41120 bits of data. In some specific implementations, q=2056 and r F0 =20.

[0234] FIG4( a ) is a schematic diagram of an embodiment of the second data processing in an embodiment of the present application. As shown in FIG4( a ), multiple bits of data are obtained from the third bit of data output after the first data processing and are polled and sent to L second data sub-processes (i.e., second data sub-process 0, second data sub-process 1, ..., second data sub-process L-1). For example, each second data sub-process inputs e bits. After L second data sub-processes, L data streams can be obtained. Then, the L data streams are merged to obtain the output of the second data processing, i.e., the fourth bit of data in FIG4( a ), where L is an integer greater than 0.

[0235] Figure 4(b) is a schematic diagram of an embodiment of the second data sub-processing in an embodiment of the present application. As shown in Figure 4(b), the operations of the second data sub-processing i (i=0,1,…,L-1) include PCS processing and first interleaving (i.e., "PCS processing and first interleaving i" in Figure 4(b)), FEC coding (i.e., "FEC coding 2i" and "FEC coding 2i+1" in Figure 4(b)), second interleaving (i.e., "second interleaving 2i" and "second interleaving 2i+1" in Figure 4(b)), and third interleaving (i.e., "third interleaving i" in Figure 4(b)). The third interleaving includes intra-matrix interleaving (i.e., "intra-matrix interleaving 2i" and "intra-matrix interleaving 2i+1" in Figure 4(b)) and inter-matrix interleaving (i.e., "inter-matrix interleaving i" in Figure 4(b)). The third interleaving is also called block interleaving. It should be understood that the various interleaving operations mentioned in the embodiments of the present application may also have other names in different scenarios. For example, interleaving may also be referred to as permutation or reordering.

[0236] Specifically, the second data sub-processing obtains multiple bits and performs PCS processing and first interleaving to obtain two first bit streams. The two first bit streams are respectively subjected to FEC encoding to obtain two second bit streams. The two second bit streams are respectively subjected to second interleaving to obtain two third bit streams. The two third bit streams are respectively subjected to third interleaving to obtain a fourth bit stream, i.e., an output data stream of the second data sub-processing. It should be understood that in some possible scenarios, the second interleaving can be a single operation, or the second interleaving can be divided into two operations: the fourth interleaving and the fifth interleaving, which will be described in detail below.

[0237] A total of L second data sub-processing output bit streams are obtained through L second data sub-processings, and one second data processing output bit stream is obtained through merging (Merge). The second data processing output bit stream contains multiple fourth-bit data. Typically, the merging operation obtains S bits from each second data sub-processing output bit stream to obtain a total of S×L bits, which are used as continuous S×L bits in the second data processing output bit stream. The merging operation can be called block merging (Block Merge) or multiplexing (MUX). It should be noted that when L=1, that is, there is only one second data sub-processing output bit stream, and the second data processing output bit stream can be obtained without merging. As an example, L can be 2 or 4 or 8, etc., which is not limited here.

[0238] Figure 5 (a) is a schematic diagram of an embodiment of the third data processing in an embodiment of the present application. As shown in Figure 5 (a), the fourth bit data is subjected to symbol mapping (Symbol Mapping) and polarization distribution (Polarization Distribution) to obtain a dual-polarization symbol sequence, wherein the symbol mapping and polarization distribution map every 12 bits in the fourth bit data to 1 dual-polarization symbol. Furthermore, a DSP framing operation is performed on the dual-polarization symbol sequence. Specifically, a frame alignment symbol sequence (Frame Alignment Word Sequence, referred to as FAW Sequence) and a training symbol sequence (Training Sequence) are respectively inserted in the X polarization (X polarization) direction and the Y polarization (Y polarization) direction, and at least one sequence of the symbol sequence (Reserved Fields) and the pilot symbol sequence (Pilot Sequence) is retained to obtain a dual-polarization symbol sequence to be sent. For example, the DSP framing operation performs DSP framing processing on every 172032 dual-polarization symbols to obtain a DSP superframe. In some specific applications, a superframe contains 175104 dual-polarization symbols. In some embodiments, in the X polarization direction or the Y polarization direction, every N G A fixed symbol in the N symbols is a pilot symbol. G The first symbol among the symbols is the pilot symbol. Typically, N G =32 or 64 or 96 or 128, etc.

[0239] It should be noted that frame synchronization symbols are used for frame synchronization alignment, training symbols are used for link training, pilot symbols are used for carrier phase recovery, and reserved symbols are reserved for future use and innovation. The values ​​of reserved symbols can be known and unchanging, or they can be randomized. The values ​​of reserved symbols can also be referred to as patterns. In some specific embodiments, a super-frame can also be referred to as a multi-frame, the reserved symbols can also be referred to as fixed stuff (FS), and the frame synchronization symbols can also be referred to as a multi-frame alignment signal (MFAS).

[0240] It should be noted that the DSP framing operation shown in Figure 5(a) operates on symbols. The DSP framing operation can also operate on bits, as shown in Figures 5(b) and 5(c). Figure 5(b) is a schematic diagram of another embodiment of the third data processing in the embodiment of the present application. As shown in Figure 5(b), the DSP framing operation can also insert bits corresponding to the frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence into the fourth bit of data before symbol mapping, and then after symbol mapping and polarization division, a superframe identical to the operation in Figure 5(a) can be obtained. Figure 5(c) is a schematic diagram of another embodiment of the third data processing in the embodiment of the present application. As shown in Figure 5(c), the DSP framing operation can also insert bits corresponding to the frame synchronization symbol sequence, training symbol sequence, reserved symbol sequence, and pilot symbol sequence into the fourth bit of data before symbol mapping, and then after polarization division and symbol mapping, a superframe identical to the operation in Figure 5(a) can be obtained. It should be understood that other framing operations are not excluded, and this application will not elaborate on them.

[0241] As shown in Figure 4(a) and Figure 4(b), the bit streams output by the third interleaving are merged to obtain the fourth bit data, and the fourth bit data is subjected to symbol mapping and polarization division to obtain a dual-polarization symbol. Specifically, a total of L bit streams output by the third interleaving are polled and merged in a group of S=12 bits, and then symbol mapping is performed (i.e., the 12 bits output from the third interleaving 0 are mapped to a dual-polarization modulation symbol, and then the 12 bits output from the third interleaving 1 are mapped to a dual-polarization modulation symbol, and then the 12 bits output from the third interleaving L-1 are mapped to a dual-polarization modulation symbol). For the case of dual-polarization 64QAM modulation (DP-64QAM), symbol mapping and polarization division will divide every 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 ,b 11 ) is mapped to a DP-64QAM symbol. A dual-polarization symbol consists of an X-polarization symbol and a Y-polarization symbol, where the X-polarization and Y-polarization symbols are orthogonal to each other. The X-polarization symbol includes the in-phase component and the Q-phase component of the X-polarization, while the Y-polarization symbol includes the in-phase component and the Q-phase component of the Y-polarization.

[0242] It should be noted that b0, b2, b4, b6, b8 and b 10 Used to map to the X polarization symbol, b1, b3, b5, b7, b9 and b in 12 bits11 For mapping to the Y polarization symbol, 4 bits of the 12 bits for mapping to the X polarization symbol come from the second bit set, and the other 2 bits of the 12 bits for mapping to the X polarization symbol come from the third bit set and / or the check bits of the FEC encoding, and 4 bits of the 12 bits for mapping to the Y polarization symbol come from the second bit set, and the other 2 bits of the 12 bits for mapping to the Y polarization symbol come from the third bit set and / or the check bits of the FEC encoding.

[0243] As an example, for DP-64QAM, consider the following first symbol mapping scheme: (b0, b2, b4) is mapped to the in-phase component of the DP-64QAM symbol on the X polarization, denoted as X I ;(b6,b8,b 10 ) is mapped to the Q-direction component (quadrature-phase component) of the DP-64QAM symbol on the X polarization, denoted as X Q ; (b1, b3, b5) is mapped to the in-phase component of the DP-64QAM symbol on the Y polarization, denoted as Y I ;(b7,b9,b 11 ) is mapped to the Q-direction component (quadrature-phase component) of the DP-64QAM symbol on the Y polarization, denoted as Y Q For each signaling dimension X I / X Q / Y I / Y Q , the three bits are mapped to the corresponding symbol amplitude using the following mapping method: (0,0,0)→-7,(0,0,1)→-5,(0,1,1)→-3,(0,1,0)→-1, (1,1,0)→+1,(1,1,1)→+3,(1,0,1)→+5,(1,0,0)→+7

[0244] At this time, 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 ,b 11 ) where b0 and b6 are the two sign bits in 64QAM in the X polarization direction, b2, b4, b8 and b 10b1 and b7 are the 2 sign bits in 64QAM in the Y polarization direction, b3, b5, b9 and b 11 These are the 4 amplitude bits in 64QAM in the Y polarization direction.

[0245] It should be noted that the real part X I and the imaginary part X Q The complex number is used to represent the modulation symbol in the X polarization direction, and the real part Y I and the imaginary part Y Q The complex number is used to represent the modulation symbol in the Y polarization direction. The dual polarization symbol can be sent out by converting the I direction component X on the X polarization direction I , Q direction component X on X polarization Q , Y polarization I direction component Y I , Q direction component Y on Y polarization Q Digital-to-analog conversion (DAC) is performed to obtain corresponding four analog signals.

[0246] As another example, for DP-64QAM, consider the following second symbol mapping scheme: (b0, b4, b6) is mapped to the in-phase component of the DP-64QAM symbol on the X polarization, denoted as X I ;(b2,b8,b 10 ) is mapped to the Q-direction component (quadrature-phase component) of the DP-64QAM symbol on the X polarization, denoted as X Q ; (b1, b5, b7) is mapped to the in-phase component of the DP-64QAM symbol on the Y polarization, denoted as Y I ;(b3,b9,b 11 ) is mapped to the Q-direction component (quadrature-phase component) of the DP-64QAM symbol on the Y polarization, denoted as Y Q For each signaling dimension X I / X Q / Y I / Y Q, the three bits are mapped to the corresponding symbol amplitude using the following mapping method: (0,0,0)→-7,(0,0,1)→-5,(0,1,1)→-3,(0,1,0)→-1, (1,1,0)→+1,(1,1,1)→+3,(1,0,1)→+5,(1,0,0)→+7

[0247] At this time, 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 ,b 11 ) where b0 and b2 are the two sign bits in 64QAM in the X polarization direction, b4, b6, b8 and b 10 b1 and b3 are the 2 sign bits in 64QAM in the Y polarization direction, b5, b7, b9 and b 11 These are the 4 amplitude bits in 64QAM in the Y polarization direction.

[0248] As another example, for DP-64QAM, consider the following third symbol mapping scheme: (b8, b0, b2) is mapped to the in-phase component of the DP-64QAM symbol on the X polarization, denoted as X I ;(b 10 ,b4,b6) is mapped to the Q direction component (quadrature-phase component) of the DP-64QAM symbol on the X polarization, denoted as X Q ; (b9, b1, b3) is mapped to the in-phase component of the DP-64QAM symbol on the Y polarization, denoted as Y I ;(b 11 ,b5,b7) is mapped to the Q direction component (quadrature-phase component) of the DP-64QAM symbol on the Y polarization, denoted as Y Q For each signaling dimension X I / X Q / Y I / Y Q, the three bits are mapped to the corresponding symbol amplitude using the following mapping method: (0,0,0)→-7,(0,0,1)→-5,(0,1,1)→-3,(0,1,0)→-1, (1,1,0)→+1,(1,1,1)→+3,(1,0,1)→+5,(1,0,0)→+7

[0249] At this time, 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 ,b 11 ) in b8 and b 10 b0, b2, b4, and b6 are the 4 amplitude bits in 64QAM in the X polarization direction; b9 and b 11 b1, b3, b5, and b7 are 2 sign bits in 64QAM in the Y polarization direction, and b1, b3, b5, and b7 are 4 amplitude bits in 64QAM in the Y polarization direction.

[0250] As another example, for DP-64QAM, consider the following fourth symbol mapping scheme: (b4, b0, b2) is mapped to the in-phase component of the DP-64QAM symbol on the X polarization, denoted as X I ;(b6,b8,b 10 ) is mapped to the Q-direction component (quadrature-phase component) of the DP-64QAM symbol on the X polarization, denoted as X Q ; (b5, b1, b3) is mapped to the in-phase component of the DP-64QAM symbol on the Y polarization, denoted as Y I ;(b7,b9,b 11 ) is mapped to the Q-direction component (quadrature-phase component) of the DP-64QAM symbol on the Y polarization, denoted as Y Q For each signaling dimension X I / X Q / Y I / Y Q, the three bits are mapped to the corresponding symbol amplitude using the following mapping method: (0,0,0)→-7,(0,0,1)→-5,(0,1,1)→-3,(0,1,0)→-1, (1,1,0)→+1,(1,1,1)→+3,(1,0,1)→+5,(1,0,0)→+7

[0251] At this time, 12 bits (b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b 10 ,b 11 ) where b4 and b6 are the two sign bits in 64QAM in the X polarization direction, b0, b2, b8 and b 10 b5 and b7 are the 2 sign bits in 64QAM in the Y polarization direction, b1, b3, b9 and b 11 These are the 4 amplitude bits in 64QAM in the Y polarization direction.

[0252] The following takes modulation using the first symbol mapping scheme as an example to introduce in detail the operations of the second data sub-processing i (i=0, 1, ..., L-1), where L is an integer greater than 0.

[0253] (1) PCS processing and first interleaving:

[0254] Figure 6(a) is a schematic diagram of an embodiment of PCS processing and first interleaving in the present application. As shown in Figure 6(a), "PCS processing and first interleaving i" specifically includes one PCS processing operation (i.e., "PCS processing i") and one first interleaving operation (i.e., "first interleaving i").

[0255] Specifically, first obtain e bits, where e is an integer greater than 0. The first bit set i of the e bits is sent to the "PCS processing i" to obtain the second bit set i. The second bit set i is combined with the third bit set i remaining after removing the first bit set i from the e bits and sent to the first interleaving i for interleaving and scrambling the order to obtain two fourth bit sets, namely the fourth bit set 2i and the fourth bit set 2i+1. It should be understood that the e bits are composed of the first bit set i and the third bit set i. It should be understood that, as shown in Figure 6(a), the first bit stream 2i output by the "PCS processing and first interleaving" can include multiple fourth bit sets 2i; the first bit stream 2i+1 output by the "PCS processing and first interleaving" can include multiple fourth bit sets 2i+1.

[0256] Typically, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is 1776×k0 bits, the number of bits in the second bit set i is 8192×k0 / 3 bits, the number of bits in the third bit set i is 3552×k0-8192×k0 / 3 bits, and the number of bits in the first bit set i is e-(3552×k0-8192×k0 / 3) bits, where k0 is an integer greater than 0 and an integer multiple of 3. For example, k0=3, 6, 9, 12, ..., 42, etc.

[0257] Several more specific examples are provided below.

[0258] Example 1: Consider k0 = 3. "PCS processing and first interleaving" obtains e1 bits, where e1 is an integer greater than 0. As shown in Figure 6(a), the number of bits in the first bit set i is e1-2464, the number of bits in the second bit set i is 8192, and the number of bits in the third bit set i is 2464. The number of bits in the fourth bit set 2i and the fourth bit set 2i+1 obtained after the first interleaving is 5328. It can be understood that the first bit set i containing e1-2464 bits is sent to "PCS processing i" to obtain the second bit set i containing 8192 bits. The second bit set i is combined with the third bit set i containing 2464 bits, a total of 8192+2464=10656 bits, and is sent to the first interleaving i for interleaving and shuffling, resulting in the fourth bit set 2i and the fourth bit set 2i+1.

[0259] Example 2: Consider k0 = 6. "PCS processing and first interleaving" obtains e1 bits, where e1 is an integer greater than 0. As shown in Figure 6(a), the number of bits in the first bit set i is e1-4928, the number of bits in the second bit set i is 16384, and the number of bits in the third bit set i is 4928. The number of bits in the fourth bit set 2i and the fourth bit set 2i+1 obtained after the first interleaving is both 10656. This can be understood as sending the first bit set i containing e1-4928 bits to "PCS processing i" to obtain the second bit set i containing 16384 bits. The second bit set i, combined with the third bit set i containing 4928 bits, a total of 16384+4928=21312 bits, is sent to the first interleaving i for interleaving and shuffling, resulting in the fourth bit set 2i and the fourth bit set 2i+1.

[0260] Example 3: Consider k0 = 42. "PCS processing and first interleaving" obtains e1 bits, where e1 is an integer greater than 0. As shown in Figure 6(a), the number of bits in the first bit set i is e1-34496, the number of bits in the second bit set i is 114688, and the number of bits in the third bit set i is 34496. The number of bits in the fourth bit set 2i and the fourth bit set 2i+1 obtained after the first interleaving is both 74592. This can be understood as sending the first bit set i containing e1-34496 bits to "PCS processing i" to obtain the second bit set i containing 114688 bits. The second bit set i, combined with the third bit set i containing 34496 bits, totaling 114688+34496=149184 bits, is sent to the first interleaving i for interleaving and shuffling, resulting in the fourth bit set 2i and the fourth bit set 2i+1.

[0261] Figure 6(b) is a schematic diagram of another embodiment of PCS processing and first interleaving in an embodiment of the present application. As shown in Figure 6(b), "PCS processing and first interleaving i" specifically includes two PCS processing operations (i.e., "PCS processing 2i" and "PCS processing 2i+1") and one first interleaving operation (i.e., "first interleaving i"). It should be understood that compared to the implementation of Figure 6(a), Figure 6(b) is divided into two PCS processing implementations, which helps reduce the complexity of a single PCS processing and makes the hardware implementation of a single PCS processing simpler.

[0262] Specifically, e bits are first obtained, where e is an integer greater than 1. These e bits comprise two first bit sets: a first bit set 2i and a first bit set 2i+1. The first bit set 2i undergoes PCS processing 2i to obtain a second bit set 2i. The first bit set 2i+1 undergoes PCS processing 2i+1 to obtain a second bit set 2i+1. Typically, e is an even integer greater than 0, and the first bit set 2i and the first bit set 2i+1 contain the same number of bits.

[0263] The e bits also include two third bit sets, namely the third bit set 2i and the third bit set 2i+1. It should be understood that the e bits are composed of the first bit set 2i, the first bit set 2i+1, the third bit set 2i and the third bit set 2i+1. The third bit set 2i, the third bit set 2i+1, the second bit set 2i and the second bit set 2i+1 are all sent to the first interleaving i for interleaving and disrupting the order, obtaining two fourth bit sets, namely the fourth bit set 2i and the fourth bit set 2i+1. It should be understood that, as shown in Figure 6(b), the first bit stream 2i output by PCS processing and the first interleaving may include multiple fourth bit sets 2i, and the first bit stream 2i+1 output by PCS processing and the first interleaving may include multiple fourth bit sets 2i+1.

[0264] Typically, the fourth bit set 2i and the fourth bit set 2i+1 have the same number of bits. More specifically, the fourth bit set 2i and the fourth bit set 2i+1 both have 1776×k0 bits, the second bit set 2i and the second bit set 2i+1 both have 4096×k0 / 3 bits, the third bit set 2i and the third bit set 2i+1 both have 1776×k0-4096×k0 / 3 bits, and the first bit set 2i and the first bit set 2i+1 both have e / 2-(1776×k0-4096×k0 / 3) bits, where k0 is an integer greater than 0 and an integer multiple of 3. For example, k0=3, 6, 9, 12, ..., 42, etc.

[0265] Several more specific examples are provided below.

[0266] Example 4: Consider k0 = 3. "PCS processing and first interleaving" obtains e0 bits, where e0 is an even integer greater than 0. As shown in Figure 6(b), the number of bits in the first bit set 2i and the first bit set 2i+1 is both e0 / 2-1232, the number of bits in the second bit set 2i and the second bit set 2i+1 is both 4096, and the number of bits in the third bit set 2i and the third bit set 2i+1 is both 1232. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is both 5328. This means that "PCS processing and first interleaving" feeds the first bit set 2i, consisting of e0 / 2-1232 bits, into "PCS processing 2i," resulting in a second bit set 2i consisting of 4096 bits; and "PCS processing and first interleaving" feeds the first bit set 2i+1, consisting of e0 / 2-1232 bits, into "PCS processing 2i+1," resulting in a second bit set 2i+1 consisting of 4096 bits. The second bit set 2i, the second bit set 2i+1, and the third bit set 2i and the third bit set 2i+1, each containing 1232 bits, totaling 10656 bits, are sent to the first interleaver i. The first interleaver i interleaves the 10656 bits in a random order to obtain the fourth bit set 2i and the fourth bit set 2i+1.

[0267] Example 5: Consider k0 = 6. "PCS processing and first interleaving" obtains e0 bits, where e0 is an even integer greater than 0. As shown in Figure 6(b), the number of bits in the first bit set 2i and the first bit set 2i+1 is both e0 / 2-2464, the number of bits in the second bit set 2i and the second bit set 2i+1 is both 8192, and the number of bits in the third bit set 2i and the third bit set 2i+1 is both 2464. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is both 10656. This can be understood as "PCS processing and first interleaving" feeding the first bit set 2i, consisting of e0 / 2-2464 bits, into "PCS processing 2i" to obtain the second bit set 2i, consisting of 8192 bits; and "PCS processing and first interleaving" feeding the first bit set 2i+1, consisting of e0 / 2-2464 bits, into "PCS processing 2i+1" to obtain the second bit set 2i+1, consisting of 8192 bits. The second bit set 2i, the second bit set 2i+1, and the third bit set 2i and the third bit set 2i+1, each containing 2464 bits, totaling 21312 bits, are fed into the first interleaver i. The first interleaver i interleaves the 21312 bits in a random order to obtain the fourth bit set 2i and the fourth bit set 2i+1.

[0268] Example 6: Consider k0 = 42. "PCS processing and first interleaving" obtains e0 bits, where e0 is an even integer greater than 0. As shown in Figure 6(b), the number of bits in the first bit set 2i and the first bit set 2i+1 is both e0 / 2-17248, the number of bits in the second bit set 2i and the second bit set 2i+1 is both 57344, and the number of bits in the third bit set 2i and the third bit set 2i+1 is both 17248. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is both 74592. This means that "PCS processing and first interleaving" feeds the first bit set 2i, consisting of e0 / 2 - 17248 bits, into "PCS processing 2i," resulting in the second bit set 2i, consisting of 57344 bits. "PCS processing and first interleaving" feeds the first bit set 2i+1, consisting of e0 / 2 - 17248 bits, into "PCS processing 2i+1," resulting in the second bit set 2i+1, consisting of 57344 bits. The second bit set 2i, the second bit set 2i+1, and the third bit set 2i and the third bit set 2i+1, each containing 17248 bits, totaling 149184 bits, are fed into the first interleaver i. The first interleaver i interleaves and shuffles the 149184 bits to produce the fourth bit set 2i and the fourth bit set 2i+1.

[0269] It should be understood that in Examples 4 to 6 above, the first bit set 2i and the third bit set 2i include a total of e0 / 2 bits, and the first bit set 2i+1 and the third bit set 2i+1 include a total of e0 / 2 bits. That is, the input e0 bits are first divided into two paths of e0 / 2 bits each before subsequent processing. In other possible scenarios, the input e0 bits can also be divided into two paths according to other ratios, that is, the number of bits included in the first bit set 2i and the third bit set 2i is different from the number of bits included in the first bit set 2i+1 and the third bit set 2i+1.

[0270] Figure 6(c) is another schematic diagram of an embodiment of PCS processing and first interleaving in the embodiment of the present application. As shown in Figure 6(c), "PCS processing and first interleaving i" specifically includes two PCS processing operations (i.e., "PCS processing 2i" and "PCS processing 2i+1") and two first interleaving operations (i.e., "first interleaving 2i" and "first interleaving 2i+1"). It should be understood that compared with the implementation of Figures 6(a) and 6(b), Figure 6(c) is divided into two first interleaving implementations, which is conducive to reducing the complexity of a single first interleaving, and the hardware implementation of a single first interleaving is simpler.

[0271] Specifically, first, e bits are obtained, where e is an integer greater than 0. These e bits comprise two first bit sets: a first bit set 2i and a first bit set 2i+1. The first bit set 2i undergoes PCS processing 2i to obtain a second bit set 2i, and the first bit set 2i+1 undergoes PCS processing 2i+1 to obtain a second bit set 2i+1. Typically, e is an even integer greater than 0, and the first bit set 2i and the first bit set 2i+1 have the same number of bits.

[0272] The e bits further include two third bit sets, namely the third bit set 2i and the third bit set 2i+1. It should be understood that the e bits are composed of the first bit set 2i, the first bit set 2i+1, the third bit set 2i and the third bit set 2i+1.

[0273] The third bit set 2i and the second bit set 2i are fed into the first interleaver 2i for interleaving and scrambling, resulting in a fourth bit set, namely, the fourth bit set 2i. The third bit set 2i+1 and the second bit set 2i+1 are fed into the first interleaver 2i+1 for interleaving and scrambling, resulting in a fourth bit set, namely, the fourth bit set 2i+1. It should be understood that, as shown in FIG6(c), the first bit stream 2i output by the "PCS processing and first interleaving" may include multiple fourth bit sets 2i, and the first bit stream 2i+1 output by the "PCS processing and first interleaving" may include multiple fourth bit sets 2i+1.

[0274] Typically, the fourth bit set 2i and the fourth bit set 2i+1 have the same number of bits. More specifically, the fourth bit set 2i and the fourth bit set 2i+1 both have 1776×k0 bits, the second bit set 2i and the second bit set 2i+1 both have 4096×k0 / 3 bits, the third bit set 2i and the third bit set 2i+1 both have 1776×k0-4096×k0 / 3 bits, and the first bit set 2i and the first bit set 2i+1 both have e / 2-(1776×k0-4096×k0 / 3) bits, where k0 is an integer greater than 0 and an integer multiple of 3. For example, k0=3, 6, 9, 12, ..., 42, etc.

[0275] Several more specific examples are provided below.

[0276] Example 7: Consider k0 = 3. "PCS processing and first interleaving" obtains e2 bits, where e2 is an even integer greater than 0. As shown in Figure 6(c), the number of bits in the first bit set 2i and the first bit set 2i+1 is both e2 / 2-1232, the number of bits in the second bit set 2i and the second bit set 2i+1 is both 4096, and the number of bits in the third bit set 2i and the third bit set 2i+1 is both 1232. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is both 5328. It can be understood that "PCS processing and first interleaving" includes two processing paths, each of which obtains e2 / 2 bits for processing. More specifically, for the first processing path, the first bit set 2i containing e2 / 2-1232 bits is sent to "PCS processing 2i" to obtain the second bit set 2i containing 4096 bits. The second bit set 2i, combined with the third bit set 2i containing 1232 bits, totaling 4096 + 1232 = 5328 bits, is sent to the first interleaver 2i for interleaving and scrambling, resulting in the fourth bit set 2i. For the second processing path, the first bit set 2i+1, containing e2 / 2 - 1232 bits, is sent to "PCS processing 2i+1" to obtain the second bit set 2i+1 containing 4096 bits. The second bit set 2i+1, combined with the third bit set 2i+1 containing 1232 bits, totaling 3824 + 1504 = 5328 bits, is sent to the first interleaver 2i+1 for interleaving and scrambling, resulting in the fourth bit set 2i+1.

[0277] Example 8: Consider k0 = 6. "PCS processing and first interleaving" obtains e2 bits, where e2 is an even integer greater than 0. As shown in Figure 6(c), the number of bits in the first bit set 2i and the first bit set 2i+1 is both e2 / 2-2464, the number of bits in the second bit set 2i and the second bit set 2i+1 is both 8192, and the number of bits in the third bit set 2i and the third bit set 2i+1 is both 2464. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is both 10656. It can be understood that "PCS processing and first interleaving" includes two processing paths, each of which obtains e2 / 2 bits for processing. More specifically, for the first processing path, the first bit set 2i containing e2 / 2-2464 bits is sent to PCS processing 2 to obtain the second bit set 2i containing 8192 bits. The second bit set 2i, combined with the third bit set 2i containing 2464 bits, totaling 8192 + 2464 = 10656 bits, is sent to the first interleaving 2i for interleaving and scrambling, resulting in the fourth bit set 2i. For the second processing path, the first bit set 2i+1, containing e2 / 2-2464 bits, is sent to the PCS processing 2i+1 for processing, resulting in the second bit set 2i+1 containing 8192 bits. The second bit set 2i+1, combined with the third bit set 2i+1 containing 2464 bits, totaling 8192 + 2464 = 10656 bits, is sent to the first interleaving 2i+1 for interleaving and scrambling, resulting in the fourth bit set 2i+1.

[0278] Example 9: Consider k0 = 42. "PCS processing and first interleaving" obtains e2 bits, where e2 is an even integer greater than 0. As shown in Figure 6(c), the number of bits in the first bit set 2i and the first bit set 2i+1 is both e2 / 2-17248, the number of bits in the second bit set 2i and the second bit set 2i+1 is both 57344, and the number of bits in the third bit set 2i and the third bit set 2i+1 is both 17248. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is both 74592. It can be understood that "PCS processing and first interleaving" includes two processing paths, each of which obtains e2 / 2 bits for processing. More specifically, for the first processing path, the first bit set 2i containing e2 / 2-17248 bits is sent to PCS processing 2i to obtain the second bit set 2i containing 57344 bits. The second bit set 2i is combined with the third bit set 2i containing 17248 bits, totaling 57344 + 17248 = 74592 bits, and is sent to the first interleaving process 2i for interleaving and scrambling, resulting in the fourth bit set 2i. For the second processing path, the first bit set 2i+1 containing e2 / 2 - 17248 bits is sent to "PCS processing 2i+1" to obtain the second bit set 2i+1 containing 57344 bits. The second bit set 2i+1 is combined with the third bit set 2i+1 containing 17248 bits, totaling 57344 + 17248 = 74592 bits, and is sent to the first interleaving process 2i+1 for interleaving and scrambling, resulting in the fourth bit set 2i+1.

[0279] It should be understood that in the above Examples 7 to 9, the first bit set 2i and the third bit set 2i include a total of e0 / 2 bits, and the first bit set 2i+1 and the third bit set 2i+1 include a total of e0 / 2 bits. That is, the input e0 bits are first divided into two halves, each consisting of e0 / 2 bits, and then subsequently processed.

[0280] Figure 6(d) is a schematic diagram of another embodiment of PCS processing and first interleaving in an embodiment of the present application. As shown in Figure 6(d), "PCS processing and first interleaving i" includes two PCS processes (i.e., "PCS processing 2i" and "PCS processing 2i+1") and one first interleaving (i.e., "first interleaving i"). It should be understood that compared to the implementation of Figure 6(a), Figure 6(d) is implemented as two PCS processes, which helps reduce the complexity of a single PCS process and simplifies the hardware implementation of a single PCS process.

[0281] The PCS processing and first interleaving process generates e bits, where e is an integer greater than 0. These e bits comprise two first bit sets: the first bit set 2i and the first bit set 2i+1. The first bit set 2i is fed into the PCS processing 2i to obtain the second bit set 2i, and the first bit set 2i+1 is fed into the PCS processing 2i+1 to obtain the second bit set 2i+1. Typically, e is an even integer greater than 0, and the first bit set 2i and the first bit set 2i+1 have the same number of bits.

[0282] The e bits include one third bit set, namely the third bit set i. It should be understood that the e bits are composed of the first bit set 2i, the first bit set 2i+1 and the third bit set i. The third bit set i, the second bit set 2i and the second bit set 2i+1 are sent to the first interleaving i for interleaving and scrambling to obtain two fourth bit sets, namely the fourth bit set 2i and the fourth bit set 2i+1. It should be understood that, as shown in Figure 6(d), the first bit stream 2i output by "PCS processing and first interleaving" may include multiple fourth bit sets 2i; the first bit stream 2i+1 output by "PCS processing and first interleaving" may include multiple fourth bit sets 2i+1.

[0283] Typically, the fourth bit set 2i and the fourth bit set 2i+1 have the same number of bits. More specifically, the fourth bit set 2i and the fourth bit set 2i+1 both have 1776×k0 bits, the second bit set 2i and the second bit set 2i+1 both have 4096×k0 / 3 bits, and the third bit set i has 1776×k0 / 3 bits. bits, the number of bits in the first bit set 2i and the first bit set 2i+1 are both e / 2-(1776×k0-4096×k0 / 3) bits, where k0 is an integer greater than 0 and an integer multiple of 3, for example, k0=3, 6, 9, 12, ..., 42, etc.

[0284] Several more specific examples are provided below.

[0285] Example 10: Consider k0 = 3. "PCS processing and first interleaving" obtains e3 bits, where e3 is an even integer greater than 0. As shown in Figure 6(d), the number of bits in the first bit set 2i and the first bit set 2i+1 is both e3 / 2-1232, the number of bits in the second bit set 2i and the second bit set 2i+1 is both 4096, and the number of bits in the third bit set i is 2464. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is both 5328. This can be understood as "PCS processing and first interleaving" feeding the first bit set 2i, consisting of e3 / 2-1232 bits, into "PCS processing 2i," resulting in a second bit set 2i consisting of 4096 bits; and "PCS processing and first interleaving" feeding the first bit set 2i+1, consisting of e3 / 2-1232 bits, into "PCS processing 2i+1," resulting in a second bit set 2i+1 consisting of 4096 bits. The second bit set 2i, the second bit set 2i+1, and the third bit set i containing 2464 bits, totaling 10656 bits, are sent to the first interleaver i. The first interleaver i interleaves the 10656 bits in a random order to obtain the fourth bit set 2i and the fourth bit set 2i+1.

[0286] Example 11: Consider k0 = 6. "PCS processing and first interleaving" obtains e3 bits, where e0 is an even integer greater than 0. As shown in Figure 6(d), the number of bits in the first bit set 2i and the first bit set 2i+1 is both e3 / 2-2464, the number of bits in the second bit set 2i and the second bit set 2i+1 is both 8192, and the number of bits in the third bit set i is 4928. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is both 10656. This can be understood as "PCS processing and first interleaving" feeding the first bit set 2i, consisting of e3 / 2-2464 bits, into "PCS processing 2i" to obtain the second bit set 2i, consisting of 8192 bits; and feeding the first bit set 2i+1, consisting of e3 / 2-2464 bits, into "PCS processing 2i+1" to obtain the second bit set 2i+1, consisting of 8192 bits. The second bit set 2i, the second bit set 2i+1, and the third bit set i containing 4928 bits, totaling 21312 bits, are sent to the first interleaver i. The first interleaver i interleaves the 21312 bits in a random order to obtain the fourth bit set 2i and the fourth bit set 2i+1.

[0287] Example 12: Consider k0 = 42. "PCS processing and first interleaving" obtains e3 bits, where e3 is an even integer greater than 0. As shown in Figure 6(d), the number of bits in the first bit set 2i and the first bit set 2i+1 is e3 / 2-17248, the number of bits in the second bit set 2i and the second bit set 2i+1 is 57344, and the number of bits in the third bit set i is 34496. After the first interleaving, the number of bits in the fourth bit set 2i and the fourth bit set 2i+1 is 74592. This can be understood as "PCS processing and first interleaving" feeding the first bit set 2i, consisting of e3 / 2-17248 bits, into "PCS processing 2i" to obtain the second bit set 2i, consisting of 57344 bits; and feeding the first bit set 2i+1, consisting of e3 / 2-17248 bits, into "PCS processing 2i+1" to obtain the second bit set 2i+1, consisting of 57344 bits. The second bit set 2i, the second bit set 2i+1, and the third bit set i containing 34496 bits, totaling 149184 bits, are sent to the first interleaver i. The first interleaver i interleaves the 149184 bits in a random order to obtain the fourth bit set 2i and the fourth bit set 2i+1.

[0288] It should be noted that, in some specific applications, PCS processing can be implemented using one or more lookup tables (LUTs). Each LUT will input k LUT The bits are mapped by LUT to get the output n LUT bits, where n LUT >k LUT For example, a lookup table is used to convert the input bit k of the PCS processing pcs Each k LUT The bits are mapped by LUT to get the output n LUT bits, a total of k pcs / k LUT ×n LUT PCS processing output bits. In some specific applications, the lookup table LUT processing can also be implemented by including multiple sub-lookup tables, and the number of input bits of the sub-lookup tables can be different, and the number of output bits can also be different. In this application, there is no limitation on the specific implementation of the LUT lookup table. At this time, PCS processing is also called PCS LUT processing. It should be noted that PCS processing can also be called Distribution Matcher (DM). In some specific applications, the first interleaving can be called block mapping (Block Map), can also be called pre-FEC interleaver (pre-FEC interleaver), and can also be called pre-FEC permutation (pre-FEC Permutation).

[0289] It should be noted that the number of bits d of the third bit data output by the first data processing is scr is an integer multiple of L×e0 or L×e1 or L×e2 or L×e3. scr bits, and then one or more second data processing operations can complete the d scr The processing of each bit does not require any additional processing such as caching, making the specific hardware implementation of the entire data processing simpler and the power consumption lower.

[0290] It should be noted that, as shown in Figures 6(a), 6(b), 6(c) and 6(d), the first bit stream contains multiple fourth bit sets. Each fourth bit set can be distributed in the form of multiple rows of bit blocks, where each row contains 7 columns of bit blocks. The bits in each of the bit blocks are continuous. It should be understood that in some possible scenarios, a bit block can also be referred to as a bit subset, and a bit block is a specific implementation form of a row and column distribution of a bit subset. Furthermore, if the number of rows and columns of a bit block is the same, the bit block can also be referred to as a bit square block, a square matrix or a square block. For example, a bit block comprising 16 rows and 16 columns appearing in the text can also be referred to as a bit square matrix, a square matrix or a square block. It should be understood that in the embodiments of the present application, all bit sets, bit subsets, bit blocks, etc. involving row and column distribution are counted from row 0 and column 0. It should also be understood that in the embodiments of the present application, all references to rows and columns in a bit set refer to bit subsets or bit blocks distributed in rows and columns, and all references to rows and columns in a bit subset or bit block in the embodiments of the present application refer to bits distributed in rows and columns.

[0291] FIG7 is a schematic diagram of a bit block with seven columns per row in an embodiment of the present application. As shown in FIG7 , the bit blocks in columns 0, 1, 2, 3, 4, and 5 each contain 16-bit rows and 16-bit columns, totaling 256 bits. The bit block in column 6 contains 16-bit rows and 15-bit columns, totaling 240 bits. In other words, the bit block in each row and seven columns contains a total of 1776 bits. It should be noted that a bit block containing 16-bit rows and 16-bit columns, totaling 256 bits, can be referred to as a square block or a square block.

[0292] As shown in Examples 1, 4, and 7 above, each fourth bit set has 5328 bits. In this case, each fourth bit set can be distributed as 21 bit blocks, each consisting of 3 rows and 7 columns. Each bit block in the first 6 columns contains 16-bit rows and 16-bit columns, and each bit block in the last column contains 16-bit rows and 15-bit columns. The bits in each bit block are continuous.

[0293] As shown in Examples 2, 5, and 8 above, the number of bits in each fourth bit set is 10656. In this case, each fourth bit set can be distributed in the form of 42 bit blocks with 6 rows and 7 columns.

[0294] Each bit block in the first six columns contains 16-bit rows and 16-bit columns, and each bit block in the last column contains 16-bit rows and 15-bit columns. The bits in each bit block are continuous.

[0295] As shown in Examples 3, 6, and 9 above, each fourth bit set has 74,592 bits. In this case, each fourth bit set can be distributed as 42 rows and 7 columns, totaling 294 bit blocks. Each bit block in the first 6 columns contains 16-bit rows and 16-bit columns, and each bit block in the last column contains 16-bit rows and 15-bit columns. The bits in each bit block are continuous.

[0296] It should be noted that, in some specific applications, the first interleaving operation in "PCS processing and first interleaving" is performed with a granularity of 149184 or 74592 bits. In other specific applications, the first interleaving operation in "PCS processing and first interleaving" is performed with a granularity of 10656 bits. In this case, the first interleaving is time-varying, that is, the interleaving operation on 10656 bits at different times is different; in other specific applications, the first interleaving operation in "PCS processing and first interleaving" is performed with a granularity of 21312 bits. In this case, the first interleaving is time-varying, that is, the interleaving operation on 21312 bits at different times is different. It should be understood that, as shown in Figure 6(c), the interleaving operations of the first interleaving 2i and the first interleaving 2i+1 are different.

[0297] It should be noted that the first bit stream includes multiple fifth bit sets, and the bits in each fifth bit set are distributed into 42 rows and 7 columns, totaling 294 bit blocks. Each bit block in the first 6 columns contains 16 bit rows and 16 bit columns, and each bit block in the last column contains 16 bit rows and 15 bit columns. Each row of bit blocks contains 7 bit blocks, for a total of 1776 bits. The specific form of this is shown in Figure 7. The bits in each bit block are continuous.

[0298] It should be noted that, in some specific applications, the 42 rows and 7 columns of bit blocks in the fifth bit set, totaling 74,592 bits, are composed of one or more fourth bit sets. More specifically, for example, for the number of bits of each fourth bit set in Examples 1, 4, and 7 above, is 5,328, then the fifth bit set can be composed of 14 fourth bit sets. For another example, for the number of bits of each fourth bit set in Examples 2, 5, and 8 above, is 10,656, then the fifth bit set can be composed of 7 fourth bit sets. As shown in Examples 3, 6, and 9 above, the number of bits of each fourth bit set is 74,592, then the fifth bit set can be composed of 1 fourth bit set, and the fourth bit set can also be represented by the fifth bit set.

[0299] FIG8 is a schematic diagram of a fifth bit set in an embodiment of the present application. As shown in FIG8 , the fifth bit set can be specifically presented in the form of a rectangular block of bits. The bit block in the i1th row and j1th column of the fifth bit set is denoted as Where 0≤i1<42 and 0≤j1<7.

[0300] As shown in FIG8 , each bit block in the first 6 columns (i.e., columns 0 to 5) of the fifth bit set contains 16-bit rows and 16-bit columns, i.e. (0≤i1<42 and 0≤j1<6) is a square matrix containing 256 bits. In some specific applications, the bit block (0≤i1<42 and 0≤j1<6) contains 16 rows and 16 columns, a total of 256 bits, which are continuous on the first bit stream. Figure 9 is a schematic diagram of a 16×16 bit block in an embodiment of the present application. As shown in Figure 9, each bit block The bit at row r0 and column c0 (0≤r0<16 and 0≤c0<16) in the bit block (0≤i1<42 and 0≤j1<6) corresponds to the 16th × r0 + c0 bit of the 256 consecutive bits. For example, the bit at row r0=1 and column c0=0 in the bit block corresponds to the 16th bit of the 256 bits. For another example, the bit at row r0=2 and column c0=3 in the bit block corresponds to the 35th bit of the 256 bits.

[0301] As shown in FIG8 , each bit block in the last column (i.e., column 6) of the fifth bit set contains 16-bit rows and 15-bit columns, i.e. (0≤i1<42 and j1=6) is a bit block containing 240 bits. In some specific applications, the bit block (0≤i1<42 and j1=6) contains 16 rows and 15 columns, totaling 240 bits, which are continuous on the first bit stream. FIG10 is a schematic diagram of a 16×15 bit block in an embodiment of the present application. As shown in FIG10, each bit block The bit at row r1 and column c1 (0 ≤ r1 < 16 and 0 ≤ c1 < 15) in the bit block (0 ≤ i1 < 42 and j1 = 6) corresponds to the 15th × r1 + c1th bit of the 240 consecutive bits. For example, the bit at row r1 = 1 and column c1 = 0 in the bit block corresponds to the 15th bit of the 240 bits. For another example, the bit at row r1 = 2 and column c1 = 3 in the bit block corresponds to the 33rd bit of the 240 bits.

[0302] It should be noted that, in some specific applications, the 42 rows and 7 columns of the fifth bit set, totaling 74,592 bits, are continuous on the first bit stream. Further, in some specific applications, the specific distribution of the 42 rows and 7 columns of the fifth bit set, totaling 294 bit blocks, on the first bit stream may be distributed continuously as 1 row of bit blocks, totaling 1,776 bits. For example, The 7 bit blocks of 1776 bits are continuous on the first bit stream, where 0≤i1<42. In other specific applications, the specific distribution of the 294 bit blocks in 42 rows and 7 columns in the fifth bit set on the first bit stream can be continuous distribution of 3552 bits in 2 rows of bit blocks. For example, The 14 bit blocks of 3552 bits are continuous on the first bit stream, where 0≤i2<21. In some specific applications, the specific distribution of the 294 bit blocks in 42 rows and 7 columns in the fifth bit set on the first bit stream can be continuous distribution of 5328 bits in 3 rows of bit blocks. For example, The 21 bit blocks of 5328 bits are continuous on the first bit stream, where 0≤i3<14. In some specific applications, the specific distribution of the 294 bit blocks in 42 rows and 7 columns in the fifth bit set on the first bit stream can be continuous distribution of 10656 bits in 6 rows of bit blocks. For example, The 42-bit blocks totaling 10656 bits are continuous on the first bit stream, where 0≤i4<7.

[0303] As shown in FIG8 , the bits in the fifth bit set are distributed as 42 rows and 7 columns, with a total of 294 bit blocks. (0≤i1<42 and 0≤j1<7). The bits in the leftmost 5 columns of the bit block in the fifth bit set, i.e., the bit block filled with the shaded background shown in FIG8. (0≤i1<42 and 0≤j1<5), some bits from the second bit set that have been processed by PCS and bits from the third bit set that have not been processed by PCS. The rightmost two columns of bit blocks in the fifth bit set are the bit blocks filled with the non-shaded (white) background shown in Figure 8 (0≤i1<42 and 5≤j1<7), bits from the remaining portion of the second bit set processed by PCS (ie, excluding bits from the third bit set).

[0304] It should be noted that the distribution of the specific bit blocks of the fifth bit set 2i on the first bit stream 2i and the fifth bit set 2i+1 on the first bit stream 2i+1 can be understood with reference to FIG8 , but the specific bit pattern of each bit block is not completely consistent, that is, the bit pattern of the fifth bit set 2i is not completely consistent. (0≤i1<42 and 0≤j1<7) and the fifth bit set 2i+1 The specific bit patterns (0≤i1<42 and 0≤j1<7) are not exactly the same.

[0305] It should be noted that the bit pattern (also known as the bit distribution pattern) is used to describe the source and purpose of each specific bit in the bit block. For specific patterns, please refer to Figures xx to xx. More specifically, the portion of the bit pattern with a shaded background (marked with the number "0") in the i0th row and j0th column indicates that the bits in the i0th row and j0th column of the bit block are from the third bit set that has not been processed by PCS and / or from the parity bits encoded by FEC, and serve as sign bits in symbol mapping (also known as modulation). The portion of the bit pattern with a non-shaded (blank) background (marked with the number "1") in the i0th row and j0th column indicates that the bits in the i0th row and j0th column of the bit block are from the second bit set that has been processed by PCS, and serve as amplitude bits in symbol mapping (also known as modulation).

[0306] The bit block patterns in the fifth bit set 2i and the fifth bit set 2i+1 are described below. It should be understood that in all figures below that include bit block patterns with shaded background fills and non-shaded (blank) background fills, the shaded background fills are also marked with the number "0," and the non-shaded (blank) background fills are also marked with the number "1." For shaded background fills marked with the number 0, the shaded background fill pattern may vary in different figures.

[0307] 8 shows a schematic diagram of a bit block with 42 rows and 7 columns. The following describes the bit block in the fifth bit set 2i on the first bit stream 2i. (0≤i1<42 and 0≤j1<7) pattern. Specifically, Figure 11(a) is a schematic diagram of a first bit pattern in an embodiment of the present application; Figure 11(b) is a schematic diagram of a second bit pattern in an embodiment of the present application; Figure 11(c) is a schematic diagram of a third bit pattern in an embodiment of the present application; Figure 12(a) is a schematic diagram of a fourth bit pattern in an embodiment of the present application; Figure 12(b) is a schematic diagram of a fifth bit pattern in an embodiment of the present application; Figure 12(c) is a schematic diagram of a sixth bit pattern in an embodiment of the present application; Figure 12(d) is a schematic diagram of another fourth bit pattern in an embodiment of the present application; Figure 12(e) is a schematic diagram of another fifth bit pattern in an embodiment of the present application; Figure 12(f) is a schematic diagram of another sixth bit pattern in an embodiment of the present application; Figure 13 is a schematic diagram of a seventh bit pattern in an embodiment of the present application; Figure 14 is a schematic diagram of an eighth bit pattern in an embodiment of the present application.

[0308] 1) For 0≤i1<21 and i1%3=0, or 21≤i1<42 and i1%3=2, i.e., i1=0,3,6,9,12,15,18,23,26,29,32,35,38,41, and j1=0,1,2,3: corresponding 56-bit block The bit pattern uses the first bit pattern. As an example, the first bit pattern when the first symbol mapping is used is shown in Figure 11(a), which includes a 16-row, 16-column bit block, with each row containing 6 shaded background-filled bits and 10 unshaded (blank) background-filled bits. The shaded background-filled bits are from the bits in the third bit set that have not been processed by PCS, and the unshaded (blank) background-filled bits are from the bits in the second bit set that have been processed by PCS.

[0309] 2) For 0≤i1<21 and i1%3=1, or 21≤i1<42 and i1%3=0, i.e., i1=1,4,7,10,13,16,19,21,24,27,30,33,36,39, and j1=0,1,2,3: corresponding 56-bit block The second bit pattern is used. As an example, the second bit pattern when the first symbol mapping is used is shown in Figure 11(b), which includes a 16-row, 16-column bit block, with each row containing 6 shaded background-filled bits and 10 unshaded (blank) background-filled bits. The shaded background-filled bits are from the bits in the third bit set that have not been processed by PCS, and the unshaded (blank) background-filled bits are from the bits in the second bit set that have been processed by PCS.

[0310] 3) For 0≤i1<21 and i1%3=2, or 21≤i1<42 and i1%3=1, i.e., i1=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j1=0, 1, 2, 3: the corresponding 56-bit block The bit pattern uses a third bit pattern. As an example, the third bit pattern when the first symbol mapping is used is shown in Figure 11(c). It includes a 16-row, 16-column bit block, with each row containing 4 shaded background-filled bits and 12 unshaded (blank) background-filled bits. The shaded background-filled bits are from the bits in the third bit set that have not been processed by PCS, and the unshaded (blank) background-filled bits are from the bits in the second bit set that have been processed by PCS.

[0311] 4) For 0≤i1<21 and i1%3=0, or 21≤i1<42 and i1%3=2, i.e., i1=0,3,6,9,12,15,18,23,26,29,32,35,38,41, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0312] As a specific implementation, the fourth bit pattern when the first symbol mapping is adopted is shown in FIG12( a ), which includes 82 bits filled with a shaded background and 174 bits filled with a non-shaded (blank) background.

[0313] As another specific implementation, when the first symbol mapping is adopted, the fourth bit pattern is shown in FIG12( d ), which includes 78 bits filled with a shaded background and 178 bits filled with a non-shaded (blank) background.

[0314] As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0315] The shaded background fill bits are from the bits in the third bit set that have not been processed by PCS, and the non-shaded (blank) background fill bits are from the bits in the second bit set that have been processed by PCS.

[0316] 5) For 0≤i1<21 and i1%3=1, or 21≤i1<42 and i1%3=0, i.e., i1=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0317] As a specific implementation, the fifth bit pattern when the first symbol mapping is adopted is shown in FIG12( b ), which includes 78 bits filled with a shaded background and 178 bits filled with a non-shaded (blank) background.

[0318] As another specific implementation, when the first symbol mapping is adopted, the fifth bit pattern is shown in FIG12( e ), which includes 90 bits filled with a shaded background and 166 bits filled with a non-shaded (blank) background.

[0319] As another specific embodiment, when the first symbol mapping is used, the fifth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0320] The shaded background fill bits are from the bits in the third bit set that have not been processed by PCS, and the non-shaded (blank) background fill bits are from the bits in the second bit set that have been processed by PCS.

[0321] 6) For 0≤i1<21 and i1%3=2, or 21≤i1<42 and i1%3=1, i.e., i1=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0322] As a specific implementation, the sixth bit pattern when the first symbol mapping is adopted is shown in FIG12( c ), which includes 48 bits filled with a shaded background and 208 bits filled with a non-shaded (blank) background.

[0323] As another specific implementation, the sixth bit pattern when the first symbol mapping is adopted is shown in FIG12( f ), which includes 40 bits filled with a shaded background and 216 bits filled with a non-shaded (blank) background.

[0324] As another specific embodiment, when the first symbol mapping is used, the sixth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0325] The shaded background fill bits are from the bits in the third bit set that have not been processed by PCS, and the non-shaded (blank) background fill bits are from the bits in the second bit set that have been processed by PCS.

[0326] 7) For 0≤i1<42 and j1=5: the corresponding 42-bit block The bit pattern uses the seventh bit pattern. As an example, the seventh bit pattern when the first symbol mapping is used is shown in FIG13 , which includes 256 non-shaded (blank) background-filled bits. The non-shaded (blank) background-filled bits are from the bits in the second bit set processed by the PCS.

[0327] 8) For 0≤i1<42 and j1=6: the corresponding 42-bit block The bit pattern uses the eighth bit pattern. As an example, the eighth bit pattern when the eighth symbol mapping is used is shown in FIG14 , which contains 240 non-shaded (blank) background-filled bits. The non-shaded (blank) background-filled bits are from the bits in the second bit set processed by the PCS.

[0328] It should be noted that when 0≤i1<42 and j1=4, the corresponding 42-bit block The 42-bit block contains 7840 bits from the second bit set and 2912 bits from the third bit set. For every three consecutive rows of bit blocks, that is, when 0≤i3<14 and j1=4, the corresponding three bit blocks The 768 bits in the 12-bit bit set include 560 bits from the second bit set and 208 bits from the third bit set. As a specific embodiment, when the first symbol mapping is used, the fourth bit pattern is shown in Figure 12(a), the fifth bit pattern is shown in Figure 12(b), and the sixth bit pattern is shown in Figure 12(c). As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is shown in Figure 12(d), the fifth bit pattern is shown in Figure 12(e), and the sixth bit pattern is shown in Figure 12(f).

[0329] 8 shows a schematic diagram of a bit block with 42 rows and 7 columns. The following describes the bit block in the fifth bit set 2i+1 on the first bit stream 2i+1. (0≤i1<42 and 0≤j1<7) pattern.

[0330] 1) For 0≤i1<21 and i1%3=0, or 21≤i1<42 and i1%3=2, i.e., i1=0,3,6,9,12,15,18,23,26,29,32,35,38,41, and j1=0,1,2,3: corresponding 56-bit block As an example, the third bit pattern when the first symbol mapping is adopted is shown in FIG11( c ).

[0331] 2) For 0≤i1<21 and i1%3=1, or 21≤i1<42 and i1%3=0, i.e., i1=1,4,7,10,13,16,19,21,24,27,30,33,36,39, and j1=0,1,2,3: corresponding 56-bit block The bit pattern of the first bit pattern is as shown in FIG11( a ).

[0332] 3) For 0≤i1<21 and i1%3=2, or 21≤i1<42 and i1%3=1, i.e., i1=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j1=0, 1, 2, 3: the corresponding 56-bit block As an example, the second bit pattern when the first symbol mapping is adopted is shown in FIG11( b ).

[0333] 4) For 0≤i1<21 and i1%3=0, or 21≤i1<42 and i1%3=2, i.e., i1=0,3,6,9,12,15,18,23,26,29,32,35,38,41, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0334] As a specific implementation, the bit block As an example, the sixth bit pattern when the first symbol mapping is adopted is shown in FIG12( c ).

[0335] As another specific implementation, the sixth bit pattern when the first symbol mapping is adopted is shown in FIG12( f ).

[0336] As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0337] 5) For 0≤i1<21 and i1%3=1, or 21≤i1<42 and i1%3=0, i.e., i1=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0338] As a specific implementation, the bit block As an example, the fourth bit pattern when the first symbol mapping is adopted is shown in FIG12( a ).

[0339] As another specific implementation, when the first symbol mapping is adopted, the fourth bit pattern is shown in FIG12( d ).

[0340] As another specific embodiment, when the first symbol mapping is used, the fifth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0341] 6) For 0≤i1<21 and i1%3=2, or 21≤i1<42 and i1%3=1, i.e., i1=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0342] As a specific implementation, the bit block As an example, the fifth bit pattern when the first symbol mapping is adopted is shown in FIG12( b ).

[0343] As another specific implementation, when the first symbol mapping is adopted, the fifth bit pattern is shown in FIG12( e ).

[0344] As another specific embodiment, when the first symbol mapping is used, the sixth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0345] 7) For 0≤i1<42 and j1=5: the corresponding 42-bit block As an example, the seventh bit pattern when the first symbol mapping is adopted is shown in FIG13 .

[0346] 8) For 0≤i1<42 and j1=6: the corresponding 42-bit block As an example, the eighth bit pattern when the first symbol mapping is adopted is shown in FIG14 .

[0347] It should be noted that when 0≤i1<42 and j1=4, the corresponding 42-bit block The 42-bit block contains 7840 bits from the second bit set and 2912 bits from the third bit set. For every three consecutive rows of bit blocks, that is, when 0≤i3<14 and j1=4, the corresponding three bit blocks The 768 bits in the 12-bit bit set include 560 bits from the second bit set and 208 bits from the third bit set. As a specific embodiment, when the first symbol mapping is used, the fourth bit pattern is shown in Figure 12(c), the fifth bit pattern is shown in Figure 12(a), and the sixth bit pattern is shown in Figure 12(b). As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is shown in Figure 12(f), the fifth bit pattern is shown in Figure 12(d), and the sixth bit pattern is shown in Figure 12(e).

[0348] It should be noted that the bit blocks (or squares) in different figures of this application are marked with the same shaded background, which does not mean that the patterns of these bit blocks are exactly the same. It is only a graphical representation method. It should be noted that the bits in the second bit set processed by PCS are used for the amplitude bits (Amplitude bits) in symbol mapping (also called modulation), and the bits in the third bit set that have not been processed by PCS are used for the sign bits (Sign bits) in symbol mapping (also called modulation). The bits in the shaded background part of Figure 11 (a), (b), (c) and Figure 12 (a), (b), (c), Figure 13 and Figure 14 are from the bits in the third bit set that have not been processed by PCS, that is, the sign bits, and the remaining bits in the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS, that is, the amplitude bits.

[0349] It should be noted that the bit block distribution of the fifth bit set 2i and the fifth bit set 2i+1 is shown in FIG8 , but the specific bit blocks included therein are The patterns are not exactly the same. More specifically, the bit blocks (0≤i1<42 and 0≤j1<5) have different distribution patterns, that is, the distribution positions of the amplitude bits and sign bits in the bit blocks are different. It should be understood that the first bit stream 2i after "PCS processing and first interleaving" can include multiple fifth bit sets 2i, and the first bit stream 2i+1 can include multiple fifth bit sets 2i+1.

[0350] (2) FEC encoding:

[0351] Figure 15 is a schematic diagram of an implementation method for data processing two first bit streams in an embodiment of the present application. As shown in Figure 15, "FEC encoding 2i" encodes the fifth bit set 2i in the first bit stream 2i and adds parity bits to obtain the sixth bit set 2i. "FEC encoding 2i+1" encodes the fifth bit set 2i+1 in the first bit stream 2i+1 and adds parity bits to obtain the sixth bit set 2i+1. It should be understood that the second bit stream 2i output by the FEC encoding may include multiple sixth bit sets 2i, and the second bit stream 2i+1 output by the FEC encoding may include multiple sixth bit sets 2i+1. It should be noted that the input processing granularity of the FEC encoding is K, and the corresponding output granularity is N. Considering K / N = 111 / 128, the coding redundancy of the FEC encoding is N / K-1 = 15.3%. As an example, K = 3552, N = 4096, and the FEC encoding uses extended BCH (256, 239). The FEC encoding process encodes each of the 2 bit rows in the fifth bit set, totaling 1776 × 2 = 3552 bits, and adds parity bits to obtain a total of 4096 encoded bits. This operation is performed 21 times to obtain the sixth bit set. The FEC encoding process encodes each bit row in the fifth bit set, totaling 111 bits, and adds 17 parity bits to obtain a row in the sixth bit set, totaling 128 bits. More specifically, a bit row in a bit block row in the fifth bit set (which can be considered the bit block row at the current moment) totaling 111 bits is combined with the 128 bits in the previous bit block rows in the fifth bit set (which can be considered the bit block rows at the previous moment), totaling 111 + 128 = 239 bits. This is then extended (256, 239) encoding, with 17 parity bits added, to obtain a codeword of 256 bits. It should be understood that the FEC encoding process is a convolutional algebraic code, also known as a spatially coupled code.

[0352] It should be noted that the second bit stream contains multiple sixth bit sets, and the bits in each sixth bit set are distributed into 42 rows and 8 columns, totaling 336 bit blocks, wherein each bit block is a square matrix containing 16 bit rows and 16 bit columns. Typically, the 256 bits in each of the square matrices are continuous on the second data stream. Figure 16 is a schematic diagram of a bit block with 8 columns per row in an embodiment of the present application. As shown in Figure 16, each row of bit blocks contains 8 bit blocks, and the total number of bits is 2048 bits. It should be understood that from the end of FEC encoding until the completion of the third interleaving, the intermediate fourth interleaving, fifth interleaving, intra-matrix interleaving, and inter-matrix interleaving operations are all performed with a granularity of 42 rows and 8 columns, totaling 336 bit blocks. It should be noted that in some specific applications, the fourth interleaving may be performed at a granularity of 3 rows and 8 columns, totaling 24 bit blocks. In this case, the fourth interleaving is time-varying, meaning that the operations on the 3 rows and 8 columns, totaling 24 bit blocks, are different at different times. In other specific applications, the fourth interleaving may be performed at a granularity of 6 rows and 8 columns, totaling 48 bit blocks. In this case, the fourth interleaving is time-varying, meaning that the operations on the 6 rows and 8 columns, totaling 48 bit blocks, are different at different times. For simplicity of description, this application material performs the fourth interleaving, fifth interleaving, intra-matrix interleaving, and inter-matrix interleaving operations at a granularity of 42 rows and 8 columns, totaling 336 bit blocks.

[0353] FIG17 is a schematic diagram of a sixth bit set in an embodiment of the present application. As shown in FIG17 , the sixth bit set is in the form of a rectangular block of bits. The square matrix of the sixth bit set in row i2 and column j2 is denoted as Where 0≤i2<42 and 0≤j2<8.

[0354] In some specific applications, bit blocks (0≤i2<42 and 0≤j2<8) contains 16 rows and 16 columns, totaling 256 bits, which are continuous on the second bit stream. More specifically, FIG9 shows a specific distribution, in which each bit block The bit at row r0 and column c0 (0≤r0<16 and 0≤c0<16) in the bit block (0≤i2<42 and 0≤j2<8) corresponds to bit 16×r0+c0 of the 256 bits. For example, the bit at row r0=1 and column c0=0 of the bit block corresponds to bit 16 of the 256 bits. For another example, the bit at row r0=2 and column c0=3 of the bit block corresponds to bit 35 of the 256 bits.

[0355] It should be noted that in some specific applications, the specific distribution of the 336 bit blocks in 42 rows and 8 columns in the sixth bit set on the second bit stream can be a continuous distribution of 2048 bits in 1 row of bit blocks. For example, The 8 bit blocks of 2048 bits are continuous on the second bit stream, where 0≤i2<42. In other specific applications, the specific distribution of the 42 rows and 8 columns of 336 bit blocks in the sixth bit set on the second bit stream can be continuous distribution of 2 rows of bit blocks with a total of 4096 bits. For example, The 16 bit blocks of 4096 bits are continuous on the second bit stream, where 0≤i2<21. In some specific applications, the specific distribution of the 42 rows and 8 columns of 336 bit blocks in the sixth bit set on the second bit stream can be continuous distribution of 3 rows of bit blocks with a total of 6144 bits. For example, The 24 bit blocks of 6144 bits are continuous on the second bit stream, where 0≤i2<14. In some specific applications, the specific distribution of the 336 bit blocks in 42 rows and 8 columns in the sixth bit set on the second bit stream can be continuous distribution of 6 rows of bit blocks with a total of 12288 bits. For example, The 48-bit blocks totaling 12288 bits are continuous on the second bit stream, where 0≤i2<7.

[0356] As shown in FIG17 , the bits in the sixth bit set are distributed as 42 rows and 8 columns, totaling 336 bit blocks. (0≤i2<42 and 0≤j2<8). The bits in the leftmost 5 columns (i.e., columns 0-4) of the sixth bit set are the bits in the bit block, i.e., the bit block filled with the shaded background shown in FIG17. (0≤i2<42 and 0≤j2<5), some bits from the second bit set that have been processed by PCS and bits from the third bit set that have not been processed by PCS. The 5th column of the bit block in the sixth bit set (0≤i2<42), and the 6th column bit block The leftmost 15 bit columns in (0≤i2<42), a total of 16+15=31 bits, are from the remaining bits of the second bit set processed by PCS (i.e., not including bits from the third bit set). The sixth bit block in the sixth bit set The rightmost bit column and the 7th bit block in (0≤i2<42) (0≤i2<42), and the bits in the 1+16=17 bit column are parity bits obtained from FEC encoding.

[0357] It should be noted that the specific bit block distribution of the sixth bit set 2i on the second bit stream 2i and the sixth bit set 2i+1 on the second bit stream 2i+1 can be understood with reference to FIG17 , but the specific bit pattern of each bit block (square matrix) is not completely consistent, that is, the sixth bit set 2i (0≤i2<42 and 0≤j2<8) and the sixth bit set 2i+1 The specific bit patterns (0≤i²<42 and 0≤j²<8) are not exactly the same. The bit block (square matrix) patterns in the sixth bit set 2i and the sixth bit set 2i+1 are described below. Figure 18(a) is a schematic diagram of a ninth bit pattern in an embodiment of the present application; Figure 18(b) is a schematic diagram of a tenth bit pattern in an embodiment of the present application.

[0358] For 0≤i2<42 and 0≤j2<6, the bit block (square matrix) in the sixth bit set 2i is The bit pattern and the corresponding bit block (square matrix) in the fifth bit set 2i before encoding Similarly, the bit block (square matrix) in the sixth bit set 2i+1 The bit pattern and the corresponding bit block (square matrix) in the fifth bit set 2i+1 before encoding Same.

[0359] For 0≤i2<42 and j2=6, the bit blocks (square matrix) in the sixth bit set 2i and the sixth bit set 2i+1 are The bit pattern uses the ninth bit pattern. As an example, the ninth bit pattern when the first symbol mapping is used is shown in Figure 18(a), which contains 240 non-shaded (blank) background-filled bits and 16 shaded background-filled bits. The non-shaded (blank) background-filled bits are from the second bit set processed by the PCS, and the shaded background-filled bits are the parity bits encoded by the FEC.

[0360] For 0≤i2<42 and j2=7, the bit blocks (square matrix) in the sixth bit set 2i and the sixth bit set 2i+1 are The bit pattern of the first symbol mapping is the tenth bit pattern. As an example, the tenth bit pattern when the first symbol mapping is used is shown in FIG18( b ), which contains 256 bits filled with shaded backgrounds. The shaded background filled bits are parity bits of the FEC encoding.

[0361] In some specific applications, a sixth bit set 2i in the second bit stream 2i is obtained by directly adding parity bits to a fifth bit set 2i before encoding, and a sixth bit set 2i+1 in the second bit stream 2i+1 is obtained by directly adding parity bits to a fifth bit set 2i+1 before encoding. More specifically, the bit data of bit columns 0-111 in the sixth bit set 2i in the second bit stream 2i is equal to the bit data of bit columns 0-111 in the fifth bit set 2i before encoding; and the bit data of bit columns 0-111 in the sixth bit set 2i+1 in the second bit stream 2i+1 is equal to the bit data of bit columns 0-111 in the fifth bit set 2i+1 before encoding.

[0362] It should be noted that the bits in the second bit set that have undergone PCS processing are used as amplitude bits in symbol mapping (also known as modulation), while the bits in the third bit set that have not undergone PCS processing and the parity bits obtained after FEC encoding are used as sign bits in symbol mapping (also known as modulation). For the sixth bit set 2i and the sixth bit set 2i+1 shown in Figure 17 , when their bit blocks use the bit patterns shown in Figures 11(a), 11(b), 11(c), and 13 , the bits in the shaded background portion of the bit pattern come from the bits in the third bit set that have not undergone PCS processing, i.e., the sign bits; the bits in the unshaded background portion of the bit pattern come from the bits in the second bit set that have undergone PCS processing, i.e., the amplitude bits. When the bit blocks use the bit patterns shown in Figures 18(a) and 18(b), the bits in the shaded background portion of the bit pattern come from the parity bits obtained by FEC encoding, i.e., the sign bits; the bits in the unshaded (blank) background portion of the bit pattern come from the bits in the second bit set that have undergone PCS processing, i.e., the amplitude bits.

[0363] It should be noted that the bit blocks (square matrix) of the sixth bit set 2i and the sixth bit set 2i+1 are distributed as shown in FIG17 , but the specific bit blocks included therein are The patterns are not exactly the same. More specifically, the bit blocks (0≤i1<42 and 0≤j1<5) have different distribution patterns, that is, the distribution positions of the amplitude bits and sign bits in the bit blocks are different. It should be understood that the second bit stream 2i after "FEC encoding" can include multiple sixth bit sets 2i, and the second bit stream 2i+1 can include multiple sixth bit sets 2i+1.

[0364] (3) Second interweaving:

[0365] As shown in Figure 15, the second interleaving may include the fourth interleaving and the fifth interleaving, which are two steps in total. More specifically, the second interleaving 2i includes the fourth interleaving 2i and the fifth interleaving 2i, and the second interleaving 2i+1 includes the fourth interleaving 2i+1 and the fifth interleaving 2i+1.

[0366] A sixth bit set 2i in the second bit stream 2i, which is distributed as a block of 42 rows and 8 columns, is fed into the fourth interleaver 2i to obtain a ninth bit set 2i. The ninth bit set 2i, which is distributed as a block of 42 rows and 8 columns, is fed into the fifth interleaver 2i to obtain a seventh bit set 2i. Similarly, a sixth bit set 2i+1 in the second bit stream 2i+1, which is distributed as a block of 42 rows and 8 columns, is fed into the fourth interleaver 2i+1 to obtain a ninth bit set 2i+1. The ninth bit set 2i+1, which is distributed as a block of 42 rows and 8 columns, is fed into the fifth interleaver 2i+1 to obtain a seventh bit set 2i+1. It should be understood that, as shown in FIG15 , the fifth bit stream 2i outputted by the fourth interleaver 2i may include multiple ninth bit sets 2i, and the fifth bit stream 2i+1 outputted by the fourth interleaver 2i+1 may include multiple ninth bit sets 2i+1. The third bit stream 2i outputted by the fifth interleaver 2i may include multiple seventh bit sets 2i, and the third bit stream 2i+1 outputted by the fifth interleaver 2i+1 may include multiple seventh bit sets 2i+1.

[0367] The fourth interleaving and the fifth interleaving are described below respectively.

[0368] In some specific application scenarios, the fourth interleaving pairs are 168 bit blocks from j2=4 to j2=7 in the sixth bit set. The bits in (0≤i2<42 and 4≤j2<8) are interleaved and disrupted to obtain the ninth bit set, that is, the 168 bit blocks from j2=0 to j2=3 in the sixth bit set are not changed. (0≤i2<42 and 0≤j2<4). Furthermore, in some specific application scenarios, the fourth interleaving does not change the fourth block column in the sixth bit set. The bit positions of some bit columns in (0≤i2<42); for example, The bit positions of the first (leftmost) bit columns in (0≤i2<42), that is, The bits of the first (i.e., leftmost) bit columns in (0≤i2<42) do not participate in the fourth interleaving. The bits of the first (i.e., leftmost) 10 bit columns in (0≤i2<42) do not participate in the fourth interleaving operation, i.e. Columns 10, 11, 12, 13, 14, and 15, combined The fourth interleaving is performed on bits of a total of 54 bit columns.

[0369] FIG19 is a schematic diagram of a ninth bit set in an embodiment of the present application. As shown in FIG19 , the bits in the ninth bit set obtained after the fourth interleaving are distributed as 42 rows and 8 columns, with a total of 336 bit blocks. (0≤i3<42 and 0≤j3<8). It should be noted that in the above 42 rows and 8 columns with a total of 336 bit blocks C, all bit blocks (0≤i3<42 and 0≤j3<8) are all 16 rows and 16 columns of bits (i.e., 16×16=256 bits), as shown in Figure 9. For simplicity of description, (r3, c3) represents the bit block located in the j3th square array in the i3th square array row. In some specific applications, the bit block A total of 256 bits, comprising 16 rows and 16 columns, are continuous on the fifth bit stream.

[0370] The bit block patterns in the ninth bit set 2i and the ninth bit set 2i+1 are introduced below respectively.

[0371] Referring to the schematic diagram of the 42-row and 8-column bit block shown in FIG19 , the following describes the bit block in the ninth bit set 2i on the fifth bit stream 2i. (0≤i3<42 and 0≤j3<8) pattern.

[0372] 1) For 0≤i3<21 and i3%3=0, or 21≤i3<42 and i3%3=2, i.e., i3=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the first bit pattern. As an example, the first bit pattern when the first symbol mapping is adopted is shown in FIG11(a), wherein the bits filled with the shaded background are bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the bits filled with the non-shaded (blank) background are bits from the second bit set that have been processed by PCS.

[0373] 2) For 0≤i3<21 and i3%3=1, or 21≤i3<42 and i3%3=0, i.e., i3=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the second bit pattern. As an example, the second bit pattern when the first symbol mapping is adopted is shown in FIG11( b ), wherein the bits filled with the shaded background are bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the bits filled with the non-shaded (blank) background are bits from the second bit set that have been processed by PCS.

[0374] 3) For 0≤i3<21 and i3%3=2, or 21≤i3<42 and i3%3=1, i.e., i3=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j3<8: the corresponding 112-bit block The bit pattern uses a third bit pattern. As an example, the third bit pattern when the first symbol mapping is used is shown in FIG11( c ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0375] Referring to the schematic diagram of the 42-row and 8-column bit block shown in FIG19 , the following describes the bit block in the ninth bit set 2i+1 on the fifth bit stream 2i+1. (0≤i3<42 and 0≤j3<8) pattern.

[0376] 1) For 0≤i3<21 and i3%3=0, or 21≤i3<42 and i3%3=2, i.e., i3=0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, 41, and 0≤j3<8: the corresponding 112-bit block The bit pattern uses a third bit pattern. As an example, the third bit pattern when the first symbol mapping is used is shown in FIG11( c ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0377] 2) For 0≤i3<21 and i3%3=1, or 21≤i3<42 and i3%3=0, i.e., i3=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the first bit pattern. As an example, the first bit pattern when the first symbol mapping is adopted is shown in FIG11(a), wherein the bits filled with the shaded background are bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the bits filled with the non-shaded (blank) background are bits from the second bit set that have been processed by PCS.

[0378] 3) For 0≤i3<21 and i3%3=2, or 21≤i3<42 and i3%3=1, i.e., i3=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the second bit pattern. As an example, the second bit pattern when the first symbol mapping is adopted is shown in FIG11( b ), wherein the bits filled with the shaded background are bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the bits filled with the non-shaded (blank) background are bits from the second bit set that have been processed by PCS.

[0379] It should be noted that the bit blocks (square matrix) of the ninth bit set 2i and the ninth bit set 2i+1 are distributed as shown in FIG19 , but the specific bit blocks they contain are The patterns are not exactly the same. More specifically, the bit blocks The distribution patterns are different, that is, the distribution positions of the amplitude bits and sign bits in the bit blocks are different. It should be understood that the third bit stream 2i after the "fourth interleaving" can include multiple ninth bit sets 2i, and the third bit stream 2i+1 can include multiple ninth bit sets 2i+1.

[0380] It should be noted that the bit patterns of the eight bit blocks in each row of the sixth bit set obtained after FEC encoding are not exactly the same. The fourth interleaving ensures that the bit patterns of the eight bit blocks in each row of the ninth bit set are the same. In some specific applications, the fourth interleaving may also be referred to as post-FEC permutation.

[0381] The fifth interleave pairs each bit block in the ninth bit set (0≤i4<42 and 0≤j4<8) are interleaved and shuffled to obtain the seventh bit set. As shown in Figure 20, the seventh bit set is distributed into 42 rows and 8 columns, with a total of 336 bit blocks. (0≤i4<42 and 0≤j4<8). Each bit block (0≤i4<42 and 0≤j4<8) are all 16 rows and 16 columns of bits (i.e., 16×16=256 bits), as shown in Figure 9. For simplicity of description, (r4, c4) represents the bit block located in the j4th square array in the i4th square array row. In some specific applications, the bit block A total of 256 bits, comprising 16 rows and 16 columns, are continuous on the third bit stream.

[0382] In some specific applications, the fifth interleaving is performed on each bit block in the ninth bit set. Each bit row in (0≤i3<42 and 0≤j3<8) has 16 bits in total, and the corresponding bit blocks in the seventh bit set are obtained by permutation. Where i4=i3, and j4=j3. The fifth interleaving shuffles the order of 16 bits in each row of each bit block, which is also called row permutation, row interleaving, or "^r" row permutation.

[0383] More specifically, the bit block in the seventh bit set The bit in the r4th bit row and c4th bit column (r4, c4) is a block of bits from the ninth bit set. The bit in the r3th bit row and c3th bit column (r3, c3), where r4 = r3 and c4 = c3^r3. Here, a^b represents the bitwise exclusive OR of two positive integers a and b. Figure 21 is a schematic diagram of an implementation of the fifth interleaving in the embodiment of the present application. As shown in Figure 21, the specific interleaving method can be understood with reference to Figure 21.

[0384] The bit block patterns in the seventh bit set 2i and the seventh bit set 2i+1 are introduced below respectively.

[0385] FIG20 is a schematic diagram of a seventh bit set in an embodiment of the present application. As shown in FIG20, referring to the schematic diagram of the 42 rows and 8 columns of the bit block shown in FIG20, the following describes the bit block in the seventh bit set 2i on the third bit stream 2i. (0≤i4<42 and 0≤j4<8) pattern. Figure 22(a) is a schematic diagram of an eleventh bit pattern in an embodiment of the present application; Figure 22(b) is a schematic diagram of a twelfth bit pattern in an embodiment of the present application; Figure 22(c) is a schematic diagram of a thirteenth bit pattern in an embodiment of the present application;

[0386] 1) For 0≤i4<21 and i4%3=0, or 21≤i4<42 and i4%3=2, i.e., i4=0,3,6,9,12,15,18,23,26,29,32,35,38,41, and 0≤j4<8: the corresponding 112-bit block The bit pattern adopts an eleventh bit pattern. As an example, the eleventh bit pattern when the first symbol mapping is adopted is shown in FIG22(a), wherein the bits filled with the shaded background are bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the bits filled with the non-shaded (blank) background are bits from the second bit set that have been processed by PCS.

[0387] 2) For 0≤i4<21 and i4%3=1, or 21≤i4<42 and i4%3=0, i.e., i4=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j4<8: the corresponding 112-bit block The bit pattern uses the twelfth bit pattern. As an example, the twelfth bit pattern when the first symbol mapping is used is shown in FIG22( b ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0388] 3) For 0≤i4<21 and i4%3=2, or 21≤i4<42 and i4%3=1, i.e., i4=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j4<8: the corresponding 112-bit block The bit pattern uses the thirteenth bit pattern. As an example, the thirteenth bit pattern when the first symbol mapping is used is shown in FIG22( c ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0389] 20 shows a schematic diagram of a 42-row 8-column bit block. The following describes the bit block in the seventh bit set 2i+1 on the third bit stream 2i+1. (0≤i4<42 and 0≤j4<8) pattern.

[0390] 1) For 0≤i4<21 and i4%3=0, or 21≤i4<42 and i4%3=2, i.e., i4=0,3,6,9,12,15,18,23,26,29,32,35,38,41, and 0≤j4<8: the corresponding 112-bit block The bit pattern uses the thirteenth bit pattern. As an example, the thirteenth bit pattern when the first symbol mapping is used is shown in FIG22( c ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0391] 2) For 0≤i4<21 and i4%3=1, or 21≤i4<42 and i4%3=0, i.e., i4=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j4<8: the corresponding 112-bit block The bit pattern adopts an eleventh bit pattern. As an example, the eleventh bit pattern when the first symbol mapping is adopted is shown in FIG22(a), wherein the bits filled with the shaded background are bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the bits filled with the non-shaded (blank) background are bits from the second bit set that have been processed by PCS.

[0392] 3) For 0≤i4<21 and i4%3=2, or 21≤i4<42 and i4%3=1, i.e., i4=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j4<8: the corresponding 112-bit block The bit pattern uses the twelfth bit pattern. As an example, the twelfth bit pattern when the first symbol mapping is used is shown in FIG22( b ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0393] It should be noted that the bit blocks (square matrix) of the seventh bit set 2i and the seventh bit set 2i+1 are distributed as shown in FIG20 , but the specific bit blocks they contain are The patterns are not exactly the same. More specifically, the bit blocks The distribution patterns are different, that is, the distribution positions of the amplitude bits and sign bits in the bit blocks are different. It should be understood that the fourth bit stream 2i after the "fifth interleaving" can include multiple seventh bit sets 2i, and the fourth bit stream 2i+1 can include multiple seventh bit sets 2i+1.

[0394] (4) The third interweaving:

[0395] As shown in FIG15 , the third interleaving may also be referred to as block interleaving, and the third interleaving includes intra-block interleaving and inter-block interleaving.

[0396] A seventh bit set 2i in the third bit stream 2i, distributed across 42 rows and 8 columns, is fed into intra-matrix interleaving 2i to obtain a tenth bit set 2i. A seventh bit set 2i+1 in the third bit stream 2i+1, distributed across 42 rows and 8 columns, is interleaved intra-matrix 2i+1 to obtain a tenth bit set 2i+1. Inter-matrix interleaving i shuffles the order of the tenth bit set 2i and the tenth bit set 2i+1 to obtain an eighth bit set i distributed across 84 rows and 8 columns. It should be noted that in some specific applications, matrix interleaving is also referred to as OFEC interleaving.

[0397] The following describes the intra-matrix interleaving and inter-matrix interleaving respectively.

[0398] FIG23 is a schematic diagram of an implementation method of intra-matrix interleaving in an embodiment of the present application. As shown in FIG23 , intra-matrix interleaving first receives each seventh bit set of bit blocks. (0≤i4<42 and 0≤j4<8) After interleaving within the square matrix, the bit distribution is 42 rows and 8 columns, with a total of 336 bit blocks, the bit block of the tenth bit set (0≤i5<42 and 0≤j5<8). That is, each input matrix of 16 rows and 16 columns is interleaved and shuffled according to the interleaving rules shown in Figure 23 to obtain an output matrix of 16 rows and 16 columns. The element of the mth row and nth column (0≤m<16 and 0≤n<16) in the matrix of 16 rows and 16 columns in Figure 23 is (a,b), which means that the bits of the mth row and nth column in the output matrix after intra-matrix interleaving come from the bits of the ath row and bth column in the input matrix. For example, the element of the 1st row and 0th column in Figure 23 is (14,15), then the bits of the 1st row and 0th column in the output matrix after intra-matrix interleaving come from the bits of the 14th row and 15th column in the input matrix. More specifically, the bit block after intra-matrix interleaving The bit at row 1, column 0 in the bit block In some specific applications, the square matrix The total of 256 bits, consisting of 16 rows and 16 columns, are continuous in the bit stream output by the interleaving in the square matrix.

[0399] The following describes the bit block patterns in the tenth bit set 2i and the tenth bit set 2i+1, respectively. Figure 24(a) is a schematic diagram of a fourteenth bit pattern in an embodiment of the present application; Figure 24(b) is a schematic diagram of a fifteenth bit pattern in an embodiment of the present application; and Figure 24(c) is a schematic diagram of a sixteenth bit pattern in an embodiment of the present application.

[0400] The following describes the bit block in the tenth bit set 2i. (0≤i5<42 and 0≤j5<8) pattern.

[0401] 1) For 0≤i5<21 and i5%3=0, or 21≤i5<42 and i5%3=2, i.e., i5=0,3,6,9,12,15,18,23,26,29,32,35,38,41, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the fourteenth bit pattern. As an example, the fourteenth bit pattern when the first symbol mapping is used is shown in FIG24(a), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the non-shaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0402] 2) For 0≤i5<21 and i5%3=1, or 21≤i5<42 and i5%3=0, i.e., i5=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the fifteenth bit pattern. As an example, the fifteenth bit pattern when the first symbol mapping is used is shown in FIG24( b ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0403] 3) For 0≤i5<21 and i5%3=2, or 21≤i5<42 and i5%3=1, i.e., i5=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the sixteenth bit pattern. As an example, the sixteenth bit pattern when the first symbol mapping is used is shown in FIG24( c ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the non-shaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0404] The following describes the bit block in the tenth bit set 2i+1. (0≤i5<42 and 0≤j5<8) pattern.

[0405] 1) For 0≤i5<21 and i5%3=0, or 21≤i5<42 and i5%3=2, i.e., i5=0,3,6,9,12,15,18,23,26,29,32,35,38,41, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the fourteenth bit pattern. As an example, the fourteenth bit pattern when the first symbol mapping is used is shown in FIG24( c ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the non-shaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0406] 2) For 0≤i5<21 and i5%3=1, or 21≤i5<42 and i5%3=0, i.e., i5=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the fourteenth bit pattern. As an example, the fourteenth bit pattern when the first symbol mapping is used is shown in FIG24(a), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the non-shaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0407] 3) For 0≤i5<21 and i5%3=2, or 21≤i5<42 and i5%3=1, i.e., i5=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the fifteenth bit pattern. As an example, the fifteenth bit pattern when the first symbol mapping is used is shown in FIG24( b ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0408] It should be noted that the bit blocks (square matrix) of the tenth bit set 2i and the tenth bit set 2i+1 are The distribution patterns are different, that is, the distribution positions of the amplitude bits and sign bits in the bit block are different.

[0409] After the bits are interleaved within the matrix, they are interleaved between matrices to improve the overall anti-burst performance. The following describes the inter-matrix interleaving operation.

[0410] Figure 25 is a schematic diagram of an embodiment of inter-matrix interleaving in an embodiment of the present application. As shown in Figure 25, inter-matrix interleaving includes an interleaver buffer M with 84 rows and 8 columns, each row includes 8 matrices, and each matrice includes 16 rows and 16 columns for a total of 256 bits, that is, the interleaver buffer M contains a total of 84×16=1344 bit rows and 8×16=128 bit columns. The interleaver buffer size of inter-matrix interleaving is 84×8×256=172032 bits, wherein the output packet comes from the output packet of interleaving 2i within the matrix and is located in the even rows of the interleaver buffer M, and the output packet comes from the output packet of interleaving 2i+1 within the matrix and is located in the odd rows of the interleaver buffer M.

[0411] FIG26 is a schematic diagram of a bit set after interleaving between matrices in an embodiment of the present application. As shown in FIG26 , the bit block of 84 rows and 8 columns in the interleaving buffer M (0≤i6<84 and 0≤j6<8), the following describes the bit block pattern.

[0412] 1) For 0≤i6<42 and i6%3=0, or 42≤i6<84 and i6%3=1, i.e., i6=0,3,6,9,12,15,18,21,24,27,30,33,36,39,43,46,49,52,55,58,61,64,67,70,73,76,79,82, and 0≤j5<8: corresponding 224-bit block The bit pattern uses the fourteenth bit pattern. As an example, the fourteenth bit pattern when the first symbol mapping is used is shown in FIG24(a), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the non-shaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0413] 2) For 0≤i6<42 and i6%3=2, or 42≤i6<84 and i6%3=0, i.e., i6=2,5,8,11,14,17,20,23,26,29,32,35,38,41,42,45,48,51,54,57,60,63,66,69,72,75,78,81, and 0≤j5<8: the corresponding 224-bit block The bit pattern uses the fifteenth bit pattern. As an example, the fifteenth bit pattern when the first symbol mapping is used is shown in FIG24( b ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the unshaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0414] 3) For 0≤i6<42 and i6%3=1, or 42≤i6<84 and i6%3=2, i.e., i6=1,4,7,10,13,16,19,22,25,28,31,34,37,40,44,47,50,53,56,59,62,65,68,71,74,77,80,83, and 0≤j5<8: corresponding 224-bit block The bit pattern uses the sixteenth bit pattern. As an example, the sixteenth bit pattern when the first symbol mapping is used is shown in FIG24( c ), where the shaded background is filled with bits from the third bit set that have not been processed by PCS and / or parity bits from FEC coding, and the non-shaded (blank) background is filled with bits from the second bit set that have been processed by PCS.

[0415] The interleaving buffer M for interleaving between square matrices can be divided into four sets, as shown in Figure 25. The 0th set contains the square matrices of the 0th, 2nd, 4th, ..., 40th rows in the interleaving buffer M, totaling 21×16×128=43008 bits. The 1st set contains the square matrices of the 1st, 3rd, 5th, ..., 41st rows in the interleaving buffer M, totaling 43008 bits. The 2nd set contains the square matrices of the 42nd, 44th, 46th, ..., 82nd rows in the interleaving buffer M, totaling 43008 bits. The 3rd set contains the square matrices of the 43rd, 45th, 47th, ..., 83rd rows in the interleaving buffer M, totaling 43008 bits.

[0416] From the interleaved buffer M, with a granularity of 8 bits, polling is performed to read the bits in each column from each set. After reading all the bits in each column, the bits in the next column are read. First, the first group of 8 bits are read from the 0th set from top to bottom, and then the first 8 bits are read from the 1st set, the 2nd set, and the 3rd set from top to bottom, respectively. A total of 32 bits are read in one cycle. Then, the next cycle reads the next group of 8 bits from the 0th set, the 1st set, the 2nd set, and the 3rd set from top to bottom, respectively, for a total of 32 bits. After a total of 42 cycles, the 1344 bits of the current column are read out. For reading the bits in each column from each set, the specific operations are as follows:

[0417] First, read 8 bits from the 0th row of the interleaved buffer M from top to bottom (bit rows 0-7 in the matrix).

[0418] Read 8 bits from the first row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-7 in the matrix),

[0419] Read 8 bits from the 42nd row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-7 in the matrix),

[0420] Read 8 bits from the 43rd row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-7 in the matrix),

[0421] Then read 8 bits from the 0th row of the matrix in the interleaving buffer M from top to bottom (the 8th to 15th bit rows in the matrix),

[0422] Read 8 bits from the first row of the matrix in the interleaving buffer M from top to bottom (bit rows 8-15 in the matrix),

[0423] Read 8 bits from the 42nd row of the matrix in the interleaving buffer M from top to bottom (bit rows 8-15 in the matrix),

[0424] Read 8 bits from the 43rd row of the interleaving buffer M from top to bottom (bit rows 8-15 in the matrix),

[0425] Then read 8 bits from the second row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-7 in the matrix),

[0426] ..., until a total of 1344 bits in the current bit column in the interleaving buffer M are completely read out.

[0427] Next, similarly, the above operations are repeated to completely read out the 1,344 bits in the next bit column in interleaving buffer M, until the 1,344 bits in the last bit column in interleaving buffer M are completely read out. At this point, all 172,032 bits in interleaving buffer M have been read out. The 172,032 bits read from interleaving buffer M serve as the output of the third interleaving operation, i.e., the eighth bit set. It should be understood that interleaving buffer M contains a total of 128 bit columns.

[0428] It should be noted that in the first symbol mapping, bits b2 and b4 are two amplitude bits of the DP-64QAM symbol on the I direction component on the X polarization, and bits b8 and b 10 The two amplitude bits of the DP-64QAM symbol on the Q direction component on the X polarization, bits b3 and b5 are the two amplitude bits of the DP-64QAM symbol on the I direction component on the Y polarization, bits b9 and b 11 It is the two amplitude bits of the Q direction component of the DP-64QAM symbol on the Y polarization.

[0429] It should be noted that the bit stream output by the third interleaving (including intra-matrix interleaving and inter-matrix interleaving) is merged to obtain the fourth bit data, and the fourth bit data is symbol mapped and polarization divided to obtain a dual-polarization symbol. Specifically, a total of L bit streams output by the third interleaving are polled and merged in a group of S=12 bits, and then symbol mapping is performed, that is, the 12 bits output from the third interleaving 0 are mapped to a dual-polarization modulation symbol, and then the 12 bits output from the third interleaving 1 are mapped to a dual-polarization modulation symbol, and then until the 12 bits output from the third interleaving L-1 are mapped to a dual-polarization modulation symbol. The interleaving buffer used for the inter-matrix interleaving in the third interleaving contains 172032 bits, that is, the interleaving granularity is 172032 bits, and the 172032 bits are mapped to 172032 / 12=14336 DP-64QAM symbols. That is, the output of the third interleaving is the eighth bit set, and a total of 172032 bits are mapped to 172032 / 12=14336 DP-64QAM symbols.

[0430] FIG27 is a schematic diagram of a constellation diagram in one polarization direction in an embodiment of the present application. As shown in FIG27 , in some specific application scenarios, by designing specific PCS processing operations, some symbols (constellation points) in the 64QAM constellation diagram may not appear, such as only the inner 36 symbols. In this case, DP-64QAM symbols are also called DP-36QAM symbols, and 64QAM modulation may also be called 36QAM modulation. For simplicity of description, this application does not distinguish between DP-36QAM.

[0431] It should be noted that the above-mentioned description of the various operations of the second data sub-processing i (i=0, 1,…, L-1) is based on the example of the first symbol mapping scheme. The following describes the first to sixteenth bit patterns when the second, third, and fourth symbol mapping schemes are adopted, respectively. Figure 28(a) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 28(b) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 28(c) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 29(a) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 29(b) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 29(c) is a schematic diagram of another bit pattern in an embodiment of the present application. Figure 30(a) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 30(b) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 30(c) is a schematic diagram of another bit pattern in an embodiment of the present application. Figure 31(a) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 31(b) is a schematic diagram of another bit pattern in an embodiment of the present application; Figure 31(c) is a schematic diagram of another bit pattern in an embodiment of the present application.

[0432] 1) When the second symbol mapping is adopted:

[0433] The first bit pattern adopts the bit distribution pattern shown in FIG. 28( a ), the second bit pattern adopts the bit distribution pattern shown in FIG. 28( b ), and the third bit pattern adopts the bit distribution pattern shown in FIG. 28( c ).

[0434] In some specific embodiments, the fourth bit pattern adopts the bit distribution pattern shown in FIG29( a). In other specific embodiments, the fourth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0435] In some specific embodiments, the fifth bit pattern adopts the bit distribution pattern shown in FIG29( b). In other specific embodiments, the fifth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0436] In some specific embodiments, the sixth bit pattern adopts the bit distribution pattern shown in FIG29( c). In other specific embodiments, the sixth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0437] The seventh bit pattern adopts the bit distribution pattern shown in Figure 13, the eighth bit pattern adopts the bit distribution pattern shown in Figure 14, the ninth bit pattern is shown in Figure 18(a), the tenth bit pattern is shown in Figure 18(b), the eleventh bit pattern is shown in Figure 30(a), the twelfth bit pattern is shown in Figure 30(b), the thirteenth bit pattern is shown in Figure 30(c), the fourteenth bit pattern is shown in Figure 31(a), the fifteenth bit pattern is shown in Figure 31(b), and the sixteenth bit pattern is shown in Figure 31(c).

[0438] 2) When the third symbol mapping is adopted:

[0439] The first bit pattern adopts the bit distribution pattern shown in FIG. 28( b ), the second bit pattern adopts the bit distribution pattern shown in FIG. 28( c ), and the third bit pattern adopts the bit distribution pattern shown in FIG. 28( a ).

[0440] In some specific embodiments, the fourth bit pattern adopts the bit distribution pattern shown in FIG29( b). In other specific embodiments, the fourth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0441] In some specific embodiments, the fifth bit pattern adopts the bit distribution pattern shown in FIG29( c). In other specific embodiments, the fifth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0442] In some specific embodiments, the sixth bit pattern adopts the bit distribution pattern shown in FIG29( a). In other specific embodiments, the sixth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background-filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background-filled bits. As another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background-filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background-filled bits. As yet another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background-filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background-filled bits.

[0443] The seventh bit pattern adopts the bit distribution pattern shown in Figure 13, the eighth bit pattern adopts the bit distribution pattern shown in Figure 14, the ninth bit pattern is shown in Figure 18(a), the tenth bit pattern is shown in Figure 18(b), the eleventh bit pattern is shown in Figure 30(b), the twelfth bit pattern is shown in Figure 30(c), the thirteenth bit pattern is shown in Figure 30(a), the fourteenth bit pattern is shown in Figure 31(b), the fifteenth bit pattern is shown in Figure 31(c), and the sixteenth bit pattern is shown in Figure 31(a).

[0444] 3) When the fourth symbol mapping is adopted:

[0445] The first bit pattern adopts the bit distribution pattern shown in FIG. 28( c ), the second bit pattern adopts the bit distribution pattern shown in FIG. 28( a ), and the third bit pattern adopts the bit distribution pattern shown in FIG. 28( b ).

[0446] In some specific embodiments, the fourth bit pattern adopts the bit distribution pattern shown in FIG29( c). In other specific embodiments, the fourth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0447] In some specific embodiments, the fifth bit pattern adopts the bit distribution pattern shown in FIG29( a). In other specific embodiments, the fifth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0448] In some specific embodiments, the sixth bit pattern adopts the bit distribution pattern shown in FIG29( b). In other specific embodiments, the sixth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0449] The seventh bit pattern adopts the bit distribution pattern shown in Figure 13, the eighth bit pattern adopts the bit distribution pattern shown in Figure 14, the ninth bit pattern is shown in Figure 18(a), the tenth bit pattern is shown in Figure 18(b), the eleventh bit pattern is shown in Figure 30(c), the twelfth bit pattern is shown in Figure 30(a), the thirteenth bit pattern is shown in Figure 30(b), the fourteenth bit pattern is shown in Figure 31(c), the fifteenth bit pattern is shown in Figure 31(a), and the sixteenth bit pattern is shown in Figure 31(b).

[0450] The number of scrambled bits output by the first data processing scr =q×r Frame +d CP It is an integer multiple of L×e, which makes the specific hardware implementation of the entire data processing simpler and has lower power consumption; the number of input bits corresponding to PCS processing k PCS It is an integer multiple of 2, which makes PCS processing easy to implement in hardware and has better performance. scr The scrambled bits are processed by PCS and FEC encoded to obtain bits, It is an integer multiple of the total size of the interleaving buffer M between the two matrices, 172032×2=344064, which makes the specific hardware implementation of the entire data processing simpler and the power consumption lower.

[0451] As shown in FIG6 , the e bits are processed by PCS and the first interleaving to obtain the fourth bit set 2i and the fourth bit set 2i+1. The number of bits in the fourth bit set 2i and the fourth bit set 2i+1 are both 1776×k0 bits. When d scrThe scrambled bits are processed by PCS and FEC, and then interleaved for the second and third times to obtain bits, which after DP-64QAM symbol mapping and polarization division just get 172032 dual-polarization symbols, and after DSP framing just get a superframe. That is, when When , a superframe corresponds to the first data processing each time to obtain r rows and q columns of data from the data frame, which simplifies the data processing. When F DSP superframes as a combination, so that F DSP Superframes correspond to F Frame The first data processing output d scr ×F Frame Bit, now there is Among them F Frame and F DSP is a positive integer. By designing the reserved symbols inserted in each superframe, the receiving end can identify F DSP superframes to identify F Frame The first data processing output d scr ×F Frame The bit corresponds to the boundary.

[0452] In some specific scenarios, consider k0=3, and d scr =168×e, one DSP superframe corresponds to the first data processing of r rows and q columns of data obtained from the data frame each time, which simplifies data processing. In other specific scenarios, consider k0=6, and d scr =84×e, one DSP superframe corresponds to the first data processing of r rows and q columns of data obtained from the data frame each time, which simplifies data processing. In some specific scenarios, consider k0=42, and d scr =12×e, one DSP superframe corresponds to r rows and q columns of data bits obtained from the data frame each time by the first data processing, thereby simplifying data processing.

[0453] As can be seen from the above description of the first and second data processing, DP-64QAM will be adopted in future metropolitan telecom transmission and metropolitan DCI interconnection scenarios, combined with FEC coding and PCS processing technologies to achieve longer transmission distances. The introduction of PCS processing requires that during symbol mapping, the symbol bits mapped to a modulation symbol are equally likely to be 0 or 1, and the amplitude bits mapped to a modulation symbol are unequally likely to be 0 or 1. More specifically, the levels corresponding to the amplitude bits mapped to a modulation symbol may have varying probabilities of 1, 3, 5, or 7. In some specific scenarios, the specific implementation of PCS processing can be designed to prevent the occurrence of level 7, which is also called DP-36QAM modulation. Taking OFEC coding as an example, in order to minimize the impact on the existing OFEC coding and OFEC interleaver, it is necessary to introduce a new interleaver after OFEC coding and before the symbol mapping operation, so that the bits with unequal probabilities of 0 and 1 obtained after PCS processing can be mapped to the amplitude bits of the modulation symbol, realizing the change of the probability of the occurrence of the constellation points while keeping the position of the constellation points unchanged, making them non-uniformly distributed, and improving the overall performance to meet the future demand for longer transmission distances.

[0454] Several specific embodiments are given below in combination with the above introduction to the second data processing.

[0455] Example 1:

[0456] Figure 32 is a schematic diagram of an application scenario of the second data processing in an embodiment of the present application. As shown in Figure 32, consider that the second data processing includes 2 PCS processes and the first interleaving, namely "PCS processing and first interleaving 0" and "PCS processing and first interleaving 1", at this time L=2. The corresponding second data processing includes 4 FEC codes, namely "FEC code 0", "FEC code 1", "FEC code 2" and "FEC code 3". The corresponding second data processing includes 4 second interleavings, namely "second interleaving 0", "second interleaving 1", "second interleaving 2" and "second interleaving 3". The corresponding second data processing includes 2 third interleavings, namely "third interleaving 0" and "third interleaving 1".

[0457] Some bits in the third bit data are fed into PCS processing and first interleaving 0 to obtain first bit stream 0 and first bit stream 1. The bits in the third bit data other than the bits fed into PCS processing and first interleaving 0 are fed into PCS processing and first interleaving 1 to obtain first bit stream 2 and first bit stream 3. The two outputs of each PCS processing and first interleaving are fed into two FEC encodings and two second interleavings, respectively, and the two second interleaving outputs are fed into one third interleaving.

[0458] Specifically, the first bit stream 0 and the first bit stream 1 are respectively sent to FEC coding 0 and FEC coding 1 to obtain the second bit stream 0 and the second bit stream 1, and then the second bit stream 0 and the second bit stream 1 are respectively sent to the second interleaving 0 and the second interleaving 1 to obtain the third bit stream 0 and the third bit stream 1, and then the third bit stream 0 and the third bit stream 1 are sent to the third interleaving 0 to obtain the fourth bit stream 0.

[0459] Similarly, the first bit stream 2 and the first bit stream 3 are respectively sent to FEC encoding 2 and FEC encoding 3 to obtain second bit stream 2 and second bit stream 3, and then the second bit stream 2 and the second bit stream 3 are respectively sent to the second interleaving 2 and the second interleaving 3 to obtain third bit stream 2 and third bit stream 3, and then the third bit stream 2 and the third bit stream 3 are sent to the third interleaving 1 to obtain fourth bit stream 1.

[0460] Finally, the fourth bit stream 0 and the fourth bit stream 1 are sent in and combined to obtain the fourth bit data.

[0461] Example 2:

[0462] Figure 33 is a schematic diagram of another application scenario of the second data processing in an embodiment of the present application. As shown in Figure 33, consider that the second data processing includes 4 PCS processes and the first interleave, namely "PCS process and first interleave 0", "PCS process and first interleave 1", "PCS process and first interleave 2", and "PCS process and first interleave 3". At this time, L=4. The corresponding second data processing includes 8 FEC codes, namely "FEC code 0", "FEC code 1", "FEC code 2", "FEC code 3", "FEC code 4", "FEC code 5", "FEC code 6", and "FEC code 7". The corresponding second data processing includes 8 second interleavings, namely "second interleaving 0", "second interleaving 1", "second interleaving 2", "second interleaving 3", "second interleaving 4", "second interleaving 5", "second interleaving 6", and "second interleaving 7". The corresponding second data processing includes 4 third interleavings, namely "third interleaving 0", "third interleaving 1", "third interleaving 2", and "third interleaving 3".

[0463] Part of the third bit data is sent to PCS processing and first interleaving 0 to obtain first bit stream 0 and first bit stream 1. Part of the third bit data, except the bits sent to PCS processing and first interleaving 0, is sent to PCS processing and first interleaving 1 to obtain first bit stream 2 and first bit stream 3. Part of the third bit data, except the bits sent to PCS processing and first interleaving 0 and PCS processing and first interleaving 1, is sent to PCS processing and first interleaving 2 to obtain first bit stream 4 and first bit stream 5. Part of the third bit data, except the bits sent to PCS processing and first interleaving 0, PCS processing and first interleaving 1, and PCS processing and first interleaving 2, is sent to PCS processing and first interleaving 3 to obtain first bit stream 6 and first bit stream 7. The two outputs of each PCS processing and first interleaving are respectively sent to two FEC codes and two second interleavings, and the two second interleaving outputs are sent to one third interleaving.

[0464] Specifically, the first bit stream 0 and the first bit stream 1 are respectively sent to FEC coding 0 and FEC coding 1 to obtain the second bit stream 0 and the second bit stream 1, and then the second bit stream 0 and the second bit stream 1 are respectively sent to the second interleaving 0 and the second interleaving 1 to obtain the third bit stream 0 and the third bit stream 1, and then the third bit stream 0 and the third bit stream 1 are sent to the third interleaving 0 to obtain the fourth bit stream 0.

[0465] Similarly, the first bit stream 2 and the first bit stream 3 are respectively sent to FEC encoding 2 and FEC encoding 3 to obtain second bit stream 2 and second bit stream 3, and then the second bit stream 2 and the second bit stream 3 are respectively sent to the second interleaving 2 and the second interleaving 3 to obtain third bit stream 2 and third bit stream 3, and then the third bit stream 2 and the third bit stream 3 are sent to the third interleaving 1 to obtain fourth bit stream 1.

[0466] Similarly, the first bit stream 4 and the first bit stream 5 are respectively sent to FEC encoding 4 and FEC encoding 5 to obtain the second bit stream 4 and the second bit stream 5, and then the second bit stream 4 and the second bit stream 5 are respectively sent to the second interleaving 4 and the second interleaving 5 to obtain the third bit stream 4 and the third bit stream 5, and then the third bit stream 4 and the third bit stream 5 are sent to the third interleaving 2 to obtain the fourth bit stream 2.

[0467] Similarly, the first bit stream 6 and the first bit stream 7 are respectively sent to FEC encoding 6 and FEC encoding 7 to obtain the second bit stream 6 and the second bit stream 7, and then the second bit stream 6 and the second bit stream 7 are respectively sent to the second interleaving 6 and the second interleaving 7 to obtain the third bit stream 6 and the third bit stream 7, and then the third bit stream 6 and the third bit stream 7 are sent to the third interleaving 3 to obtain the fourth bit stream 3.

[0468] Finally, the fourth bit stream 0, the fourth bit stream 1, the fourth bit stream 2 and the fourth bit stream 3 are input and combined to obtain the fourth bit data.

[0469] Example 3:

[0470] Considering the use of the first symbol mapping, a sixth bit set 2i in the second bit stream 2i, which is distributed as a 42-row and 8-column bit block, is sent to the fourth interleaving 2i to obtain a ninth bit set 2i, and a sixth bit set 2i+1 in the second bit stream 2i+1, which is distributed as a 42-row and 8-column bit block, is sent to the fourth interleaving 2i+1 to obtain a ninth bit set 2i+1.

[0471] FIG34(a) is a schematic diagram of a bit distribution of the last 51 bit columns in the sixth bit set 2i and the sixth bit set 2i+1 in an embodiment of the present application. As an example, for 0≤i2<42, the bit block in the i2th row and j2=4th column in the sixth bit set 2i and the sixth bit set 2i+1 is: The pattern of the last three bit columns in the 6th bit set 2i and the 6th bit set 2i+1 is shown in FIG34(a), that is, these bits are amplitude bits; the bit blocks of the i2th row and j2=5, 6 and 7th columns in the 6th bit set 2i and the 6th bit set 2i+1 and The pattern of the bits in is shown in Figure 34(a), that is, The bits in are amplitude bits, The first 15 bits in the bit column are all amplitude bits and The last bit column in the bit column all comes from FEC check bits (that is, all are sign bits). The bits in are all from FEC check bits (ie, they are all sign bits).

[0472] Figure 34(b) is a schematic diagram of a bit distribution of the ninth bit set 2i in an embodiment of the present application. The bits of the last 51 bit columns in the sixth bit set 2i are fed into the fourth interleaving 2i to obtain the bits of the last 51 bit columns in the ninth bit set 2i as shown in Figure 34(b).

[0473] In the ninth bit set 2i, for 0≤i3<21 and i3%3=0, or, 21≤i3<42 and i3%3=2, i.e., i3=0,3,6,9,12,15,18,23,26,29,32,35,38,41: when j3=4, the bit block The distribution patterns of the last three bit columns in the bit block, i.e., the bit columns r3=13, r3=14, and r3=15, are shown in FIG11(a) for the 13th, 14th, and 15th bit columns. When j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(a).

[0474] In the ninth bit set 2i, for 0≤i3<21 and i3%3=1, or, 21≤i3<42 and i3%3=0, i.e., i3=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39: when j3=4, the bit block The distribution patterns of the last three bit columns in the bit block, i.e., the bit columns r3=13, r3=14, and r3=15, are shown in FIG11(b) for the 13th, 14th, and 15th bit columns; when j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(b).

[0475] In the ninth bit set 2i, for 0≤i3<21 and i3%3=2, or, 21≤i3<42 and i3%3=1, i.e., i3=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40: when j3=4, the bit block The distribution patterns of the last three bit columns in the bit block, i.e., the bit columns r3=13, r3=14, and r3=15, are shown in FIG11(c) for the 13th, 14th, and 15th bit columns; when j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(c).

[0476] FIG34( c ) is a schematic diagram of a bit distribution of the ninth bit set 2i+1 according to an embodiment of the present application. The bits of the last 51 bit columns in the sixth bit set 2i+1 are fed into the fourth interleaving 2i+1 to obtain the bits of the last 51 bit columns in the ninth bit set 2i+1 as shown in FIG34( c ).

[0477] In the ninth bit set 2i+1, for 0≤i3<21 and i3%3=0, or, 21≤i3<42 and i3%3=2, i.e., i3=0,3,6,9,12,15,18,23,26,29,32,35,38,41: when j3=4, the bit block The distribution patterns of the last three bit columns in the bit block, i.e., the bit columns r3=13, r3=14, and r3=15, are shown in FIG11(c) for the 13th, 14th, and 15th bit columns; when j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(c).

[0478] In the ninth bit set 2i+1, for 0≤i3<21 and i3%3=1, or, 21≤i3<42 and i3%3=0, i.e., i3=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39: when j3=4, the bit block The distribution patterns of the last three bit columns in the bit block, i.e., the bit columns r3=13, r3=14, and r3=15, are shown in FIG11(a) for the 13th, 14th, and 15th bit columns. When j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(a).

[0479] In the ninth bit set 2i+1, for 0≤i3<21 and i3%3=2, or, 21≤i3<42 and i3%3=1, i.e., i3=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40: when j3=4, the bit block The distribution patterns of the last three bit columns in the bit block, i.e., the bit columns r3=13, r3=14, and r3=15, are shown in FIG11(b) for the 13th, 14th, and 15th bit columns; when j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(b).

[0480] Example 4:

[0481] Considering the use of the first symbol mapping, a sixth bit set 2i in the second bit stream 2i, which is distributed as a 42-row and 8-column bit block, is sent to the fourth interleaving 2i to obtain a ninth bit set 2i, and a sixth bit set 2i+1 in the second bit stream 2i+1, which is distributed as a 42-row and 8-column bit block, is sent to the fourth interleaving 2i+1 to obtain a ninth bit set 2i+1.

[0482] FIG35( a ) is a schematic diagram of a bit distribution of the last 54 bit columns in the sixth bit set 2i and the sixth bit set 2i+1 in an embodiment of the present application. As an example, for 0≤i2<42, the bit block in the i2th row and j2=4th column in the sixth bit set 2i and the sixth bit set 2i+1 is: The pattern of the last 6 bits in the bit block is shown in Figure 35(a). The 10th bit is the sign bit, and the bit block The 11th to 15th bit columns in the sixth bit set 2i and the sixth bit set 2i+1 are all amplitude bits; the bit blocks in the i2th row and j2=5, 6 and 7th columns in the sixth bit set 2i+1 and The pattern of the bits in is shown in Figure 35(a), that is, The bits in are amplitude bits, The first 15 bits in the bit column are all amplitude bits and The last bit column in the bit column all comes from FEC check bits (that is, all are sign bits). The bits in are all from FEC check bits (ie, they are all sign bits).

[0483] Figure 35(b) is a schematic diagram of a bit distribution of the ninth bit set 2i in an embodiment of the present application. The bits of the last 54 bit columns in the sixth bit set 2i are fed into the fourth interleaving 2i to obtain the bits of the last 54 bit columns in the ninth bit set 2i as shown in Figure 35(b).

[0484] In the ninth bit set 2i, for 0≤i3<21 and i3%3=0, or, 21≤i3<42 and i3%3=2, i.e., i3=0,3,6,9,12,15,18,23,26,29,32,35,38,41: when j3=4, the bit block The distribution pattern of the last 6 bit columns in the bit block, i.e., the bit columns r3=10, 11, 12, 13, 14, and 15, is shown in FIG11(a). When j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(a).

[0485] In the ninth bit set 2i, for 0≤i3<21 and i3%3=1, or, 21≤i3<42 and i3%3=0, i.e., i3=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39: when j3=4, the bit block The distribution pattern of the last three bit columns in the bit block, i.e., the bit columns r3=10, 11, 12, 13, 14, and 15, is shown in FIG11(b) as the 10th, 11th, 12th, 13th, 14th, and 15th bit columns; when j3=5, 6, and 7, the bit block and The distribution patterns are shown in Figure 11(b).

[0486] In the ninth bit set 2i, for 0≤i3<21 and i3%3=2, or, 21≤i3<42 and i3%3=1, i.e., i3=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40: when j3=4, the bit block The last three bit columns in the bit block, i.e., the bit columns r3=10, 11, 12, 13, 14, and 15, are shown in FIG11(c). When j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(c).

[0487] FIG35( c ) is a schematic diagram of a bit distribution of the ninth bit set 2i+1 according to an embodiment of the present application. The bits of the last 54 bit columns in the sixth bit set 2i+1 are fed into the fourth interleaving 2i+1 to obtain the bits of the last 54 bit columns in the ninth bit set 2i+1 as shown in FIG35( c ).

[0488] In the ninth bit set 2i+1, for 0≤i3<21 and i3%3=0, or, 21≤i3<42 and i3%3=2, i.e., i3=0,3,6,9,12,15,18,23,26,29,32,35,38,41: when j3=4, the bit block The last three bit columns in the bit block, i.e., the bit columns r3=10, 11, 12, 13, 14, and 15, are shown in FIG11(c). When j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(c).

[0489] In the ninth bit set 2i+1, for 0≤i3<21 and i3%3=1, or, 21≤i3<42 and i3%3=0, i.e., i3=1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, 39: when j3=4, the bit block The distribution pattern of the last three bit columns in the bit block, i.e., the bit columns r3=10, 11, 12, 13, 14, and 15, is shown in FIG11(a). When j3=5, 6, or 7, the bit block and The distribution patterns are shown in Figure 11(a).

[0490] In the ninth bit set 2i+1, for 0≤i3<21 and i3%3=2, or, 21≤i3<42 and i3%3=1, i.e., i3=2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, 40: when j3=4, the bit block The distribution pattern of the last three bit columns in the bit block, i.e., the bit columns r3=10, 11, 12, 13, 14, and 15, is shown in FIG11(b) as the 10th, 11th, 12th, 13th, 14th, and 15th bit columns; when j3=5, 6, and 7, the bit block and The distribution patterns are shown in Figure 11(b).

[0491] Example 5:

[0492] Figure 36 is a schematic diagram of another application scenario of the second data processing in an embodiment of the present application. As shown in Figure 36, consider the second bit data processing L=2, and the PCS processing and the first interleaving specifically adopt the method shown in Figure 6(c). In some application scenarios, the PCS processing, the first interleaving and the fourth interleaving can be collectively referred to as a probabilistic constellation shaper (Probabilistic Constellation Shaper), as shown in the grid shaded area in Figure 36. In some application scenarios, the input processing granularity of the FEC coding is K=3552 bits, and the corresponding output granularity is N=4096 bits. An extended BCH (256,239) with a coding redundancy of 15.3% is used. The FEC coding and the fifth interleaving can be collectively referred to as OFEC coding, as shown in the oblique shaded area in Figure 36.

[0493] Consider a data frame with q=10280 bits per row. The first data processing step is to obtain r from the data frame. Frame The data of the row is d in =q×r Frame bits. Then, the first bit data is CRCed and / or filled with padding bits to obtain the second bit data. In the CRC operation, d CRC CRC check bits are inserted during the padding operation. PAD Then, the second bit data is scrambled to obtain the third bit data. The number of bits of the third bit data is d scr =q×r Frame +d CP scrambled bits, where d CP =d CRC +d PAD .

[0494] Considering k0=42, the number of the third data bit after scrambling is dCP =12×e². The number of bits sent to each PCS process and the first interleaving is e² / 2 bits. e² / 2-17248 bits from the first bit set 0, first bit set 1, first bit set 2, and first bit set 3 are sent to PCS process 0, PCS process 1, PCS process 2, and PCS process 3, respectively. The resulting number of bits in the second bit set 0, second bit set 1, second bit set 2, and second bit set 3 is 57344 bits each. The corresponding number of bits in the third bit set 0, third bit set 1, third bit set 2, and third bit set 3, which are not processed by PCS, is 17248 bits each. Next, a total of 57344+17248=74592 bits of the second bit set 0 and the third bit set 0 are fed into the first interleaving 0, resulting in a fifth bit set with 0 bits of 74592 bits. Similarly, a total of 57344+17248=74592 bits of the second bit set 1 and the third bit set 1 are fed into the first interleaving 1, resulting in a fifth bit set with 1 bits of 74592 bits. A total of 57344+17248=74592 bits of the second bit set 2 and the third bit set 2 are fed into the first interleaving 2, resulting in a fifth bit set with 2 bits of 74592 bits. A total of 57344+17248=74592 bits of the second bit set 3 and the third bit set 3 are fed into the first interleaving 3, resulting in a fifth bit set with 3 bits of 74592 bits.

[0495] The fifth bit set 0, the fifth bit set 1, the fifth bit set 2, and the fifth bit set 3 are respectively fed into FEC code 0, FEC code 1, FEC code 2, and FEC code 3, resulting in a sixth bit set 0, a sixth bit set 1, a sixth bit set 2, and a sixth bit set 3, each of which has a number of 86016 bits. Taking the FEC code using extended BCH (256, 239) as an example, the number of FEC parity bits in the sixth bit set 0, the sixth bit set 1, the sixth bit set 2, and the sixth bit set 3 is 544 × 21 = 11424 bits.

[0496] The sixth bit set 0, the sixth bit set 1, the sixth bit set 2, and the sixth bit set 3 are respectively sent to the fourth interleave 0, the fourth interleave 1, the fourth interleave 2, and the fourth interleave 3, so that the number of bits in the ninth bit set 0, the ninth bit set 1, the ninth bit set 2, and the ninth bit set 3 are all 86016 bits. Next, the ninth bit set 0, the ninth bit set 1, the ninth bit set 2, and the ninth bit set 3 are respectively sent to the fifth interleave 0, the fifth interleave 1, the fifth interleave 2, and the fifth interleave 3, so that the number of bits in the seventh bit set 0, the seventh bit set 1, the seventh bit set 2, and the seventh bit set 3 are all 86016 bits.

[0497] The seventh bit set 0, the seventh bit set 1, the seventh bit set 2, and the seventh bit set 3 are respectively sent to the third interleave 0, the third interleave 1, the third interleave 2, and the third interleave 3, resulting in the tenth bit set 0, the tenth bit set 1, the tenth bit set 2, and the tenth bit set 3, each with a number of 86016 bits. Next, the tenth bit set 0 and the tenth bit set 1, totaling 86016 + 86016 = 172032 bits, are sent to the interleave buffer M of inter-matrix interleave 0 and read out to obtain the eighth bit set 0. Similarly, the tenth bit set 2 and the tenth bit set 3, totaling 86016 + 86016 = 172032 bits, are sent to the interleave buffer M of inter-matrix interleave 1 and read out to obtain the eighth bit set 1.

[0498] It should be understood that the fourth bit stream 0 obtained by reading the bits in the interleaving buffer M of inter-matrix interleave 0 contains six bits of the eighth bit set 0; similarly, the fourth bit stream 1 obtained by reading the bits in the interleaving buffer M of inter-matrix interleave 1 contains six bits of the eighth bit set 1. Therefore, the fourth bit data obtained by combining the fourth bit stream 0 and the fourth bit stream 1 contains a total of 2,064,384 bits.

[0499] Considering DP-64QAM, every 12 bits of the fourth bit data are mapped to a dual-polarization symbol, resulting in a total of 2064384 / 12 = 172032 dual-polarization symbols. DSP framing is performed on these 172032 dual-polarization symbols, inserting frame synchronization symbols, training symbols, reserved symbols, and pilot symbols into the X- and Y-polarization symbols to create a superframe containing 175104 dual-polarization symbols, which is then transmitted.

[0500] It should be noted that, as shown in FIG25 , the above-mentioned inter-matrix interleaving in the matrix interleaving in the second data sub-processing i (i=0, 1, …, L-1) is performed by polling the interleaving buffer M at an 8-bit granularity to read the bits in each column from each set. In other application scenarios, the inter-matrix interleaving in the matrix interleaving in the second data sub-processing i is performed by polling the interleaving buffer M at a 16-bit granularity to read the bits in each column from each set. The following description uses the method of polling the interleaving buffer M at a 16-bit granularity to read the bits in each column from each set.

[0501] Figure 37 is a schematic diagram of another embodiment of inter-matrix interleaving in an embodiment of the present application. As shown in Figure 37, the first group of 16 bits is first read from the 0th set from top to bottom, and then the first 16 bits are read from the 1st set, the 2nd set, and the 3rd set respectively from top to bottom, and a total of 64 bits are read in one cycle. Then, the next cycle reads the next group of 16 bits from the 0th set, the 1st set, the 2nd set, and the 3rd set respectively from top to bottom, and a total of 64 bits are read. After a total of 21 cycles, the 1344 bits of the current column are read out. For reading the bits in each column from each set, the specific operations are as follows:

[0502] First, read 16 bits from the 0th row of the interleaved buffer M from top to bottom (bit rows 0-15 in the matrix).

[0503] Read 16 bits from the first row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-15 in the matrix),

[0504] Read 16 bits from the 42nd row of the matrix in the interleaving buffer M (bit rows 0-15 in the matrix) from top to bottom.

[0505] Read 16 bits from the 43rd row of the matrix in the interleaving buffer M (bit rows 0-15 in the matrix) from top to bottom.

[0506] Then read 16 bits from the second row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-15 in the matrix),

[0507] Read 16 bits from the third row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-15 in the matrix),

[0508] Read 16 bits from the 44th row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-15 in the matrix),

[0509] Read 16 bits from the 45th row of the interleaving buffer M (bit rows 0-15 in the matrix) from top to bottom.

[0510] Then read 16 bits from the 4th row of the matrix in the interleaving buffer M from top to bottom (bit rows 0-15 in the matrix),

[0511] ..., until a total of 1344 bits in the current bit column in the interleaving buffer M are completely read out.

[0512] Next, similarly, the above operations are repeated to completely read out the 1,344 bits in the next bit column in interleaving buffer M, until the 1,344 bits in the last bit column in interleaving buffer M are completely read out. At this point, all 172,032 bits in interleaving buffer M have been read out. The 172,032 bits read from interleaving buffer M serve as the output of the third interleaving operation, i.e., the eighth bit set. It should be understood that interleaving buffer M contains a total of 128 bit columns.

[0513] It should be noted that, due to the differences in the implementation of inter-matrix interleaving between FIG25 and FIG37 , the specific implementation of the second data sub-processing i may also differ. Based on the implementation of inter-matrix interleaving described in FIG37 , the specific bit patterns of the fifth bit set, the sixth bit set, the ninth bit set, the seventh bit set, and the tenth bit set are described below using the first symbol mapping as an example of the second data sub-processing i (i=0, 1, ..., L-1, where L is an integer greater than 0):

[0514] 1) PCS processing and first interleaving:

[0515] 8 shows a schematic diagram of a bit block with 42 rows and 7 columns. The following describes the bit block in the fifth bit set 2i on the first bit stream 2i. (0≤i1<42 and 0≤j1<7) pattern.

[0516] 1) For 0≤i1<21 and i1%3=0, or 21≤i1<42 and i1%3=1, i.e., i1=0,3,6,9,12,15,18,22,25,28,31,34,37,40, and j1=0,1,2,3: corresponding 56-bit block The bit pattern uses a first bit pattern. As an example, when the first symbol mapping is used, the first bit pattern is shown in FIG11(a). As shown in FIG11(a), it includes a bit block of 16 rows and 16 columns, each row of which includes 6 shaded background-filled bits and 10 non-shaded (blank) background-filled bits. The shaded background-filled bits are from the bits in the third bit set that have not been processed by PCS, and the non-shaded (blank) background-filled bits are from the bits in the second bit set that have been processed by PCS.

[0517] 2) For 0≤i1<21 and i1%3=1, or 21≤i1<42 and i1%3=2, i.e., i1=1,4,7,10,13,16,19,23,26,29,32,35,38,41, and j1=0,1,2,3: corresponding 56-bit block The bit pattern uses a second bit pattern. As an example, when the first symbol mapping is used, the second bit pattern is shown in Figure 11(b). As shown in Figure 11(b), it includes a bit block of 16 rows and 16 columns, each row of which includes 6 shaded background-filled bits and 10 non-shaded (blank) background-filled bits. The shaded background-filled bits are from the bits in the third bit set that have not been processed by PCS, and the non-shaded (blank) background-filled bits are from the bits in the second bit set that have been processed by PCS.

[0518] 3) For 0≤i1<21 and i1%3=2, or 21≤i1<42 and i1%3=0, i.e., i1=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and j1=0, 1, 2, 3: the corresponding 56-bit block The bit pattern uses a third bit pattern. As an example, when the first symbol mapping is used, the third bit pattern is shown in FIG11( c ). As shown in FIG11( c ), the bit pattern comprises a 16-row, 16-column bit block, with each row containing 4 shaded background-filled bits and 12 unshaded (blank) background-filled bits. The shaded background-filled bits are from the bits in the third bit set that have not been processed by the PCS, and the unshaded (blank) background-filled bits are from the bits in the second bit set that have been processed by the PCS.

[0519] 4) For 0≤i1<21 and i1%3=0, or 21≤i1<42 and i1%3=1, i.e., i1=0,3,6,9,12,15,18,22,25,28,31,34,37,40, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0520] As a specific implementation, when the first symbol mapping is adopted, the fourth bit pattern is shown in FIG12( a ), which includes 82 bits filled with a shaded background and 174 bits filled with a non-shaded (blank) background.

[0521] As another specific implementation, when the first symbol mapping is adopted, the fourth bit pattern is shown in FIG12( d ), which includes 78 bits filled with a shaded background and 178 bits filled with a non-shaded (blank) background.

[0522] As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0523] The shaded background filled bits are from bits in the third bit set that have not been processed by PCS, and the non-shaded (blank) background filled bits are from bits in the second bit set that have been processed by PCS.

[0524] 5) For 0≤i1<21 and i1%3=1, or 21≤i1<42 and i1%3=2, i.e., i1=1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0525] As a specific implementation, when the first symbol mapping is adopted, the fifth bit pattern is shown in FIG12( b ), which includes 78 bits filled with a shaded background and 178 bits filled with a non-shaded (blank) background.

[0526] As another specific implementation, when the first symbol mapping is adopted, the fourth bit pattern is shown in FIG12( e ), which includes 90 bits filled with a shaded background and 166 bits filled with a non-shaded (blank) background.

[0527] As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0528] The shaded background filled bits are from bits in the third bit set that have not been processed by PCS, and the non-shaded (blank) background filled bits are from bits in the second bit set that have been processed by PCS.

[0529] 6) For 0≤i1<21 and i1%3=2, or 21≤i1<42 and i1%3=0, i.e., i1=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0530] As a specific implementation, the bit block The bit pattern uses the sixth bit pattern. As an example, when the first symbol mapping is adopted, the sixth bit pattern is shown in Figure 12(c), which contains 48 bits filled with shaded backgrounds and 208 bits filled with non-shaded (blank) backgrounds.

[0531] As another specific implementation, the sixth bit pattern when the first symbol mapping is adopted is shown in FIG12( f ), which includes 40 bits filled with a shaded background and 216 bits filled with a non-shaded (blank) background.

[0532] As another specific embodiment, when the first symbol mapping is used, the sixth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0533] The shaded background filled bits are from bits in the third bit set that have not been processed by PCS, and the non-shaded (blank) background filled bits are from bits in the second bit set that have been processed by PCS.

[0534] 7) For 0≤i1<42 and j1=5: the corresponding 42-bit block The bit pattern uses the seventh bit pattern. As an example, when the first symbol mapping is used, the seventh bit pattern is shown in FIG13 , which includes 256 non-shaded (blank) background-filled bits. The non-shaded (blank) background-filled bits are from the bits in the second bit set processed by the PCS.

[0535] 8) For 0≤i1<42 and j1=6: the corresponding 42-bit block The bit pattern uses the eighth bit pattern. As an example, when the first symbol mapping is used, the eighth bit pattern is shown in FIG14 , which includes 240 non-shaded (blank) background-filled bits. The non-shaded (blank) background-filled bits are from the bits in the second bit set processed by the PCS.

[0536] It should be noted that when 0≤i1<42 and j1=4, the corresponding 42-bit block The 42-bit block contains 7840 bits from the second bit set and 2912 bits from the third bit set. For every three consecutive rows of bit blocks, that is, when 0≤i3<14 and j1=4, the corresponding three bit blocks The 768 bits in the 12-bit bit set include 560 bits from the second bit set and 208 bits from the third bit set. As a specific embodiment, when the first symbol mapping is used, the fourth bit pattern is shown in Figure 12(a), the fifth bit pattern is shown in Figure 12(b), and the sixth bit pattern is shown in Figure 12(c). As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is shown in Figure 12(d), the fifth bit pattern is shown in Figure 12(e), and the sixth bit pattern is shown in Figure 12(f).

[0537] 8 shows a schematic diagram of a bit block with 42 rows and 7 columns. The following describes the bit block in the fifth bit set 2i+1 on the first bit stream 2i+1. (0≤i1<42 and 0≤j1<7) pattern.

[0538] 1) For 0≤i1<21 and i1%3=0, or 21≤i1<42 and i1%3=1, i.e., i1=0,3,6,9,12,15,18,22,25,28,31,34,37,40, and j1=0,1,2,3: corresponding 56-bit block The bit pattern adopts the second bit pattern. As an example, when the first symbol mapping is adopted, the second bit pattern is shown in Figure 11(b).

[0539] 2) For 0≤i1<21 and i1%3=1, or 21≤i1<42 and i1%3=2, i.e., i1=1,4,7,10,13,16,19,21,24,27,30,33,36,39, and j1=0,1,2,3: corresponding 56-bit block The bit pattern adopts the third bit pattern. As an example, when the first symbol mapping is adopted, the third bit pattern is shown in FIG11( c ).

[0540] 3) For 0≤i1<21 and i1%3=2, or 21≤i1<42 and i1%3=0, i.e., i1=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and j1=0, 1, 2, 3: the corresponding 56-bit block The bit pattern adopts the first bit pattern. As an example, the first bit pattern is shown in FIG11( a ).

[0541] 4) For 0≤i1<21 and i1%3=0, or 21≤i1<42 and i1%3=1, i.e., i1=0,3,6,9,12,15,18,22,25,28,31,34,37,40, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0542] As a specific implementation, the bit block The bit pattern uses the fifth bit pattern. As an example, when the first symbol mapping is adopted, the fifth bit pattern is shown in FIG12( b ).

[0543] As another specific implementation, when the first symbol mapping is adopted, the fifth bit pattern is shown in FIG12( e ).

[0544] As another specific embodiment, when the first symbol mapping is used, the sixth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the sixth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0545] 5) For 0≤i1<21 and i1%3=1, or 21≤i1<42 and i1%3=2, i.e., i1=1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0546] As a specific implementation, the bit block The bit pattern uses the sixth bit pattern. As an example, when the first symbol mapping is adopted, the sixth bit pattern is shown in FIG12( c ).

[0547] As another specific implementation, the sixth bit pattern when the first symbol mapping is adopted is shown in FIG12( f ).

[0548] As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fourth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0549] 6) For 0≤i1<21 and i1%3=2, or 21≤i1<42 and i1%3=0, i.e., i1=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and j1=4: the corresponding 14-bit block The bit patterns all use the fourth bit pattern.

[0550] As a specific implementation, the bit block The bit pattern adopts the fourth bit pattern. As an example, when the first symbol mapping is adopted, the fourth bit pattern is shown in Figure 12(a).

[0551] As another specific implementation, when the first symbol mapping is adopted, the fourth bit pattern is shown in FIG12( d ).

[0552] As another specific embodiment, when the first symbol mapping is used, the fifth bit pattern is described as follows: 5×16=80 bits in the first 5 bit columns of the bit block are shaded background filled bits, and 11×16=176 bits in the last 11 bit columns are non-shaded (blank) background filled bits. As another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 4×16=64 bits in the first 4 bit columns of the bit block are shaded background filled bits, and 12×16=192 bits in the last 12 bit columns are non-shaded (blank) background filled bits. As yet another example, when the first symbol mapping is used, the fifth bit pattern is described as follows: 3×16=48 bits in the first 3 bit columns of the bit block are shaded background filled bits, and 13×16=208 bits in the last 13 bit columns are non-shaded (blank) background filled bits.

[0553] 7) For 0≤i1<42 and j1=5: the corresponding 42-bit block The bit pattern uses the seventh bit pattern. As an example, when the first symbol mapping is adopted, the seventh bit pattern is shown in FIG13 .

[0554] 8) For 0≤i1<42 and j1=6: the corresponding 42-bit block The bit pattern adopts the eighth bit pattern. As an example, the eighth bit pattern when the first symbol mapping is adopted is shown in Figure 14.

[0555] It should be noted that when 0≤i1<42 and j1=4, the corresponding 42-bit block The 42-bit block contains 7840 bits from the second bit set and 2912 bits from the third bit set. For every three consecutive rows of bit blocks, that is, when 0≤i3<14 and j1=4, the corresponding three bit blocks The 768 bits in the 12-bit bit set include 560 bits from the second bit set and 208 bits from the third bit set. As a specific embodiment, when the first symbol mapping is used, the fourth bit pattern is shown in Figure 12(b), the fifth bit pattern is shown in Figure 12(c), and the sixth bit pattern is shown in Figure 12(a). As another specific embodiment, when the first symbol mapping is used, the fourth bit pattern is shown in Figure 12(e), the fifth bit pattern is shown in Figure 12(f), and the sixth bit pattern is shown in Figure 12(d).

[0556] It should be noted that the bit blocks (or squares) in different figures of this application are marked with the same shaded background, which does not mean that the patterns of these bit blocks are exactly the same. It is only a graphical representation method. It should be noted that the bits in the second bit set processed by PCS are used for the amplitude bits (Amplitude bits) in symbol mapping (also called modulation), and the bits in the third bit set that have not been processed by PCS are used for the sign bits (Sign bits) in symbol mapping (also called modulation). The bits in the shaded background part of Figure 11 (a), (b), (c) and Figure 12 (a), (b), (c), Figure 13 and Figure 14 are from the bits in the third bit set that have not been processed by PCS, that is, the sign bits, and the remaining bits in the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS, that is, the amplitude bits.

[0557] It should be noted that the bit block distribution of the fifth bit set 2i and the fifth bit set 2i+1 is shown in FIG8 , but the specific bit blocks included therein are The patterns are not exactly the same. More specifically, the bit blocks The distribution patterns of (0≤i1<42 and 0≤j1<5) are different, that is, the distribution positions of the amplitude bits and sign bits in the bit blocks are different. It should be understood that the first bit stream 2i after the "PCS processing and first interleaving" can include multiple fifth bit sets 2i, and the first bit stream 2i+1 can include multiple fifth bit sets 2i+1.

[0558] (2) FEC encoding:

[0559] As shown in FIG17 , the bits in the sixth bit set are distributed as 42 rows and 8 columns, totaling 336 bit blocks. (0≤i2<42 and 0≤j2<8). The bits in the leftmost 5 columns (i.e., columns 0-4) of the sixth bit set are the bits in the bit block, i.e., the bit block filled with the shaded background shown in FIG17. (0≤i2<42 and 0≤j2<5), some bits from the second bit set that have been processed by PCS and bits from the third bit set that have not been processed by PCS. The 5th column of the bit block in the sixth bit set (0≤i2<42) and the 6th column bit block The bits in the leftmost 15 bit columns (16+15=31 bit columns) in (0≤i2<42) are from the remaining bits in the second bit set processed by PCS (i.e., not including bits from the third bit set). The sixth bit block in the sixth bit set The rightmost bit column and the 7th bit block in (0≤i2<42) (0≤i2<42) and the bits in the 1+16=17 bit column are parity bits obtained from FEC encoding.

[0560] It should be noted that the specific bit patterns of the sixth bit set 2i on the second bit stream 2i and the sixth bit set 2i+1 on the second bit stream 2i+1 can be understood with reference to FIG17 , but the specific bit patterns of each bit block (square matrix) therein are not completely consistent, that is, the sixth bit set 2i (0≤i2<42 and 0≤j2<8) and the sixth bit set 2i+1 The specific bit patterns (0≤i2<42 and 0≤j2<8) are not exactly the same. The bit block (square matrix) patterns in the sixth bit set 2i and the sixth bit set 2i+1 are introduced below.

[0561] For 0≤i2<42 and 0≤j2<6, the bit block (square matrix) in the sixth bit set 2i is The pattern and the corresponding bit block (square matrix) in the fifth bit set 2i before encoding Similarly, the bit block (square matrix) in the sixth bit set 2i+1 The pattern and the corresponding bit block (square matrix) in the fifth bit set 2i+1 before encoding Same.

[0562] For 0≤i2<42 and j2=6, the bit blocks (square matrix) in the sixth bit set 2i and the sixth bit set 2i+1 are The bit pattern uses the ninth bit pattern. As an example, the ninth bit pattern when the first symbol mapping is used is shown in FIG18( a ), which includes 240 non-shaded (blank) background-filled bits and 16 shaded background-filled bits. The non-shaded (blank) background-filled bits are from the second bit set processed by the PCS, and the shaded background-filled bits are from the parity bits encoded by the FEC.

[0563] For 0≤i2<42 and j2=7, the bit blocks (square matrix) in the sixth bit set 2i and the sixth bit set 2i+1 are The bit pattern adopts the tenth bit pattern. As an example, when the first symbol mapping is adopted, the tenth bit pattern is shown in FIG18( b ), which contains 256 bits filled with a shaded background. The bits filled with the shaded background come from the parity bits of the FEC encoding.

[0564] In some specific applications, a sixth bit set 2i in the second bit stream 2i is obtained by directly adding parity bits to a fifth bit set 2i before encoding, and a sixth bit set 2i+1 in the second bit stream 2i+1 is obtained by directly adding parity bits to a fifth bit set 2i+1 before encoding. More specifically, the bit data of bit columns 0-111 in the sixth bit set 2i in the second bit stream 2i is equal to the bit data of bit columns 0-111 in the fifth bit set 2i before encoding; and the bit data of bit columns 0-111 in the sixth bit set 2i+1 in the second bit stream 2i+1 is equal to the bit data of bit columns 0-111 in the fifth bit set 2i+1 before encoding.

[0565] It should be noted that the bits in the second bit set that have undergone PCS processing are used as amplitude bits in symbol mapping (also known as modulation), while the bits in the third bit set that have not undergone PCS processing and the parity bits obtained after FEC encoding are used as sign bits in symbol mapping (also known as modulation). For the sixth bit set 2i and the sixth bit set 2i+1 shown in Figure 17, when the matrix adopts the bit patterns shown in Figures 11(a), (b), (c) and 13, the bits in the shaded background portion of the bit pattern come from the bits in the third bit set that have not undergone PCS processing, i.e., the sign bits; the bits in the unshaded background portion of the bit pattern come from the bits in the second bit set that have undergone PCS processing, i.e., the amplitude bits. When the matrix adopts the bit patterns shown in Figures 18(a) and 18(b), the bits in the shaded background portion of the bit pattern come from the parity bits obtained by FEC encoding, i.e., the sign bits; the bits in the unshaded (blank) background portion of the bit pattern come from the bits in the second bit set that have undergone PCS processing, i.e., the amplitude bits.

[0566] It should be noted that the bit blocks (square matrix) of the sixth bit set 2i and the sixth bit set 2i+1 are distributed as shown in FIG17 , but the specific bit blocks included therein are The patterns are not exactly the same. More specifically, the bit blocks The distribution patterns of (0≤i1<42 and 0≤j1<5) are different, that is, the distribution positions of the amplitude bits and sign bits in the bit blocks are different. It should be understood that the second bit stream 2i after the "FEC encoding" can include multiple sixth bit sets 2i, and the second bit stream 2i+1 can include multiple sixth bit sets 2i+1.

[0567] (3) Second interweaving:

[0568] As shown in FIG19 , the bits in the ninth bit set obtained after the fourth interleaving are distributed into 42 rows and 8 columns, with a total of 336 bit blocks. (0≤i3<42 and 0≤j3<8). It should be noted that in the above 42 rows and 8 columns with a total of 336 bit blocks C, all bit blocks The sizes of (0≤i3<42 and 0≤j3<8) are all 16 rows and 16 columns of bits (ie, 16×16=256 bits).

[0569] The bit block patterns in the ninth bit set 2i and the ninth bit set 2i+1 are introduced below respectively.

[0570] Referring to the schematic diagram of the 42 rows and 8 columns of the bit block shown in FIG19 , the bit block in the ninth bit set 2i on the fifth bit stream 2i is described below. (0≤i3<42 and 0≤j3<8) pattern.

[0571] 1) For 0≤i3<21 and i3%3=0, or 21≤i3<42 and i3%3=1, i.e., i3=0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37, 40, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the first bit pattern. As an example, the first bit pattern when the first symbol mapping is adopted is shown in Figure 11(a), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0572] 2) For 0≤i3<21 and i3%3=1, or 21≤i3<42 and i3%3=2, i.e., i3=1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the second bit pattern. As an example, the second bit pattern when the first symbol mapping is adopted is shown in Figure 11(b), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0573] 3) For 0≤i3<21 and i3%3=2, or 21≤i3<42 and i3%3=0, i.e., i3=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the third bit pattern. As an example, the third bit pattern when the first symbol mapping is adopted is shown in Figure 11(c), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0574] Referring to the schematic diagram of the 42-row and 8-column bit block shown in FIG19 , the following describes the bit block in the ninth bit set 2i+1 on the fifth bit stream 2i+1. (0≤i3<42 and 0≤j3<8) pattern.

[0575] 1) For 0≤i3<21 and i3%3=0, or 21≤i3<42 and i3%3=1, i.e., i3=0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37, 40, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the second bit pattern. As an example, the second bit pattern when the first symbol mapping is adopted is shown in Figure 11(b), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0576] 2) For 0≤i3<21 and i3%3=1, or 21≤i3<42 and i3%3=2, i.e., i3=1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the third bit pattern. As an example, the third bit pattern when the first symbol mapping is adopted is shown in Figure 11(c), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0577] 3) For 0≤i3<21 and i3%3=2, or 21≤i3<42 and i3%3=0, i.e., i3=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and 0≤j3<8: the corresponding 112-bit block The bit pattern adopts the first bit pattern. As an example, the first bit pattern when the first symbol mapping is adopted is shown in Figure 11(a), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0578] It should be noted that the bit blocks (square matrix) of the ninth bit set 2i and the ninth bit set 2i+1 are distributed as shown in FIG19 , but the specific bit blocks they contain are The patterns are not exactly the same. More specifically, the bit blocks The distribution patterns are different, that is, the distribution positions of the amplitude bits and sign bits in the bit blocks are different. It should be understood that the fifth bit stream 2i after the fourth interleaving may include multiple ninth bit sets 2i, and the fifth bit stream 2i+1 may include multiple ninth bit sets 2i+1.

[0579] As shown in FIG20 , the seventh bit set is distributed into 42 rows and 8 columns with a total of 336 bit blocks. (0≤i4<42 and 0≤j4<8). Each bit block The sizes of (0≤i4<42 and 0≤j4<8) are all 16 rows and 16 columns of bits (ie, 16×16=256 bits).

[0580] The bit block patterns in the seventh bit set 2i and the seventh bit set 2i+1 are introduced below respectively.

[0581] 20 shows a schematic diagram of a 42-row 8-column bit block. The following describes the bit block in the seventh bit set 2i on the third bit stream 2i. (0≤i4<42 and 0≤j4<8) pattern.

[0582] 1) For 0≤i4<21 and i4%3=0, or 21≤i4<42 and i4%3=1, i.e., i4=0,3,6,9,12,15,18,22,25,28,31,34,37,40, and 0≤j4<8: the corresponding 112-bit block The bit pattern adopts the eleventh bit pattern. As an example, the eleventh bit pattern when the first symbol mapping is adopted is shown in Figure 22(a), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0583] 2) For 0≤i4<21 and i4%3=1, or 21≤i4<42 and i4%3=2, i.e., i4=1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, and 0≤j4<8: the corresponding 112-bit block The bit pattern uses the twelfth bit pattern. As an example, the twelfth bit pattern when the first symbol mapping is adopted is shown in Figure 22(b), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0584] 3) For 0≤i4<21 and i4%3=2, or 21≤i4<42 and i4%3=0, i.e., i4=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and 0≤j4<8: the corresponding 112-bit block The bit pattern uses the thirteenth bit pattern. As an example, the thirteenth bit pattern when the first symbol mapping is adopted is shown in FIG22( c ), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0585] 20 shows a schematic diagram of a 42-row 8-column bit block. The following describes the bit block in the seventh bit set 2i+1 on the third bit stream 2i+1. (0≤i4<42 and 0≤j4<8) pattern.

[0586] 1) For 0≤i4<21 and i4%3=0, or 21≤i4<42 and i4%3=1, i.e., i4=0,3,6,9,12,15,18,22,25,28,31,34,37,40, and 0≤j4<8: the corresponding 112-bit block The bit pattern uses the twelfth bit pattern. As an example, the twelfth bit pattern when the first symbol mapping is adopted is shown in Figure 22(b), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0587] 2) For 0≤i4<21 and i4%3=1, or 21≤i4<42 and i4%3=2, i.e., i4=1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, and 0≤j4<8: the corresponding 112-bit block The bit pattern uses the thirteenth bit pattern. As an example, the thirteenth bit pattern when the first symbol mapping is adopted is shown in FIG22( c ), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0588] 3) For 0≤i4<21 and i4%3=2, or 21≤i4<42 and i4%3=0, i.e., i4=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and 0≤j4<8: the corresponding 112-bit block The bit pattern adopts the eleventh bit pattern. As an example, the eleventh bit pattern when the first symbol mapping is adopted is shown in Figure 22(a), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0589] It should be noted that the bit blocks (square matrix) of the seventh bit set 2i and the seventh bit set 2i+1 are distributed as shown in FIG20 , but the specific bit blocks they contain are The patterns are not exactly the same. More specifically, the bit blocks The distribution patterns are different, that is, the distribution positions of the amplitude bits and sign bits in the bit blocks are different. It should be understood that the third bit stream 2i after the "fifth interleaving" may include multiple seventh bit sets 2i, and the third bit stream 2i+1 may include multiple seventh bit sets 2i+1.

[0590] (4) The third interweaving:

[0591] The bits in the tenth bit set obtained after interleaving in the matrix are distributed into 42 rows and 8 columns, totaling 336 bit blocks. (0≤i5<42 and 0≤j5<8).

[0592] The bit block patterns in the tenth bit set 2i and the tenth bit set 2i+1 are introduced below respectively.

[0593] The following describes the bit block in the tenth bit set 2i. (0≤i5<42 and 0≤j5<8) pattern.

[0594] 1) For 0≤i5<21 and i5%3=0, or 21≤i5<42 and i5%3=1, i.e., i5=0,3,6,9,12,15,18,22,25,28,31,34,37,40, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the fourteenth bit pattern. As an example, the fourteenth bit pattern when the first symbol mapping is adopted is shown in Figure 24(a), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0595] 2) For 0≤i5<21 and i5%3=1, or 21≤i5<42 and i5%3=2, i.e., i5=1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the fifteenth bit pattern. As an example, the fifteenth bit pattern when the first symbol mapping is adopted is shown in Figure 24(b), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0596] 3) For 0≤i5<21 and i5%3=2, or 21≤i5<42 and i5%3=0, i.e., i5=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the sixteenth bit pattern. As an example, the sixteenth bit pattern when the first symbol mapping is adopted is shown in FIG24( c ), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0597] The following describes the bit block in the tenth bit set 2i+1. (0≤i5<42 and 0≤j5<8) pattern.

[0598] 1) For 0≤i5<21 and i5%3=0, or 21≤i5<42 and i5%3=1, i.e., i5=0,3,6,9,12,15,18,22,25,28,31,34,37,40, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the fifteenth bit pattern. As an example, the fifteenth bit pattern when the first symbol mapping is adopted is shown in Figure 24(b), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0599] 2) For 0≤i5<21 and i5%3=1, or 21≤i5<42 and i5%3=2, i.e., i5=1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, and 0≤j5<8: the corresponding 112-bit block The bit pattern uses the sixteenth bit pattern. As an example, the sixteenth bit pattern when the first symbol mapping is adopted is shown in FIG24( c ), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0600] 3) For 0≤i5<21 and i5%3=2, or 21≤i5<42 and i5%3=0, i.e., i5=2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, 39, and 0≤j5<8: the corresponding 112-bit block The bit pattern adopts the fourteenth bit pattern. As an example, the fourteenth bit pattern when the first symbol mapping is adopted is shown in Figure 24(a), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0601] It should be noted that the bit blocks (square matrix) of the tenth bit set 2i and the tenth bit set 2i+1 are The distribution patterns are different, that is, the distribution positions of the amplitude bits and sign bits in the bit block are different.

[0602] Referring to the bit block of 84 rows and 8 columns in the interleaving buffer M shown in FIG. 26 (0≤i6<84 and 0≤j6<8), the following describes the bit block pattern.

[0603] 1) For 0≤i6<42 and i6%6=0 or i6%6=5, or, 42≤i6<84 and i6%6=1 or i6%6=2, i.e., i6=0,5,6,11,12,17,18,23,24,29,30,35,36,41,43,44,49,50,55,56,61,62,67,68,73,74,79,80, and 0≤j5<8: corresponding 224-bit block The bit pattern uses the fourteenth bit pattern. As an example, the fourteenth bit pattern when the first symbol mapping is adopted is shown in Figure 24(a), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC encoding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0604] 2) For 0≤i6<42 and i6%6=1 or i6%6=2, or 42≤i6<84 and i6%6=3 or i6%6=4, i.e., i6=1,2,7,8,13,14,19,20,25,26,31,32,37,38,45,46,51,52,57,58,63,64,69,70,75,76,81,82; and 0≤j5<8: corresponding 224-bit block The bit pattern uses the fifteenth bit pattern. As an example, the fifteenth bit pattern when the first symbol mapping is adopted is as shown in FIG24( b ), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0605] 3) For 0≤i6<42 and i6%6=3 or i6%6=4, or 42≤i6<84 and i6%6=0 or i6%6=5, i.e., i6=3,4,9,10,15,16,21,22,27,28,33,34,39,40,42,47,48,53,54,59,60,65,66,71,72,77,78,83; and 0≤j5<8: corresponding 224-bit block The bit pattern uses the sixteenth bit pattern. As an example, the sixteenth bit pattern when the first symbol mapping is adopted is shown in FIG24( c ), wherein the bits filled with the shaded background are from the bits in the third bit set that have not been processed by PCS and / or from the check bits of FEC coding, and the bits filled with the non-shaded (blank) background are from the bits in the second bit set that have been processed by PCS.

[0606] Several specific embodiments are given below in combination with the above introduction to the second data processing.

[0607] Example 6:

[0608] Figure 38 is a schematic diagram of another application scenario of the second data processing in an embodiment of the present application. As shown in Figure 37, consider the second bit data processing L=4, and the PCS processing and the first interleaving specifically adopt the method shown in Figure 6(c). In some application scenarios, the PCS processing, the first interleaving and the fourth interleaving can be collectively referred to as a probabilistic constellation shaper (Probabilistic Constellation Shaper), as shown in the grid shaded area in Figure 38. In some application scenarios, the input processing granularity of the FEC coding is K=3552 bits, the corresponding output granularity is N=4096 bits, and an extended BCH (256,239) with a coding redundancy of 15.3% is used. The FEC coding and the fifth interleaving can be collectively referred to as OFEC coding, as shown in the oblique shaded area in Figure 38.

[0609] Consider a data frame with q=10280 bits per row. The first data processing step is to obtain r from the data frame. Frame The data of the row is d in =q×r Frame bits. Then, the first bit data is CRCed and / or filled with padding bits to obtain the second bit data. In the CRC operation, d CRC CRC check bits are inserted during the padding operation. PAD Then, the second bit data is scrambled to obtain the third bit data. The number of bits of the third bit data is d scr =q×r Frame +d CP scrambled bits, where d CP =d CRC +d PAD .

[0610] Considering k0=42, the number of the third data bit after scrambling is d CP =12×e². The number of bits sent to each PCS process and the first interleaving is e² / 2 bits. Specifically, e² / 2-17248 bits from the first bit set 0, first bit set 1, first bit set 2, first bit set 3, first bit set 4, first bit set 5, first bit set 6, and first bit set 7 are sent to PCS process 0, PCS process 1, PCS process 2, PCS process 3, PCS process 4, PCS process 5, PCS process 6, and PCS process 7, respectively. The resulting number of bits in the second bit set 0, second bit set 1, second bit set 2, second bit set 3, second bit set 4, second bit set 5, second bit set 6, and second bit set 7 is 57344 bits each.

[0611] The corresponding numbers of bits in the third bit 0, third bit set 1, third bit set 2, third bit set 3, third bit 4, third bit set 5, third bit set 6 and third bit set 7 that have not been processed by PCS are all 17248 bits. Next, a total of 57344+17248=74592 bits of the second bit set 0 and the third bit set 0 are fed into the first interleaving 0, resulting in a fifth bit set with 0 bits of 74592 bits. Similarly, a total of 57344+17248=74592 bits of the second bit set 1 and the third bit set 1 are fed into the first interleaving 1, resulting in a fifth bit set with 1 bits of 74592 bits. A total of 57344+17248=74592 bits of the second bit set 2 and the third bit set 2 are fed into the first interleaving 2, resulting in a fifth bit set with 2 bits of 74592 bits. A total of 57344+17248=74592 bits of the second bit set 3 and the third bit set 3 are fed into the first interleaving 3, resulting in a fifth bit set with 3 bits of 74592 bits. bits; a total of 57344+17248=74592 bits of the second bit set 4 and the third bit set 4 are fed into the first interleaving 4, and the number of bits of 4 in the fifth bit set obtained is 74592 bits; a total of 57344+17248=74592 bits of the second bit set 5 and the third bit set 5 are fed into the first interleaving 5, and the number of bits of 5 in the fifth bit set obtained is 74592 bits; a total of 57344+17248=74592 bits of the second bit set 6 and the third bit set 6 are fed into the first interleaving 6, and the number of bits of 6 in the fifth bit set obtained is 74592 bits; a total of 57344+17248=74592 bits of the second bit set 7 and the third bit set 7 are fed into the first interleaving 7, and the number of bits of 7 in the fifth bit set obtained is 74592 bits.

[0612] The fifth bit set 0, fifth bit set 1, fifth bit set 2, fifth bit set 3, fifth bit set 4, fifth bit set 5, fifth bit set 6, and fifth bit set 7 are respectively fed into FEC code 0, FEC code 1, FEC code 2, FEC code 3, FEC code 4, FEC code 5, FEC code 6, and FEC code 7, resulting in a sixth bit set 0, sixth bit set 1, sixth bit set 2, sixth bit set 3, sixth bit set 4, sixth bit set 5, sixth bit set 6, and sixth bit set 7, each with a number of 86016 bits. Taking the FEC code using extended BCH (256, 239) as an example, the number of FEC parity bits in the sixth bit set 0, sixth bit set 1, sixth bit set 2, sixth bit set 3, sixth bit set 4, sixth bit set 5, sixth bit set 6, and sixth bit set 7 is 544×21=11424 bits.

[0613] The sixth bit set 0, the sixth bit set 1, the sixth bit set 2, the sixth bit set 3, the sixth bit set 4, the sixth bit set 5, the sixth bit set 6 and the sixth bit set 7 are respectively input into the fourth interleave 0, the fourth interleave 1, the fourth interleave 2, the fourth interleave 3, the fourth interleave 4, the fourth interleave 5, the fourth interleave 6 and the fourth interleave 7 to obtain the ninth bit set 0, the ninth bit set 1, the ninth bit set 2, the ninth bit set 3, the ninth bit set 4, the ninth bit set 5, the ninth bit set 6 and the ninth bit set 7, each of which has 86016 bits. Next, Next, the ninth bit set 0, the ninth bit set 1, the ninth bit set 2, the ninth bit set 3, the ninth bit set 4, the ninth bit set 5, the ninth bit set 6 and the ninth bit set 7 are respectively sent to the fifth interleaving 0, the fifth interleaving 1, the fifth interleaving 2, the fifth interleaving 3, the fifth interleaving 4, the fifth interleaving 5, the fifth interleaving 6 and the fifth interleaving 7 to obtain the seventh bit set 0, the seventh bit set 1, the seventh bit set 2, the seventh bit set 3, the seventh bit set 4, the seventh bit set 5, the seventh bit set 6 and the seventh bit set 7, each of which has a number of bits of 86016 bits.

[0614] The seventh bit set 0, seventh bit set 1, seventh bit set 2, seventh bit set 3, seventh bit set 4, seventh bit set 5, seventh bit set 6 and seventh bit set 7 are respectively sent to intra-square-matrix interleaving 0, intra-square-matrix interleaving 1, intra-square-matrix interleaving 2, intra-square-matrix interleaving 3, intra-square-matrix interleaving 4, intra-square-matrix interleaving 5, intra-square-matrix interleaving 6 and intra-square-matrix interleaving 7 to obtain the tenth bit set 0, tenth bit set 1, tenth bit set 2, tenth bit set 3, tenth bit set 4, tenth bit set 5, tenth bit set 6 and tenth bit set 7, and the number of bits in each is 86016 bits.

[0615] Next, the tenth bit set 0 and the tenth bit set 1, totaling 86016+86016=172032 bits, are sent to the interleave buffer M of inter-matrix interleave 0, and are read out to obtain the eighth bit set 0. Similarly, the tenth bit set 2 and the tenth bit set 3, totaling 86016+86016=172032 bits, are sent to the interleave buffer M of inter-matrix interleave 1, and are read out to obtain the eighth bit set 1. The tenth bit set 4 and the tenth bit set 5, totaling 86016+86016=172032 bits, are sent to the interleave buffer M of inter-matrix interleave 2, and are read out to obtain the eighth bit set 2. The tenth bit set 6 and the tenth bit set 7, totaling 86016+86016=172032 bits, are sent to the interleave buffer M of inter-matrix interleave 3, and are read out to obtain the eighth bit set 3.

[0616] It should be understood that the fourth bit stream 0 obtained after reading the bits from the interleaving buffer M of inter-matrix interleave 0 contains three eighth bit sets 0; similarly, the fourth bit stream 1 obtained after reading the bits from the interleaving buffer M of inter-matrix interleave 1 contains three eighth bit sets 1; the fourth bit stream 2 obtained after reading the bits from the interleaving buffer M of inter-matrix interleave 2 contains three eighth bit sets 2; and the fourth bit stream 3 obtained after reading the bits from the interleaving buffer M of inter-matrix interleave 3 contains three eighth bit sets 3. Therefore, the fourth bit data obtained by combining the fourth bit stream 0, the fourth bit stream 1, the fourth bit stream 2, and the fourth bit stream 3 contains a total of 2,064,384 bits.

[0617] Considering DP-64QAM, every 12 bits of the fourth bit data are mapped to a dual-polarization symbol, resulting in a total of 2064384 / 12 = 172032 dual-polarization symbols. DSP framing is performed on these 172032 dual-polarization symbols, inserting frame synchronization symbols, training symbols, reserved symbols, and pilot symbols into the X- and Y-polarization symbols to create a superframe containing 175104 dual-polarization symbols, which is then transmitted.

[0618] Figure 39 is a schematic diagram of the structure of a data processing device in an embodiment of the present application. As shown in Figure 39, the data processing device includes: a PCS unit 101, a first interleaving unit 102, an FEC encoding unit 103, a second interleaving unit 104, and a third interleaving unit 105. The PCS unit 101 is specifically configured to perform the PCS processing operations in the above-described embodiment. The first interleaving unit 102 is specifically configured to perform the first interleaving operations in the above-described embodiment. The FEC encoding unit 103 is specifically configured to perform the FEC encoding operations in the above-described embodiment. The second interleaving unit 104 is specifically configured to perform the second interleaving operations in the above-described embodiment. The third interleaving unit 105 is specifically configured to perform the third interleaving operations in the above-described embodiment. It should be understood that the data processing device provided in this application may also be implemented in other ways. For example, the unit division in the above-described device is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system. Furthermore, the functional units in various embodiments of the present application may be integrated into a single processing unit, may be separate physical units, or may be two or more functional units integrated into a single processing unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0619] Figure 40 is a structural diagram of an optical module in an embodiment of the present application. As shown in Figure 40, the optical module includes a processor 201 and an interface 202, and the processor 201 is used to perform the operations of the first data processing, the second data processing and the third data processing described in the above embodiment. In a possible implementation, the processor 201 includes the PCS unit 101, the first interleaving unit 102, the FEC encoding unit 103, the second interleaving unit 104 and the third interleaving unit 105 shown in Figure 39 above. The interface 202 can be a transceiver or an input / output interface, and the interface 202 is used to receive signals from other devices outside the optical module and transmit them to the processor 201 or send signals from the processor 201 to other devices outside the optical module. As an example, the processor 201 obtains a DSP superframe after performing the above-mentioned first data processing, the second data processing and the third data processing, and sends the DSP superframe through the interface 202. In this example, the interface 202 can specifically refer to an electrical interface. As another example, processor 201 performs the first, second, and third data processing steps to obtain a DSP superframe. The modulator in the optical module performs signal processing such as electrical-to-optical conversion based on the DSP superframe to obtain an optical signal, which is then transmitted via interface 202. In this example, interface 202 may specifically be an optical interface. Optionally, the optical module may further include memory 203, where memory 203 is configured to store program instructions and data.

[0620] Figure 41 is a structural diagram of a sending device in an embodiment of the present application. As shown in Figure 41, the sending device includes a host-side device 301 and an optical module 302. The host-side device 301 is used to send data to the optical module 302, and the optical module 302 generates an optical signal based on the data sent by the host-side device 301 and sends the optical signal through a channel. For example, the host-side device can specifically be a switch or a router. The sending device can be a communication device including the host-side device 301 and the optical module 302. It should also be understood that the sending device in the embodiment of the present application is named based on the direction of data flow, and does not limit the function of the device. For example, the sending device can also have a receiving function.

[0621] Embodiments of the present application also provide an optical transport network (OTN) device, which includes a line-side device and a client-side device. In some scenarios, the client-side device may also be referred to as a branch-side device. The line-side device includes a processor and an interface, and the processor is configured to perform the first data processing, second data processing, and third data processing operations described in the above embodiments. The interface may be a transceiver or an input / output interface, and is configured to receive signals from devices other than the line-side device and transmit them to the processor, or to transmit signals from the processor to devices other than the line-side device.

[0622] The present application also provides a chip. This chip integrates circuitry and one or more interfaces for implementing the functions of the processor 201 described above. As an example, the chip integrates memory. As another example, if the chip does not integrate memory, it can be connected to an external memory via an interface. This chip can perform the method steps of any one or more of the aforementioned embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the aforementioned embodiments based on program code stored in the memory.

[0623] An embodiment of the present application further provides a computer-readable storage medium, including a program or instructions. When the program or instructions are executed on a computer, the method executed by the processor 201 in the above method embodiment is executed.

[0624] It should be understood that the processors mentioned in the embodiments of the present application can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented by software, the processor can be a general-purpose processor that is implemented by reading software code stored in a memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0625] As an example, the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, or any conventional processor, or a processing circuit that implements a specific function.

[0626] In the embodiments of the present application, the memory may be a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and the storage medium may be located in an ASIC. In addition, the ASIC may be located in a network device or a terminal device. Of course, the processor and the storage medium may also exist in a network device or a terminal device as discrete components.

[0627] In the above embodiments, all or part of them can be implemented by software, hardware, firmware or any combination thereof.

[0628] When implemented using hardware, the data processing method provided in the embodiments of the present application may be implemented without reading software code or instructions. For example, it may be implemented by a CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0629] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; it may also be an optical medium, such as a digital versatile disc (DVD); it may also be a semiconductor medium, such as a solid state disk (SSD).

[0630] Finally, it should be noted that the above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: include: Performing probabilistic constellation shaping (PCS) processing on a first bit set among the multiple bits to obtain a second bit set; performing a first interleaving on the second bit set and a third bit set of the plurality of bits excluding the first bit set to obtain a fourth bit set 1 and a fourth bit set 2; performing forward error correction (FEC) encoding on the two fifth bit sets respectively to obtain two sixth bit sets, where a fifth bit set 1 of the two fifth bit sets includes at least one of the fourth bit set 1, and a fifth bit set 2 of the two fifth bit sets includes at least one of the fourth bit set 2; performing a second interleaving on the two sixth bit sets respectively to obtain two seventh bit sets; A third interleaving is performed on the two seventh bit sets to obtain an eighth bit set, wherein 12 consecutive bits in the eighth bit set are used to map to obtain a dual-polarization symbol, and the dual-polarization symbol includes a first polarization symbol and a second polarization symbol. The 0th bit, the 2nd bit, the 4th bit, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used to map to the first polarization symbol, and the 1st bit, the 3rd bit, the 5th bit, the 7th bit, the 9th bit and the 11th bit of the 12 bits are used to map to the second polarization symbol. Four bits of the 12 bits used to map to the first polarization symbol come from the second bit set, and the other two bits of the 12 bits used to map to the first polarization symbol come from the third bit set and / or the check bits of the FEC code. Four bits of the 12 bits used to map to the second polarization symbol come from the second bit set, and the other two bits of the 12 bits used to map to the second polarization symbol come from the third bit set and / or the check bits of the FEC code.

2. The method according to claim 1, characterized in that The two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, the seventh bit set 1 and the seventh bit set 2 each including 42 rows and 8 columns of a total of 336 first bit subsets, the first bit subset including 16 rows and 16 columns of a total of 256 bits, and a bit distribution pattern of the first bit subset is used to indicate positions of bits from the second bit set in the first bit subset and positions of bits from the third bit set and / or the parity bits of the FEC code in the first bit subset; The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 1 is a first bit distribution pattern; the bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36, and row 39 in the seventh bit set 1 is a second bit distribution pattern; the bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37, and row 40 in the seventh bit set 1 is a third bit distribution pattern; the bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38, and row 41 in the seventh bit set 2 is the third bit distribution pattern; The bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36, and row 39 in the seventh bit set 2 is the first bit distribution pattern; The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 2 is the second bit distribution pattern.

3. The method according to claim 1 or 2, characterized in that Performing a second interleaving on the two sixth bit sets to obtain two seventh bit sets includes: Performing a fourth interleaving on the two sixth bit sets to obtain two ninth bit sets, where the two ninth bit sets include a ninth bit set 1 and a ninth bit set 2, each of the ninth bit set 1 and the ninth bit set 2 includes 42 rows and 8 columns, totaling 336 second bit subsets, and the second bit subset includes 16 rows and 16 columns, totaling 256 bits; Performing a fifth interleaving on the two ninth bit sets respectively to obtain the two seventh bit sets, wherein the fifth interleaving is used to interleave 16 bits in each row of each second bit subset in the ninth bit set.

4. The method according to claim 3, characterized in that The bit distribution pattern of the second bit subset is used to indicate positions of bits from the second bit set in the second bit subset and positions of bits from the third bit set and / or the parity bits of the FEC code in the second bit subset; The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 1 is a fourth bit distribution pattern; the bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36, and row 39 in the ninth bit set 1 is a fifth bit distribution pattern; the bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37, and row 40 in the ninth bit set 1 is a sixth bit distribution pattern; The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 2 is the sixth bit distribution pattern; the bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 21, row 24, row 27, row 30, row 33, row 36, and row 39 in the ninth bit set 2 is the fourth bit distribution pattern; The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 2 is the fifth bit distribution pattern.

5. The method according to any one of claims 1 to 4, characterized in that The two sixth bit sets include a sixth bit set 1 and a sixth bit set 2, each of the sixth bit set 1 and the sixth bit set 2 including 42 rows and 8 columns, totaling 336 third bit subsets, and the third bit subset includes 16 rows and 16 columns, totaling 256 bits; In the 336 third bit subsets of 42 rows and 8 columns, the bits in the third bit subsets from column 0 to column 4 come from the second bit set and the third bit set, the bits in the third bit subset of column 5 and the bits from column 0 to column 14 of the third bit subset of column 6 come from the second bit set, and the bits in column 15 of the third bit subset of column 6 and the bits in the third bit subset of column 7 are the check bits of the FEC encoding.

6. The method according to claim 5, characterized in that The bit distribution pattern of the third bit subset is used to indicate positions of bits from the second bit set in the third bit subset and positions of bits from the third bit set and / or the parity bits of the FEC code in the third bit subset; The bit distribution pattern of the third bit subset of columns 0 to 3, rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, and 41 in the sixth bit set 1 is a fourth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, and 39 from column 0 to column 3 in the sixth bit set 1 is a fifth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37, and 40 from column 0 to column 3 in the sixth bit set 1 is a sixth bit distribution pattern; The bit distribution pattern of the third bit subset of columns 0 to 3, rows 0, 3, 6, 9, 12, 15, 18, 23, 26, 29, 32, 35, 38, and 41 in the sixth bit set 2 is the sixth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 21, 24, 27, 30, 33, 36, and 39 from columns 0 to 3 in the sixth bit set 2 is the fourth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 22, 25, 28, 31, 34, 37 and 40 from column 0 to column 3 in the sixth bit set 2 is the fifth bit distribution pattern.

7. The method according to claim 1, characterized in that The two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, the seventh bit set 1 and the seventh bit set 2 each including 42 rows and 8 columns of a total of 336 first bit subsets, the first bit subset including 16 rows and 16 columns of a total of 256 bits, and a bit distribution pattern of the first bit subset is used to indicate positions of bits from the second bit set in the first bit subset and positions of bits from the third bit set and / or the parity bits of the FEC code in the first bit subset; The bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the seventh bit set 1 is a first bit distribution pattern; the bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 1 is a second bit distribution pattern; the bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36, and row 39 in the seventh bit set 1 is a third bit distribution pattern; the bit distribution pattern of the first bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37, and row 40 in the seventh bit set 2 is the second bit distribution pattern; the bit distribution pattern of the first bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the seventh bit set 2 is the third bit distribution pattern; The bit distribution pattern of the first bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the seventh bit set 2 is the first bit distribution pattern.

8. The method according to claim 1 or 7, characterized in that Performing a second interleaving on the two sixth bit sets to obtain two seventh bit sets includes: Performing a fourth interleaving on the two sixth bit sets to obtain two ninth bit sets, where the two ninth bit sets include a ninth bit set 1 and a ninth bit set 2, each of the ninth bit set 1 and the ninth bit set 2 includes 42 rows and 8 columns, totaling 336 second bit subsets, and the second bit subset includes 16 rows and 16 columns, totaling 256 bits; Performing a fifth interleaving on the two ninth bit sets respectively to obtain the two seventh bit sets, wherein the fifth interleaving is used to interleave 16 bits in each row of each second bit subset in the ninth bit set.

9. The method according to claim 8, characterized in that The bit distribution pattern of the second bit subset is used to indicate positions of bits from the second bit set in the second bit subset and positions of bits from the third bit set and / or the parity bits of the FEC code in the second bit subset; The bit distribution pattern of the second bit subset of row 0, row 3, row 6, row 9, row 12, row 15, row 18, row 22, row 25, row 28, row 31, row 34, row 37 and row 40 in the ninth bit set 1 is a fourth bit distribution pattern; The bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 1 is a fifth bit distribution pattern; the bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36, and row 39 in the ninth bit set 1 is a sixth bit distribution pattern; The bit distribution pattern of the second bit subset of rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37 and 40 in the ninth bit set 2 is the fifth bit distribution pattern; the bit distribution pattern of the second bit subset of row 1, row 4, row 7, row 10, row 13, row 16, row 19, row 23, row 26, row 29, row 32, row 35, row 38 and row 41 in the ninth bit set 2 is the sixth bit distribution pattern; The bit distribution pattern of the second bit subset of row 2, row 5, row 8, row 11, row 14, row 17, row 20, row 21, row 24, row 27, row 30, row 33, row 36 and row 39 in the ninth bit set 2 is the fourth bit distribution pattern.

10. The method according to claim 1, 7, 8 or 9, characterized in that The two sixth bit sets include a sixth bit set 1 and a sixth bit set 2, each of the sixth bit set 1 and the sixth bit set 2 including 42 rows and 8 columns, totaling 336 third bit subsets, and the third bit subset includes 16 rows and 16 columns, totaling 256 bits; In the 336 third bit subsets of 42 rows and 8 columns, the bits in the third bit subsets from column 0 to column 4 come from the second bit set and the third bit set, the bits in the third bit subset of column 5 and the bits from column 0 to column 14 of the third bit subset of column 6 come from the second bit set, and the bits in column 15 of the third bit subset of column 6 and the bits in the third bit subset of column 7 are the check bits of the FEC encoding.

11. The method according to claim 10, characterized in that The bit distribution pattern of the third bit subset is used to indicate positions of bits from the second bit set in the third bit subset and positions of bits from the third bit set and / or the parity bits of the FEC code in the third bit subset; The bit distribution pattern of the third bit subset of columns 0 to 3, rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37, and 40 in the sixth bit set 1 is a fourth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 1 is a fifth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36, and 39 from column 0 to column 3 in the sixth bit set 1 is a sixth bit distribution pattern; The bit distribution pattern of the third bit subset of columns 0 to 3, rows 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 34, 37, and 40 in the sixth bit set 2 is the fifth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 1, 4, 7, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38 and 41 from column 0 to column 3 in the sixth bit set 2 is the sixth bit distribution pattern; The bit distribution pattern of the third bit subset of rows 2, 5, 8, 11, 14, 17, 20, 21, 24, 27, 30, 33, 36 and 39 from column 0 to column 3 in the sixth bit set 2 is the fourth bit distribution pattern.

12. The method according to any one of claims 1 to 11, characterized in that The 0th bit, the 2nd bit and the 4th bit of the 12 bits are used to map to the first component of the first polarization symbol, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 1st bit, the 3rd bit and the 5th bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 7th bit, the 9th bit and the 11th bit of the 12 bits are used to map to the second component of the second polarization symbol.

13. The method according to any one of claims 1 to 11, characterized in that The 0th bit, the 4th bit and the 6th bit of the 12 bits are used to map to the first component of the first polarization symbol, the 2nd bit, the 8th bit and the 10th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 1st bit, the 5th bit and the 7th bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 3rd bit, the 9th bit and the 11th bit of the 12 bits are used to map to the second component of the second polarization symbol.

14. The method according to any one of claims 1 to 11, characterized in that The 8th bit, the 0th bit and the 2nd bit of the 12 bits are used to map to the first component of the first polarization symbol, the 10th bit, the 4th bit and the 6th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 9th bit, the 1st bit and the 3rd bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 11th bit, the 5th bit and the 7th bit of the 12 bits are used to map to the second component of the second polarization symbol.

15. The method according to any one of claims 1 to 11, characterized in that The 4th bit, the 0th bit and the 2nd bit of the 12 bits are used to map to the first component of the first polarization symbol, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used to map to the second component of the first polarization symbol, the 5th bit, the 1st bit and the 3rd bit of the 12 bits are used to map to the first component of the second polarization symbol, and the 7th bit, the 9th bit and the 11th bit of the 12 bits are used to map to the second component of the second polarization symbol.

16. The method according to any one of claims 12 to 15, characterized in that The polarization direction of the first polarization sign and the deflection direction of the second polarization sign are orthogonal to each other; The first component is an I-path component, and the second component is a Q-path component; or, the first component is a Q-path component, and the second component is an I-path component.

17. The method according to any one of claims 1 to 16, characterized in that The two seventh bit sets include a seventh bit set 1 and a seventh bit set 2, and performing a third interleaving on the two seventh bit sets to obtain an eighth bit set includes: Performing intra-matrix interleaving on the seventh bit set 1 to obtain a tenth bit set 1, and performing intra-matrix interleaving on the seventh bit set 2 to obtain a tenth bit set 2, wherein the tenth bit set 1 and the tenth bit set 2 each include 42 rows and 8 columns of a fourth bit subset totaling 336 bits, and the fourth bit subset includes 16 rows and 16 columns of a total of 256 bits; The tenth bit set 1 and the tenth bit set 2 are interleaved between square matrices to obtain the eighth bit set, and the eighth bit set includes 84 rows and 8 columns, totaling 672 fourth bit subsets.

18. The method according to any one of claims 1 to 17, characterized in that The first bit set includes a first bit set 1 and a first bit set 2, and performing PCS processing on the first bit set among the multiple bits to obtain a second bit set includes: Perform PCS processing on the first bit set 1 to obtain a second bit set 1, and perform PCS processing on the first bit set 2 to obtain a second bit set 2, wherein the second bit set includes the second bit set 1 and the second bit set 2.

19. The method according to claim 18, characterized in that The third bit set includes the third bit set 1 and the third bit set 2, and performing a first interleaving on the second bit set and the third bit set in the plurality of bits except the first bit set to obtain the fourth bit set 1 and the fourth bit set 2 includes: The second bit set 1, the second bit set 2, the third bit set 1 and the third bit set 2 are first interleaved to obtain the fourth bit set 1 and the fourth bit set 2.

20. The method according to claim 18, wherein The third bit set includes the third bit set 1 and the third bit set 2, and performing a first interleaving on the second bit set and the third bit set in the plurality of bits except the first bit set to obtain the fourth bit set 1 and the fourth bit set 2 includes: The second bit set 1 and the third bit set 1 are first interleaved to obtain the fourth bit set 1, and the second bit set 2 and the third bit set 2 are first interleaved to obtain the fourth bit set 2.

21. The method according to claim 18, wherein Performing a first interleaving on the second bit set and a third bit set excluding the first bit set in the plurality of bits to obtain a fourth bit set 1 and a fourth bit set 2 includes: The second bit set 1, the second bit set 2, and the third bit set are first interleaved to obtain the fourth bit set 1 and the fourth bit set 2.

22. The method according to any one of claims 1 to 21, characterized in that The amplitude bits mapped to the dual-polarization symbols come from the second bit set, and the sign bits mapped to the dual-polarization symbols come from the third bit set and / or the parity bits of the FEC code.

23. A data processing device, characterized in that: The data processing device includes: a probabilistic constellation shaping PCS unit, a first interleaving unit, a forward error correction FEC encoding unit, a second interleaving unit and a third interleaving unit; The PCS unit is configured to: perform PCS processing on a first bit set among the multiple bits to obtain a second bit set; The first interleaving unit is configured to: perform a first interleaving on the second bit set and a third bit set in the plurality of bits excluding the first bit set, to obtain a fourth bit set 1 and a fourth bit set 2; The FEC encoding unit is configured to: perform FEC encoding on two fifth bit sets respectively to obtain two sixth bit sets, where a fifth bit set 1 of the two fifth bit sets includes at least one of the fourth bit set 1, and a fifth bit set 2 of the two fifth bit sets includes at least one of the fourth bit set 2; The second interleaving unit is configured to: perform a second interleaving on the two sixth bit sets respectively to obtain two seventh bit sets; The third interleaving unit is used to: perform a third interleaving on the two seventh bit sets to obtain an eighth bit set, wherein 12 consecutive bits in the eighth bit set are used to map to obtain a dual-polarization symbol, the dual-polarization symbol includes a first polarization symbol and a second polarization symbol, the 0th bit, the 2nd bit, the 4th bit, the 6th bit, the 8th bit and the 10th bit of the 12 bits are used to map to the first polarization symbol, and the 1st bit, the 3rd bit, the 5th bit, the 7th bit, the 9th bit and the 11th bit of the 12 bits are used to map to the first polarization symbol. For mapping to the second polarization symbol, 4 bits of the 12 bits used to map to the first polarization symbol come from the second bit set, and the other 2 bits of the 12 bits used to map to the first polarization symbol come from the third bit set and / or the check bits of the FEC code, 4 bits of the 12 bits used to map to the second polarization symbol come from the second bit set, and the other 2 bits of the 12 bits used to map to the second polarization symbol come from the third bit set and / or the check bits of the FEC code.

24. A chip, characterized in that: The chip includes a processor configured to execute the method according to any one of claims 1 to 22.

25. An optical module, characterized in that: The optical module includes a processor and an interface, wherein the processor is configured to execute the method according to any one of claims 1 to 22 and send a signal through the interface.

26. The optical module according to claim 25, wherein: The processor is configured to perform data processing on the eighth bit set to obtain a DSP superframe, and send the DSP superframe through the interface.

27. The optical module according to claim 25, wherein: The optical module also includes a modulator. The processor is used to perform data processing on the eighth bit set to obtain a DSP superframe. The modulator is used to perform electrical-to-optical conversion according to the DSP superframe to obtain an optical signal and send the optical signal through the interface.

28. A sending device, characterized in that: The sending device includes a host-side device and an optical module according to any one of claims 25 to 27, wherein the optical module is configured to generate an optical signal according to data from the host-side device and send the optical signal.

29. A communication system, characterized in that: include: The transmitting device and receiving device according to claim 28, wherein the transmitting device is used to send an optical signal to the receiving device.

Images