Circuit rearrangement method and apparatus, electronic device, storage medium, and program product

Abstract

The present application provides a circuit rearrangement method and apparatus, an electronic device, a storage medium, and a program product. The method comprises: acquiring a hardware description of a first circuit, the hardware description being used for representing logic relationships between devices in the first circuit; on the basis of the hardware description, rearranging circuit structures of a plurality of first sub-circuits in the first circuit, and obtaining a plurality of second sub-circuits, the plurality of first sub-circuits and the plurality of second sub-circuits being a plurality of sub-circuits connected in series; traversing the plurality of second sub-circuits, and obtaining a plurality of candidate circuit topologies, each candidate circuit topology among the plurality of candidate circuit topologies comprising at least one second sub-circuit; and determining an optimal topology of the first circuit from among the plurality of candidate circuit topologies, the optimal topology being a circuit topology having the lowest layout cost among the plurality of candidate circuit topologies, and the layout cost being determined on the basis of at least the number of diffusion gaps. According to the present application, circuit rearrangement efficiency is improved.

Description

Circuit rearrangement method, device, electronic device, storage medium and program product

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 5, 2024, with application number 202410165497.6 and application name “Circuit Rearrangement Method, Device, Electronic Device, Storage Medium and Program Product”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic circuit technology, and in particular to a circuit rearrangement method, device, electronic device, storage medium, and program product. Background Art

[0003] Integrated circuits (ICs) have become a core component of various electronic devices. With the continuous advancement of electronic circuit technology, IC design has become increasingly complex and sophisticated. Layout design is a critical step in the IC design process, transforming circuit topology into a manufacturable physical structure. Different circuit topologies require different layout qualities. For example, a high-quality transistor-level circuit layout must meet requirements such as high performance, a small number of diffusion gaps, and a small layout area. Therefore, the IC design process requires a rapid search across various circuit topologies and the rapid identification of the optimal one. Summary of the Invention

[0004] The purpose of this application is to provide a circuit rearrangement method, device, electronic device, storage medium and program product, which can quickly and efficiently determine the optimal circuit topology corresponding to the minimum number of diffusion gaps by rearranging the series sub-circuits in the circuit and determining the layout cost based on the number of diffusion gaps.

[0005] According to a first aspect of an embodiment of the present application, a circuit rearrangement method is provided, comprising: obtaining a hardware description of a first circuit, the hardware description being used to represent devices in the first circuit and logical relationships between devices; based on the hardware description, rearranging the circuit structures of a plurality of first sub-circuits in the first circuit to obtain a plurality of second sub-circuits; the plurality of first sub-circuits and the plurality of second sub-circuits are a plurality of sub-circuits connected in series; traversing the plurality of second sub-circuits to obtain a plurality of candidate circuit topologies, each of the plurality of candidate circuit topologies containing at least one of the second sub-circuits; determining an optimal topology of the first circuit from the plurality of candidate circuit topologies, the optimal topology being a circuit topology with the smallest layout cost among the plurality of candidate circuit topologies, the layout cost being determined based at least on the number of diffusion gaps.

[0006] In some embodiments, the circuit structures of multiple first sub-circuits in the first circuit are rearranged to obtain multiple second sub-circuits, including: determining multiple first sub-circuits in the first circuit based on the hardware description; determining target intersections of each sub-circuit in the multiple first sub-circuits, where the target intersections are the source and drain of the circuit structure; and rearranging the circuit structures of the multiple first sub-circuits based on the target intersections to obtain multiple second sub-circuits.

[0007] In some embodiments, based on the target intersection, the circuit structures of the multiple first sub-circuits are rearranged to obtain multiple second sub-circuits, including: for the i-th first sub-circuit among the multiple first sub-circuits, i is a positive integer, performing the following steps in sequence: exchanging the first circuit structure and the second circuit structure connected by the target intersection in the i-th first sub-circuit to obtain the second sub-circuit corresponding to the i-th first sub-circuit; assigning i to i+1, and returning to the step of exchanging the first circuit structure and the second circuit structure connected by the target intersection in the i-th first sub-circuit, until multiple second sub-circuits corresponding to the multiple first sub-circuits are obtained.

[0008] In some embodiments, based on the hardware description, multiple first sub-circuits are determined in the first circuit, including: determining multiple sub-circuits of the first circuit based on the hardware description; traversing the multiple sub-circuits of the first circuit to determine multiple third sub-circuits, and merging the multiple third sub-circuits into a fourth sub-circuit to form a second circuit, the multiple third sub-circuits and the multiple fourth sub-circuits being multiple sub-circuits connected in parallel; traversing the multiple sub-circuits of the second circuit to determine the multiple first sub-circuits.

[0009] In some embodiments, traversing multiple sub-circuits of the second circuit to determine the multiple first sub-circuits includes: starting from the first transistor of the second circuit, determining at least one second transistor connected in series with the first transistor; determining the sub-circuit consisting of the first transistor and the at least one second transistor as the first sub-circuit; determining the third transistor of the second circuit as the first transistor, and returning to the step of starting from the first transistor of the second circuit and determining at least one second transistor connected in series with the first transistor, until traversing the transistors of the second circuit to determine the multiple first sub-circuits.

[0010] In some embodiments, traversing the multiple second subcircuits to obtain multiple candidate circuit topology structures includes: selecting m second subcircuits from the multiple second subcircuits, where m is a positive integer; combining the m second subcircuits with a fifth subcircuit to obtain a candidate circuit topology structure corresponding to the m second subcircuits; the fifth subcircuit is a subcircuit in the first circuit other than the first subcircuit corresponding to the m second subcircuits; assigning m a value of m+1, and returning to the step of selecting m second subcircuits from the multiple second subcircuits until multiple candidate circuit topology structures are obtained.

[0011] In some embodiments, the layout cost is further determined based on at least one of: the number of gate mismatches; the layout width; the maximum routing ratio; the sum of squares of routing density; and the total routing length.

[0012] According to a second aspect of an embodiment of the present application, a circuit rearrangement device is provided, comprising:

[0013] an acquisition module configured to obtain a hardware description of the first circuit, wherein the hardware description is used to represent components in the first circuit and logical relationships between components;

[0014] a rearrangement module configured to rearrange the circuit structures of the plurality of first sub-circuits in the first circuit based on the hardware description to obtain a plurality of second sub-circuits; the plurality of first sub-circuits and the plurality of second sub-circuits being a plurality of sub-circuits connected in series;

[0015] a traversal module configured to traverse the plurality of second sub-circuits to obtain a plurality of candidate circuit topologies, each candidate circuit topology in the plurality of candidate circuit topologies including at least one of the second sub-circuits;

[0016] A determination module is configured to determine an optimal topology of the first circuit from the multiple candidate circuit topologies, wherein the optimal topology is a circuit topology with the smallest layout cost among the multiple candidate circuit topologies, and the layout cost is determined based on at least the number of diffusion gaps.

[0017] In some embodiments, the rearrangement module is further configured to: determine multiple first sub-circuits in the first circuit based on the hardware description; determine the target intersection of each sub-circuit in the multiple first sub-circuits, where the target intersection is the source and drain of the circuit structure; and rearrange the circuit structure of the multiple first sub-circuits based on the target intersection to obtain multiple second sub-circuits.

[0018] In some embodiments, the rearrangement module is further configured to: for the i-th first subcircuit among the multiple first subcircuits, where i is a positive integer, perform the following steps in sequence: swap the first circuit structure and the second circuit structure connected at the target intersection in the i-th first subcircuit to obtain the second subcircuit corresponding to the i-th first subcircuit; assign i to i+1, and return to the step of swapping the first circuit structure and the second circuit structure connected at the target intersection in the i-th first subcircuit, until multiple second subcircuits corresponding to the multiple first subcircuits are obtained.

[0019] In some embodiments, the rearrangement module is further configured to: determine multiple sub-circuits of the first circuit based on the hardware description; traverse the multiple sub-circuits of the first circuit to determine multiple third sub-circuits, and merge the multiple third sub-circuits into a fourth sub-circuit to form a second circuit, wherein the multiple third sub-circuits and the multiple fourth sub-circuits are multiple sub-circuits connected in parallel; traverse the multiple sub-circuits of the second circuit to determine the multiple first sub-circuits.

[0020] In some embodiments, the rearrangement module is further configured to: starting from the first transistor of the second circuit, determine at least one second transistor connected in series with the first transistor; determine the sub-circuit consisting of the first transistor and the at least one second transistor as the first sub-circuit; determine the third transistor of the second circuit as the first transistor, and return to the step of starting from the first transistor of the second circuit and determining at least one second transistor connected in series with the first transistor until traversing the transistors of the second circuit to determine the multiple first sub-circuits.

[0021] In some embodiments, the traversal module is further configured to: select m second subcircuits from the multiple second subcircuits, where m is a positive integer; combine the m second subcircuits with a fifth subcircuit to obtain a candidate circuit topology structure corresponding to the m second subcircuits; the fifth subcircuit is a subcircuit in the first circuit other than the first subcircuit corresponding to the m second subcircuits; assign m to m+1, and return to the step of selecting m second subcircuits from the multiple second subcircuits until multiple candidate circuit topologies are obtained.

[0022] According to a third aspect of the embodiments of the present application, there is provided an electronic device, including:

[0023] processor;

[0024] a memory configured to store processor-executable instructions;

[0025] The processor is configured to execute the circuit rearrangement method described in the first aspect above when calling the executable instructions in the memory.

[0026] According to a fourth aspect of an embodiment of the present application, a non-temporary computer-readable storage medium is provided. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the circuit rearrangement method described in the first aspect above.

[0027] According to a fifth aspect of an embodiment of the present application, a computer program product is provided, comprising a computer program or instructions, wherein when the computer program or instructions are executed by a processor, the circuit rearrangement method described in the first aspect above is implemented.

[0028] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0029] A hardware description of a first circuit is obtained. The hardware description of the first circuit represents the components and the logical relationships between the components in the first circuit. Based on the hardware description, the circuit structures of multiple first subcircuits in the first circuit are rearranged to obtain multiple second subcircuits. Each of the multiple first subcircuits and the multiple second subcircuits is a series-connected subcircuit. This allows for bottom-up circuit decomposition and reorganization based on the hardware description of the first circuit, improving traversal efficiency. The multiple second subcircuits are traversed to obtain multiple candidate circuit topologies, each of which contains at least one second subcircuit. This allows for traversal of the entire first circuit by traversing only the full permutation of the series-connected subcircuits in the first circuit. The series-connected subcircuits limit the traversal search space, improving circuit rearrangement efficiency. An optimal topology for the first circuit is determined from the multiple candidate circuit topologies. The optimal topology is the circuit topology with the lowest layout cost among the multiple candidate circuit topologies. The layout cost is determined based at least on the number of diffusion gaps, thereby effectively optimizing the number of diffusion gaps in the layout corresponding to the first circuit.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a flowchart of a circuit rearrangement method according to an embodiment of the present application.

[0032] FIG2 is a second flowchart of the circuit rearrangement method provided in an embodiment of the present application.

[0033] FIG3 is a third flowchart of the circuit rearrangement method provided in an embodiment of the present application.

[0034] FIG4 is a fourth flowchart of the circuit rearrangement method provided in an embodiment of the present application.

[0035] FIG5 is a fifth flowchart of the circuit rearrangement method provided in an embodiment of the present application.

[0036] FIG6A is a sixth flowchart of the circuit rearrangement method provided in an embodiment of the present application.

[0037] FIG6B is a flow chart of a method for identifying series sub-circuits provided in an embodiment of the present application.

[0038] FIG6C is a flowchart of a method for determining parallel sub-circuits and series sub-circuits provided in an embodiment of the present application.

[0039] FIG7A is a circuit topology diagram before executing the circuit rearrangement method provided in an embodiment of the present application.

[0040] FIG7B is a circuit layout corresponding to the circuit topology before executing the circuit rearrangement method provided in an embodiment of the present application.

[0041] FIG7C is a circuit topology diagram after executing the circuit rearrangement method provided in an embodiment of the present application.

[0042] FIG7D is a circuit layout corresponding to the circuit topology after executing the circuit rearrangement method provided in an embodiment of the present application.

[0043] FIG8 is a schematic structural diagram of a circuit rearrangement device provided in an embodiment of the present application.

[0044] FIG9 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] FIG1 is a flowchart of a circuit rearrangement method according to an exemplary embodiment. As shown in FIG1 , the method mainly includes the following steps:

[0046] In step 101, a hardware description of a first circuit is obtained, where the hardware description is used to represent components in the first circuit and logical relationships between components.

[0047] In some embodiments, the first circuit may be a series circuit, a parallel circuit, or a series-parallel hybrid circuit. In some embodiments, the first circuit may be a DC circuit, an AC circuit, or other circuits of other types, structures, and functions, which are not limited in this application.

[0048] In some embodiments, the hardware description of the first circuit may include: electronic devices included in the first circuit, types of electronic devices, number of electronic devices, locations of electronic devices, connection relationships between electronic devices, electronic parameters of electronic devices, etc.

[0049] In some embodiments, the hardware description of the first circuit can be obtained and stored in the form of a circuit netlist. A circuit netlist is a file format used in Electronic Design Automation (EDA) that primarily describes the components, wires, and connections of a circuit. Netlist files are typically automatically generated by schematic, layout, or circuit simulation software.

[0050] In some embodiments, the circuit netlist may include a component list, wire net information, electrical parameter information, annotation information, etc. The component list lists all electronic components used in the first circuit, including their models and pinout information. The wire net information may indicate the connection relationships between electronic components, including the interconnection and electrical connections between the pins of the electronic components. The electrical parameter information may indicate the electrical parameters of each electronic component, including resistance, capacitance, inductance, power supply, and clock speed and input level of digital components. The annotation information may indicate the design concept, function, etc. of the first circuit.

[0051] In step 102 , based on the hardware description, the circuit structures of the plurality of first sub-circuits in the first circuit are rearranged to obtain a plurality of second sub-circuits; the plurality of first sub-circuits and the plurality of second sub-circuits are a plurality of sub-circuits connected in series.

[0052] In some embodiments, based on the devices in the first circuit and the logical relationship between the devices, multiple first sub-circuits can be determined from the first circuit. The multiple first sub-circuits are multiple sub-circuits connected in series, that is, the first circuit is disassembled from small to large and from bottom to top to obtain multiple series sub-circuits.

[0053] That is, by traversing and searching all devices in the first circuit, a plurality of series sub-circuits (ie, the first sub-circuit) or a plurality of parallel sub-circuits can be determined based on the logical relationship between the devices.

[0054] It should be noted that the first sub-circuit includes at least two electronic devices or at least two circuit structures, and a parallel connection relationship may exist in the first sub-circuit.

[0055] In one example, structure A and structure B in the first circuit are connected in series, and the sub-circuit formed by structure A and structure B is the first sub-circuit; structure A includes multiple electronic devices a, and some of the multiple electronic devices a are connected in parallel; structure B includes multiple electronic devices b, and the multiple electronic devices b are mixed in series and parallel.

[0056] In one example, an electronic device a and another electronic device b in the first circuit are connected in series, and the sub-circuit formed by the electronic device a and the electronic device b is a first sub-circuit.

[0057] In some embodiments, taking a transistor circuit as an example, at least two transistors with connected sources and drains are connected in series; at least two transistors with connected sources and drains are connected in parallel.

[0058] In some embodiments, multiple second sub-circuits can be obtained by rearranging the circuit structures of multiple first sub-circuits. The multiple second sub-circuits are also multiple sub-circuits connected in series, i.e., series sub-circuits. In other words, the first sub-circuits and the second sub-circuits have different circuit structures but implement the same circuit functions.

[0059] In some embodiments, the plurality of first subcircuits and the plurality of second subcircuits may have a one-to-one correspondence, i.e., the circuit structure of the first subcircuit can be changed once, so it can be understood that the number of rearrangeable nodes in the first subcircuit is one. The plurality of first subcircuits and the plurality of second subcircuits may also have a one-to-many correspondence, i.e., the circuit structure of the first subcircuit can be changed multiple times, so it can be understood that the number of rearrangeable nodes in the first subcircuit is multiple.

[0060] In step 103 , multiple second sub-circuits are traversed to obtain multiple candidate circuit topologies, each of which includes at least one second sub-circuit.

[0061] In some embodiments, after obtaining multiple second sub-circuits having different circuit structures from the multiple first sub-circuits, multiple candidate circuit topologies can be obtained by traversing the multiple second sub-circuits. That is, the multiple candidate circuit topologies have the same functions as the first circuit but different circuit structures.

[0062] In some embodiments, assuming that there are 4 second subcircuits, when the candidate circuit topology includes 1 second subcircuit, there are 4 different candidate circuit topologies; when the candidate circuit topology includes 2 second subcircuits, there are 6 different candidate circuit topologies; when the candidate circuit topology includes 3 second subcircuits, there are 4 different candidate circuit topologies; when the candidate circuit topology includes 4 second subcircuits, there is 1 candidate circuit topology. That is, when there are 4 second subcircuits, a total of 2 4 -1=15 different candidate circuit topologies. That is, when there are N second subcircuits, 2 N -1 different candidate circuit topologies, where N is a positive integer.

[0063] In other words, by rearranging the circuit structure of the series sub-circuit and traversing the rearranged first sub-circuit, the traversal rearrangement of the first circuit can be completed, that is, the first circuit is disassembled and reorganized based on the series sub-circuit, so as to limit the traversal search space, effectively reduce the complexity of the circuit structure, and improve the circuit rearrangement efficiency.

[0064] In step 104, an optimal topology of the first circuit is determined from multiple candidate circuit topologies. The optimal topology is a circuit topology with the lowest layout cost among the multiple candidate circuit topologies. The layout cost is determined based on at least the number of diffusion gaps.

[0065] In some embodiments, candidate circuit layouts corresponding to each candidate circuit topology may be obtained, and then layout costs corresponding to each candidate circuit layout may be calculated. The circuit topology corresponding to the candidate circuit layout with the lowest layout cost may be selected as the optimal topology for the first circuit. The layout cost may be determined based on at least the number of diffusion gaps.

[0066] In some embodiments, the layout cost may also be determined based on at least one of: the number of gate mismatches, the layout width, the maximum routing ratio, the sum of squares of routing density, and the total routing length.

[0067] The number of diffusion gaps can be understood as the number of gaps between active areas, which will affect the layout width. The greater the number, the greater the layout width.

[0068] The number of gate mismatches can be understood as the number of inconsistent gate input signals between P-type transistors and N-type transistors in the circuit. This will affect circuit routing. The greater the number, the more difficult the layout routing becomes, resulting in waste of layout area.

[0069] The maximum winding ratio can be understood as the overall width of the layout. The larger the value, the larger the layout area.

[0070] The sum of squares of winding density can be understood as another indicator for evaluating winding quality. It affects circuit winding and layout area. The larger the value, the larger the layout area.

[0071] The total winding length can be understood as the overall winding length in the layout. The larger the value, the larger the layout area.

[0072] That is to say, the layout cost can be determined based on one or more of the parameters listed above, and can also be determined based on other parameters that affect the quality of the circuit layout, which is not limited in this application.

[0073] In some embodiments, the layout cost may further include weight parameters. The weight parameters may include at least one of the following: a weight parameter corresponding to the number of gate mismatches, a weight parameter corresponding to the layout width, a weight parameter corresponding to the maximum winding ratio, a weight parameter corresponding to the sum of squares of the winding density, and a weight parameter corresponding to the total winding length.

[0074] In some embodiments, the weight parameter value corresponding to the number of gate mismatches is 4, the weight parameter value corresponding to the layout width is 3, the weight parameter value corresponding to the maximum winding ratio is 4, the weight parameter value corresponding to the sum of the squares of the winding density is 2, and the weight parameter value corresponding to the total winding length is 1.

[0075] In some embodiments, the circuit rearrangement method described above can be applied to dual transistor-level circuits or non-dual transistor-level circuits.

[0076] FIG2 is a second flowchart of a circuit rearrangement method according to an exemplary embodiment. As shown in FIG2 , based on the hardware description, step 102 includes steps 202 to 204 .

[0077] In step 201, a hardware description of a first circuit is obtained, where the hardware description is used to represent components in the first circuit and logical relationships between components.

[0078] The optional implementation of step 201 in this embodiment can refer to the optional implementation of step 101 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0079] In step 202 , a plurality of first sub-circuits are determined in a first circuit based on a hardware description.

[0080] In some embodiments, based on the devices in the first circuit and the logical relationships between the devices, a plurality of serially connected sub-circuits, ie, a plurality of first sub-circuits, may be determined.

[0081] In some embodiments, each device in the first circuit can be labeled, and each device can be traversed in sequence according to the label order to determine the connection relationship between the device corresponding to the current label and the device corresponding to the next label. When the connection relationship between two devices is a series connection, the sub-circuit formed by the two devices is determined to be a series sub-circuit, that is, the first sub-circuit.

[0082] In one example, the devices corresponding to number 1 are traversed. If it is determined that the device corresponding to number 1 and the device corresponding to number 2 are connected in series, then the sub-circuit formed by the device corresponding to number 1 and the device corresponding to number 2 is the first sub-circuit S1. The devices corresponding to number 2 are traversed. If the device corresponding to number 2 and the device corresponding to number 3 are connected in series, then the sub-circuit formed by the device corresponding to number 2 and the device corresponding to number 3 is the second first sub-circuit S2.

[0083] At this point, the first sub-circuit S1 formed by the device corresponding to number 1 and the device corresponding to number 2, and the first sub-circuit S2 formed by the device corresponding to number 2 and the device corresponding to number 3 can also be determined as one first sub-circuit. A specific operation can be to add the first sub-circuit S2 to the first sub-circuit S1. In this case, after the addition operation is performed, the first sub-circuit S1 includes the device corresponding to number 1, the device corresponding to number 2, and the device corresponding to number 3.

[0084] In step 203 , a target intersection point of each sub-circuit in the plurality of first sub-circuits is determined, where the target intersection point is a source and a drain of the circuit structure.

[0085] In some embodiments, since the first sub-circuit is a sub-circuit connected in series, the target intersection point can be determined from the first sub-circuit. The target intersection point can have different meanings and determination methods based on different circuits.

[0086] In one example, the target intersection point may be a connection point where at least two electronic devices or at least two circuit structures are connected in series. For example, if the first circuit is a transistor-level circuit, and the first subcircuit is a subcircuit where two transistors are connected in series, specifically where the source of one transistor is connected to the drain of another transistor, then the target intersection point is the source and drain of the transistors.

[0087] In another example, the target intersection may be a connection point connecting only two electronic devices or only two circuit structures.

[0088] In another example, the target intersection point may be a connection point connecting only two circuit structures, and at least one of the two circuit structures has a parallel connection relationship.

[0089] In some embodiments, a first subcircuit may include one or more target intersections. Since the target intersection connects two electronic devices or two circuit structures, the circuit structure of the first subcircuit can be rearranged based on the target intersection. That is, the target intersection can be understood as a rearrangeable node. Generally speaking, the more target intersections included in the first subcircuit, the greater the number of different circuit structures that can be obtained by rearrangement.

[0090] In step 204 , the circuit structures of the plurality of first sub-circuits are rearranged based on the target intersection point to obtain a plurality of second sub-circuits.

[0091] In some embodiments, because the target intersection connects two electronic devices or two circuit structures, the circuit structure of the first sub-circuit can be changed based on the target intersection without changing the circuit function of the first sub-circuit. In one example, the positions of the two electronic devices or two circuit structures connected by the target intersection can be swapped. In another example, the circuit structure of at least one of the two circuit structures connected by the target intersection can be changed.

[0092] In step 205 , multiple second sub-circuits are traversed to obtain multiple candidate circuit topologies, each of which includes at least one second sub-circuit.

[0093] The optional implementation of step 205 in this embodiment can refer to the optional implementation of step 103 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0094] In step 206, an optimal topology of the first circuit is determined from multiple candidate circuit topologies. The optimal topology is a circuit topology with the lowest layout cost among the multiple candidate circuit topologies. The layout cost is determined based on at least the number of diffusion gaps.

[0095] The optional implementation of step 206 in this embodiment can refer to the optional implementation of step 104 in Figure 1 and other related parts in the embodiment involved in Figure 1, and will not be repeated here.

[0096] FIG3 is a flowchart of a circuit rearrangement method according to an exemplary embodiment. As shown in FIG3 , step 202 includes steps 302 to 304:

[0097] In step 301, a hardware description of a first circuit is obtained, where the hardware description is used to represent components in the first circuit and logical relationships between components.

[0098] The optional implementation of step 301 in this embodiment can refer to the optional implementation of step 101 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0099] In step 302 , a plurality of sub-circuits of a first circuit are determined based on a hardware description.

[0100] In some embodiments, a subcircuit includes at least two electronic devices, and the subcircuit can be a parallel subcircuit or a series subcircuit. In other words, based on the logical relationships between the devices in the first circuit, the first circuit is initially decomposed into multiple series subcircuits and / or parallel subcircuits.

[0101] In some embodiments, in the process of disassembling the first circuit to obtain multiple sub-circuits, each device can be traversed in sequence according to the device number or position order, or each device can be traversed in sequence according to the direction of current flow in the first circuit, or each device can be traversed in sequence according to the connection relationship of the device pins.

[0102] In step 303, multiple subcircuits of the first circuit are traversed to determine multiple third subcircuits, and the multiple third subcircuits are merged into a fourth subcircuit to form a second circuit. The multiple third subcircuits and the multiple fourth subcircuits are multiple subcircuits connected in parallel.

[0103] In some embodiments, a plurality of third sub-circuits are determined from the plurality of sub-circuits of the first circuit. The third sub-circuits are sub-circuits connected in parallel, i.e., parallel sub-circuits. In one example, if the source of transistor a is connected to the source of transistor b, and the drain of transistor a is connected to the drain of transistor b, then the sub-circuit formed by transistors a and b is a parallel sub-circuit.

[0104] It should be noted that the third sub-circuit includes at least two electronic devices or at least two circuit structures, and a series connection relationship may exist in the third sub-circuit.

[0105] In one example, structure A and structure B in the first circuit are connected in parallel, and the sub-circuit formed by structure A and structure B is the third sub-circuit; structure A includes multiple electronic devices a, and some of the multiple electronic devices a are connected in series; structure B includes multiple electronic devices b, and the multiple electronic devices b are mixed in series and parallel.

[0106] In one example, an electronic device a and another electronic device b in the first circuit are connected in parallel, and the sub-circuit formed by the electronic device a and the electronic device b is the third sub-circuit.

[0107] After determining the plurality of third sub-circuits, the connection relationship between the plurality of third sub-circuits can be determined. If the plurality of third sub-circuits are connected in parallel, the plurality of third sub-circuits can be combined into a fourth sub-circuit. This can further simplify the topology of the first circuit and thereby improve the efficiency of circuit rearrangement.

[0108] In some embodiments, after obtaining multiple sub-circuits, the multiple sub-circuits can be merged, that is, multiple series sub-circuits are merged into one series sub-circuit, and / or multiple parallel sub-circuits are merged into one parallel sub-circuit. The merging in the embodiments of the present application can be understood as a logical merging rather than a structural merging. That is, multiple series sub-circuits are identified as one series sub-circuit, and multiple parallel sub-circuits are identified as one parallel sub-circuit.

[0109] When merging multiple parallel sub-circuits, if the multiple parallel sub-circuits have: transistor sources connected to sources and transistor drains connected to drains, then the multiple parallel sub-circuits can be merged into one parallel sub-circuit.

[0110] When merging multiple series sub-circuits, if the multiple series sub-circuits are all connected in such a way that the source and drain of the transistors are connected, and only two circuit structures are connected at the intersection of the source and drain, then the multiple series sub-circuits can be merged into one series sub-circuit.

[0111] In step 304 , multiple sub-circuits of the second circuit are traversed to determine multiple first sub-circuits.

[0112] In some embodiments, after merging the parallel subcircuits in the first circuit, a second circuit with a simpler circuit structure is obtained, and multiple subcircuits (including series subcircuits and parallel subcircuits) in the second circuit are traversed to screen out multiple first subcircuits.

[0113] In some embodiments, traversing multiple sub-circuits of the second circuit to determine multiple first sub-circuits includes: starting from the first transistor of the second circuit, determining at least one second transistor connected in series with the first transistor; determining the sub-circuit consisting of the first transistor and the at least one second transistor as the first sub-circuit; determining the third transistor of the second circuit as the first transistor, and returning to the step of starting from the first transistor of the second circuit and determining at least one second transistor connected in series with the first transistor, until traversing the transistors of the second circuit to determine multiple first sub-circuits.

[0114] In the embodiment of the present application, each transistor in the second circuit is sequentially traversed, each transistor is regarded as a first transistor, and based on the hardware description, at least one second transistor connected in series with the first transistor is determined, and the subcircuit formed by the first transistor and the at least one second transistor is determined as the first subcircuit. Then, the traversal continues to the next transistor.

[0115] In the process of determining at least one second transistor connected in series with the next first transistor, transistors that have been traversed previously may be excluded, thereby reducing redundant traversal and avoiding repeated determination.

[0116] In step 305 , a target intersection point of each sub-circuit in the plurality of first sub-circuits is determined, where the target intersection point is a source and a drain of the circuit structure.

[0117] The optional implementation of step 305 in this embodiment can refer to the optional implementation of step 203 in Figure 2 and other related parts in the embodiment involved in Figure 2, which will not be repeated here.

[0118] In step 306 , the circuit structures of the plurality of first sub-circuits are rearranged based on the target intersection point to obtain a plurality of second sub-circuits.

[0119] The optional implementation of step 306 in this embodiment can refer to the optional implementation of step 204 in Figure 2 and other related parts in the embodiment involved in Figure 2, which will not be repeated here.

[0120] In step 307 , multiple second sub-circuits are traversed to obtain multiple candidate circuit topologies, each of which includes at least one second sub-circuit.

[0121] The optional implementation of step 307 in this embodiment can refer to the optional implementation of step 103 in Figure 1 and other related parts in the embodiment involved in Figure 1, and will not be repeated here.

[0122] In step 308, an optimal topology of the first circuit is determined from multiple candidate circuit topologies. The optimal topology is a circuit topology with the lowest layout cost among the multiple candidate circuit topologies. The layout cost is determined based on at least the number of diffusion gaps.

[0123] The optional implementation of step 308 in this embodiment can refer to the optional implementation of step 104 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0124] FIG4 is a fourth flow chart of a circuit rearrangement method according to an exemplary embodiment. As shown in FIG4 , step 204 includes steps 404 to 405:

[0125] In step 401, a hardware description of a first circuit is obtained, where the hardware description is used to represent components in the first circuit and logical relationships between components.

[0126] The optional implementation of step 401 in this embodiment can refer to the optional implementation of step S101 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0127] In step 402 , a plurality of first sub-circuits are determined in a first circuit based on a hardware description.

[0128] The optional implementation of step 402 in this embodiment can refer to the optional implementation of step 302 in Figure 3 and other related parts in the embodiment involved in Figure 3, which will not be repeated here.

[0129] In step 403 , a target intersection point of each sub-circuit in the plurality of first sub-circuits is determined, where the target intersection point is a source and a drain of the circuit structure.

[0130] The optional implementation of step S403 in this embodiment can refer to the optional implementation of step S203 in Figure 2 and other related parts in the embodiment involved in Figure 2, which will not be repeated here.

[0131] After step 403 , for the i-th first sub-circuit among the multiple first sub-circuits, where i is a positive integer, steps 404 and 405 are executed in a loop in sequence until all the first sub-circuits are traversed.

[0132] In step 404 , the first circuit structure and the second circuit structure connected at the target intersection in the i-th first sub-circuit are exchanged to obtain a second sub-circuit corresponding to the i-th first sub-circuit.

[0133] In some embodiments, the first circuit structure and the second circuit structure connected by the target intersection may include one electronic device or multiple electronic devices. When the first circuit structure includes multiple electronic devices or the second circuit structure includes multiple electronic devices, a parallel connection relationship may exist within the first circuit structure and the second circuit structure.

[0134] In some embodiments, swapping the first circuit structure and the second circuit structure connected at the target intersection is equivalent to swapping the position of the first circuit structure with the position of the second circuit structure in the circuit topology. In this case, the connection relationship between the first circuit structure and other circuit structures also changes, and the connection relationship between the second circuit structure and other circuit structures also changes.

[0135] That is, by exchanging the positions of the two circuit structures in the series sub-circuit, the circuit structure of the first circuit can be effectively changed, thereby affecting the quality of the corresponding circuit layout.

[0136] In step 405 , i is assigned a value of i+1 until a plurality of second sub-circuits corresponding to the plurality of first sub-circuits are obtained.

[0137] In some embodiments, each first subcircuit is traversed in sequence by assigning i to i+1, and step 404 is performed until all first subcircuits are traversed, thereby obtaining all second subcircuits corresponding to all first subcircuits.

[0138] In step 406 , multiple second sub-circuits are traversed to obtain multiple candidate circuit topologies, each of which includes at least one second sub-circuit.

[0139] The optional implementation of step 406 in this embodiment can refer to the optional implementation of step 103 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0140] In step 407, an optimal topology of the first circuit is determined from multiple candidate circuit topologies. The optimal topology is a circuit topology with the lowest layout cost among the multiple candidate circuit topologies. The layout cost is determined based on at least the number of diffusion gaps.

[0141] The optional implementation of step 407 in this embodiment can refer to the optional implementation of step 104 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0142] FIG5 is a fifth flow chart of a circuit rearrangement method according to an exemplary embodiment. As shown in FIG5 , step 205 includes steps 503 to 505:

[0143] In step 501, a hardware description of a first circuit is obtained, where the hardware description is used to represent components in the first circuit and the logical relationships between the components.

[0144] The optional implementation of step 501 in this embodiment can refer to the optional implementation of step 101 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0145] In step 502, based on the hardware description, the circuit structures of the plurality of first sub-circuits in the first circuit are rearranged to obtain a plurality of second sub-circuits; the plurality of first sub-circuits and the plurality of second sub-circuits are a plurality of sub-circuits connected in series.

[0146] The optional implementation of step 502 in this embodiment can refer to the optional implementation of step 102 in Figure 1, steps 202 to 204 in Figure 2, other related parts in the embodiment involved in Figure 1 and other related parts in the embodiment involved in Figure 2, and will not be repeated here.

[0147] In step 503 , m second sub-circuits are selected from a plurality of second sub-circuits, where m is a positive integer.

[0148] In some embodiments, when obtaining candidate circuit topologies corresponding to the first circuit, the number m of sub-circuits whose circuit structures need to be changed can be first determined, and then m second sub-circuits can be selected from the plurality of second sub-circuits. That is, the circuit structures of the m sub-circuits in the first circuit are changed to the corresponding second sub-circuits, while the circuit structures of the remaining sub-circuits remain unchanged.

[0149] In step 504, the m second subcircuits are combined with the fifth subcircuit to obtain a candidate circuit topology corresponding to the m second subcircuits; the fifth subcircuit is a subcircuit in the first circuit excluding the first subcircuits corresponding to the m second subcircuits.

[0150] In some embodiments, after m second sub-circuits are selected from multiple second sub-circuits, a sub-circuit other than the first sub-circuits corresponding to the m second sub-circuits is determined in the first circuit, i.e., a fifth sub-circuit. The circuit structure of the fifth sub-circuit remains unchanged. The m second sub-circuits are combined with the fifth sub-circuit to obtain a candidate circuit topology structure corresponding to the m second sub-circuits.

[0151] In other words, the process of obtaining a candidate circuit topology can be understood as dividing all subcircuits of the first circuit into two parts: a circuit structure rearrangement part (i.e., the second subcircuit) and a circuit structure unchanged part (i.e., the fifth subcircuit). Any one or more subcircuits in the first circuit can be used as the circuit structure rearrangement part to change their own circuit structure to obtain a candidate circuit structure. In some examples, the circuit structure unchanged part may not exist.

[0152] In step 505 , m is assigned a value of m+1 until a plurality of candidate circuit topologies are obtained.

[0153] In some embodiments, the number m of sub-circuits requiring circuit structure changes may be increased sequentially until the structures of all sub-circuits in the first circuit are changed, ie, multiple candidate circuit topologies are obtained.

[0154] In step 506, an optimal topology of the first circuit is determined from multiple candidate circuit topologies. The optimal topology is a circuit topology with the lowest layout cost among the multiple candidate circuit topologies. The layout cost is determined based on at least the number of diffusion gaps.

[0155] The optional implementation of step 506 in this embodiment can refer to the optional implementation of step 104 in Figure 1 and other related parts in the embodiment involved in Figure 1, which will not be repeated here.

[0156] FIG6A is a sixth flowchart of a circuit rearrangement method according to an exemplary embodiment, including steps 6101 to 6103 .

[0157] In step 6101, the target intersection is identified.

[0158] In some embodiments, a target intersection point (ie, a swappable node in a circuit rearrangement algorithm) that needs to be fully permuted is searched for in the series subcircuits of the first circuit.

[0159] In step 6102, the circuit topology is traversed.

[0160] In some embodiments, after the identification is completed, different circuit topologies generated after each exchange of the target intersection are traversed.

[0161] In step 6103, the optimal circuit topology is output.

[0162] In some embodiments, based on various factors affecting the quality of the circuit layout, a layout cost equation that quantifies the quality of the circuit layout is weighted and defined, the layout cost values ​​of different circuit topologies are calculated, and the circuit topology corresponding to the minimum layout cost value is selected as the optimal circuit topology.

[0163] In some embodiments, the pseudo code of the circuit rearrangement algorithm is as follows:

[0164] Algoritym 1 circuit rearrangement algorithm

[0165] FIG6B shows a method for identifying a series sub-circuit according to an exemplary embodiment, including steps 6201 to 6204 .

[0166] In step 6201, the transistor circuit is split based on the source and drain.

[0167] In step 6202, transistors / sub-circuits with consistent source and drain are connected in parallel.

[0168] In step 6203, the transistor / sub-circuit structure with the source and drain connected is identified as a series sub-circuit.

[0169] In step 6204, it is determined whether all transistors have been identified.

[0170] If all transistors have been identified, the identification of the series sub-circuit is completed. If all transistors have not been identified, step 6202 is executed.

[0171] FIG6C shows a method for determining parallel sub-circuits and series sub-circuits according to an exemplary embodiment, including steps 6301 to 6303 .

[0172] In step 6301, all parallel circuit structures (with equal terminals) are combined into a parallel sub-circuit based on series-parallel transistors.

[0173] In step 6302, all series-connected circuit structures are added to a new series sub-circuit.

[0174] In step 6303, all circuit structures are added.

[0175] If all circuit structures are added, all series sub-circuits can be obtained. If all circuit structures are not added, step 6301 is executed.

[0176] Figure 7A is the circuit topology before executing the circuit rearrangement method, Figure 7B is the circuit layout corresponding to the circuit topology before executing the circuit rearrangement method, Figure 7C is the optimal circuit topology obtained after executing the circuit rearrangement method, and Figure 7D is the circuit layout corresponding to the optimal circuit topology.

[0177] The circuit shown in Figure 7A is a five-input AND-OR gate circuit. In its corresponding circuit layout, Figure 7B, there is a diffusion gap 703 in each of the pull-up network 701 and the pull-down network 702. The overall width of the layout includes the width of the diffusion gap. The original circuit is rearranged, and the two parts of the series subcircuit in the pull-up network are rearranged to obtain the optimal circuit topology, as shown in Figure 7C. At this time, the number of diffusion gaps in the pull-up network 701 and the pull-down network 702 in the circuit layout corresponding to the optimal circuit topology is shown as 0, as shown in Figure 7D. Comparing the two layouts, it can be seen that the circuit rearrangement reduces the diffusion gaps in the original layout, thereby effectively reducing the layout width.

[0178] FIG8 shows a circuit rearrangement device according to an exemplary embodiment. As shown in FIG8 , the device includes:

[0179] An acquisition module 801 is configured to obtain a hardware description of a first circuit, where the hardware description is used to represent components in the first circuit and logical relationships between components.

[0180] a rearrangement module 802 configured to rearrange the circuit structures of the plurality of first sub-circuits in the first circuit based on the hardware description to obtain a plurality of second sub-circuits; the plurality of first sub-circuits and the plurality of second sub-circuits being a plurality of sub-circuits connected in series;

[0181] a traversal module 803 configured to traverse the plurality of second subcircuits to obtain a plurality of candidate circuit topologies, each candidate circuit topology in the plurality of candidate circuit topologies including at least one second subcircuit;

[0182] The determination module 804 is configured to determine an optimal topology of the first circuit from multiple candidate circuit topologies, where the optimal topology is a circuit topology with the smallest layout cost among the multiple candidate circuit topologies, and the layout cost is determined based on at least the number of diffusion gaps.

[0183] In some embodiments, the rearrangement module 802 is further configured to: determine a plurality of first subcircuits in the first circuit based on the hardware description; determine a target intersection of each of the plurality of first subcircuits, where the target intersection is the source and drain of the circuit structure; and rearrange the circuit structures of the plurality of first subcircuits based on the target intersection to obtain a plurality of second subcircuits.

[0184] In some embodiments, the rearrangement module 802 is further configured to: for the i-th first subcircuit among multiple first subcircuits, where i is a positive integer, sequentially perform the following steps: swap the first circuit structure and the second circuit structure connected at the target intersection in the i-th first subcircuit to obtain the second subcircuit corresponding to the i-th first subcircuit; assign i to i+1, and return to the step of swapping the first circuit structure and the second circuit structure connected at the target intersection in the i-th first subcircuit, until multiple second subcircuits corresponding to the multiple first subcircuits are obtained.

[0185] In some embodiments, the rearrangement module 802 is further configured to: determine multiple sub-circuits of the first circuit based on the hardware description; traverse the multiple sub-circuits of the first circuit to determine multiple third sub-circuits, and merge the multiple third sub-circuits into a fourth sub-circuit to form a second circuit, wherein the multiple third sub-circuits are multiple sub-circuits connected in parallel; traverse the multiple sub-circuits of the second circuit to determine multiple first sub-circuits.

[0186] In some embodiments, the rearrangement module 802 is further configured to: starting from the first transistor of the second circuit, determine at least one second transistor connected in series with the first transistor; determine the subcircuit consisting of the first transistor and the at least one second transistor as the first subcircuit; determine the third transistor of the second circuit as the first transistor, and return to the step of starting from the first transistor of the second circuit and determining at least one second transistor connected in series with the first transistor, until traversing the transistors of the second circuit to determine multiple first subcircuits.

[0187] In some embodiments, the traversal module 803 is further configured to: select m second subcircuits from multiple second subcircuits, where m is a positive integer; combine the m second subcircuits with the fifth subcircuit to obtain a candidate circuit topology structure corresponding to the m second subcircuits; the fifth subcircuit is a subcircuit in the first circuit other than the first subcircuit corresponding to the m second subcircuits; assign m to m+1, and return to the step of selecting m second subcircuits from multiple second subcircuits until multiple candidate circuit topologies are obtained.

[0188] Regarding the circuit rearrangement device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0189] As shown in FIG9 , an embodiment of the present application further provides an electronic device 900, including:

[0190] Memory 904 for storing processor-executable instructions;

[0191] Processor 920, connected to memory 904;

[0192] Among them, the processor 920 is configured to execute the zoom processing method provided by any of the aforementioned technical solutions.

[0193] A block diagram of an electronic device 900 according to an exemplary embodiment is shown. For example, the electronic device 900 may be a smart phone, a tablet computer, a notebook computer, a portable learning machine, etc.

[0194] 9 , electronic device 900 may include one or more of the following components: a processing component 902 , a memory 904 , a power component 906 , a multimedia component 909 , an audio component 910 , an input / output (I / O) interface 912 , a sensor component 914 , and a communication component 918 .

[0195] The processing component 902 generally controls the overall operation of the electronic device 900, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 902 may include one or more processors 920 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 902 may include one or more modules to facilitate interaction between the processing component 902 and other components. For example, the processing component 902 may include a multimedia module to facilitate interaction between the multimedia component 908 and the processing component 902.

[0196] The memory 904 is configured to store various types of data to support operations on the electronic device 900. Examples of such data include instructions for any application or method operating on the electronic device 900, contact data, phone book data, messages, pictures, videos, etc. The memory 904 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0197] The power supply component 906 provides power to the various components of the electronic device 900. The power supply component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 900.

[0198] The multimedia component 908 includes a screen that provides an output interface between the electronic device 900 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 908 includes a front camera and / or a rear camera. When the electronic device 900 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0199] The audio component 910 is configured to output and / or input audio signals. For example, the audio component 910 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 900 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 904 or transmitted via the communication component 918. In some embodiments, the audio component 910 also includes a speaker for outputting audio signals.

[0200] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0201] The sensor assembly 914 includes one or more sensors for providing various aspects of status assessment for the electronic device 900. For example, the sensor assembly 914 can detect the open / closed state of the electronic device 900, the relative positioning of components, such as the display and keypad of the electronic device 900. The sensor assembly 914 can also detect changes in the position of the electronic device 900 or a component of the electronic device 900, the presence or absence of user contact with the electronic device 900, the orientation or acceleration / deceleration of the electronic device 900, and temperature changes of the electronic device 900. The sensor assembly 914 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 914 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 914 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0202] The communication component 918 is configured to facilitate wired or wireless communication between the electronic device 900 and other devices. The electronic device 900 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 918 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 918 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0203] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described methods.

[0204] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions, and the instructions can be executed by the processor 920 of the electronic device 900 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data writing device, etc.

[0205] An embodiment of the present application provides a non-temporary computer-readable storage medium. When the instructions in the storage medium are executed by a processor of a computer, the computer is enabled to perform the zoom processing method of one or more of the aforementioned technical solutions.

[0206] The present invention provides a computer program product comprising a computer program or executable instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer program or executable instructions from the computer-readable storage medium and executes the computer program or executable instructions, causing the computer device to perform any of the circuit rearrangement methods described above.

[0207] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A circuit rearrangement method, characterized in that: include: Obtaining a hardware description of a first circuit, wherein the hardware description is used to represent components in the first circuit and logical relationships between components; Based on the hardware description, rearrange the circuit structures of the plurality of first sub-circuits in the first circuit to obtain a plurality of second sub-circuits; the plurality of first sub-circuits and the plurality of second sub-circuits are a plurality of sub-circuits connected in series; Traversing the plurality of second sub-circuits to obtain a plurality of candidate circuit topologies, each candidate circuit topology in the plurality of candidate circuit topologies including at least one second sub-circuit; An optimal topology of the first circuit is determined from the multiple candidate circuit topologies, where the optimal topology is a circuit topology with the smallest layout cost among the multiple candidate circuit topologies, and the layout cost is determined based on at least the number of diffusion gaps.

2. The method according to claim 1, characterized in that The method of rearranging the circuit structures of the plurality of first sub-circuits in the first circuit based on the hardware description to obtain the plurality of second sub-circuits includes: Based on the hardware description, determining a plurality of first sub-circuits in the first circuit; Determining a target intersection point of each sub-circuit in the plurality of first sub-circuits, the target intersection point being a source and a drain of the circuit structure; Based on the target intersection, the circuit structures of the plurality of first sub-circuits are rearranged to obtain a plurality of second sub-circuits.

3. The method according to claim 2, characterized in that The step of rearranging the circuit structures of the plurality of first sub-circuits based on the target intersection to obtain a plurality of second sub-circuits includes: For the i-th first sub-circuit among the multiple first sub-circuits, where i is a positive integer, the following steps are performed in sequence: swapping the first circuit structure and the second circuit structure connected at the target intersection in the i-th first subcircuit to obtain a second subcircuit corresponding to the i-th first subcircuit; Assign i a value of i+1, and return to the step of exchanging the first circuit structure and the second circuit structure connected by the target intersection in the i-th first sub-circuit, until a plurality of second sub-circuits corresponding to the plurality of first sub-circuits are obtained.

4. The method according to claim 2, characterized in that The determining of a plurality of first sub-circuits in the first circuit based on the hardware description includes: determining a plurality of sub-circuits of the first circuit based on the hardware description; Traversing multiple sub-circuits of the first circuit, determining multiple third sub-circuits, and merging the multiple third sub-circuits into a fourth sub-circuit to form a second circuit, wherein the multiple third sub-circuits and the multiple fourth sub-circuits are multiple sub-circuits connected in parallel; The plurality of sub-circuits of the second circuit are traversed to determine the plurality of first sub-circuits.

5. The method according to claim 4, characterized in that: The traversing the plurality of sub-circuits of the second circuit to determine the plurality of first sub-circuits includes: Starting from a first transistor of the second circuit, determining at least one second transistor connected in series with the first transistor; determining a subcircuit consisting of the first transistor and the at least one second transistor as the first subcircuit; The third transistor of the second circuit is determined as the first transistor, and the step of starting from the first transistor of the second circuit and determining at least one second transistor connected in series with the first transistor is returned to, until the transistors of the second circuit are traversed to determine the multiple first sub-circuits.

6. The method according to claim 1, characterized in that The traversing the plurality of second sub-circuits to obtain a plurality of candidate circuit topology structures includes: Selecting m second sub-circuits from the plurality of second sub-circuits, where m is a positive integer; combining the m second subcircuits with a fifth subcircuit to obtain a candidate circuit topology corresponding to the m second subcircuits; the fifth subcircuit being a subcircuit in the first circuit excluding the first subcircuits corresponding to the m second subcircuits; Assign m a value of m+1, and return to the step of selecting m second sub-circuits from the plurality of second sub-circuits until a plurality of candidate circuit topologies are obtained.

7. The method according to any one of claims 1 to 6, characterized in that The layout cost is further determined based on at least one of the following: The number of gate mismatches; Layout width; Maximum winding ratio; Sum of squares of winding density; Total winding length.

8. A circuit rearrangement device, characterized in that: include: an acquisition module configured to obtain a hardware description of the first circuit, wherein the hardware description is used to represent components in the first circuit and logical relationships between components; a rearrangement module configured to rearrange the circuit structures of the plurality of first sub-circuits in the first circuit based on the hardware description to obtain a plurality of second sub-circuits; the plurality of first sub-circuits and the plurality of second sub-circuits being a plurality of sub-circuits connected in series; a traversal module configured to traverse the plurality of second sub-circuits to obtain a plurality of candidate circuit topologies, each candidate circuit topology in the plurality of candidate circuit topologies including at least one of the second sub-circuits; A determination module is configured to determine an optimal topology of the first circuit from the multiple candidate circuit topologies, wherein the optimal topology is a circuit topology with the smallest layout cost among the multiple candidate circuit topologies, and the layout cost is determined based on at least the number of diffusion gaps.

9. An electronic device, characterized in that: include: processor; a memory configured to store processor-executable instructions; The processor is configured to execute the circuit rearrangement method according to any one of claims 1 to 7 when calling the executable instructions in the memory.

10. A non-transitory computer-readable storage medium, characterized in that When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the circuit rearrangement method according to any one of claims 1 to 7.

11. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the circuit rearrangement method according to any one of claims 1 to 7 is implemented.

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