Display device

Abstract

A first TFT (9a) is provided with a first gate electrode (16a) that, on a first semiconductor layer (14a), overlaps a first channel region (14ac) of the first semiconductor layer (14a) via a first gate insulating film (15a). A second TFT (9b) is provided with a second gate electrode (16b) that, on a second semiconductor layer (14b), overlaps a second channel region (12bc) of the second semiconductor layer (14b) via a second gate insulating film (15b). The first gate insulating film (15a) is provided larger in plan view than the second gate insulating film (15b). The channel length of the first channel region (14ac) is longer than that of the second channel region (12bc).

Description

display device

[0001] The present invention relates to a display device.

[0002] In recent years, self-emitting organic electroluminescence (EL) display devices using organic electroluminescence (EL) elements have been attracting attention as a display device that can replace liquid crystal display devices. In these organic EL display devices, a plurality of thin film transistors (TFTs) are provided for each subpixel, which is the smallest unit of an image. Well-known examples of semiconductor layers that constitute TFTs include a semiconductor layer made of polysilicon, which has high mobility, and a semiconductor layer made of an oxide semiconductor such as In—Ga—Zn—O, which has low leakage current.

[0003] For example, Patent Document 1 discloses a display device including a drive transistor in which a first gate electrode of a dual gate structure is provided on the upper side of a semiconductor layer made of an oxide semiconductor, and a second gate electrode is provided on the lower side of the semiconductor layer.

[0004] International Publication No. 2021 / 199112

[0005] In an organic EL display device in which each subpixel is provided with a plurality of TFTs using an oxide semiconductor, for example, a drive TFT for controlling the current flowing through an organic EL element must precisely control the luminance of the organic EL element by adjusting the current value. Therefore, a small change in current value relative to a change in gate voltage in the Vg (gate voltage)-Id (drain current) characteristic, i.e., a large subthreshold coefficient (S value), is required. Furthermore, selection TFTs other than the drive TFT must switch quickly, so a small S value is required. Generally, in a TFT, reducing the gate electrode width (channel length) reduces the S value, while increasing the gate electrode width (channel length) increases the S value. Therefore, for example, increasing the gate electrode width to increase the S value increases the size of the TFT, which in turn narrows the space between the wirings around the TFT, making wiring patterning difficult. Given this, organic EL display devices, which have recently been required to achieve increasingly higher resolution, are finding it difficult to increase the S value by adjusting the gate electrode width, leaving room for improvement.

[0006] The present invention has been made in view of the above points, and an object of the present invention is to optimize the characteristics of each TFT in a display device in which a plurality of TFTs using an oxide semiconductor are provided in a sub-pixel.

[0007] In order to achieve the above object, a display device according to the present invention includes a base substrate and a thin film transistor layer provided on the base substrate, wherein the thin film transistor layer includes a first thin film transistor having a first semiconductor layer formed of an oxide semiconductor and a second thin film transistor having a second semiconductor layer formed of an oxide semiconductor, the first thin film transistor being provided for each sub-pixel constituting a display area, and the first thin film transistor includes the first semiconductor layer having a first conductor region and a second conductor region defined to be spaced apart from each other and a first channel region defined between the first conductor region and the second conductor region, and a gate insulating film disposed on the first semiconductor layer. a first gate electrode provided so as to overlap the first channel region, and the second thin film transistor includes the second semiconductor layer in which a third conductor region and a fourth conductor region are defined so as to be spaced apart from each other and a second channel region is defined between the third conductor region and the fourth conductor region, and a second gate electrode provided on the second semiconductor layer via a second gate insulating film so as to overlap the second channel region, wherein the first gate insulating film is larger than the second gate insulating film in a planar view, and the channel length of the first channel region is larger than the channel length of the second channel region.

[0008] According to the present invention, in a display device in which a plurality of TFTs using an oxide semiconductor are provided in a sub-pixel, it is possible to optimize the characteristics of each TFT.

[0009] FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention. FIG. 2 is a plan view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 4 is a plan view of a first TFT constituting the organic EL display device according to the first embodiment of the present invention. FIG. 5 is a plan view of a second TFT constituting the organic EL display device according to the first embodiment of the present invention. FIG. 6 is an equivalent circuit diagram of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view showing a part of a manufacturing process of the organic EL display device according to the first embodiment of the present invention. FIG. 9 is a cross-sectional view showing a part of a manufacturing process of the organic EL display device according to the first embodiment of the present invention, subsequent to FIG. 8. FIG. 10 is a cross-sectional view of a display region of an organic EL display device according to a second embodiment of the present invention. FIG. 11 is a plan view of a first TFT constituting the organic EL display device according to the second embodiment of the present invention. FIG. 12 is a plan view of a second TFT constituting the organic EL display device according to the second embodiment of the present invention. FIG. 13 is a cross-sectional view showing a part of a manufacturing process of the organic EL display device according to the second embodiment of the present invention. FIG. 14 is a cross-sectional view showing a part of the manufacturing process of an organic EL display device according to a second embodiment of the present invention, following FIG. 13 . FIG. 15 is a cross-sectional view of a display region of an organic EL display device according to a third embodiment of the present invention. FIG. 16 is a plan view of a first TFT constituting an organic EL display device according to the third embodiment of the present invention. FIG. 17 is a plan view of a second TFT constituting an organic EL display device according to the third embodiment of the present invention. FIG. 18 is a cross-sectional view showing a part of the manufacturing process of an organic EL display device according to the third embodiment of the present invention. FIG. 19 is a cross-sectional view showing a part of the manufacturing process of an organic EL display device according to the third embodiment of the present invention, following FIG. 18 . FIG. 20 is a cross-sectional view of a display region of an organic EL display device according to a fourth embodiment of the present invention. FIG. 21 is a plan view of a first TFT constituting an organic EL display device according to the fourth embodiment of the present invention. FIG. 22 is a plan view of a second TFT constituting an organic EL display device according to the fourth embodiment of the present invention.Fig. 23 is a cross-sectional view of a display region of an organic EL display device according to a fifth embodiment of the present invention. Fig. 24 is a plan view of a first TFT constituting an organic EL display device according to the fifth embodiment of the present invention. Fig. 25 is a plan view of a second TFT constituting an organic EL display device according to the fifth embodiment of the present invention. Fig. 26 is a cross-sectional view showing a part of a manufacturing process of an organic EL display device according to the fifth embodiment of the present invention. Fig. 27 is a cross-sectional view showing a part of a manufacturing process of an organic EL display device according to the fifth embodiment of the present invention, subsequent to Fig. 26.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0011] First Embodiment FIGS. 1 to 9 illustrate a first embodiment of a display device according to the present invention. In the following embodiments, an organic EL display device including an organic EL element layer is exemplified as a display device including a light-emitting element layer. FIG. 1 is a plan view showing a schematic configuration of an organic EL display device 50a according to this embodiment. FIGS. 2 and 3 are a plan view and a cross-sectional view of a display region D of the organic EL display device 50a. FIGS. 4 and 5 are plan views of a first TFT 9a and a second TFT 9b constituting the organic EL display device 50a. FIG. 6 is an equivalent circuit diagram of a TFT layer 20a constituting the organic EL display device 50a. FIG. 7 is a cross-sectional view of an organic EL layer 33 constituting the organic EL display device 50a. FIG. 8 is a cross-sectional view showing a part of a manufacturing process for the organic EL display device 50a. FIG. 9 is a cross-sectional view showing a part of a manufacturing process for the organic EL display device 50a subsequent to FIG. 8.

[0012] 1, the organic EL display device 50a includes, for example, a rectangular display area D for displaying images, and a frame area F provided in a frame shape around the display area D. Note that, although the present embodiment illustrates a rectangular display area D, this rectangular shape also includes, for example, a substantially rectangular shape with arc-shaped sides, arc-shaped corners, or a shape with a notch in one of the sides.

[0013] In the display region D, a plurality of sub-pixels P are arranged in a matrix as shown in Fig. 2. In the display region D, for example, a sub-pixel P having a red light-emitting region Er for displaying red, a sub-pixel P having a green light-emitting region Eg for displaying green, and a sub-pixel P having a blue light-emitting region Eb for displaying blue are provided adjacent to each other as shown in Fig. 2. In the display region D, one pixel is configured by, for example, three adjacent sub-pixels P having the red light-emitting region Er, the green light-emitting region Eg, and the blue light-emitting region Eb.

[0014] 1, a terminal portion T is provided to extend in one direction (the Y direction in the figure) at the right end of the frame region F. Furthermore, as shown in Fig. 1, between the display region D and the terminal portion T, that is, in the frame region F, on the display region D side of the terminal portion T, a folding portion B is provided to extend in one direction (the Y direction in the figure) that can be folded, for example, 180° (in a U-shape) with the Y direction in the figure as the folding axis.

[0015] As shown in FIG. 3, the organic EL display device 50a includes a resin substrate 10 provided as a base substrate, a TFT layer 20a provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 20a, and a sealing film 45 provided on the organic EL element layer 40.

[0016] The resin substrate 10 is made of, for example, polyimide resin.

[0017] As shown in FIG. 3 , the TFT layer 20a includes a base coat film 12 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 12, and a planarization film 19 provided on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. As shown in FIG. 2 , the TFT layer 20a includes a plurality of gate lines 16g extending parallel to each other in the X direction in the drawing. Also, as shown in FIG. 2 , the TFT layer 20a includes a plurality of source lines 18f extending parallel to each other in a direction intersecting (orthogonal to) the plurality of gate lines 16g, i.e., in the Y direction in the drawing. Also, as shown in FIG. 2 , the TFT layer 20a includes a plurality of power supply lines 18g extending parallel to each other in the Y direction in the drawing. Each power supply line 18g is adjacent to each of the source lines 18f, as shown in FIG. 2 . 6, the TFT layer 20a includes a first TFT 9a, a second TFT 9b, and a capacitor 9c in each sub-pixel P. In the TFT layer 20a, as shown in FIG. 3, a base coat film 12, a semiconductor film that will become a first semiconductor layer 14a and a second semiconductor layer 14b (to be described later) and the like, a first gate insulating film 15a and a second gate insulating film 15b, a first metal film that will become a gate line 16g and the like, an interlayer insulating film 17, a second metal film that will become a source line 18f and a power line 18g and the like, and a planarization film 19 are laminated in this order on a resin substrate 10.

[0018] The base coat film 12, the first gate insulating film 15a, the second gate insulating film 15b, and the interlayer insulating film 17, which will be described later, are each made of an inorganic insulating film, such as a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or the like, which is a single layer or a multilayer film. The interlayer insulating film 17 is made of, for example, a silicon nitride film, a single layer of silicon nitride film, or a multilayer film of silicon nitride film (upper) / silicon oxide film (lower), and includes a silicon nitride film.

[0019] The first TFT 9a is provided as a drive TFT, and as shown in Fig. 6, is electrically connected to the corresponding second TFT 9b and power supply line 18g in each subpixel P. Here, as shown in Fig. 3, the first TFT 9a includes a first semiconductor layer 14a provided on the base coat film 12, a first gate electrode 16a provided on the first semiconductor layer 14a via a first gate insulating film 15a, and a first source electrode 18a and a first drain electrode 18b provided on the interlayer insulating film 17 so as to be spaced apart from each other.

[0020] The first semiconductor layer 14a is formed of a semiconductor film made of an oxide semiconductor such as an In—Ga—Zn—O system, and includes a first conductor region 14aa and a second conductor region 14ab spaced apart from each other, and a first channel region 14ac defined between the first conductor region 14aa and the second conductor region 14ab, as shown in FIG. Here, the In—Ga—Zn—O system semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not particularly limited. The In—Ga—Zn—O system semiconductor may be amorphous or crystalline. Note that a crystalline In—Ga—Zn—O system semiconductor with a c-axis oriented generally perpendicular to the layer plane is preferred as the crystalline In—Ga—Zn—O system semiconductor. Furthermore, other oxide semiconductors may be included instead of the In—Ga—Zn—O system semiconductor. Other oxide semiconductors include, for example, In—Sn—Zn—O-based semiconductors (e.g., In ２ O ３ -SnO ２In—ZnO; InSnZnO). Here, the In—Sn—Zn—O based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Other oxide semiconductors include In—Al—Zn—O based semiconductors, In—Al—Sn—Zn—O based semiconductors, Zn—O based semiconductors, In—Zn—O based semiconductors, Zn—Ti—O based semiconductors, Cd—Ge—O based semiconductors, Cd—Pb—O based semiconductors, CdO (cadmium oxide), Mg—Zn—O based semiconductors, In—Ga—Sn—O based semiconductors, In—Ga—O based semiconductors, Zr—In—Zn—O based semiconductors, Hf—In—Zn—O based semiconductors, Al—Ga—Zn—O based semiconductors, Ga—Zn—O based semiconductors, In—Ga—Zn—Sn—O based semiconductors, InGaO ３ (ZnO) ５ , magnesium zinc oxide (Mg ｘ Zn １－ｘ O), cadmium zinc oxide (Cd ｘ Zn １－ｘ The Zn—O-based semiconductor may be ZnO in an amorphous state, a polycrystalline state, a microcrystalline state in which the amorphous state and the polycrystalline state are mixed, or a semiconductor in which no impurity element is added, to which one or more impurity elements selected from the group 1 elements, the group 13 elements, the group 14 elements, the group 15 elements, the group 17 elements, etc. are added.

[0021] The first gate electrode 16a is provided so as to overlap the first channel region 14ac of the first semiconductor layer 14a and is configured to control conduction between the first conductor region 14aa and the second conductor region 14ab of the first semiconductor layer 14a. Here, the first gate electrode 16a is formed of the first metal film, similar to the gate line 16g and the like.

[0022] 3, the first source electrode 18a and the second drain electrode 18b are electrically connected to the first conductor region 14aa and the second conductor region 14ab of the first semiconductor layer 14a, respectively, via first contact holes Ha and second contact holes Hb formed in the first gate insulating film 15a and the interlayer insulating film 17. Here, the first source electrode 18a and the second drain electrode 18b are formed of the second metal film, similar to the source line 18f and the power supply line 18g.

[0023] The second TFT 9b is provided as a selection TFT, and is electrically connected to the corresponding gate line 16g and source line 18f in each subpixel P, as shown in Fig. 6. Here, as shown in Fig. 3, the second TFT 9b includes a second semiconductor layer 14b provided on the base coat film 12, a second gate electrode 16b provided on the second semiconductor layer 14b with a second gate insulating film 15b interposed therebetween, and a second source electrode 18c and a second drain electrode 18d provided spaced apart from each other on the interlayer insulating film 17. Note that, as shown in Fig. 3, the interlayer insulating film 17 is provided so as to cover the first gate electrode 16a and the second gate electrode 16b.

[0024] Like the first semiconductor layer 14a, the second semiconductor layer 14b is formed of a semiconductor film made of an oxide semiconductor such as an In-Ga-Zn-O system, and as shown in FIG. 3, includes a third conductor region 14ba and a fourth conductor region 14bb that are defined to be spaced apart from each other, and a second channel region 14bc that is defined between the third conductor region 14ba and the fourth conductor region 14bb.

[0025] The second gate electrode 16b is provided so as to overlap the second channel region 14bc of the second semiconductor layer 14b and is configured to control conduction between the third conductor region 14ba and the fourth conductor region 14bb of the second semiconductor layer 14b. Here, the second gate electrode 16b is formed of the first metal film, similar to the gate line 16g and the like.

[0026] 3, the second source electrode 18c and the second drain electrode 18d are electrically connected to the third conductor region 14ba and the fourth conductor region 14bb of the second semiconductor layer 14b, respectively, via the third contact hole Hc and the fourth contact hole Hd formed in the interlayer insulating film 17. Here, the second source electrode 18c and the second drain electrode 18d are formed of the second metal film, similar to the source line 18f and the power supply line 18g.

[0027] As shown in FIGS. 3, 4, and 5, in the first TFT 9a and the second TFT 9b, the first gate insulating film 15a is larger than the second gate insulating film 15b in plan view, so that the channel length La of the first channel region 14ac is larger than the channel length Lb of the second channel region 14bc. In the first TFT 9a and the second TFT 9b, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the width of the second gate electrode 16b in the channel length direction (horizontal direction in the figure), as shown in FIG. 3. The width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the channel length La of the first channel region 14ac, as shown in FIG. 3. The portions of the first TFT 9a and the second TFT 9b in the cross-sectional view of FIG. 3 correspond to the portions along line A-A in FIG. 4 and the portions along line B-B in FIG. 5.

[0028] 6, the capacitor 9c is electrically connected to the corresponding second TFT 9b and power supply line 18g in each subpixel P. Here, the capacitor 9c includes, for example, a lower conductive layer formed from the first metal film, an upper conductive layer formed from the second metal film, and an interlayer insulating film 17 provided between the lower conductive layer and the upper conductive layer. The upper conductive layer is electrically connected to the power supply line 18g.

[0029] The planarization film 19 has a flat surface in the display region D and is made of an organic resin material such as polyimide resin.

[0030] 3, the organic EL element layer 40 includes a plurality of organic EL elements 35 provided as a plurality of light-emitting elements so as to be arranged in a matrix on the TFT layer 20a, corresponding to a plurality of sub-pixels P. Here, as shown in Fig. 3, each organic EL element 35 includes a first electrode 31 provided on the TFT layer 20a, an organic EL layer 33 provided on the first electrode 31, and a second electrode 34 provided on the organic EL layer 33 so as to be common to the entire display region D.

[0031] As shown in FIG. 3 , the first electrode 31 is electrically connected to the first drain electrode 18 b of the first TFT 9 a of each subpixel P through a contact hole formed in the planarization film 19. The first electrode 31 also has a function of injecting holes (positive holes) into the organic EL layer 33. The first electrode 31 is preferably formed of a material with a large work function to improve the efficiency of hole injection into the organic EL layer 33. Examples of materials that can be used for the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). The material constituting the first electrode 31 is, for example, astatine (At) / astatine oxide (AtO ２The first electrode 31 may be made of an alloy such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The first electrode 31 may be formed by stacking multiple layers of the above materials. Examples of compound materials with high work functions include indium tin oxide (ITO) and indium zinc oxide (IZO). The peripheral edge of the first electrode 31 is covered with an edge cover 32 arranged in a grid pattern over the entire display area D. The edge cover 32 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based spin-on-glass (SOG) material. As shown in FIG. 3 , a portion of the surface of the edge cover 32 protrudes upward and forms an island-shaped pixel photospacer.

[0032] As shown in FIG. 7, the organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are stacked in this order on the first electrode 31.

[0033] The hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 closer to each other, thereby improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0034] The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0035] The light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and where the holes and electrons recombine when a voltage is applied between the first electrode 31 and the second electrode 34. The light-emitting layer 3 is made of a material with high luminous efficiency. Examples of materials that can be used for the light-emitting layer 3 include metal oxinoid compounds (8-hydroxyquinoline metal complexes), naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, trisstyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidin derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, and polysilane.

[0036] The electron transport layer 4 has a function of efficiently transferring electrons to the light-emitting layer 3. Examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds.

[0037] The electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 closer to each other and improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33, and this function can reduce the driving voltage of the organic EL element 35. The electron injection layer 5 is also called a cathode buffer layer. Here, examples of materials constituting the electron injection layer 5 include lithium fluoride (LiF), magnesium fluoride (MgF ２ ), calcium fluoride (CaF ２ ), strontium fluoride (SrF ２ ), barium fluoride (BaF ２ inorganic alkali compounds such as aluminum oxide (Al ２ O ３ ), strontium oxide (SrO), etc.

[0038] As shown in FIG. 3 , the second electrode 34 is provided to cover each organic EL layer 33 and the edge cover 32. The second electrode 34 has a function of injecting electrons into the organic EL layer 33. To improve the efficiency of electron injection into the organic EL layer 33, the second electrode 34 is preferably made of a material with a small work function. Examples of materials that can be used for the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Examples of materials that can be used for the second electrode 34 include magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), and astatine (At) / astatine oxide (AtO).２ The second electrode 34 may be formed of an alloy such as lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). The second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The second electrode 34 may be formed by stacking multiple layers made of the above materials. Examples of materials with a low work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0039] 3 , the sealing film 45 is provided so as to cover the second electrode 34, and includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43 laminated in this order on the second electrode 34, and is configured to protect the organic EL layer 33 of the organic EL element 35 from moisture, oxygen, etc. Here, the first inorganic sealing film 41 and the second inorganic sealing film 43 are made of inorganic insulating films such as silicon nitride films, silicon oxide films, and silicon oxynitride films. In addition, the organic sealing film 42 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin.

[0040] The organic EL display device 50a described above is configured such that, in each subpixel P, a gate signal is input to the second TFT 9b via the gate line 16g to turn on the second TFT 9b, a data signal is written to the first gate electrode 16a and capacitor 9c of the first TFT 9a via the source line 18f, and a current from the power supply line 18g corresponding to the gate voltage of the first TFT 9a is supplied to the organic EL layer 33 of the organic EL element 35, causing the light-emitting layer 3 of the organic EL layer 33 to emit light, thereby displaying an image. In the organic EL display device 50a, even if the second TFT 9b is turned off, the gate voltage of the first TFT 9a is held by the capacitor 9c, so that light emission by the light-emitting layer 3 is maintained until a gate signal for the next frame is input.

[0041] Next, a manufacturing method of the organic EL display device 50a of this embodiment will be described with reference to Figures 8 and 9. The manufacturing method of the organic EL display device 50a of this embodiment includes a TFT layer forming process, an organic EL element layer forming process, and a sealing film forming process. In Figure 9 and Figures 14, 19, and 27 described below, solid arrows in the figures indicate the movement of hydrogen due to hydrogen diffusion, and dashed arrows in the figures indicate the movement of oxygen due to deoxidation.

[0042] <TFT Layer Forming Process> First, for example, a silicon oxide film (about 100 nm thick) is formed on a resin substrate 10 formed on a glass substrate by plasma CVD (Chemical Vapor Deposition) to form a base coat film 12.

[0043] Next, on the surface of the substrate on which the base coat film 12 has been formed, InGaZnO ４ After forming a semiconductor film made of an oxide semiconductor by depositing a film (thickness: about 30 nm) or the like, the semiconductor film is patterned to form the first semiconductor layer 14a, the second semiconductor layer 14b, and the like.

[0044] Thereafter, an inorganic insulating film such as a silicon oxide film (with a thickness of about 100 nm) is formed on the surface of the substrate on which the first semiconductor layer 14a and the like are formed, for example, by plasma CVD, and then the inorganic insulating film is patterned to form the first gate insulating film 15a, the second gate insulating film 15b and the like.

[0045] Furthermore, on the surface of the substrate on which the first gate insulating film 15a etc. has been formed, for example, by sputtering, a first metal film such as a single layer film of molybdenum film (thickness: about 200 nm), a laminated film in which an aluminum film (thickness: about 300 nm) and a titanium film (thickness: about 50 nm) are laminated in that order, or a laminated film in which a titanium film (thickness: about 50 nm), an aluminum film (thickness: about 300 nm), and a titanium film (thickness: about 50 nm) are laminated in that order, and then the first metal film is patterned to form a first gate electrode 16a, a second gate electrode 16b, a gate line 16g, etc., as shown in FIG. 8.

[0046] Next, a silicon oxide film (about 300 nm thick) and a silicon nitride film (about 150 nm thick) are sequentially formed by, for example, plasma CVD on the substrate surface on which the first gate electrode 16a and the like are formed, thereby forming an interlayer insulating film 17 as shown in Fig. 9. At this time, a heat treatment performed when forming the interlayer insulating film 17 converts a part of the first semiconductor layer 14a and a part of the second semiconductor layer 14b into conductors, so that a first conductor region 14aa, a second conductor region 14ab, and a first channel region 14ac are formed in the first semiconductor layer 14a, and a third conductor region 14ba, a fourth conductor region 14bb, and a second channel region 14bc are formed in the second semiconductor layer 14b. Here, in the portion where the first TFT 9a is formed (the right side in FIG. 9 ), the first gate insulating film 15a covers the first semiconductor layer 14a relatively widely, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a, and therefore the region of the first semiconductor layer 14a that is made conductive does not increase, and a reduction in the (effective) channel length La of the first channel region 14ac is suppressed. That is, in the first TFT 9a, the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the portion where the second TFT 9b is formed (the left side in FIG. 9 ), the second gate insulating film 15b covers the second semiconductor layer 14b relatively narrowly, thereby not suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b, and therefore the region of the second semiconductor layer 14b that is made conductive increases, and the (effective) channel length Lb of the second channel region 14bc decreases. That is, in the second TFT 9 b, the channel length Lb of the second channel region 14 bc is smaller than the width in the channel direction of the second gate electrode 16 b. This makes it possible to fabricate the first TFT 9 a and the second TFT 9 b having different characteristics on the same plane, even if the width in the channel length direction of the first gate electrode 16 a and the second gate electrode 16 b is the same.

[0047] Then, on the substrate surface on which the interlayer insulating film 17 is formed, the first gate insulating film 15a and the interlayer insulating film 17 are appropriately patterned to form a first contact hole Ha, a second contact hole Hb, a third contact hole Hc, a fourth contact hole Hd, etc.

[0048] Furthermore, on the substrate surface on which the first contact holes Ha etc. have been formed, a titanium film (thickness: about 50 nm), an aluminum film (thickness: about 400 nm), and a titanium film (thickness: about 100 nm) etc. are sequentially formed by, for example, a sputtering method to form a second metal film, and then the second metal film is patterned to form a first source electrode 18a, a first drain electrode 18b, a second source electrode 18c, a second drain electrode 18d, a source line 18f, a power line 18g, etc.

[0049] Finally, an acrylic photosensitive resin film (about 2 μm thick) is applied to the substrate surface on which the first source electrode 18 a and the like are formed, for example, by spin coating or slit coating, and then the applied film is pre-baked, exposed to light, developed, and post-baked to form a planarization film 19 having contact holes.

[0050] In this manner, the TFT layer 20a can be formed.

[0051] <Organic EL element layer formation process> Using a well-known method, a first electrode 31, an edge cover 32, an organic EL layer 33, and a second electrode 34 are formed on the planarization film 19 of the TFT layer 20a formed in the above-mentioned TFT layer formation process, thereby forming an organic EL element layer 40.

[0052] <Sealing film forming process> First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask on the surface of the substrate on which the organic EL element layer 40 formed in the organic EL element layer forming process is formed, thereby forming a first inorganic sealing film 41.

[0053] Subsequently, an organic resin material such as an acrylic resin is deposited by, for example, an inkjet method on the surface of the substrate on which the first inorganic sealing film 41 has been formed, to form an organic sealing film 42 .

[0054] Then, using a mask, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is deposited by plasma CVD on the substrate surface on which the organic sealing film 42 has been formed, thereby forming a second inorganic sealing film 43, thereby forming a sealing film 45.

[0055] Finally, a protective sheet (not shown) is attached to the surface of the substrate on which the sealing film 45 is formed, and then laser light is irradiated from the glass substrate side of the resin substrate 10 to peel the glass substrate from the underside of the resin substrate 10, and a protective sheet (not shown) is attached to the underside of the resin substrate 10 from which the glass substrate has been peeled.

[0056] In this manner, the organic EL display device 50a of this embodiment can be manufactured.

[0057] As described above, in the organic EL display device 50a of this embodiment, in the first TFT 9a, the first gate insulating film 15a disposed between the first semiconductor layer 14a and the first gate electrode 16a is larger in plan view than the second gate insulating film 15b disposed between the second semiconductor layer 14b and the second gate electrode 16b in the second TFT 9a. As a result, in the first TFT 9a, the first gate insulating film 15a covers the first semiconductor layer 14a relatively widely, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a. On the other hand, in the second TFT 9b, the second gate insulating film 15b covers the second semiconductor layer 14b relatively narrowly, thereby not suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b. Therefore, in the first TFT 9a, the conductive region of the first semiconductor layer 14a does not increase, and the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the second TFT 9b, the conductive region of the second semiconductor layer 14b increases, and the channel length Lb of the second channel region 14bc is smaller than the width of the second gate electrode 16b in the channel direction. Here, because the width of the first gate electrode 16a in the channel length direction is the same as the width of the second gate electrode 16b in the channel length direction, the S value of the first TFT 9a can be relatively increased, and the S value of the second TFT 9b can be relatively decreased. Therefore, the first TFT 9 a and the second TFT 9 b having desired S values ​​different from each other can be formed without making the widths of the first gate electrode 16 a and the second gate electrode 16 b in the channel length direction different from each other. Therefore, in an organic EL display device 50 a in which the first TFT 9 a and the second TFT 9 b using an oxide semiconductor are provided in the sub-pixel P, the characteristics of the first TFT 9 a and the second TFT 9 b can be optimized.

[0058] Second Embodiment FIGS. 10 to 14 show a second embodiment of a display device according to the present invention. FIG. 10 is a cross-sectional view of a display region D of an organic EL display device 50b according to this embodiment. FIGS. 11 and 12 are plan views of the first TFT 9a and the second TFT 9b constituting the organic EL display device 50b, and correspond to FIGS. 4 and 5 of the first embodiment. FIG. 13 is a cross-sectional view showing a part of a manufacturing process for the organic EL display device 50b. FIG. 14 is a cross-sectional view showing a part of a manufacturing process for the organic EL display device 50b subsequent to FIG. 13. In the following embodiments, the same components as those in FIGS. 1 to 9 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0059] In the first embodiment described above, an organic EL display device 50a is exemplified in which the first gate insulating film 15a and the second gate insulating film 15b are provided independently for the first TFT 9a and the second TFT 9b, respectively. However, in the present embodiment, an organic EL display device 50b is exemplified in which the first TFT 9a and the second TFT 9b are integrally provided with a common gate insulating film 15c.

[0060] Similar to the organic EL display device 50a of the first embodiment, the organic EL display device 50b includes, for example, a rectangular display area D for displaying an image and a frame area F provided in a frame shape around the periphery of the display area D. As shown in Fig. 10 , the organic EL display device 50b also includes a resin substrate 10 provided as a base substrate, a TFT layer 20b provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 20b, and a sealing film 45 provided on the organic EL element layer 40.

[0061] 10 , the TFT layer 20b includes a base coat film 12 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 12, and a planarization film 19 provided on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. Here, the TFT layer 20b is provided with a plurality of gate lines 16g, a plurality of source lines 18f, and a plurality of power supply lines 18g, similar to the TFT 20a of the first embodiment. Furthermore, in the TFT layer 20b, each sub-pixel P is provided with a first TFT 9a, a second TFT 9b, and a capacitor 9c, similar to the TFT 20a of the first embodiment. As shown in FIG. 10 , in the TFT layer 20b, a base coat film 12, a semiconductor film that will become the first semiconductor layer 14a, the second semiconductor layer 14b, etc., a common gate insulating film 15c, a first metal film that will become the gate line 16g, etc., an interlayer insulating film 17, a second metal film that will become the source line 18f, the power supply line 18g, etc., and a planarization film 19 are laminated in this order on a resin substrate 10.

[0062] 10, the first TFT 9a includes a first semiconductor layer 14a provided on the base coat film 12, a first gate electrode 16a provided on the first semiconductor layer 14a via a common gate insulating film 15c, and a first source electrode 18a and a first drain electrode 18b provided spaced apart from each other on the interlayer insulating film 17. Note that the first source electrode 18a and the second drain electrode 18b are electrically connected to a first conductor region 14aa and a second conductor region 14ab of the first semiconductor layer 14a via a first contact hole Ha and a second contact hole Hb formed in the common gate insulating film 15c and the interlayer insulating film 17, respectively, as shown in FIG.

[0063] 10, the second TFT 9b includes a second semiconductor layer 14b provided on the base coat film 12, a second gate electrode 16b provided on the second semiconductor layer 14b via a common gate insulating film 15c, and a second source electrode 18c and a second drain electrode 18d provided so as to be spaced apart from each other on the interlayer insulating film 17. The common gate insulating film 15c is provided with a first opening Ma and a second opening Mb so as to expose a part of the third conductor region 14ba and a part of the fourth conductor region 14bb of the second semiconductor layer 14b.

[0064] 10, 11, and 12, the portion of the common gate insulating film 15c disposed in the first TFT 9a is larger than the portion of the common gate insulating film 15c disposed in the second TFT 9b in plan view, so that the channel length La of the first channel region 14ac is larger than the channel length Lb of the second channel region 14bc. Furthermore, in the first TFT 9a and the second TFT 9b, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the width of the second gate electrode 16b in the channel length direction (horizontal direction in the figure), as shown in FIG. 10. Furthermore, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the channel length La of the first channel region 14ac, as shown in FIG.

[0065] The organic EL display device 50b described above is flexible, similar to the organic EL display device 50a of the first embodiment, and is configured to display an image by appropriately causing the light-emitting layer 3 of the organic EL layer 33 to emit light in each sub-pixel P via the first TFT 9a and the second TFT 9b.

[0066] Next, a method for manufacturing the organic EL display device 50b of this embodiment will be described. The method for manufacturing the organic EL display device 50b of this embodiment includes a TFT layer forming step, an organic EL element layer forming step, and a sealing film forming step. However, since the organic EL element layer forming step and the sealing film forming step are the same as those in the first embodiment, the TFT layer forming step will be mainly described.

[0067] First, in the TFT layer formation process of the first embodiment, an inorganic insulating film such as a silicon oxide film (with a thickness of about 100 nm) is formed on the surface of the substrate on which the first semiconductor layer 14a and the like are formed, for example, by plasma CVD, and then the inorganic insulating film is patterned to form a common gate insulating film 15c and the like having a first opening Ma and a second opening Mb (see FIG. 13).

[0068] Next, a first metal film such as a single layer of molybdenum film (about 200 nm thick), a laminated film in which an aluminum film (about 300 nm thick) and a titanium film (about 50 nm thick) are laminated in that order, or a laminated film in which a titanium film (about 50 nm thick), an aluminum film (about 300 nm thick), and a titanium film (about 50 nm thick) are laminated in that order is formed by, for example, sputtering on the substrate surface on which the common gate insulating film 15 c and the like are formed, and then the first metal film is patterned to form a first gate electrode 16 a, a second gate electrode 16 b, a gate line 16 g, and the like, as shown in FIG. 13 .

[0069] Thereafter, a silicon oxide film (about 300 nm thick) and a silicon nitride film (about 150 nm thick) are sequentially formed by, for example, plasma CVD on the substrate surface on which the first gate electrode 16a and the like have been formed, thereby forming an interlayer insulating film 17 as shown in Fig. 14. At this time, a heat treatment performed when forming the interlayer insulating film 17 converts a part of the first semiconductor layer 14a and a part of the second semiconductor layer 14b into conductors, so that a first conductor region 14aa, a second conductor region 14ab, and a first channel region 14ac are formed in the first semiconductor layer 14a, and a third conductor region 14ba, a fourth conductor region 14bb, and a second channel region 14bc are formed in the second semiconductor layer 14b. Here, in the portion where the first TFT 9a is formed (the right side in FIG. 14), the common gate insulating film 15c covers a relatively large area of ​​the first semiconductor layer 14a, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a, so that the area of ​​the first semiconductor layer 14a that is made conductive does not increase, and reduction in the (effective) channel length La of the first channel region 14ac is suppressed (more than in the first embodiment). That is, in the first TFT 9a, the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the portion where the second TFT 9b is formed (left side in FIG. 14 ), the common gate insulating film 15c covers the second semiconductor layer 14b relatively narrowly, so that hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b are not suppressed, resulting in a larger conductive region of the second semiconductor layer 14b and a smaller (effective) channel length Lb of the second channel region 14bc. That is, in the second TFT 9b, the channel length Lb of the second channel region 14bc is smaller than the width of the second gate electrode 16b in the channel direction. This makes it possible to form first TFTs 9a and second TFTs 9b having different characteristics on the same plane, even if the widths of the first gate electrode 16a and the second gate electrode 16b in the channel length direction are the same.

[0070] Furthermore, on the substrate surface on which the interlayer insulating film 17 is formed, the common gate insulating film 15c and the interlayer insulating film 17 are appropriately patterned to form a first contact hole Ha, a second contact hole Hb, a third contact hole Hc, a fourth contact hole Hd, etc.

[0071] Finally, similarly to the first embodiment, after forming the first source electrode 18 a, the first drain electrode 18 b, the second source electrode 18 c, the second drain electrode 18 d, the source line 18 f, the power line 18 g, etc., the planarization film 19 is formed, thereby forming the TFT layer 20 b.

[0072] Thereafter, similarly to the first embodiment, an organic EL element layer forming step and a sealing film forming step are performed, thereby manufacturing the organic EL display device 50b of this embodiment.

[0073] As described above, in the organic EL display device 50b of this embodiment, the portion of the common gate insulating film 15c disposed between the first semiconductor layer 14a and the first gate electrode 16a in the first TFT 9a is larger in plan view than the portion of the common gate insulating film 15c disposed between the second semiconductor layer 14b and the second gate electrode 16b in the second TFT 9b. As a result, in the first TFT 9a, the common gate insulating film 15c covers a relatively large area of ​​the first semiconductor layer 14a, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a. On the other hand, in the second TFT 9b, the common gate insulating film 15c covers a relatively small area of ​​the second semiconductor layer 14b, thereby not suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b. Therefore, in the first TFT 9a, the conductive region of the first semiconductor layer 14a does not increase, and the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the second TFT 9b, the conductive region of the second semiconductor layer 14b increases, and the channel length Lb of the second channel region 14bc is smaller than the width of the second gate electrode 16b in the channel direction. Here, because the width of the first gate electrode 16a in the channel length direction is the same as the width of the second gate electrode 16b in the channel length direction, the S value of the first TFT 9a can be relatively increased, and the S value of the second TFT 9b can be relatively decreased. Therefore, the first TFT 9 a and the second TFT 9 b having different desired S values ​​can be formed without making the widths of the first gate electrode 16 a and the second gate electrode 16 b in the channel length direction different from each other, and therefore, in an organic EL display device 50 b in which the first TFT 9 a and the second TFT 9 b using an oxide semiconductor are provided in the sub-pixel P, the characteristics of the first TFT 9 a and the second TFT 9 b can be optimized.

[0074] Third Embodiment Figures 15 to 19 show a third embodiment of a display device according to the present invention. Here, Figure 15 is a cross-sectional view of a display region D of an organic EL display device 50c of this embodiment. Also, Figures 16 and 17 are plan views of the first TFT 9a and second TFT 9b constituting the organic EL display device 50c, and correspond to Figures 4 and 5 of the first embodiment. Also, Figure 18 is a cross-sectional view showing a part of a manufacturing process for the organic EL display device 50c. Also, Figure 19 is a cross-sectional view showing a part of a manufacturing process for the organic EL display device 50c subsequent to Figure 18.

[0075] In the first embodiment described above, an organic EL display device 50a having a first TFT 9a and a second TFT 9b with a single gate structure is exemplified, but in this embodiment, an organic EL display device 50c having a first TFT 9a and a second TFT 9b with a double gate structure is exemplified.

[0076] Similar to the organic EL display device 50a of the first embodiment, the organic EL display device 50c includes, for example, a rectangular display area D for displaying an image and a frame area F provided in a frame shape around the periphery of the display area D. As shown in Fig. 10 , the organic EL display device 50c also includes a resin substrate 10 provided as a base substrate, a TFT layer 20c provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 20c, and a sealing film 45 provided on the organic EL element layer 40.

[0077] 15 , the TFT layer 20c includes a base coat film 12 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 12, and a planarization film 19 provided on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. Here, the TFT layer 20c is provided with a plurality of gate lines 16g, a plurality of source lines 18f, and a plurality of power supply lines 18g, similar to the TFT 20a of the first embodiment. Furthermore, in the TFT layer 20c, each sub-pixel P is provided with a first TFT 9a, a second TFT 9b, and a capacitor 9c, similar to the TFT 20a of the first embodiment. As shown in FIG. 10 , in the TFT layer 20c, a third metal film that will become a third gate electrode 11a and a fourth gate electrode 11b (described later), a base coat film 12, a semiconductor film that will become a first semiconductor layer 14a and a second semiconductor layer 14b, etc., a first gate insulating film 15aa and a second gate insulating film 15b (described later), a first metal film that will become a gate line 16g, etc., an interlayer insulating film 17, a second metal film that will become a source line 18f and a power supply line 18g, etc., and a planarization film 19 are laminated in this order on a resin substrate 10.

[0078] 15, the first TFT 9a includes a first semiconductor layer 14a provided on the base coat film 12, a first gate electrode 16a provided on the first semiconductor layer 14a with a first gate insulating film 15aa interposed therebetween, a third gate electrode 11a provided on the resin substrate 10 side of a first channel region 14ac of the first semiconductor layer 14a with a third gate insulating film (base coat film 12) interposed therebetween, and a first source electrode 18a and a first drain electrode 18b provided spaced apart from each other on the interlayer insulating film 17. Here, the third gate electrode 11a is electrically connected to the first gate electrode 16a and is configured to control conduction between the first conductor region 14aa and the second conductor region 14ab of the first semiconductor layer 14a. As shown in FIG. 15, the first source electrode 18a and the second drain electrode 18b are electrically connected to the first conductor region 14aa and the second conductor region 14ab of the first semiconductor layer 14a, respectively, via a first contact hole Ha and a second contact hole Hb formed in the first gate insulating film 15aa and the interlayer insulating film 17.

[0079] 15, the second TFT 9b includes a second semiconductor layer 14b provided on the base coat film 12, a second gate electrode 16b provided on the second semiconductor layer 14b with a second gate insulating film 15b interposed therebetween, a fourth gate electrode 11b provided on the resin substrate 10 side of a second channel region 14bc of the second semiconductor layer 14b with a third gate insulating film (base coat film 12) interposed therebetween, and a second source electrode 18c and a second drain electrode 18d provided spaced apart from each other on the interlayer insulating film 17. Here, the fourth gate electrode 11b is electrically connected to the second gate electrode 16b and is configured to control conduction between the third conductor region 14ba and the fourth conductor region 14bb of the second semiconductor layer 14b.

[0080] 15, 16, and 17, in the first TFT 9a and the second TFT 9b, the first gate insulating film 15aa is larger than the second gate insulating film 15b in plan view, so that the channel length La of the first channel region 14ac is larger than the channel length Lb of the second channel region 14bc. Furthermore, in the first TFT 9a and the second TFT 9b, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the width of the second gate electrode 16b in the channel length direction (horizontal direction in the figure), as shown in FIG. 15. Furthermore, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the channel length La of the first channel region 14ac, as shown in FIG.

[0081] The organic EL display device 50c described above is flexible, similar to the organic EL display device 50a of the first embodiment, and is configured to display an image by appropriately causing the light-emitting layer 3 of the organic EL layer 33 to emit light in each sub-pixel P via the first TFT 9a and the second TFT 9b.

[0082] Next, a method for manufacturing the organic EL display device 50c of this embodiment will be described. The method for manufacturing the organic EL display device 50c of this embodiment includes a TFT layer forming step, an organic EL element layer forming step, and a sealing film forming step. However, since the organic EL element layer forming step and the sealing film forming step are the same as those in the first embodiment, the TFT layer forming step will be mainly described.

[0083] First, for example, a third metal film such as a molybdenum film (thickness: about 200 nm) is formed by sputtering on a resin substrate 10 formed on a glass substrate, and then the third metal film is patterned to form a third gate electrode 11 a, a fourth gate electrode 11 b, etc.

[0084] Subsequently, a silicon oxide film (about 100 nm thick) is formed by, for example, plasma CVD on the surface of the substrate on which the third gate electrode 11a and the like are formed, thereby forming a base coat film 12.

[0085] Thereafter, InGaZnO is deposited on the surface of the substrate on which the base coat film 12 has been formed, for example, by sputtering. ４ After forming a semiconductor film made of an oxide semiconductor by depositing a film (thickness: about 30 nm) or the like, the semiconductor film is patterned to form the first semiconductor layer 14a, the second semiconductor layer 14b, and the like.

[0086] Furthermore, an inorganic insulating film such as a silicon oxide film (about 100 nm thick) is formed on the substrate surface on which the first semiconductor layer 14a etc. are formed, for example, by plasma CVD, and then the inorganic insulating film is patterned to form the first gate insulating film 15aa, the second gate insulating film 15b etc. (see FIG. 18).

[0087] Next, a first metal film such as a single layer of molybdenum film (about 200 nm thick), a laminated film in which an aluminum film (about 300 nm thick) and a titanium film (about 50 nm thick) are laminated in that order, or a laminated film in which a titanium film (about 50 nm thick), an aluminum film (about 300 nm thick), and a titanium film (about 50 nm thick) are laminated in that order is formed by, for example, a sputtering method on the substrate surface on which the first gate insulating film 15aa and the like are formed, and then the first metal film is patterned to form a first gate electrode 16a, a second gate electrode 16b, a gate line 16g, and the like, as shown in FIG. 18 .

[0088] Thereafter, a silicon oxide film (about 300 nm thick) and a silicon nitride film (about 150 nm thick) are sequentially formed by, for example, plasma CVD on the substrate surface on which the first gate electrode 16a and the like have been formed, thereby forming an interlayer insulating film 17 as shown in Fig. 19. At this time, a heat treatment performed when forming the interlayer insulating film 17 converts a part of the first semiconductor layer 14a and a part of the second semiconductor layer 14b into conductors, so that a first conductor region 14aa, a second conductor region 14ab, and a first channel region 14ac are formed in the first semiconductor layer 14a, and a third conductor region 14ba, a fourth conductor region 14bb, and a second channel region 14bc are formed in the second semiconductor layer 14b. Here, in the portion where the first TFT 9a is formed (the right side in FIG. 19 ), the first gate insulating film 15aa covers a relatively large area of ​​the first semiconductor layer 14a, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a, so that the area of ​​the first semiconductor layer 14a that is made conductive does not increase, and reduction in the (effective) channel length La of the first channel region 14ac is suppressed (more than in the first embodiment). That is, in the first TFT 9a, the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the portion where the second TFT 9b is formed (the left side in FIG. 19 ), the second gate insulating film 15b covers the second semiconductor layer 14b relatively narrowly, and therefore hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b are not suppressed, resulting in a larger conductive region of the second semiconductor layer 14b and a smaller (effective) channel length Lb of the second channel region 14bc. That is, in the second TFT 9b, the channel length Lb of the second channel region 14bc is smaller than the width of the second gate electrode 16b in the channel direction. This makes it possible to fabricate first TFTs 9a and second TFTs 9b having different characteristics on the same plane, even if the widths of the first gate electrode 16a and the second gate electrode 16b in the channel length direction are the same.

[0089] Furthermore, on the substrate surface on which the interlayer insulating film 17 is formed, the first gate insulating film 15aa and the interlayer insulating film 17 are appropriately patterned to form a first contact hole Ha, a second contact hole Hb, a third contact hole Hc, a fourth contact hole Hd, etc.

[0090] Finally, similarly to the first embodiment, after forming the first source electrode 18 a, the first drain electrode 18 b, the second source electrode 18 c, the second drain electrode 18 d, the source line 18 f, the power line 18 g, etc., the planarization film 19 is formed, thereby forming the TFT layer 20 c.

[0091] Thereafter, similarly to the first embodiment, an organic EL element layer forming step and a sealing film forming step are performed, thereby manufacturing the organic EL display device 50c of this embodiment.

[0092] As described above, in the organic EL display device 50c of this embodiment, in the first TFT 9a, the first gate insulating film 15aa disposed between the first semiconductor layer 14a and the first gate electrode 16a is larger in plan view than the second gate insulating film 15b disposed between the second semiconductor layer 14b and the second gate electrode 16b in the second TFT 9a. As a result, in the first TFT 9a, the first gate insulating film 15aa covers a relatively large area of ​​the first semiconductor layer 14a, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a. On the other hand, in the second TFT 9b, the second gate insulating film 15b covers a relatively small area of ​​the second semiconductor layer 14b, thereby not suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b. Therefore, in the first TFT 9a, the conductive region of the first semiconductor layer 14a does not increase, and the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the second TFT 9b, the conductive region of the second semiconductor layer 14b increases, and the channel length Lb of the second channel region 14bc is smaller than the width of the second gate electrode 16b in the channel direction. Here, because the width of the first gate electrode 16a in the channel length direction is the same as the width of the second gate electrode 16b in the channel length direction, the S value of the first TFT 9a can be relatively increased, and the S value of the second TFT 9b can be relatively decreased. Therefore, the first TFT 9 a and the second TFT 9 b having desired S values ​​different from each other can be formed without making the widths of the first gate electrode 16 a and the second gate electrode 16 b in the channel length direction different from each other. Therefore, in an organic EL display device 50 c in which the first TFT 9 a and the second TFT 9 b using an oxide semiconductor are provided in the sub-pixel P, the characteristics of the first TFT 9 a and the second TFT 9 b can be optimized.

[0093] Furthermore, according to the organic EL display device 50c of this embodiment, the first TFT 9a and the second TFT 9b have a double gate structure, which makes it possible to improve the on-current of the first TFT 9a and the second TFT 9b, and also to block moisture, impurity ions, etc. from the resin substrate 10 by the third gate electrode 11a and the fourth gate electrode 11b, thereby suppressing deterioration of the first TFT 9a and the second TFT 9b.

[0094] 20 to 22 show a fourth embodiment of a display device according to the present invention. Fig. 20 is a cross-sectional view of a display region D of an organic EL display device 50d according to this embodiment. Figs. 21 and 22 are plan views of the first TFT 9a and second TFT 9b that constitute the organic EL display device 50d, and correspond to Figs. 4 and 5 of the first embodiment.

[0095] In the first embodiment described above, an organic EL display device 50a is illustrated as having a first TFT 9a in which the entire first contact hole Ha and the entire second contact hole Hb overlap the first gate insulating film 15a. In the present embodiment, an organic EL display device 50d is illustrated as having a first TFT 9a in which a portion of the first contact hole Ha and a portion of the second contact hole Hb overlap the first gate insulating film 15ab.

[0096] Similar to the organic EL display device 50a of the first embodiment, the organic EL display device 50d includes, for example, a rectangular display area D for displaying images and a frame area F provided in a frame shape around the periphery of the display area D. As shown in Fig. 20 , the organic EL display device 50d also includes a resin substrate 10 provided as a base substrate, a TFT layer 20d provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 20d, and a sealing film 45 provided on the organic EL element layer 40.

[0097] 20 , the TFT layer 20d includes a base coat film 12 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 12, and a planarization film 19 provided on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. Here, the TFT layer 20d is provided with a plurality of gate lines 16g, a plurality of source lines 18f, and a plurality of power supply lines 18g, similar to the TFT 20a of the first embodiment. Furthermore, in the TFT layer 20d, each subpixel P is provided with a first TFT 9a, a second TFT 9b, and a capacitor 9c, similar to the TFT 20a of the first embodiment. As shown in FIG. 20 , in the TFT layer 20d, a base coat film 12, a semiconductor film to become the first semiconductor layer 14a, the second semiconductor layer 14b, etc., a first gate insulating film 15ab, a second gate insulating film 15b, a first metal film to become the gate line 16g, etc., an interlayer insulating film 17, a second metal film to become the source line 18f, the power supply line 18g, etc., and a planarization film 19 are laminated in this order on a resin substrate 10.

[0098] 20, the first TFT 9a includes a first semiconductor layer 14a provided on the base coat film 12, a first gate electrode 16a provided on the first semiconductor layer 14a via a first gate insulating film 15ab, and a first source electrode 18a and a first drain electrode 18b provided spaced apart from each other on an interlayer insulating film 17. The first source electrode 18a and the second drain electrode 18b are electrically connected to a first conductor region 14aa and a second conductor region 14ab of the first semiconductor layer 14a via first contact holes Ha and second contact holes Hb formed at both ends of the first gate insulating film 15ab and in the interlayer insulating film 17, respectively, as shown in FIG.

[0099] As shown in Figure 10, the second TFT 9b includes a second semiconductor layer 14b provided on the base coat film 12, a second gate electrode 16b provided on the second semiconductor layer 14b via a second gate insulating film 15b, and a second source electrode 18c and a second drain electrode 18d provided on the interlayer insulating film 17 so as to be spaced apart from each other.

[0100] 20, 21, and 22, in the first TFT 9a and the second TFT 9b, the first gate insulating film 15ab is larger than the second gate insulating film 15b in plan view, so that the channel length La of the first channel region 14ac is larger than the channel length Lb of the second channel region 14bc. Furthermore, in the first TFT 9a and the second TFT 9b, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the width of the second gate electrode 16b in the channel length direction (horizontal direction in the figure), as shown in FIG. 20. Furthermore, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the channel length La of the first channel region 14ac, as shown in FIG.

[0101] The organic EL display device 50d described above is flexible, similar to the organic EL display device 50a of the first embodiment, and is configured to display an image by appropriately causing the light-emitting layer 3 of the organic EL layer 33 to emit light in each sub-pixel P via the first TFT 9a and the second TFT 9b.

[0102] The organic EL display device 50d of this embodiment can be manufactured by changing the pattern shape of the first gate insulating film 14a in the TFT formation process of the first embodiment.

[0103] As described above, in the organic EL display device 50d of this embodiment, in the first TFT 9a, the first gate insulating film 15ab disposed between the first semiconductor layer 14a and the first gate electrode 16a is larger in plan view than the second gate insulating film 15b disposed between the second semiconductor layer 14b and the second gate electrode 16b in the second TFT 9a. As a result, in the first TFT 9a, the first gate insulating film 15ab covers a relatively large area of ​​the first semiconductor layer 14a, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a. On the other hand, in the second TFT 9b, the second gate insulating film 15b covers a relatively small area of ​​the second semiconductor layer 14b, thereby not suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b. Therefore, in the first TFT 9a, the conductive region of the first semiconductor layer 14a does not increase, and the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the second TFT 9b, the conductive region of the second semiconductor layer 14b increases, and the channel length Lb of the second channel region 14bc is smaller than the width of the second gate electrode 16b in the channel direction. Here, because the width of the first gate electrode 16a in the channel length direction is the same as the width of the second gate electrode 16b in the channel length direction, the S value of the first TFT 9a can be relatively increased, and the S value of the second TFT 9b can be relatively decreased. Therefore, the first TFT 9 a and the second TFT 9 b having different desired S values ​​can be formed without making the widths of the first gate electrode 16 a and the second gate electrode 16 b in the channel length direction different from each other, so that in an organic EL display device 50 d in which the first TFT 9 a and the second TFT 9 b using an oxide semiconductor are provided in the sub-pixel P, the characteristics of the first TFT 9 a and the second TFT 9 b can be optimized.

[0104] Fifth Embodiment Figures 23 to 27 show a fifth embodiment of a display device according to the present invention. Here, Figure 23 is a cross-sectional view of a display region D of an organic EL display device 50e of this embodiment. Also, Figures 24 and 25 are plan views of the first TFT 9a and second TFT 9b constituting the organic EL display device 50e, and correspond to Figures 4 and 5 of the first embodiment. Also, Figure 26 is a cross-sectional view showing a part of a manufacturing process for the organic EL display device 50e. Also, Figure 27 is a cross-sectional view showing a part of a manufacturing process for the organic EL display device 50e subsequent to Figure 26.

[0105] In the first embodiment described above, an organic EL display device 50a having a first TFT 9a and a second TFT 9b with a top-contact structure is exemplified, whereas in the present embodiment, an organic EL display device 50e having a first TFT 9a and a second TFT 9b with a bottom-contact structure is exemplified.

[0106] Similar to the organic EL display device 50a of the first embodiment, the organic EL display device 50e includes, for example, a rectangular display area D for displaying images and a frame area F provided in a frame shape around the periphery of the display area D. Also, as shown in Fig. 23 , the organic EL display device 50b includes a resin substrate 10 provided as a base substrate, a TFT layer 20e provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 20e, and a sealing film 45 provided on the organic EL element layer 40.

[0107] 23 , the TFT layer 20e includes a base coat film 12 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 12, and a planarization film 19 provided on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. Here, the TFT layer 20e is provided with a plurality of gate lines 16g, a plurality of source lines 18f, and a plurality of power supply lines 18g, similar to the TFT 20a of the first embodiment. Furthermore, in the TFT layer 20e, each sub-pixel P is provided with a first TFT 9a, a second TFT 9b, and a capacitor 9c, similar to the TFT 20a of the first embodiment. 23, in the TFT layer 20e, the following are stacked in order on the resin substrate 10: a base coat film 12; a fourth metal film which will become a first relay electrode 13a, a second relay electrode 13b, a third relay electrode 13c, a fourth relay electrode 13d, etc., which will be described later; a semiconductor film which will become a first semiconductor layer 14a, a second semiconductor layer 14b, etc.; a first gate insulating film 15ac, a second gate insulating film 15b, etc., which will be described later; a first metal film which will become a gate line 16g, etc.; an interlayer insulating film 17; a second metal film which will become a source line 18f, a power line 18g, etc.; and a planarization film 19.

[0108] 23, the first TFT 9e includes a first semiconductor layer 14a provided on the base coat film 12, a first relay electrode 13a and a second relay electrode 13b provided on the resin substrate 10 side of the first semiconductor layer 14a so as to be spaced apart from each other, a first gate electrode 16a provided on the first semiconductor layer 14a with a first gate insulating film 15ac interposed therebetween, and a first source electrode 18a and a first drain electrode 18b provided on the interlayer insulating film 17 so as to be spaced apart from each other. Here, as shown in FIG. 23, the first relay electrode 13a and the second relay electrode 13b are provided on the base coat film 12 and are provided so as to be in contact with the lower surfaces of the first conductor region 14aa and the second conductor region 14ab of the first semiconductor layer 14a, respectively. In addition, as shown in FIG. 23, the first source electrode 18a and the second drain electrode 18b are electrically connected to the first conductor region 14aa and the second conductor region 14ab of the first semiconductor layer 14a, respectively, via a first contact hole Ha and a second contact hole Hb formed in the first gate insulating film 15ac and the interlayer insulating film 17.

[0109] 23, the second TFT 9b includes a second semiconductor layer 14b provided on the base coat film 12, a third relay electrode 13c and a fourth relay electrode 13d provided on the resin substrate 10 side of the second semiconductor layer 14b so as to be spaced apart, a second gate electrode 16b provided on the second semiconductor layer 14b via a second gate insulating film 15b, and a second source electrode 18c and a second drain electrode 18d provided on the interlayer insulating film 17 so as to be spaced apart. Here, as shown in FIG. 23, the third relay electrode 13c and the fourth relay electrode 13d are provided on the base coat film 12 and are provided so as to be in contact with the lower surfaces of the third conductor region 14ba and the fourth conductor region 14bb of the second semiconductor layer 14b, respectively. In addition, the second source electrode 18c and the second drain electrode 18d are electrically connected to the third conductor region 14ba and the fourth conductor region 14bb of the first semiconductor layer 14b, respectively, via the third contact hole Hc and the fourth contact hole Hd formed in the interlayer insulating film 17, as shown in FIG.

[0110] 23, 24, and 25, in the first TFT 9a and the second TFT 9b, the first gate insulating film 15ac is larger than the second gate insulating film 15b in plan view, so that the channel length La of the first channel region 14ac is larger than the channel length Lb of the second channel region 14bc. Furthermore, in the first TFT 9a and the second TFT 9b, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the width of the second gate electrode 16b in the channel length direction (horizontal direction in the figure), as shown in FIG. 23. Furthermore, the width of the first gate electrode 16a in the channel length direction (horizontal direction in the figure) is the same as the channel length La of the first channel region 14ac, as shown in FIG.

[0111] The organic EL display device 50e described above is flexible, similar to the organic EL display device 50a of the first embodiment, and is configured to display an image by appropriately causing the light-emitting layer 3 of the organic EL layer 33 to emit light in each sub-pixel P via the first TFT 9a and the second TFT 9b.

[0112] Next, a method for manufacturing the organic EL display device 50e of this embodiment will be described. The method for manufacturing the organic EL display device 50e of this embodiment includes a TFT layer forming step, an organic EL element layer forming step, and a sealing film forming step. However, since the organic EL element layer forming step and the sealing film forming step are the same as those in the first embodiment, the TFT layer forming step will be mainly described.

[0113] First, for example, a silicon oxide film (about 100 nm thick) is formed on a resin substrate 10 formed on a glass substrate by plasma CVD (Chemical Vapor Deposition) to form a base coat film 12 .

[0114] Next, a fourth metal film such as a molybdenum film (about 200 nm thick) is formed on the surface of the substrate on which the base coat film 12 has been formed, for example, by sputtering, and then the fourth metal film is patterned to form a first relay electrode 13 a, a second relay electrode 13 b, a third relay electrode 13 c, a fourth relay electrode 13 d, etc.

[0115] Thereafter, InGaZnO is deposited by, for example, sputtering on the surface of the substrate on which the first relay electrode 13a and the like are formed. ４ After forming a semiconductor film made of an oxide semiconductor by depositing a film (thickness: about 30 nm) or the like, the semiconductor film is patterned to form the first semiconductor layer 14a, the second semiconductor layer 14b, and the like.

[0116] Furthermore, an inorganic insulating film such as a silicon oxide film (with a thickness of about 100 nm) is formed on the substrate surface on which the first semiconductor layer 14a and the like are formed, for example, by plasma CVD, and then the inorganic insulating film is patterned to form a first gate insulating film 15ac, a second gate insulating film 15b and the like (see FIG. 18).

[0117] Subsequently, a first metal film such as a single layer of molybdenum film (about 200 nm thick), a laminated film in which an aluminum film (about 300 nm thick) and a titanium film (about 50 nm thick) are laminated in this order, or a laminated film in which a titanium film (about 50 nm thick), an aluminum film (about 300 nm thick), and a titanium film (about 50 nm thick) are laminated in this order is formed by, for example, a sputtering method on the substrate surface on which the first gate insulating film 15ac and the like are formed, and then the first metal film is patterned to form a first gate electrode 16a, a second gate electrode 16b, a gate line 16g, and the like, as shown in FIG. 26 .

[0118] Thereafter, a silicon oxide film (about 300 nm thick) and a silicon nitride film (about 150 nm thick) are sequentially formed by, for example, plasma CVD on the substrate surface on which the first gate electrode 16a and the like have been formed, thereby forming an interlayer insulating film 17 as shown in Fig. 27. At this time, a heat treatment performed when forming the interlayer insulating film 17 converts a part of the first semiconductor layer 14a and a part of the second semiconductor layer 14b into conductors, so that a first conductor region 14aa, a second conductor region 14ab, and a first channel region 14ac are formed in the first semiconductor layer 14a, and a third conductor region 14ba, a fourth conductor region 14bb, and a second channel region 14bc are formed in the second semiconductor layer 14b. Here, in the portion where the first TFT 9a is formed (the right side in FIG. 27), the first gate insulating film 15ac covers a relatively large area of ​​the first semiconductor layer 14a, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a, so that the area of ​​the first semiconductor layer 14a that is made conductive does not increase, and reduction in the (effective) channel length La of the first channel region 14ac is suppressed (more than in the first embodiment). That is, in the first TFT 9a, the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the portion where the second TFT 9b is formed (left side in FIG. 27 ), the second gate insulating film 15b covers the second semiconductor layer 14b relatively narrowly, and therefore hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b are not suppressed, resulting in a larger conductive region of the second semiconductor layer 14b and a smaller (effective) channel length Lb of the second channel region 14bc. That is, in the second TFT 9b, the channel length Lb of the second channel region 14bc is smaller than the width of the second gate electrode 16b in the channel direction. This makes it possible to fabricate first TFTs 9a and second TFTs 9b having different characteristics on the same plane, even if the widths of the first gate electrode 16a and the second gate electrode 16b in the channel length direction are the same.

[0119] Furthermore, on the substrate surface on which the interlayer insulating film 17 is formed, the first gate insulating film 15ac and the interlayer insulating film 17 are appropriately patterned to form a first contact hole Ha, a second contact hole Hb, a third contact hole Hc, a fourth contact hole Hd, etc.

[0120] Finally, similarly to the first embodiment, after forming the first source electrode 18 a, the first drain electrode 18 b, the second source electrode 18 c, the second drain electrode 18 d, the source line 18 f, the power line 18 g, etc., the planarization film 19 is formed, thereby forming the TFT layer 20 e.

[0121] Thereafter, similarly to the first embodiment, an organic EL element layer forming step and a sealing film forming step are performed, thereby manufacturing the organic EL display device 50e of this embodiment.

[0122] As described above, in the organic EL display device 50e of this embodiment, in the first TFT 9a, the first gate insulating film 15ac disposed between the first semiconductor layer 14a and the first gate electrode 16a is larger in plan view than the second gate insulating film 15b disposed between the second semiconductor layer 14b and the second gate electrode 16b in the second TFT 9a. As a result, in the first TFT 9a, the first gate insulating film 15ac covers a relatively large area of ​​the first semiconductor layer 14a, thereby suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the first semiconductor layer 14a. On the other hand, in the second TFT 9b, the second gate insulating film 15b covers a relatively small area of ​​the second semiconductor layer 14b, thereby not suppressing hydrogen diffusion from the interlayer insulating film 17 and deoxidation from the second semiconductor layer 14b. Therefore, in the first TFT 9a, the conductive region of the first semiconductor layer 14a does not increase, and the channel length La of the first channel region 14ac is approximately the same as the width of the first gate electrode 16a in the channel direction. On the other hand, in the second TFT 9b, the conductive region of the second semiconductor layer 14b increases, and the channel length Lb of the second channel region 14bc is smaller than the width of the second gate electrode 16b in the channel direction. Here, because the width of the first gate electrode 16a in the channel length direction is the same as the width of the second gate electrode 16b in the channel length direction, the S value of the first TFT 9a can be relatively increased, and the S value of the second TFT 9b can be relatively decreased. Therefore, the first TFT 9 a and the second TFT 9 b having different desired S values ​​can be formed without making the widths of the first gate electrode 16 a and the second gate electrode 16 b in the channel length direction different from each other, so that in an organic EL display device 50 e in which the first TFT 9 a and the second TFT 9 b using an oxide semiconductor are provided in the sub-pixel P, the characteristics of the first TFT 9 a and the second TFT 9 b can be optimized.

[0123] Furthermore, according to the organic EL display device 50e of this embodiment, the first TFT 9a and the second TFT 9b have a bottom-contact structure, so when forming the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, and the fourth contact hole Hd, the first semiconductor layer 14a and the second semiconductor layer 14b are not etched, and the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, and the fourth contact hole Hd can be easily formed.

[0124] Other Embodiments In the above-described embodiments, the organic EL layer has a five-layer laminated structure including a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. However, the organic EL layer may have a three-layer laminated structure including, for example, a hole injection layer / hole transport layer, a light-emitting layer, and an electron transport layer / electron injection layer.

[0125] In addition, in each of the above embodiments, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, and the first electrode is a cathode and the second electrode is an anode.

[0126] Furthermore, in each of the above embodiments, an organic EL display device is exemplified in which the electrode of the TFT connected to the first electrode is used as the drain electrode, but the present invention can also be applied to an organic EL display device in which the electrode of the TFT connected to the first electrode is called the source electrode.

[0127] Furthermore, in each of the above embodiments, an organic EL display device has been described as an example of a display device. However, the present invention can be applied to a display device including a plurality of light-emitting elements driven by current, and can be applied to, for example, a display device including QLEDs (Quantum-dot light emitting diodes), which are light-emitting elements using a quantum dot-containing layer.

[0128] Furthermore, in the above-described embodiments, various organic EL display devices have been exemplified, but it goes without saying that the present invention is not limited to the above-described embodiments, and combinations of the embodiments are also included in the scope of the present invention.

[0129] As described above, the present invention is useful for flexible display devices.

[0130] D Display area Ma First opening Mb Second opening P Sub-pixel 9a First TFT (first thin film transistor, drive thin film transistor) 9b Second TFT (second thin film transistor, selection thin film transistor) 10 Resin substrate (base substrate) 11a Third gate electrode 11b Fourth gate electrode 12 Base coat film (third gate insulating film) 13a First relay electrode 13b Second relay electrode 13c Third relay electrode 13d Fourth relay electrode 14a First semiconductor layer 14aa First conductor region 14ab Second conductor region 14ac First channel region 14b Second semiconductor layer 14ba Third conductor region 14bb Fourth conductor region 14bc Second channel region 15a, 15aa, 15ab, 15ac First gate insulating film 15b Second gate insulating film 15c Common gate insulating film 16a First gate electrode 16b Second gate electrode 17 Interlayer insulating film 20a, 20b, 20c, 20d, 20e TFT layer (thin film transistor layer) 35 Organic EL element (organic electroluminescence element, light emitting element) 40 Organic EL element layer (light emitting element layer) 45 Sealing film 50a, 50b, 50c, 50d, 50e Organic EL display device

Claims

1. A display device comprising: a base substrate; and a thin film transistor layer provided on the base substrate; in the thin film transistor layer, a first thin film transistor having a first semiconductor layer formed of an oxide semiconductor, and a second thin film transistor having a second semiconductor layer formed of an oxide semiconductor, are provided for each sub-pixel constituting a display area; the first thin film transistor comprises: the first semiconductor layer having a first conductor region and a second conductor region defined so as to be spaced apart, and a first channel region defined between the first conductor region and the second conductor region; and a first gate electrode provided on the first semiconductor layer via a first gate insulating film so as to overlap the first channel region; the second thin film transistor comprises: the second semiconductor layer having a third conductor region and a fourth conductor region defined so as to be spaced apart, and a second channel region defined between the third conductor region and the fourth conductor region; and a second gate electrode provided on the second semiconductor layer via a second gate insulating film so as to overlap the second channel region; the first gate insulating film is larger than the second gate insulating film in a plan view; A display device characterized in that the channel length of the first channel region is longer than the channel length of the second channel region.

2. A display device according to claim 1, wherein the width of said first gate electrode in the channel length direction is the same as the width of said second gate electrode in the channel length direction.

3. A display device according to claim 2, wherein the width of the first gate electrode in the channel length direction is the same as the channel length of the first channel region.

4. A display device according to any one of claims 1 to 3, wherein an interlayer insulating film is provided in the thin film transistor layer so as to cover the first gate electrode and the second gate electrode, and the interlayer insulating film includes a silicon nitride film.

5. A display device according to any one of claims 1 to 4, wherein the first gate insulating film and the second gate insulating film are a common gate insulating film formed integrally, and a first opening and a second opening are formed in the common gate insulating film so as to expose a part of the third conductor region and a part of the fourth conductor region.

6. A display device according to any one of claims 1 to 5, characterized in that a third gate electrode and a fourth gate electrode are provided on the base substrate side of the first channel region and the second channel region, respectively, via a third gate insulating film.

7. A display device according to any one of claims 1 to 6, wherein the first thin film transistor comprises a first relay electrode and a second relay electrode provided on the base substrate side of the first semiconductor layer and arranged so as to contact the first conductor region and the second conductor region, respectively; and the second thin film transistor comprises a third relay electrode and a fourth relay electrode provided on the base substrate side of the second semiconductor layer and arranged so as to contact the third conductor region and the fourth conductor region, respectively.

8. A display device according to any one of claims 1 to 7, characterized in that a drive thin film transistor is provided as the first thin film transistor, and a selection thin film transistor is provided as the second thin film transistor.

9. A display device according to any one of claims 1 to 8, characterized in that it comprises: a light emitting element layer provided on the thin film transistor layer, in which a plurality of light emitting elements are arranged corresponding to a plurality of sub-pixels constituting the display area; and a sealing film provided on the light emitting element layer.

10. The display device according to claim 9, wherein each of the light-emitting elements is an organic electroluminescence element.

Images