Imaging systems and methods

Abstract

Imaging systems and methods are described An imaging system comprises: a pixel array having a plurality of pixels, each pixel comprising a light sensor configured to generate a pixel signal in response to light incident on the pixel; a saliency detection circuit configured to detect salient events from the pixel signals; and a segmentation circuit configured to segment salient pixels by performing erosion and dilation operations on pixels corresponding to the salient events.

Description

[0001] IMAGING SYSTEMS AND METHODS

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to imaging systems and methods and in particular to imaging systems with embedded event detection and object segmentation.

[0004] BACKGROUND

[0005] Relentless power reductions in always-on untethered imagers for distributed vision are demanded to fit the power budget available from their tightly-constrained energy source. As an effective approach to reduce power, event detection has been explored to reduce system activity in uninteresting frames or regions. In imagers with event detection, one of the main challenges is to simultaneously achieve substantial activity reduction for lower system power (i.e., low event detection false-positives) and low power consumption in the event detection circuitry (generally higher when targeting lower false positives). Frame difference for motion detection is relatively simple and hence power-inexpensive, although it is well known to offer limited activity reductions due to background motion. Background subtraction is generally more effective in reducing activity, but it comes at the cost of higher power due to its higher complexity. Further opportunities to reduce activity are potentially added by object segmentation, which can suppress readout and potentially restrict subsequent processing (e.g., neural network) to specific regions of interest rather than the entire frame. However, in this case event detection inaccuracies severely limit potential activity reductions, thus requiring further mitigation of false positives. Accordingly, morphological transformations such as erosion have been demonstrated to remove isolated and noisy areas for lower false positives, although at high power consumption due to the digital implementation outside the pixel array. From the above fundamental tradeoff, new solutions with more favorable false positives-power reduction tradeoff are necessary to simultaneously suppress activity / readout in uninteresting regions via object segmentation and accurate event detection, while keeping the latter energy competitive. SUMMARY

[0006] According to a first aspect of the present disclosure an imaging system is provided. The imagining system comprises: a pixel array having a plurality of pixels, each pixel comprising a light sensor configured to generate a pixel signal in response to light incident on the pixel; a saliency detection circuit configured to detect salient events from the pixel signals; and a segmentation circuit configured to segment salient pixels by performing erosion and dilation operations on pixels corresponding to the salient events.

[0007] The proposed imaging system uniquely includes dilation, whose combination with erosion also allows image opening and closing transformations. Such morphological transformations reduce redundant activations due to background motion and enable more accurate event detection, while keeping the object size intact. This enables a saliency-gated object-segmented readout operation reducing the conversion activity by 6.1X, hence reducing power.

[0008] In an embodiment, the saliency detection circuit is configured to perform background subtraction to detect salient events.

[0009] In an embodiment, the saliency detection circuit is configured to detect a salient event if a number of salient pixels exceeds a threshold.

[0010] In an embodiment, the imaging system further comprises an analog to digital converter configured to generate digital signals using the pixel signals; and a controller configured to activate the analog to digital converter in response to the salient events.

[0011] The proposed system reduces redundant data movement and analog-to-digital conversion in event detection image sensors by focusing only on regions of interest to increase energy-efficiency.

[0012] In an embodiment, the pixel array comprises a plurality of tiles each comprising a plurality of clusters. In an embodiment, the saliency detection circuit is configured to detect salient events within each tile.

[0013] In an embodiment, the segmentation circuit comprises a three input NOR gate and a three input NAND gate. Such embodiments provide a simple circuit that can perform both the erosion and the dilation operations.

[0014] In an embodiment, wherein the erosion operation and the dilation operation are performed using complementary thresholds.

[0015] In an embodiment, the morphological filters which perform the erosion and dilation operations are programmable. This increases the accuracy and adaptability of event detection operation in varied noisy outdoor scenarios.

[0016] In an embodiment, each pixel comprises four common transistors.

[0017] In an embodiment, wherein a size of the erosion and dilation operations is configurable. The size of the erosion operation and the dilation operation may be configured adjusting a number of times which the respective operation is run.

[0018] According to a second aspect of the present disclosure an imaging method is provided. The imaging method comprises: detecting salient events in analog pixel signals from a plurality of pixels; and segmenting salient pixels by performing an erosion operation and a dilation operation on pixels corresponding to the salient events.

[0019] In an embodiment, the method further comprises activating an analog to digital converter in response to the salient events; and converting analog pixel signals from the segmented salient pixels into digital pixel signals.

[0020] In an embodiment, the method further comprises identifying an object of interest in the segmented salient pixels using the digital pixel signals.

[0021] In an embodiment, the erosion operation and the dilation operation are performed using complementary thresholds. In an embodiment, a saliency map is generated from the salient events and the saliency map is segmented by performing the erosion operation and the dilation operation.

[0022] In an embodiment, a salient event is detected when a number of salient pixels exceeds a threshold.

[0023] In an embodiment, wherein a size of the erosion and dilation operations is configurable. The size of the erosion operation and the dilation operation may be configured adjusting a number of times which the respective operation is run.

[0024] BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the following, embodiments of the present invention will be described as non-limiting examples with reference to the accompanying drawings in which:

[0026] FIG.1 is a block diagram showing an imaging system according to an embodiment of the present invention;

[0027] FIG.2 is a block diagram showing an imaging system according to an embodiment of the present invention;

[0028] FIG.3 is a block diagram showing vision sensor operation and flow in an embodiment of the present invention;

[0029] FIG.4A to FIG.4F are images showing an example of event detection;

[0030] FIG.5 shows to graphs illustrating the potential power saving by pixel readout suppression;

[0031] FIG.6A shows a pixel circuit of an imaging system according to an embodiment of the present invention; FIG.6B shows a comparator circuit of an imaging system according to an embodiment of the present invention;

[0032] FIG.6C shows a tile level flip-flop circuit of an imaging system according to an embodiment of the present invention;

[0033] FIG.7 is a graph showing an example background subtraction operation in an embodiment of the present invention;

[0034] FIG.8 shows a post processing circuit of an imaging system according to an embodiment of the present invention;

[0035] FIG.9A shows a column pixel readout circuit of an imaging system according to an embodiment of the present invention;

[0036] FIG.9B shows a saliency gated analog digital converter circuit of an imaging system according to an embodiment of the present invention;

[0037] FIG.10 is a timing diagram for the saliency detection circuit;

[0038] FIG.11 is a timing diagram for the saliency gated column pixel readout circuit;

[0039] FIG.12 shows a comparison of saliency detection with and without morphological filters;

[0040] FIG.13 is a graph showing power measurements for different operating modes of an imaging system according to an embodiment of the present invention;

[0041] FIG.14 shows alert generation in different saliency detection operations; and

[0042] FIG.15 shows pixel activity comparison for different saliency operations. DETAILED DESCRIPTION

[0043] FIG.1 is a block diagram showing an imaging system according to an embodiment of the present invention. The imaging system 100 comprises a pixel array 110, a saliency detection circuit 120, a segmentation circuit 130, an analog to digital converter 140, a controller 150, an image analysis module 160 and an interface 170.

[0044] The pixel array 110 comprises a plurality of pixels, and each of the pixels comprises a light sensor such as a photodiode which generates a pixel signal in response to light incident on the pixel. The saliency detection circuit 120 is configured to detect salient events form the pixel signals. The saliency detection circuit may be configured to perform background subtraction to detect salient events. The segmentation circuit 130 is configured to segment salient pixels by performing erosion and dilation operations on pixels corresponding to salient events. For example, the saliency detection circuit 120 may generate a saliency map and the segmentation circuit may perform the erosion and dilation operations on the saliency map.

[0045] The analog to digital converter 140 converts the analog signals generated by the light sensors in the pixels into digital signals. In some operating modes of the imaging system, controller 150 controls the analog to digital converter 140 to operate only on pixels corresponding to salient events.

[0046] The image analysis module 160 performs image analysis on the digital signals generated by the analog to digital converter 140. For example, the image analysis module 160 may implement a neural network trained to recognize objects.

[0047] FIG.2 is a block diagram showing an imaging system according to an embodiment of the present invention. FIG.2 shows an embodiment of the imaging system 100. As shown in FIG.2, the imaging system 100 comprises a pixel array 110. The pixel array 110 is divided into tiles 1 12 comprising 8x8 pixel clusters. The array comprises 40 tiles in each column and 30 tiles in each row and thus has 240x320 pixels. Each pixel 114 comprises a photodiode 116 and 4 common transistors 118 for pixel aggregation. Each pixel is associated with a pixel circuit comprising a flip-flop and comparator which are described in more detail below. A digital controller 150 controls a row decoder 152 and a ramp generator 154. Column parallel saliency and pixel readout signals from the pixel circuits and output to a column decoder system 156. Saliency signals from the pixel circuits are used to gate operation of an analog to digital converter 140. The output of the analog to digital converter 140 is provided to an output encoder and decoder which corresponds to the interface 170.

[0048] The imaging system 100 normally operates in Saliency Detection (SD) mode, activating only the digital controller 150, the row-decoder 152 and the in-pixel SD circuitry. In a QVGA array, a 30x40 binary saliency map is generated via global insensor background subtraction, and its performance is improved by post-processing the saliency map with morphological filters. When the salient pixel count exceeds a threshold, an event is detected and the image sensor switches to the Object Segmentation (OS) mode. In this mode, saliency detection and saliency-gated image readout are time-interleaved, allowing only the salient object data to be converted for subsequent object recognition. Upon detecting an object of interest, the image sensor can trigger an alert and switches to full imaging (IM) mode, operating as a traditional rolling-shutter image sensor and capturing full-resolution images for recording and / or transmission.

[0049] FIG.3 is a block diagram showing vision sensor operation and flow in an embodiment of the present invention. As shown in FIG.3, the imaging system has three operating modes: a saliency detection (SD) mode 310, an object segmentation (OS) mode 330 and a full imaging (IM) mode 350. As indicated in FIG.3, the power consumption is lowest in the saliency detection (SD) mode 310, increases in the object segmentation (OS) mode 330 and is highest in the full imaging (IM) mode 350.

[0050] In the saliency detection mode 310, background subtraction and morphological operations (comprising erosion and dilation) 315 are carried out. Analysis 320 is carried out by the controller 150. If a number of salient pixels is greater than a threshold, then a saliency event is identified and the imaging system 100 switches to the object segmentation mode 330. In the object segmentation mode 330, saliency detection and saliency gated image readout 335 are carried out. Following image readout, object recognition 340 is carried out, using, for example a neural network. If an object of interest is detected, the imaging system 100 switches to the full imaging mode 350. In the full imaging mode 350, standard rolling shutter image readout 355 is carried out and recording and transmission 360 of the captured images is carried out if required. As shown in FIG.3, in the saliency detection mode 310, no analog to digital converter (ADC) readout is carried out. In the object segmentation mode 330, saliency gated ADC readout is carried out. In the full imaging mode 350, full ADC readout is carried out.

[0051] FIG.4A to FIG.4F are images showing an example of event detection. FIG.4A shows the original image which is a grayscale image 240 x 320 (QVGA) of an outdoor scenario. The outdoor scenario shown in FIG.4A is noisy scenario. FIG.4B shows a frame difference 30 x 40 binary image. The image shown in FIG.4B is not suitable for object recognition or segmentation. FIG.4C shows an image with background subtraction again as a 30 x 40 binary image. As can be seen from FIG.4C, a large object corresponding to the boat can be seen, however, the image includes lots of noise due to movement in the water. FIG.4D shows the background subtraction image with erosion as a 30 x 40 binary image. As can be seen from FIG.4D, the erosion operation reduces the amount of noise, but it also trims the object making segmentation difficult. FIG.4E shows an image with background subtraction with erosion and dilation as a 30 x 40 binary image. As can be seen from FIG.4E, the erosion and dilation operations preserve the object size. FIG.4F shows object segmentation of a 240 x 230 image using the saliency map shown in FIG.4E. As can be seen in FIG.4F, the object can be recognized.

[0052] FIG.5 shows to graphs illustrating the potential power saving by pixel readout suppression.

[0053] The left hand graph shows a scenario in which background subtraction and erosion are carried out and the right hand graph shows a scenario in which background subtraction, erosion and dilation are carried out. Since pixel readout (analog to digital conversion) is often the power bottleneck in an image sensor, readout suppression can improve the energy efficiency of the always-on imager sensor significantly. Saliency-gated conversion in OS mode can reduce the number of required pixel readouts by two orders of magnitude (-128X) compared to standard imaging mode, and 6.14X compared to saliency-gated full image readout (with erosion).

[0054] FIG.6A shows a pixel circuit of an imaging system according to an embodiment of the present invention. The pixels are formed in an 8x8 pixel tile 605 with 64 pixels connected together. Each pixel of the tile 605 comprises 8 transistors split into a group of four transistors 610 for pixel readout which comprise a standard 3T pixel configuration 61 1 -613 with an additional pass transistor 614 for full-tile pixel aggregation. Each pixel comprises a photodiode PD which generates a current in response to incident light. The voltage Vtiie output to a shared tile circuit. The pixel output voltage V pixel is sent to an analog digital converter (ADC) for conversion when the ADC is activated.

[0055] Four additional transistor form distributed saliency detection circuit 620. The saliency detection circuit functions such that a tile is deemed to be salient if the difference of the aggregated pixel value and its background (long term average) exceeds a threshold. The saliency detection circuit 620 comprises a source follower 621 , a switched capacitor circuit 622 and an analog memory 625. The analog memory comprises a dynamic source follower 626.

[0056] The distributed saliency detection circuit 620 comprises a switch GS_R which is used to hard-reset the photodiodes globally before a soft reset and integration of the outputs each individual pixel. The source follower 621 integrates Vtiie such that its output Vsampie = Vtiie + A.

[0057] After photocurrent integration, the aggregated photodiode voltage Vsampie is sampled on capacitor Csampie via the clock-gated source follower 621 , and then checked whether it is in the vicinity of its long-term average Vmem stored by the capacitor Cmem of the sample capacitor circuit 622 (comparisons C1 and C2 with Vmem ± (Vthp-Vthn), where (Vthp-Vthn) is a threshold).

[0058] C1 = (Vsampie — Vmemc) > (Vthn — Vthp)

[0059] C2 = (Vsampie — Vmemc) > (Vthp — Vthn) The switch S_U is turned on for memory update. The switched capacitor circuit has a tunable memory update factor a.

[0060] KnemG + 1)—(1 — Ct) X Vsampie+ Ct X Vmem(T) a can be tuned by changing the number of switched capacitor cycles, N.

[0061] The analog memory 625 functions to update Vmem with Vsampie by charge sharing. The analog memory 625 is coupled to the capacitor Csampieby a large length stacked switch S_LL and a small stacked switch S_LI. The large length stacked switch S_LL is provided to reduce leakage. The small switch has a half width dummy and is turned off before the large length switch and turned on after the large length switch to reduce charge injection. The large length stacked switch and the small switch may be implemented as low leakage PMOS transistors. As shown in FIG.6A, the bodies of the low-leakage PMOS transistors may be biased to V_mem + A during the inactive state and to VDDA otherwise.

[0062] FIG.6B shows a comparator circuit of an imaging system according to an embodiment of the present invention. The comparator circuit 630 comprises a clock-gated preamplifier 632 with input-referred auto-zeroing switches, followed by a latch 634. Autozeroing switches 631 are configured to connect to Vthp (Vthn) during C1 (C2), effectively injecting a programmable offset (Vthp-Vthn) in the comparator while simultaneously cancelling the inherent offset due to mismatch. The comparator output for both C1 and C2 is then digitally processed and stored in a tile-level flip-flop.

[0063] FIG.6C shows a tile level flip-flop circuit of an imaging system according to an embodiment of the present invention. The flip flop circuit 640 takes the outputs OUTP and OUTN from the latch 634 of the comparator circuit 630 and generates Qij as

[0064] Qi, = Cl 4- C2 The current sample voltage Vsampie is incorporated into the new long-term average Vmem for the next iteration via charge sharing between Cmem and Csampie, whose ratio sets the minimum update weight of Vsampie. The update weight of Vsampie can be increased via the number of cycles of the switched capacitor circuit 622.

[0065] FIG.7 is a graph showing an example background subtraction operation in an embodiment of the present invention.

[0066] As shown in FIG.7, an event is detected when |Vmem - VSampie| > A. Here A = |Vthn - VthP|. Activity is only detected when changes exceed the controllable threshold. Small changes are not classified as an event. A pixel is remains salient (i.e. Qij is high) until |V mem - Vsampie| becomes less than A.

[0067] The robustness of the above background subtraction is improved by post-processing the above saliency map (outputs of all the above comparisons) via in-sensor morphological filters. In most scenarios, post-processing with erosion (with a fixed optimal threshold of 9) offers significant reduction in the activity caused by background motion. However, using only erosion also reduces the size of the detected object and often introduces gaps / holes within the same object. This issue is here alleviated by performing the complementary transformation of dilation after erosion, restoring the original size of the detected object.

[0068] The erosion operation is carried out using the following morphological filter:

[0069] The dilation operation is carried out using the following morphological filter:

[0070] Using the fixed threshold of 9 simplifies the circuit to NOR / NAND logic shown in FIG.8. The width may be programmable by running multiple cycles of erosion and dilation. The size of the erosion and dilation operations may be configurable by running the operations multiple times. The minimum size for these filers is 3x3, which is the size when the filter is run once. When we run the same filter twice, the filter size increases from 3x3 to 3x3, and so on. For generalization, when erosion / dilation is run consecutively N times, the size of the filter becomes (2N+1 )x(2N+1 ).

[0071] The size of the filters may be configured by a user of the imaging system.

[0072] FIG.8 shows a post processing circuit of an imaging system according to an embodiment of the present invention. The post processing circuit may also be referred to as a segmentation circuit.

[0073] As shown in FIG.8, the post processing circuit 800 comprises two input multiplexers 802 804, a three input NOR 806, a three input NAND 808 and an output multiplexer 810. It is notable that the post processing circuit shown in FIG.8 allows an erosion operation and a transformation operation to be implemented in a relatively simple circuit. Moreover, it was also found that the dilation operation using the complementary threshold of erosion (as required to restore object size) can be implemented with the very same circuit, thus allowing its full reuse and simplification for both erosion and dilation.

[0074] FIG.9A shows a column pixel readout circuit of an imaging system according to an embodiment of the present invention.

[0075] The column pixel readout circuit 910 takes the saliency readout Qpfrom the pixel array as input. This is fed into a flip-flop 912. The output Q from the flip flop 912 is connected to a level shifter 914 which if connected to two AND gates 916. When operating in OS mode, before digitizing a given pixel, the saliency output coming from its tile is first locally stored in the flip-flop 912 that gates the pre-amp enable Gated_P and the latch clock Gated_LA signals.

[0076] FIG.9B shows a saliency gated analog digital converter circuit of an imaging system according to an embodiment of the present invention. The saliency gated analog digital converter circuit 920 takes the pixel readout Vrow from the pixel array as input. A parasitic capacitance Cparform the row lead line is used to store a pixel reset voltage Vr.

[0077] The saliency gated analog digital converter circuit 920 comprises a pre-amplifier 922, a latch 924 and an asynchronous counter 926. The inverting input of the pre-amplifier is switchably connected to a ramp signal VRAMP from a global ramp generator. As shown in FIG.9B, anti-zeroing switches S_AZA are provided for cancelling mismatch induced offset in the pre-amplifier 922. The non-inverting input to the pre-amplifier 922 is coupled to a capacitor Ccds for storing the pixel voltage signal Vs.

[0078] The latch 924 generates a clock pulse until Vr - Vs> VRAMP. The asynchronous counter 926 provides a final analog to digital conversion output as count. The input S_RR on the asynchronous counter 926 resets the count before conversion starts.

[0079] When operating in OS mode, before digitizing a given pixel, the saliency output coming from its tile is first locally stored in a flip-flop that gates the pre-amp enable and the latch clock signals. In case the pixel is salient, the saliency-gated single-slope (SS) ADC digitizes the difference of the pixel sample voltage Vs (as read out from the row line) and its reset voltage Vr (similar to Correlated Double Sampling, used to cancel offset). For non-salient pixels, the comparator in the SS-ADC is simply disabled to inhibit digitization, while also suppressing object-segmented image memory write. A ‘0’ stored in the saliency map will simply force a ‘0’ in later read of this memory.

[0080] FIG.10 is a timing diagram for the saliency detection circuit. As shown in FIG.10, GS is the input to the gate of the pass transistor 614 of the pixel circuit shown in FIG.6A and GS_R is the hard reset signal. When GS_R goes high, all of the pixels are reset and integration on the photodiode proceeds while GS is high. The larger stacked switch S_LL is closed followed by the smaller stacked switch S_LI. While S_SA is high, the value Vsampie is stored on the capacitor Csampie The switches AZ1 and AZ2 cancel offset and injecting the threshold in the comparator circuit 630. The signal S_PA turns the preamplifier 632 on and off. The switch S_C connects the inputs to the comparator circuit 630. S-L is the comparator latch signal. S_LF signals the first comparison (C1 ). S_FF is the FF clock signal. SJJ is the update signal for charge sharing between Csampie and Cmem. S_OP and S_VH carry erosion and dilation on the background subtraction output.

[0081] FIG.11 is a timing diagram for the saliency gated column pixel readout circuit. FIG.11 shows salient pixel readout (Qp=1 ) and Non-salient pixel readout suppression (Qp=0). As shown in FIG.11 , the signal Gated_P suppresses the pre-amplifier for non-salient pixels. Similarly, the latch clock Gated_LA is also suppressed for non-salient pixels. As shown at the bottom of FIG.11 , the voltage VRAMP gradually increases and Vp and Count are stopped after VRAMP crosses Vr-Vs.

[0082] FIG.12 shows a comparison of saliency detection with and without morphological filters. As shown in FIG.12, with background subtraction alone noise may be introduced by motion in the background. Combining background subtraction and erosion reduces this noise however, the erosion operation may introduce gaps in objects and remove object edges making object recognition impossible. If a dilation operation is carried out after the erosion operation, object size is recovered and object recognition is possible.

[0083] FIG.13 is a graph showing power measurements for different operating modes of an imaging system according to an embodiment of the present invention. As shown in FIG.13, the power consumption for object segmentation (OS) is 38.6 times less than that for full imaging (IM) and the power consumption for saliency detection (SD) is 2.1 time less than that for object segmentation (OS). Thus the saliency gated operation of embodiments of the present disclosure provide a significant power reduction.

[0084] FIG.14 shows alert generation in different saliency detection operations. As shown in FIG.14, saliency detection with erosion and dilation provides significantly fewer alerts compared to saliency detection alone. Further, the alerts generally correspond to those of the ground truth so no events are missed. Generating fewer alerts means that there are fewer activations of the object recognition neural network.

[0085] FIG.15 shows pixel activity comparison for different saliency operations. As shown in FIG.15, with background subtraction alone, there are a larger number of active (salient) pixels, this may be due to background motion such as water causing redundant alerts. The use of erosion and dilation reduces the number of active (salient) pixels to close to the ground truth level. Whilst the foregoing description has described exemplary embodiments, it will be understood by those skilled in the art that many variations of the embodiments can be made within the scope and spirit of the present invention.

Claims

CLAIMS1 . An imaging system comprising: a pixel array having a plurality of pixels, each pixel comprising a light sensor configured to generate a pixel signal in response to light incident on the pixel; a saliency detection circuit configured to detect salient events tram the pixel signals; and a segmentation circuit configured to segment salient pixels by performing erosion and dilation operations on pixels corresponding to the salient events2. The imaging system according to claim 1 , wherein the saliency detection circuit is configured to perform background subtraction to detect salient events.

3. The imaging system according to claim 1 or claim 2, wherein the saliency detection circuit is configured to detect a salient event if a number of salient pixels exceeds a threshold.

4. The imaging system according to any preceding claim, further comprising an analog to digital converter configured to generate digital signals using the pixel signals; and a controller configured to activate the analog to digital converter in response to the salient events.

5. The imaging system according to any preceding claim, wherein the pixel array comprises a plurality of tiles each comprising a plurality of clusters.

6. The imaging system according to claim 5, wherein the saliency detection circuit is configured to detect salient events within each tile.

7. The imaging system according to any preceding claim, wherein the segmentation circuit comprises a three input NOR gate and a three input NAND gate.

8. The imaging system according to any preceding claim, wherein the erosion operation and the dilation operation are performed using complementary thresholds.

9. The imaging system according any preceding ciaim wherein each pixel comprises four common transistors.

10. The imaging system according to any preceding claim, wherein a size of the erosion and dilation operations is configurable.

11. The imaging system according to claim 10, wherein the size of the erosion operation and the dilation operation is configured adjusting a number ot times which the respective operation is run.

12. An imaging method comprising: detecting salient events in analog pixel signals from a plurality of pixels; and segmenting salient pixels by performing an erosion operation and a dilation operation on pixels corresponding to the salient events.

13. The imaging method according to claim 12, further comprising: activating an analog to digital converter in response to the salient events; and converting analog pixel signals from the segmented salient pixels into digital pixel signals.

14. The imaging method according to claim 13, further comprising: identifying an object of interest in the segmented salient pixels using the digital pixel signals.

15. The imaging method according to any one of claims 12 to 14, wherein the erosion operation and the dilation operation are performed using complementary thresholds.

16. The imaging method according to any one of claims 12 to 15, wherein a saliency map is generated from the salient events and the saliency map is segmented by performing the erosion operation and the dilation operation.

17. The imagining method according to any one of claims 12 to 16, wherein a salient event is detected when a number of salient pixels exceeds a threshold.

18. The imaging method according to any one of claims 12 to 17, wherein a size of the erosion operation and the dilation operation is configurable.

19. The imaging method according to claim 18, wherein the size of the erosion operation and the dilation operation is configured adjusting a number of times which the respective operation is run.

Images