Scanning-signal-line drive circuit and display device equipped with same

Abstract

The present invention implements a scanning-signal-line drive circuit that enables high-speed driving without reducing display quality.　The scanning-signal-line drive circuit comprises a shift register (401) that is operated on the basis of six gate clock signals GCK1-GCK6 forming three sets of two-phase clocks. A plurality of unit circuits (4) forming the shift register (401) form a block for every six consecutive unit circuits (4). For every block, six consecutives unit circuits (4) are each imparted with a different gate clock signal as a scan-signal-line driving clock signal in a similar manner. Using such a configuration, the shift register (401) is imparted with gate start pulses GSP such that, during each of vertical scanning periods, each of the unit circuits (4) outputs write pulses three times at, for example, intervals of eight horizontal scanning periods.

Description

Scanning signal line driving circuit and display device including same

[0001] The following disclosure relates to a display device, and more particularly to a scanning signal line driving circuit that drives scanning signal lines arranged in a display unit of the display device.

[0002] In recent years, organic EL display devices equipped with pixel circuits including organic EL elements have been put to practical use. Organic EL elements, also known as OLEDs (organic light-emitting diodes), are self-luminous display elements that emit light at a brightness corresponding to the current flowing through them. Because organic EL elements are self-luminous display elements, organic EL display devices can be easily made thinner, consume less power, and have higher brightness than liquid crystal display devices that require a backlight, color filters, etc.

[0003] In pixel circuits of organic EL display devices, thin-film transistors (TFTs) are typically used as drive transistors for controlling the supply of current to organic EL elements. However, thin-film transistors are prone to variations in their characteristics. Specifically, variations in threshold voltage are likely to occur. Threshold voltage variations in drive transistors provided within a display unit result in variations in brightness, thereby degrading display quality. Therefore, various processes (compensation processes) have been proposed to compensate for threshold voltage variations. Known compensation processes include an internal compensation process, which performs compensation by providing a capacitor within the pixel circuit to retain information about the threshold voltage of the drive transistor, and an external compensation process, which performs compensation by, for example, measuring the magnitude of the current flowing through the drive transistor under specified conditions using a circuit external to the pixel circuit and correcting the video signal based on the measurement results. A pixel circuit of an organic EL display device employing internal compensation for compensation is composed of, for example, one organic EL element OL, seven transistors T1 to T7, and one retention capacitor Cst (see FIG. 3 ).

[0004] While typical display devices have a frame rate of 120 Hz, in recent years, there has been an increasing demand for higher-speed drive, such as a frame rate of 240 Hz, for display devices used in games, for example. However, when the frame rate is increased in organic EL display devices such as those described above, if a driving method known as "single-pulse driving" is adopted, in which a write pulse for turning on the write control transistor T3 (see FIG. 3 ) in the pixel circuit to write a data voltage to the pixel circuit is generated only once per row per vertical scanning period, it may take several frames to reach the target luminance when the display screen is switched. Taking several frames to reach the target luminance results in poor video display. Therefore, organic EL display devices have been proposed that employ a driving method known as "multi-pulse driving" (a driving method in which the write pulse is generated multiple times per row per vertical scanning period) to quickly achieve the target luminance. For example, paragraphs 0402 to 0434 of Japanese Patent Publication No. 2018-112741 describe the configuration of a scanning signal line driving circuit that achieves multi-pulse driving. In the following description, a driving method in which a write pulse is generated K times for each row in each vertical scanning period, where K is a natural number, will be referred to as "K pulse driving."

[0005] FIG. 15 shows a waveform diagram equivalent to that shown in FIG. 22B of Japanese Patent Application Laid-Open No. 2018-112741. In FIG. 15, FLM1 is a start pulse, CLK1 to CLK4 are clock signals, and G10 to G13 are scanning signals. Clock signals CLK1 and CLK2 are 180 degrees out of phase with each other, and clock signals CLK3 and CLK4 are 180 degrees out of phase with each other. Clock signals CLK1 and CLK3 are in phase with each other, and clock signals CLK2 and CLK4 are in phase with each other. As described above, the four clock signals CLK1 to CLK4 constitute two sets of two-phase clocks. In FIG. 15, for example, the write pulse denoted by reference numeral 91 is output based on clock signal CLK2, and the write pulse denoted by reference numeral 92 is output based on clock signal CLK4. For example, the write pulse denoted by reference numeral 93 is output based on clock signal CLK1, and the write pulse denoted by reference numeral 94 is output based on clock signal CLK3. In this way, two write pulses output to different rows at the same timing are generated based on two different clock signals of the same phase. In contrast, if only one set of two-phase clocks is used as the clock signal, two write pulses output to different rows at the same timing are generated based on one clock signal. From the above, it can be seen that using two sets of two-phase clocks reduces the drive load per clock signal compared to using only one set of two-phase clocks. In other words, using two sets of two-phase clocks makes it possible to increase the frame rate while suppressing degradation in display quality.

[0006] Japanese Patent Publication No. 2018-112741

[0007] However, the configuration disclosed in Japanese Patent Application Laid-Open No. 2018-112741 does not sufficiently reduce the driving load of the clock signal. This will be explained below.

[0008] According to the above configuration, the waveforms of scanning signals G10 to G17 are as shown in FIG. 16. From FIG. 16, it can be seen that three write pulses are output at the same timing. In this regard, for example, the write pulses labeled 901 and 903 are output based on clock signal CLK2, and the write pulse labeled 902 is output based on clock signal CLK4. Furthermore, for example, the write pulse labeled 912 is output based on clock signal CLK1, and the write pulses labeled 911 and 913 are output based on clock signal CLK3. In this way, two of the three write pulses output at the same timing are generated based on one clock signal.

[0009] For example, the configuration related to the output of the three write pulses denoted by reference numerals 901 to 903 in FIG. 16 is schematically shown in FIG. 17. In FIG. 17, with regard to the unit circuits constituting the shift register included in the scanning signal line driving circuit, the unit circuits that output the scanning signals G10, G12, and G14 are denoted by reference numerals 9(10), 9(12), and 9(14), respectively. Furthermore, although each unit circuit includes a large number of transistors, FIG. 17 shows only a buffer transistor 95. From FIG. 17, it can be seen that the drive load of the clock signal CLK2 at the timing of outputting the three write pulses denoted by reference numerals 901 to 903 in FIG. 16 is the sum of the load of the wiring 96 for the clock signal CLK2, the load of the wiring (scanning signal line) 97 for the scanning signal G10, and the load of the wiring (scanning signal line) 98 for the scanning signal G14.

[0010] As described above, according to the configuration disclosed in Japanese Patent Application Laid-Open No. 2018-112741, two write pulses to be output at the same timing must be generated based on a single clock signal. In this case, the driving load of the clock signal that generates the two write pulses increases. Therefore, there is a concern that a delay in the scanning signal (write pulse) may cause a decrease in display quality when the frame rate is increased.

[0011] Therefore, the following disclosure aims to realize a scanning signal line driving circuit that enables high-speed driving without degrading the display quality.

[0012] A scanning signal line driving circuit according to some embodiments of the present disclosure is a scanning signal line driving circuit for driving a plurality of scanning signal lines, the scanning signal line driving circuit comprising a shift register made up of a plurality of unit circuits cascade-connected to each other, which operate based on a start pulse and (K×2) clock signals constituting K sets of two-phase clocks, where K is an integer equal to or greater than 3, each of the plurality of unit circuits including a buffer transistor having a first conduction terminal to which one of the (K×2) clock signals is supplied as a scanning signal line driving clock signal and a second conduction terminal connected to a corresponding scanning signal line, the start pulse is supplied to the shift register such that K write pulses are output from each unit circuit to a corresponding scanning signal line based on the scanning signal line driving clock signal in each vertical scanning period, each set of two-phase clocks is made up of a clock signal of a first waveform and a clock signal of a second waveform that is 180 degrees out of phase with the clock signal of the first waveform, and the first waveform clock signal is supplied to odd-numbered unit circuits of the plurality of unit circuits as the scanning signal line driving clock signal, The clock signal of the second waveform is supplied to even-numbered unit circuits among the plurality of unit circuits as the scanning signal line driving clock signal, the plurality of unit circuits are configured into blocks each consisting of (K×2) consecutive unit circuits, and each of the (K×2) consecutive unit circuits is supplied with a mutually different clock signal from the (K×2) clock signals as the scanning signal line driving clock signal, and in all blocks, one of the (K×2) clock signals is supplied to each of the (K×2) consecutive unit circuits in the same manner as above as the scanning signal line driving clock signal.

[0013] According to some embodiments of the present disclosure, multiple scanning signal lines are driven based on (K×2) clock signals constituting K sets of two-phase clocks, where K is an integer greater than or equal to three. The multiple unit circuits constituting the shift register are organized into blocks, each consisting of a group of (K×2) consecutive unit circuits, each of which receives a different clock signal as a scanning signal line driving clock signal. Furthermore, the method of providing the scanning signal line driving clock signal to the consecutive (K×2) unit circuits is the same for all blocks. With this configuration, a start pulse is provided to the shift register so that K write pulses are output from each unit circuit during each vertical scanning period. In this regard, the above configuration allows a start pulse to be provided to the shift register so that K write pulses output at the same timing are generated based on K different clock signals. This configuration, in which K write pulses output at the same timing are generated based on K different clock signals, reduces the driving load of the clock signals compared to conventional configurations. Therefore, it is possible to increase the frame rate without causing a delay in the scanning signal (write pulse). As described above, a scanning signal line driving circuit is realized that enables high-speed driving without degrading the display quality.

[0014] 1 is a diagram for explaining features of an embodiment. It is a block diagram showing the overall configuration of a display device according to the embodiment. It is a circuit diagram showing the configuration of a pixel circuit according to the embodiment. It is a timing chart showing the operation of a pixel circuit according to the embodiment. It is a block diagram showing a schematic configuration of a scanning side driving circuit according to the embodiment. It is a block diagram showing a schematic configuration of a scanning signal line driving circuit according to the embodiment. It is a block diagram showing a detailed configuration of a shift register according to the embodiment. It is a waveform diagram of a gate clock signal according to the embodiment. It is a diagram showing that a block is configured for every six consecutive unit circuits according to the embodiment. It is a circuit diagram showing the configuration of a unit circuit according to the embodiment. It is a timing chart showing the operation of a unit circuit according to the embodiment. It is a signal waveform diagram showing a method of driving a scanning signal line according to the embodiment. It is a diagram showing the connection relationship between each of three unit circuits that output write pulses at the same timing and each signal line according to the embodiment. It is a diagram schematically showing a configuration related to the output of three write pulses that occur at the same timing according to the embodiment. It is a waveform diagram equivalent to the waveform diagram shown in FIG. 22B of Japanese Patent Application Laid-Open No. 2018-112741. It is a diagram showing the reason why the drive load of the clock signal is insufficient in the conventional example. 10A and 10B are diagrams for explaining why the driving load of a clock signal is not sufficiently reduced in the conventional example.

[0015] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0016] 2 is a block diagram showing the overall configuration of a display device 10 according to one embodiment. The display device 10 is an organic EL display device that performs internal compensation. That is, in the display device 10, each pixel circuit 15 has a function of compensating for variations and fluctuations in the threshold voltage of the drive transistor therein.

[0017] As shown in FIG. 2 , the display device 10 includes a display unit 11, a display control circuit 20, a data-side drive circuit 30, a scanning-side drive circuit 40, and a power supply circuit 50. The data-side drive circuit 30 functions as a data signal line drive circuit (source driver). The scanning-side drive circuit 40 functions as a scan signal line drive circuit (gate driver) and a light-emitting control circuit (emission driver). In the example shown in FIG. 2 , the scanning-side drive circuit 40 is disposed only to the left of the display unit 11, but the scanning-side drive circuit 40 may be disposed on both the left and right sides of the display unit 11. Furthermore, at least a portion of the data-side drive circuit 30 and the scanning-side drive circuit 40 may be formed integrally with the display unit 11. The power supply circuit 50 generates a high-level power supply voltage ELVDD, a low-level power supply voltage ELVSS, and an initialization voltage Vini to be supplied to the display unit 11, as well as power supply voltages (not shown) to be supplied to the display control circuit 20, the data-side drive circuit 30, and the scanning-side drive circuit 40.

[0018] The display unit 11 is provided with m data signal lines D(1) to D(m), (n+2) first scanning signal lines NS(-1) to NS(n), n second scanning signal lines PS(1) to PS(n), and n light-emission control lines EM(1) to EM(n), which intersect with the data signal lines D(1) to D(m). The first scanning signal lines NS(-1) to NS(n), the second scanning signal lines PS(1) to PS(n), and the light-emission control lines EM(1) to EM(n) are typically parallel to one another. The first scanning signal lines NS(-1) to NS(n) and the data signal lines D(1) to D(m) are perpendicular to one another. Hereinafter, as necessary, the data signals respectively given to the data signal lines D(1) to D(m) will also be given the symbols D(1) to D(m), the first scanning signals respectively given to the first scanning signal lines NS(-1) to NS(n) will also be given the symbols NS(-1) to NS(n), the second scanning signals respectively given to the second scanning signal lines PS(1) to PS(n) will also be given the symbols PS(1) to PS(n), and the light emission control signals respectively given to the light emission control lines EM(1) to EM(n) will also be given the symbols EM(1) to EM(n).

[0019] Furthermore, n×m pixel circuits 15 are provided in the display unit 11 at intersections between the n first scanning signal lines NS(1) to NS(n) and the m data signal lines D(1) to D(m). By providing the n×m pixel circuits 15 in this manner, a pixel matrix of n rows and m columns is formed in the display unit 11.

[0020] Furthermore, the display unit 11 is provided with power supply lines (not shown) that are common to each pixel circuit 15. More specifically, a power supply line (hereinafter referred to as a "high-level power supply line") that supplies a high-level power supply voltage ELVDD for driving the organic EL elements, a power supply line (hereinafter referred to as a "low-level power supply line") that supplies a low-level power supply voltage ELVSS for driving the organic EL elements, and a power supply line (hereinafter referred to as an "initialization power supply line") that supplies an initialization voltage Vini for initializing each pixel circuit 15 are provided.

[0021] The display control circuit 20 receives an input signal Sin from outside the display device 10, which includes image information representing an image to be displayed and timing control information for image display, and outputs a data-side control signal Scd that controls the operation of the data-side drive circuit 30 and a scan-side control signal Scs that controls the operation of the scan-side drive circuit 40. The data-side drive circuit 30 applies data signals to the data signal lines D(1) to D(m) based on the data-side control signal Scd output from the display control circuit 20. The scan-side drive circuit 40 applies first scan signals to the first scan signal lines NS(-1) to NS(n), applies second scan signals to the second scan signal lines PS(1) to PS(n), and applies light-emission control signals to the light-emission control lines EM(1) to EM(n), based on the scan-side control signal Scs output from the display control circuit 20.

[0022] As described above, a data signal is applied to the data signal lines D(1) to D(m), a first scanning signal is applied to the first scanning signal lines NS(-1) to NS(n), a second scanning signal is applied to the second scanning signal lines PS(1) to PS(n), and a light emission control signal is applied to the light emission control lines EM1(1) to EM1(n), whereby an image based on the input signal Sin is displayed on the display unit 11.

[0023] 3 is a circuit diagram showing the configuration of the pixel circuit 15 in this embodiment. Note that attention is focused here on the pixel circuit 15(i, j) in the i-th row and j-th column. The configuration of the pixel circuit 15 shown here is an example, and the configuration is not limited to this.

[0024] The pixel circuit 15(i,j) is connected to the first scanning signal line NS(i-2), the first scanning signal line NS(i), the second scanning signal line PS(i), the light emission control line EM(i), the data signal line D(j), the high-level power supply line, the low-level power supply line, and the initialization power supply line.

[0025] Each pixel circuit 15(i,j) includes one organic EL element (organic light-emitting diode) OL as a display element, seven transistors (typically thin-film transistors) T1 to T7 (initialization transistor T1, threshold compensation transistor T2, write control transistor T3, drive transistor T4, first light-emission control transistor T5, second light-emission control transistor T6, and reset transistor T7), and one storage capacitor Cst. The storage capacitor Cst is a capacitive element consisting of two electrodes (a first electrode and a second electrode). As can be seen from FIG. 3 , the first light-emission control transistor T5, the drive transistor T4, the second light-emission control transistor T6, and the organic EL element OL are connected in series. In the pixel circuit 15(i,j), the transistors T1 to T3 and T5 to T7, other than the drive transistor T4, function as switching elements.

[0026] The initialization transistor T1 has a control terminal connected to the first scanning signal line NS(i-2), a first conduction terminal connected to the second conduction terminal of the threshold compensation transistor T2, the control terminal of the drive transistor T4, and the second electrode of the hold capacitor Cst, and a second conduction terminal connected to the initialization power supply line. The threshold compensation transistor T2 has a control terminal connected to the first scanning signal line NS(i), a first conduction terminal connected to the first conduction terminal of the drive transistor T4 and the second conduction terminal of the second light-emitting control transistor T6, and a second conduction terminal connected to the first conduction terminal of the initialization transistor T1, the control terminal of the drive transistor T4, and the second electrode of the hold capacitor Cst. The write control transistor T3 has a control terminal connected to the second scanning signal line PS(i), a first conduction terminal connected to the second conduction terminal of the drive transistor T4 and the first conduction terminal of the first light-emitting control transistor T5, and a second conduction terminal connected to the data signal line D(j). As for the driving transistor T4, the control terminal is connected to the first conduction terminal of the initialization transistor T1, the second conduction terminal of the threshold compensation transistor T2, and the second electrode of the holding capacitor Cst, the first conduction terminal is connected to the first conduction terminal of the threshold compensation transistor T2 and the second conduction terminal of the second light-emitting control transistor T6, and the second conduction terminal is connected to the first conduction terminal of the write control transistor T3 and the first conduction terminal of the first light-emitting control transistor T5.

[0027] The first light-emission control transistor T5 has a control terminal connected to the light-emission control line EM(i), a first conduction terminal connected to the first conduction terminal of the write control transistor T3 and the second conduction terminal of the drive transistor T4, and a second conduction terminal connected to the high-level power supply line. The second light-emission control transistor T6 has a control terminal connected to the light-emission control line EM(i), a first conduction terminal connected to the first conduction terminal of the reset transistor T7 and the anode electrode of the organic EL element OL, and a second conduction terminal connected to the first conduction terminal of the threshold compensation transistor T2 and the first conduction terminal of the drive transistor T4. The reset transistor T7 has a control terminal connected to the light-emission control line EM(i), a first conduction terminal connected to the first conduction terminal of the second light-emission control transistor T6 and the anode electrode of the organic EL element OL, and a second conduction terminal connected to the initialization power supply line.

[0028] The first electrode of the storage capacitor Cst is connected to the high-level power supply line, and the second electrode is connected to the first conduction terminal of the initialization transistor T1, the second conduction terminal of the threshold compensation transistor T2, and the control terminal of the drive transistor T4. The anode electrode of the organic EL element OL is connected to the first conduction terminal of the second light-emission control transistor T6 and the first conduction terminal of the reset transistor T7, and the cathode electrode is connected to the low-level power supply line.

[0029] In the pixel circuit 15(i,j) of this embodiment, transistors T1, T2, and T7 are N-type transistors, and transistors T3 to T6 are P-type transistors. The N-type transistors T1, T2, and T7 are, for example, oxide TFTs (thin film transistors using an oxide semiconductor as the material for the channel layer), and the P-type transistors T3 to T6 are, for example, LTPS-TFTs (thin film transistors using low-temperature polysilicon as the material for the channel layer). Such pixel circuit 15(i,j) takes advantage of the advantages of oxide TFTs, such as low leakage current, and LTPS-TFTs, such as high mobility, making it possible to display high-resolution images with low power consumption.

[0030] Next, the operation of the pixel circuit 15(i,j) in the i-th row and j-th column will be described with reference to the timing chart shown in Figure 4. Just before time t1, the light-emission control signal EM(i) is at a low level, and the first light-emission control transistor T5 and the second light-emission control transistor T6 are in an on state. Therefore, a current flows through the organic EL element OL, and the pixel circuit 15(i,j) is in an emitting state.

[0031] When the light-emission control signal EM(i) changes from low to high at time t1, the first light-emission control transistor T5 and the second light-emission control transistor T6 change from an on state to an off state. While the light-emission control signal EM(i) is maintained at a high level, the first light-emission control transistor T5 and the second light-emission control transistor T6 are maintained in an off state. Therefore, during periods t1 to t8, no current flows through the organic EL element OL, and the pixel circuit 15(i,j) is in a non-light-emitting state. Furthermore, during periods t1 to t8 when the pixel circuit 15(i,j) is in a non-light-emitting state (non-light-emitting period), the reset transistor T7 is maintained in an on state, thereby initializing the anode voltage of the organic EL element OL.

[0032] When the first scanning signal NS(i-2) changes from low to high at time t2, the initialization transistor T1 changes from off to on. While the first scanning signal NS(i-2) is maintained at high level, the initialization transistor T1 is maintained in the on state. During the period (initialization period) t2 to t3 when the initialization transistor T1 is in the on state, the holding capacitor Cst is initialized, and the voltage Vg (hereinafter referred to as the "gate voltage") of the control terminal (gate terminal) of the drive transistor T4 becomes the initialization voltage Vini.

[0033] After the first scanning signal NS(i-2) changes from high to low at time t3, the first scanning signal NS(i) changes from low to high at time t4. This causes the threshold compensation transistor T2 to change from an off state to an on state. While the first scanning signal NS(i) is maintained at a high level, the threshold compensation transistor T2 is maintained in an on state, and the drive transistor T4 is in a diode-connected state.

[0034] When the second scanning signal PS(i) changes from high to low at time t5, the write control transistor T3 changes from an off state to an on state. While the second scanning signal PS(i) is maintained at a low level, the write control transistor T3 is maintained in an on state. During the period from t5 to t6 when the write control transistor T3 is in an on state (hereinafter referred to as the "data write period"), the voltage of the data signal D(j) is applied as a data voltage to the holding capacitor Cst via the diode-connected driving transistor T4. As a result, the threshold-compensated data voltage is written to the holding capacitor Cst, and the gate voltage Vg (the voltage at the control terminal of the driving transistor T4) is maintained at the voltage of the second electrode of the holding capacitor Cst. If the data voltage is represented by Vdata and the threshold voltage of the driving transistor T4 is represented by Vth (<0), the gate voltage Vg at this time is expressed by the following equation (1): Vg=Vdata+Vth (1) In this way, during the data writing period t5 to t6, the data voltage is written to the pixel circuit 15(i, j) while performing internal compensation.

[0035] When the first scanning signal NS(i) changes from high to low at time t7, the threshold compensation transistor T2 changes from on to off. When the light-emission control signal EM(i) changes from high to low at time t8, the first light-emission control transistor T5 and the second light-emission control transistor T6 change from off to on. This starts the light-emission period.

[0036] <3. Scanning Side Drive Circuit> <3.1 General Configuration> Fig. 5 is a block diagram showing a general configuration of the scanning side drive circuit 40 in this embodiment. The scanning side drive circuit 40 is composed of a scanning signal line drive circuit 410 and a light emission control circuit 450. The scanning signal line drive circuit 410 applies first scanning signals to the first scanning signal lines NS(-1) to NS(n) and applies second scanning signals to the second scanning signal lines PS(1) to PS(n). The light emission control circuit 450 applies light emission control signals to the light emission control lines EM(1) to EM(n).

[0037] <3.2 Scanning Signal Line Drive Circuit> A description will be given of the configuration of the scanning signal line drive circuit 410. Note that a known configuration can be adopted for the light emission control circuit 450, so detailed description of the configuration of the light emission control circuit 450 will be omitted.

[0038] 6 is a block diagram showing a schematic configuration of the scanning signal line drive circuit 410. As shown in FIG. 6, the scanning signal line drive circuit 410 in this embodiment includes a shift register 401 made up of (n+2) unit circuits 4(-1) to 4(n) that correspond one-to-one to the (n+2) first scanning signal lines NS(-1) to NS(n). The (n+2) unit circuits 4(-1) to 4(n) are cascade-connected to one another. Hereinafter, when the (n+2) unit circuits 4(-1) to 4(n) are not to be distinguished from one another, the unit circuits will be designated by the symbol 4.

[0039] The shift register 401 will be described in detail with reference to Fig. 7. Note that Fig. 7 shows only the unit circuits 4(1) to 4(6) in the first to sixth stages out of the (n+2) unit circuits 4(-1) to 4(n) that make up the shift register 401.

[0040] The shift register 401 receives a gate start pulse and six clock signals (first to sixth gate clock signals GCK1 to GCK6) as the scanning-side control signal Scs. The gate start pulse is a signal provided to the unit circuit 4(-1) in the -1st stage as the set signal S and is omitted in FIG. 7 . The shift register 401 also receives a gate low voltage VGL and a gate high voltage VGH. The gate low voltage VGL is a voltage level that turns N-type transistors off and P-type transistors on. The gate high voltage VGH is a voltage level that turns N-type transistors on and P-type transistors off. Furthermore, the shift register 401 receives a mode signal VM that distinguishes between write frames in which data voltages are written and pause frames in which data voltages are not written when pause driving (a driving method that provides a period during which the writing operation of data voltages to pixel circuits 15 is stopped) is employed. Since pause driving is not directly related to the disclosure of this specification, the operation of the pause frame will not be described below.

[0041] 8, with respect to the six clock signals provided to the shift register 401, the first gate clock signal GCK1 and the second gate clock signal GCK2 are shifted in phase by 180 degrees, the third gate clock signal GCK3 and the fourth gate clock signal GCK4 are shifted in phase by 180 degrees, and the fifth gate clock signal GCK5 and the sixth gate clock signal GCK6 are shifted in phase by 180 degrees. Also, as shown in FIG. 8, the first gate clock signal GCK1, the third gate clock signal GCK3, and the fifth gate clock signal GCK5 are in phase, and the second gate clock signal GCK2, the fourth gate clock signal GCK4, and the sixth gate clock signal GCK6 are in phase. As described above, the first to sixth gate clock signals GCK1 to GCK6 constitute three sets of two-phase clocks. Hereinafter, when the first to sixth gate clock signals GCK1 to GCK6 are not to be distinguished from one another, the gate clock signals are denoted by the symbol GCK.

[0042] Each unit circuit 4 includes input terminals for receiving the first control clock signal CK1, the second control clock signal CK2, the mode signal VM, the gate high voltage VGH, the gate low voltage VGL, and the set signal S, respectively, and output terminals for outputting the first output signal OUT1 and the second output signal OUT2, respectively (see FIG. 7 ). The first output signal OUT1 is a signal for controlling the states of the initialization transistor T1 and the threshold compensation transistor T2 in the pixel circuit 15, and the second output signal OUT2 is a signal for controlling the state of the write control transistor T3 in the pixel circuit 15.

[0043] To the first-stage unit circuit 4(1), the second gate clock signal GCK2 is provided as the first control clock signal CK1, and the first gate clock signal GCK1 is provided as the second control clock signal CK2. To the second-stage unit circuit 4(2), the first gate clock signal GCK1 is provided as the first control clock signal CK1, and the second gate clock signal GCK2 is provided as the second control clock signal CK2. To the third-stage unit circuit 4(3), the fourth gate clock signal GCK4 is provided as the first control clock signal CK1, and the third gate clock signal GCK3 is provided as the second control clock signal CK2. To the fourth-stage unit circuit 4(4), the third gate clock signal GCK3 is provided as the first control clock signal CK1, and the fourth gate clock signal GCK4 is provided as the second control clock signal CK2. For the fifth-stage unit circuit 4(5), the sixth gate clock signal GCK6 is provided as the first control clock signal CK1, and the fifth gate clock signal GCK5 is provided as the second control clock signal CK2. For the sixth-stage unit circuit 4(6), the fifth gate clock signal GCK5 is provided as the first control clock signal CK1, and the sixth gate clock signal GCK6 is provided as the second control clock signal CK2. This configuration is repeated for six stages. That is, in this embodiment, as shown in FIG. 9 , a block is formed for each of six consecutive unit circuits 4. In all blocks, one of the first to sixth gate clock signals GCK1 to GCK6 is provided as the first control clock signal CK1, and the other of the first to sixth gate clock signals GCK1 to GCK6 is provided as the second control clock signal CK2, to each of the six consecutive unit circuits 4 in the same manner.

[0044] The gate high voltage VGH, gate low voltage VGL, and mode signal VM are commonly supplied to all unit circuits 4. Furthermore, the second output signal OUT2 output from the unit circuit 4 of the previous stage is supplied as the set signal S to the unit circuit 4 of each stage. However, a gate start pulse is supplied as the set signal S to the unit circuit 4 (-1) of the -1st stage. The first output signal OUT1 output from the unit circuit 4 of each stage is supplied to the first scanning signal line NS as the first scanning signal. The second output signal OUT2 output from the unit circuit 4 of each stage is supplied to the second scanning signal line PS as the second scanning signal, and is also supplied as the set signal S to the unit circuit 4 of the next stage.

[0045] In this embodiment, the first gate clock signal GCK1, the third gate clock signal GCK3, and the fifth gate clock signal GCK5 correspond to clock signals of a first waveform, the second gate clock signal GCK2, the fourth gate clock signal GCK4, and the sixth gate clock signal GCK6 correspond to clock signals of a second waveform, and the second control clock signal CK2 corresponds to a clock signal for driving a scanning signal line.

[0046] 3.3 Unit Circuit FIG. 10 is a circuit diagram showing the configuration of a unit circuit 4 in this embodiment. Note that the configuration shown here is an example and is not limited to this. As shown in FIG. 10, the unit circuit 4 includes ten transistors M1 to M10 and one capacitor C1. The transistors M1 to M4, M6, and M8 to M10 are P-type transistors, and the transistors M5 and M7 are N-type transistors. The unit circuit 4 also has an input terminal to which a gate low voltage VGL is applied and an input terminal to which a gate high voltage VGH is applied, as well as four input terminals 41 to 44 and two output terminals 48 and 49. 10, the input terminal for receiving the set signal S is labeled 41, the input terminal for receiving the first control clock signal CK1 is labeled 42, the input terminal for receiving the second control clock signal CK2 is labeled 43, the input terminal for receiving the mode signal VM is labeled 44, the output terminal for outputting the first output signal OUT1 is labeled 48, and the output terminal for outputting the second output signal OUT2 is labeled 49. Note that, hereinafter, the output terminal 48 for outputting the first output signal OUT1 will be referred to as the "first output terminal," and the output terminal 49 for outputting the second output signal OUT2 will be referred to as the "second output terminal."

[0047] The second conduction terminal of transistor M3, the control terminal of transistor M4, the control terminal of transistor M5, the control terminal of transistor M6, the control terminal of transistor M7, the second conduction terminal of transistor M8, and the second conduction terminal of transistor M10 are connected to each other. A node where these are connected to each other is called a "first internal node." The first internal node is denoted by the symbol N1. The control terminal of transistor M2, the second conduction terminal of transistor M6, the first conduction terminal of transistor M7, and the control terminal of transistor M9 are connected to each other. A node where these are connected to each other is called a "second internal node." The second internal node is denoted by the symbol N2. The control terminal of transistor M1, the first conduction terminal of transistor M10, and one end of capacitor C1 are connected to each other. A node where these are connected to each other is called a "third internal node." The third internal node is denoted by the symbol N3. The first conduction terminal of transistor M8 and the second conduction terminal of transistor M9 are connected to each other. A node where these are connected to each other is called a "fourth internal node." The fourth internal node is labeled N4.

[0048] The unit circuit 4 includes a first control circuit 411 that controls the voltage of the first internal node N1, a first output circuit 423 that controls the output of the first output signal OUT1, a second control circuit 421 that controls the voltage of the second internal node N2, a second output circuit 422 that controls the output of the second output signal OUT2, and a third control circuit 412 that controls the voltage of the first internal node N1. The first control circuit 411 includes a transistor M3. The second control circuit 421 includes a transistor M6 and a transistor M7. The third control circuit 412 includes a stabilization circuit 430 and a transistor M10. The stabilization circuit 430 includes a transistor M8 and a transistor M9. The first output circuit 423 includes a transistor M4 and a transistor M5. The second output circuit 422 includes a transistor M1, a transistor M2, and a capacitor C1.

[0049] The transistor M1 has a control terminal connected to the third internal node N3, a first conduction terminal connected to the input terminal 43, and a second conduction terminal connected to the second output terminal 49. This transistor M1 functions as a buffer transistor. The transistor M2 has a control terminal connected to the second internal node N2, a first conduction terminal connected to the input terminal for the gate high voltage VGH, and a second conduction terminal connected to the second output terminal 49. The transistor M3 has a control terminal connected to the input terminal 42, a first conduction terminal connected to the input terminal 41, and a second conduction terminal connected to the first internal node N1. The transistor M4 has a control terminal connected to the first internal node N1, a first conduction terminal connected to the input terminal 44, and a second conduction terminal connected to the first output terminal 48. The transistor M5 has a control terminal connected to the first internal node N1, a first conduction terminal connected to the first output terminal 48, and a second conduction terminal connected to the input terminal for the gate low voltage VGL. For transistor M6, the control terminal is connected to the first internal node N1, the first conduction terminal is connected to the input terminal for the gate high voltage VGH, and the second conduction terminal is connected to the second internal node N2. For transistor M7, the control terminal is connected to the first internal node N1, the first conduction terminal is connected to the second internal node N2, and the second conduction terminal is connected to the input terminal for the gate low voltage VGL. For transistor M8, the control terminal is connected to the input terminal 43, the first conduction terminal is connected to the fourth internal node N4, and the second conduction terminal is connected to the first internal node N1. For transistor M9, the control terminal is connected to the second internal node N2, the first conduction terminal is connected to the input terminal for the gate high voltage VGH, and the second conduction terminal is connected to the fourth internal node N4. For transistor M10, the control terminal is connected to the input terminal for the gate low voltage VGL, the first conduction terminal is connected to the third internal node N3, and the second conduction terminal is connected to the first internal node N1. As for the capacitor C1, one end is connected to the third internal node N3, and the other end is connected to the second output terminal 49.

[0050] 10 (operation in a period around the time when the set signal S becomes active) will be described with reference to Fig. 11. It is assumed that the frame of interest here is a write frame, and the mode signal VM is maintained at a high level.

[0051] During the period before time t11, the voltage of the first internal node N1 is maintained at a high level, the voltage of the second internal node N2 is maintained at a low level, the voltage of the third internal node N3 is maintained at a high level, the voltage of the fourth internal node N4 is maintained at a high level, the first output signal OUT1 is maintained at a low level, and the second output signal OUT2 is maintained at a high level. Note that, since the voltage of the second internal node N2 is maintained at a low level, the transistor M2 is maintained in an on state.

[0052] At time t11, the first control clock signal CK1 changes from high to low. This turns on transistor M3. Also at time t11, the set signal S changes from high to low. This causes the voltage at the first internal node N1 to drop to low, transistors M4 and M6 to turn on, and transistors M5 and M7 to turn off. With transistor M6 on and transistor M7 off, the voltage at the second internal node N2 changes from low to high. Furthermore, since the mode signal VM is maintained at high, transistor M4 is on and transistor M5 is off, causing the first output signal OUT1 to change from low to high. However, even though the voltage at the first internal node N1 drops to low at time t11, transistor M10 remains on in the third control circuit 412. Therefore, the voltage at the third internal node N3 also drops from high to low, turning on transistor M1.

[0053] At time t12, the first control clock signal CK1 changes from low to high, turning off the transistor M3. Also at time t12, the set signal S changes from low to high.

[0054] At time t13, the second control clock signal CK2 changes from high to low. At this time, because the transistor M1 is in the on state, the voltage at the input terminal 43 drops, and the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) drops. Because the capacitor C1 is provided between the third internal node N3 and the second output terminal 49, the voltage at the third internal node N3 also drops as the voltage at the second output terminal 49 drops (the third internal node N3 enters a boosted state). As a result, a large negative voltage is applied to the control terminal of the transistor M1, and the voltage of the second output signal OUT2 drops to a level sufficient to turn on the write control transistor T3 connected to the second output terminal 49. When the voltage at the third internal node N3 drops at time t13, the voltage at the first conduction terminal of the transistor M10 becomes lower than the voltage at the control terminal. This turns the transistor M10 off. Therefore, the voltage at the first internal node N1 does not change at time t13.

[0055] At time t14, the second control clock signal CK2 changes from low to high. This causes the voltage at the input terminal 43 to rise, and the voltage at the second output terminal 49 (the voltage of the second output signal OUT2) to rise. When the voltage at the second output terminal 49 rises, the voltage at the third internal node N3 also rises via the capacitor C1. This turns on the transistor M10.

[0056] At time t15, the first control clock signal CK1 changes from high to low. This turns on the transistor M3. At this time, the set signal S is maintained at high. This causes the voltage at the first internal node N1 to rise to high, turning off the transistors M4 and M6 and turning on the transistors M5 and M7. This causes the first output signal OUT1 to change from high to low, and the voltage at the second internal node N2 also changes from high to low. As the voltage at the second internal node N2 changes from high to low, the transistors M2 and M9 turn on. As the transistor M9 turns on, the voltage at the fourth internal node N4 rises. Furthermore, since the transistor M10 is on, the voltage at the third internal node N3 also rises to high. This turns the transistor M1 off.

[0057] During the period after time t15, as in the period before time t11, the voltage of the first internal node N1 is maintained at a high level, the voltage of the second internal node N2 is maintained at a low level, the voltage of the third internal node N3 is maintained at a high level, the voltage of the fourth internal node N4 is maintained at a high level, the first output signal OUT1 is maintained at a low level, and the second output signal OUT2 is maintained at a high level.

[0058] As described above, the first output signal OUT1 is maintained at a high level during the period t11 to t15, and the second output signal OUT2 is maintained at a low level during the period t13 to t14. This causes data to be rewritten in the pixel circuit 15.

[0059] <4. Scanning Signal Line Driving Method> Next, a method for driving the scanning signal lines (first scanning signal line NS and second scanning signal line PS) will be described. In this embodiment, three-pulse driving is performed using first to sixth gate clock signals GCK1 to GCK6, which constitute three sets of two-phase clocks. That is, a write pulse is applied three times during each vertical scanning period to the second scanning signal line PS connected to the control terminal of the write control transistor T3 in each pixel circuit 15. In this regard, when the third write pulse is applied to the second scanning signal line PS during each vertical scanning period, a desired data voltage is written to the pixel circuit 15 including the write control transistor T3 having the control terminal connected to the second scanning signal line PS.

[0060] In this embodiment, in each vertical scanning period, a gate start pulse GSP is applied to the shift register 401 three times at intervals of eight horizontal scanning periods (8H), as shown in part A of FIG. 1 . As a result, the shift pulse is transferred three times within the shift register 401 in each vertical scanning period. As a result, the waveforms of the first scanning signal NS and the second scanning signal PS change as shown in FIG. 12 , and a write pulse is applied to each second scanning signal line PS three times in each vertical scanning period. In this manner, three-pulse driving is performed. Note that, as described above, since the gate start pulse GSP is applied to the shift register 401 at intervals of eight horizontal scanning periods, the write pulses applied to each second scanning signal line PS are also generated at intervals of eight horizontal scanning periods, as shown in part A of FIG. 1 .

[0061] If the interval between three write pulses applied to each second scanning signal line PS is six horizontal scanning periods, the three write pulses applied to the three second scanning signal lines PS at the same timing will be generated based on the same gate clock signal GCK. Therefore, in this embodiment, the gate start pulse GSP is applied to the shift register 401 at intervals of eight horizontal scanning periods, as described above, so that the interval between write pulses applied to each second scanning signal line PS is eight horizontal scanning periods. As a result, write pulses are applied to the second scanning signal lines PS(Z), PS(Z+8), and PS(Z+16) at the same timing, where Z is an integer between 1 and (n-16). For example, as shown by the dotted line portion labeled 61 in part A of FIG. 1 , write pulses are applied to the second scanning signal lines PS(1), PS(9), and PS(17) at the same timing. As can be seen from part B of FIG. 1, the write pulse applied to the second scanning signal line PS(1) is generated based on the first gate clock signal GCK1, the write pulse applied to the second scanning signal line PS(9) is generated based on the third gate clock signal GCK3, and the write pulse applied to the second scanning signal line PS(17) is generated based on the fifth gate clock signal GCK5.

[0062] The connection relationship between the unit circuits 4(1), 4(9), and 4(17) that output the second scanning signals PS(1), PS(9), and PS(17), respectively, and each signal line is as shown in FIG. 13. Therefore, the configuration related to the output of the three write pulses indicated by the dotted line portion labeled 61 in part A of FIG. 1 is schematically shown in FIG. 14. As can be seen from FIG. 14, the drive loads of the three gate clock signals (first gate clock signal GCK1, third gate clock signal GCK3, and fifth gate clock signal GCK5) at the timing when the three write pulses are output are as follows: The drive load of the first gate clock signal GCK1 is the sum of the load of the wiring 62 for the first gate clock signal GCK1 and the load of the second scanning signal line PS(1). The drive load of the third gate clock signal GCK3 is the sum of the load of the wiring 63 for the third gate clock signal GCK3 and the load of the second scanning signal line PS(9). The drive load of the fifth gate clock signal GCK5 is the sum of the load of the wiring 64 for the fifth gate clock signal GCK5 and the load of the second scanning signal line PS (17). For any gate clock signal GCK, the drive load is the sum of the load of the wiring for that gate clock signal GCK and the load of one second scanning signal line PS.

[0063] As described above, unlike the configuration disclosed in Japanese Patent Application Laid-Open No. 2018-112741, the three write pulses output at the same timing are generated based on three mutually different gate clock signals GCK. In other words, write pulses are not output to multiple second scanning signal lines PS at the same timing based on one gate clock signal GCK. In this way, the drive load of the gate clock signal GCK when three-pulse driving is performed is reduced compared to conventional configurations.

[0064] 5. Effects The scanning signal line driving circuit 410 of this embodiment drives the scanning signal lines (first scanning signal line NS, second scanning signal line PS) based on six gate clock signals GCK1 to GCK6 that constitute three sets of two-phase clocks. The multiple unit circuits 4 that constitute the shift register 401 in the scanning signal line driving circuit 410 form blocks of six consecutive unit circuits 4. A different gate clock signal GCK is applied to each of the six consecutive unit circuits 4 as a second control clock signal CK2 that is the source of a write pulse applied to the second scanning signal line PS. The second control clock signal CK2 is applied to the six consecutive unit circuits 4 in the same manner in all blocks. With this configuration, a gate start pulse GSP is applied to the shift register 401 three times at intervals of eight horizontal scanning periods during each vertical scanning period. As a result, a write pulse is applied to each second scanning signal line PS three times during each vertical scanning period. In this case, with the above configuration, the three write pulses output at the same timing are generated based on three mutually different gate clock signals GCK. Therefore, compared to the conventional technique, the drive load of the gate clock signal GCK when three-pulse driving is performed is reduced. Therefore, it is possible to increase the frame rate without causing a delay in the scan signal (write pulse). As described above, according to this embodiment, a scan signal line drive circuit 410 is realized that enables high-speed driving without degrading display quality.

[0065] 6. Modifications In the above embodiment, three-pulse driving is performed, but this is not limited to this. If the performance of the organic EL display device improves, for example, four-pulse driving or five-pulse driving can also be performed. In other words, the disclosure of this specification can be applied when K-pulse driving is performed, where K is an integer of 3 or greater.

[0066] For example, when four-pulse driving is performed, the shift register 401 in the scanning signal line driving circuit 410 is composed of a plurality of unit circuits 4 cascade-connected to each other, which operate based on eight gate clock signals GCK and a gate start pulse GSP constituting four sets of two-phase clocks. The plurality of unit circuits 4 form a block of eight consecutive unit circuits 4, and a different gate clock signal GCK is applied to each of the eight consecutive unit circuits 4 as the second control clock signal CK2. With this configuration, during each vertical scanning period, the gate start pulse GSP is applied to the shift register 401 four times at intervals of 10 horizontal scanning periods. As a result, a write pulse is applied to each second scanning signal line PS four times during each vertical scanning period. At this time, the four write pulses output at the same timing are generated based on four different gate clock signals GCK.

[0067] In general, when K pulse driving is performed, where K is an integer greater than or equal to 3, a scanning signal line driving circuit 410 having the following configuration can be employed. The scanning signal line driving circuit 410 includes a shift register 401 made up of a plurality of unit circuits 4 cascade-connected to one another, which operate based on (K×2) gate clock signals GCK and gate start pulses GSP constituting K sets of two-phase clocks. The plurality of unit circuits 4 form a block, each consisting of (K×2) consecutive unit circuits 4. A different gate clock signal GCK from the (K×2) gate clock signals GCK is supplied to each of the (K×2) consecutive unit circuits 4 as a second control clock signal CK2. In all blocks, one of the (K×2) gate clock signals GCK is supplied to each of the (K×2) consecutive unit circuits 4 in the same manner as above, as the second control clock signal CK2. A gate start pulse GSP is given to the shift register 401 so that K write pulses are output from each unit circuit 4 to the corresponding second scanning signal line PS based on the second control clock signal CK2 during each vertical scanning period.

[0068] Furthermore, in the above embodiment, the gate start pulse GSP is provided to the shift register 401 so that a write pulse is provided to each second scanning signal line PS three times at intervals of eight horizontal scanning periods during each vertical scanning period. However, the interval at which the write pulse is provided to the second scanning signal line PS is not limited to eight horizontal scanning periods. Even if the interval at which the write pulse is provided to the second scanning signal line PS is set to, for example, two horizontal scanning periods or 14 horizontal scanning periods, the three write pulses output at the same timing are generated based on three mutually different gate clock signals GCK. For the above reasons, the gate start pulse GSP may be provided to the shift register 401 so that, with respect to the three write pulses output from each unit circuit 4 to the corresponding second scanning signal line PS, one write pulse is output from that unit circuit every (6×P+2) horizontal scanning periods, where P is an integer greater than or equal to 0. More generally, in the case where K pulse driving is performed, where K is an integer greater than or equal to 3, and P is an integer greater than or equal to 0, the gate start pulse GSP may be provided to the shift register 401 so that one write pulse is output from each unit circuit 4 every (2×K×P+2) horizontal scanning periods with respect to the K write pulses output from each unit circuit 4 to the corresponding second scanning signal line PS.

[0069] 7. Others In the above embodiment, an organic EL display device has been described as an example, but the present invention is not limited to this. The disclosure of this specification can also be applied to inorganic EL display devices, QLED display devices, and other display devices that use display elements driven by current.

[0070] 4...Unit circuit 10...Display device (organic EL display device) 11...Display unit 15...Pixel circuit 30...Data side drive circuit 40...Scanning side drive circuit 401...Shift register 410...Scanning signal line drive circuit GCK1 to GCK6...First to sixth gate clock signals GSP...Gate start pulse NS...First scan signal line, first scan signal PS...Second scan signal line, second scan signal M1 to M10...Transistors (in unit circuit) N1 to N4...First to fourth internal nodes (in unit circuit)

Claims

1. A scanning signal line drive circuit for driving a plurality of scanning signal lines, comprising a shift register consisting of a plurality of unit circuits cascade-connected to each other and operating based on (K×2) clock signals constituting K sets of two-phase clocks, where K is an integer of 3 or greater, and a start pulse, wherein each of the plurality of unit circuits includes a buffer transistor having a first conduction terminal to which one of the (K×2) clock signals is supplied as a scanning signal line drive clock signal, and a second conduction terminal connected to the corresponding scanning signal line, the start pulse is supplied to the shift register so that K write pulses are output from each unit circuit to the corresponding scanning signal line based on the scanning signal line drive clock signal during each vertical scanning period, each set of two-phase clocks consists of a clock signal of a first waveform and a clock signal of a second waveform that is 180 degrees out of phase with the clock signal of the first waveform, and the first waveform clock signal is supplied to odd-numbered unit circuits of the plurality of unit circuits as the scanning signal line drive clock signal, a scanning signal line driving circuit, characterized in that: the clock signal of the second waveform is supplied to even-numbered unit circuits among the plurality of unit circuits as the scanning signal line driving clock signal; the plurality of unit circuits form blocks each consisting of (K×2) consecutive unit circuits; a mutually different clock signal from the (K×2) clock signals is supplied to each of the (K×2) consecutive unit circuits as the scanning signal line driving clock signal; and in all blocks, one of the (K×2) clock signals is supplied to each of the (K×2) consecutive unit circuits as the scanning signal line driving clock signal in the same manner.

2. The scanning signal line driving circuit according to claim 1, wherein K is 3.

3. The scanning signal line drive circuit according to claim 2, wherein the start pulse is supplied to the shift register so that one write pulse is output from each unit circuit every (6×P+2) horizontal scanning periods, where P is an integer greater than or equal to 0, for three write pulses output from each unit circuit to a corresponding scanning signal line.

4. The scanning signal line drive circuit according to claim 1, wherein the start pulse is provided to the shift register so that one write pulse is output from each unit circuit every (2×K×P+2) horizontal scanning periods, with respect to the K write pulses output from each unit circuit to the corresponding scanning signal line, where P is an integer greater than or equal to 0.

5. A display device comprising: a plurality of pixel circuits; a plurality of scanning signal lines for controlling writing of data voltages to the plurality of pixel circuits; and the scanning signal line drive circuit according to any one of claims 1 to 4.

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