Nonvolatile storage device and host device

Abstract

Provided is a nonvolatile storage device capable of reading or writing data in a state in which the random access performance of the nonvolatile storage device is guaranteed. A nonvolatile storage device connected to a host device comprises: a nonvolatile memory; a memory control unit that reads and writes data to / from the nonvolatile memory; and an interface unit that provides notification to the host device. When the read performance or the write performance fall below predetermined access performance, the interface unit notifies the host device that the read performance or the write performance has fallen below the predetermined access performance.

Description

Nonvolatile storage device and host device

[0001] The present disclosure relates to non-volatile storage devices and host devices coupled to the non-volatile storage devices.

[0002] In recent years, nonvolatile storage devices including SD cards (registered trademark) and other removable semiconductor memory devices equipped with flash memory or the like as a back-end module have become widespread. SD cards as nonvolatile storage devices are connected to host devices such as personal computers and cameras, allowing the host device to access data from the flash memory as a back-end module.

[0003] IOPS (Input / Output Per Second) is known as one indicator of the performance of the nonvolatile memory device. IOPS is defined as the number of data read (read) processes or data write (write) processes that can be performed per second under specified conditions. For example, a nonvolatile memory device with a write process of 100K [IOPS] means that it can perform 100K write processes, or 100,000 write processes, per second. Note that when measuring IOPS, it is common to repeatedly perform read or write processes in 4K byte increments at random (discrete) addresses throughout the flash memory area.

[0004] It goes without saying that the larger the IOPS value, the higher the performance of the nonvolatile storage device.

[0005] Patent Document 1 discloses a technique for improving the IOPS value when writing data.

[0006] On the other hand, some host devices require nonvolatile storage devices with a certain level of IOPS performance (hereinafter referred to as random access performance). To enable selection of an appropriate nonvolatile storage device for such a host device, random access classes are sometimes specified, which classify the minimum guaranteed random access performance.

[0007] For example, Non-Patent Document 1 discloses a random access class in an SD card as an Application Performance Class.

[0008] JP 2010-237907 A

[0009] SD Card Association, “SD Specifications Part 1 Physical Layer Simplified Specification Version 9.10”, December 1, 2023

[0010] Flash memory has the following physical characteristics:

[0011] First, there is an upper limit to the number of times that a memory block constituting a flash memory can be rewritten, and if the same memory block is repeatedly rewritten, further rewriting becomes impossible.

[0012] Secondly, if a specific memory block is repeatedly read or left unaccessed for a long period of time, when the data is read, different bits (defective bits) than those obtained when the data was written may be obtained, and correct data may not be sent to the host device.

[0013] To avoid such an undesirable state, it is necessary to process data from a memory block that has been rewritten many times to another memory block that has been rewritten fewer times, or to process data from a memory block that has a large number of defective bits when read to a memory block that has a smaller number of defective bits.

[0014] These processes take a long time because they involve reading data from a specific memory block and writing it to another memory block. Therefore, if the host device needs to perform the data movement process while it is executing a read or write process on the nonvolatile storage device, the actual random access performance will be lower than the performance specified by the random access class specified by the nonvolatile storage device.

[0015] The present disclosure provides a nonvolatile memory device and a host device in a memory system comprising the host device and the nonvolatile memory device, in which data can be read or written while the random access performance of the nonvolatile memory device is guaranteed.

[0016] The nonvolatile storage device according to the present disclosure is connected to a host device and includes a nonvolatile memory, a memory control unit that reads and writes data from and to the nonvolatile memory, and an interface unit that notifies the host device that read performance or write performance falls below a predetermined access performance.

[0017] The host device in the present disclosure is connected to a nonvolatile storage device. The host device includes a controller having an interface unit that communicates with the nonvolatile storage device. The controller receives notifications from the nonvolatile storage device via the interface unit and transmits instructions to the nonvolatile storage device. When the interface unit receives a notification that the read performance or write performance of the nonvolatile storage device is below a predetermined access performance, it instructs the nonvolatile storage device to perform a predetermined data migration process.

[0018] According to the present disclosure, data can be read or written while ensuring the random access performance of the nonvolatile storage device.

[0019] 1 is a block diagram showing the configuration of a memory system including a nonvolatile storage device and a host device according to a first embodiment; 2 is a timing diagram illustrating initialization processing of the memory system according to the first embodiment; 3 is a timing diagram illustrating Write command processing of the memory system according to the first embodiment; 4 is a timing diagram illustrating Read command processing of the memory system according to the first embodiment; 5 is a diagram illustrating the state of the flash memory before swap processing according to the first embodiment; 6 is a diagram illustrating the state of the flash memory after swap processing according to the first embodiment; 4 is a diagram explaining the performance of random read processing in Kbyte units. FIG. 5 is a diagram explaining the random access class in embodiment 1. FIG. 6 is a diagram explaining the notification of the performance evaluation flag in embodiment 1. FIG. 7 is a diagram explaining the relationship between the change mode of the swap / refresh target physical block and the performance evaluation flag according to the present invention in embodiment 1. FIG. 8 is a diagram explaining the relationship between another change mode of the swap / refresh target physical block and the performance evaluation flag according to embodiment 1. FIG. 9 is a diagram explaining the operation of the forced swap / refresh command in embodiment 1. FIG. 10 is a diagram explaining the notification of the performance index in embodiment 2. FIG. 11 is a diagram explaining the operation of the memory system in which the performance of the random access class is guaranteed by the forced refresh command in embodiment 2. FIG. 12 is a diagram explaining the operation of the memory system in which the performance of the random access class is guaranteed without sending the forced refresh command in embodiment 2. FIG. 13 is a diagram explaining the notification of the variable random access class in embodiment 3.FIG. 10 is a diagram illustrating the notification of a performance evaluation flag by a response; FIG. 11 is a diagram illustrating the operation of a forced swap refresh execution command in the fourth embodiment;

[0020] Hereinafter, the embodiments will be described in detail with reference to the drawings as appropriate. However, in some cases, more detailed explanation than necessary will be omitted. For example, detailed explanation of already well-known matters or redundant explanation of substantially identical configurations will be omitted. This is to avoid unnecessary redundancy in the following explanation and to facilitate understanding by those skilled in the art. Note that components with the same reference numerals have the same function in each embodiment.

[0021] The present invention relates to a memory system including a host device and a nonvolatile storage device, and is not limited to the above embodiments.

[0022] [1-1. Configuration of Memory System] FIG. 1 is a block diagram illustrating a memory system including a host device and a nonvolatile storage device controlled by the host device according to the first embodiment.

[0023] As shown in FIG. 1, the host device 100 comprises a power supply unit 101 that supplies at least 3.3 V power, and a host device controller 102 .

[0024] The host device controller 102 includes at least a host device I / F unit 103. The host device I / F unit 103 further includes at least a protocol control unit 104.

[0025] The nonvolatile memory device 110 is composed of at least a nonvolatile memory device controller 111 , a flash memory 112 , and a flash memory bus 113 that connects the nonvolatile memory device controller 111 and the flash memory 112 .

[0026] The nonvolatile memory device controller 111 includes at least a nonvolatile memory device I / F unit 114 and a flash memory control unit 115 .

[0027] Furthermore, the nonvolatile storage device I / F unit 114 has a protocol control unit 116 and a register unit 117 .

[0028] The flash memory 112 is divided into physical blocks of a predetermined data size (for example, 4 megabytes), and each physical block is assigned a physical address.

[0029] The host device 100 and the nonvolatile memory device 110 are connected by a VDD line 121 and an SD bus 122 .

[0030] A power supply unit 101 provided in the host device 100 supplies 3.3V power to its own host device controller 102. The power supply unit 101 also supplies 3.3V power to a nonvolatile memory device controller 111 and a flash memory 112 in the nonvolatile memory device 110 via a VDD line 121.

[0031] The SD bus 122 is made up of a CLK line 123, a CMD line 124, and a DAT line 125. The DAT line 125 is further made up of four signal lines: a DAT0 line 125a, a DAT1 line 125b, a DAT2 line 125c, and a DAT3 line 125d. A clock signal, a control signal, and a data signal are transmitted from the host device 100 or the nonvolatile memory device 110 via the SD bus 122. Signal transmission on the SD bus 122 is controlled by a protocol control unit 104 in the host device I / F unit 103 and a protocol control unit 116 in the nonvolatile memory device I / F unit 114.

[0032] [1-2. Basic Operation of Memory System] FIG. 2 is a timing diagram illustrating the operation of the initialization process of the memory system according to the first embodiment.

[0033] At time t1 , the power supply unit 101 of the host device 100 starts supplying 3.3 V power to the nonvolatile memory device 110 via the VDD line 121 .

[0034] At time t2, when sufficient time has passed since the start of power supply and a stable 3.3V power supply can be supplied, the host device I / F unit 103 of the host device 100 supplies a clock signal to the non-volatile memory device I / F unit 114 of the non-volatile memory device 110 via the CLK line 123.

[0035] After that, at time t3, the protocol control unit 104 in the host device I / F unit 103 transmits a bus condition check command 201 to the nonvolatile memory device I / F unit 114 via the CMD line 124.

[0036] When the nonvolatile memory device I / F unit 114 receives the bus condition check command 201, the protocol control unit 116 in the nonvolatile memory device I / F unit 114 sends a response 202 to the bus condition check command 201, which multiplexes the bus condition check results, to the host device I / F unit 103 via the CMD line 124.

[0037] After the host device I / F unit 103 receives the response 202 to the bus condition check command 201, when the protocol control unit 104 determines that the bus condition check result multiplexed in the response 202 to the bus condition check command 201 satisfies the specified conditions, it sends the first initialization command 203 to the non-volatile memory device I / F unit 114 via the CMD line 124 at time t4.

[0038] When the nonvolatile storage device I / F unit 114 receives the first initialization command 203, the protocol control unit 116 instructs the flash memory control unit 115 to initialize the nonvolatile storage device 110 (hereinafter simply referred to as initialization). This places the nonvolatile storage device 110 in an "initializing" state. Instructed to perform initialization, the flash memory control unit 115 reads the flash memory management information stored in the flash memory 112 via the flash memory bus 113, makes appropriate corrections, and then writes the corrected flash memory management information back to the flash memory 112 via the flash memory bus 113. The flash memory management information is also stored in a random access memory (RAM) (not shown) within the flash memory control unit 115. The flash memory management information includes a logical-physical conversion table that shows the relationship between logical addresses specified when reading or writing from the host device 100 and physical addresses assigned to each physical block within the flash memory control unit 115. Note that there may be cases where a logical address is not assigned to a physical block within the flash memory 112. Physical blocks to which no logical address is assigned are also managed using the logical-physical conversion table.

[0039] After receiving the first initialization command 203, the protocol control unit 116 transmits a response 204 of the initialization command 203 to the host device I / F unit 103 via the CMD line 124. At this time, the state of the nonvolatile memory device 110 is "initializing," so the Busy flag included in the response 204 displays 0.

[0040] When the Busy flag of the received response 204 displays 0, the host device I / F unit 103 detects that the state of the non-volatile memory device 110 is "initializing" and recognizes that initialization of the non-volatile memory device 110 has not been completed.

[0041] If the host device I / F unit 103 recognizes that initialization of the nonvolatile memory device 110 has not been completed, the protocol control unit 104 sends a second initialization command 205 to the nonvolatile memory device I / F unit 114 at time t5.

[0042] When the nonvolatile memory device I / F unit 114 receives the second initialization command 205, the protocol control unit 116, because the state of the nonvolatile memory device 110 is still "initializing", transmits a response 206 to the initialization command to the host device I / F unit 103. In the response 206, the Busy flag indicates 0.

[0043] When the initialization of the nonvolatile memory device 110 is completed at time t6, which is after time t5, the state of the nonvolatile memory device 110 transitions from "initializing" to "initialization completed." Meanwhile, the host device I / F unit 103 still recognizes that the state of the nonvolatile memory device 110 is "initializing."

[0044] Therefore, the host device I / F 103 transmits the third initialization command 207 to the nonvolatile storage device I / F unit 114 at time t7, which is after time t6.

[0045] When the nonvolatile memory device I / F unit 114 receives the third initialization command 207 at time t7, since the state of the nonvolatile memory device 110 is "initialization completed", it sends a response 208 to the initialization command 207 with a Busy flag of 1 to the host device I / F unit 103.

[0046] When the host device I / F unit 103 receives the response 208 with the Busy flag set to 1, it recognizes that the initialization is complete and stops issuing further initialization commands.

[0047] In this way, the host device I / F unit 103 repeats issuing the initialization command until 1 is displayed in the Busy flag multiplexed in the response to the initialization command.

[0048] However, even if the host device I / F unit 103 repeatedly issues an initialization command, for some reason, such as a malfunction within the nonvolatile memory device 110, it may not be able to receive a response to the initialization command with the Busy flag set to 1. As a result, the host device 100 may never detect that initialization is complete. To avoid such an undesirable situation, the nonvolatile memory device 110 is required to complete initialization within a predetermined time. In this case, if initialization is not completed within a predetermined time after the start of initialization, the host device 100 preferably detects that there is a malfunction in the connected nonvolatile memory device 110 and notifies the user of this fact. For example, if the nonvolatile memory device 110 is an SD card, it is specified that initialization must be completed within one second after receiving the first initialization command.

[0049] FIG. 3 is a timing diagram illustrating the operation of the memory system according to the first embodiment in processing a Write command.

[0050] At time t1, the host device I / F unit 103 transmits a Write command 301 to the nonvolatile memory device I / F unit 114 via the CMD line 124. The Write command 301 includes a write start logical address in the nonvolatile memory device 110 as a storage destination for the data that the host device 100 is to write first.

[0051] When the nonvolatile memory device I / F unit 114 receives the Write command 301, it transmits a response 302 of the Write command 301 to the host device I / F unit 103 via the CMD line 124. Thereafter, the flash memory control unit 115 refers to the flash memory management information expanded in RAM and converts the write start logical address multiplexed in the Write command 301 into a physical address on the flash memory 112.

[0052] After receiving the response 302 to the write command 301, the host device I / F unit 103 starts transmitting sector data 303, divided into sectors (512 bytes), to the nonvolatile storage device controller 111 at time t2 via the DAT lines 125. In the SD protocol, which is the rule for transmitting and receiving commands, responses, and data via the SD bus 122, data is generally divided into predetermined units of 512 bytes. The data is transmitted four bits per clock via four signal lines that make up the DAT lines 125: the DAT0 line (125a), the DAT1 line (125b), the DAT2 line (125c), and the DAT3 line (125d).

[0053] The nonvolatile storage device I / F unit 114 performs a cyclic redundancy check (CRC) on the received sector data 303 to determine whether there is an error or not.

[0054] The determination result of "error present" means that an error occurred during data transmission via SD bus 122. In this case, nonvolatile memory device I / F unit 114 transmits the result of "error present" as CRC result 304 to host device I / F unit 103, and does not write the corresponding sector data 303 to flash memory 112.

[0055] When the host device I / F unit 103 receives the CRC result 304 indicating "error", it is common to abort the Write command processing at this point or resend the sector data 303 .

[0056] On the other hand, a determination result of "no error" means that no error occurred during data transmission via the SD bus 122. At this time, the nonvolatile storage device I / F unit 114 transmits the "no error" result as a CRC result 304 to the host device I / F unit 103. The flash memory control unit 115 then writes the received sector data 303 via the flash memory bus 113 to a physical block on the flash memory 112 corresponding to the physical address calculated when the Write command 301 was received. At this time, an ECC (Error Correction Code) is calculated from the data to be written, and written together with the write data to a predetermined physical block. The ECC is used to correct defective bits whose values ​​differ from those at the time of writing when the write data is read from the flash memory 112.

[0057] The time required to write data to the flash memory 112 varies depending on the conditions, and in some cases it may take on the order of 100 ms (milliseconds) per sector. If the nonvolatile storage device controller 111 receives the next sector data before writing of the sector data to the flash memory 112 is complete, the received sector data cannot be retained and the memory system will fail.

[0058] To avoid the above situation, the nonvolatile memory device I / F unit 114 notifies the host device I / F unit 103 that the nonvolatile memory device 110 is busy while writing data to the flash memory 112. At this time, the host device I / F unit 103 prevents the next sector data from being sent to the nonvolatile memory device 110.

[0059] 3, from time t4 when transmission of the CRC result 304 is completed, the nonvolatile memory device I / F unit 114 controls the DAT0 line 125a to Low to notify the host device I / F unit 103 that the nonvolatile memory device 110 is Busy. Here, controlling the signal line to Low means controlling the potential of the signal line to 0 V or close to 0 V.

[0060] After writing of the sector data 303 to the flash memory 112 is completed, the nonvolatile memory device I / F unit 114 controls the DAT0 line 125a to High at time t5 to notify the host device I / F unit 103 that the nonvolatile memory device 110 is not Busy. Here, controlling the signal line to High means controlling the potential of the signal line to be higher than 0 V and distinguishable from Low.

[0061] In the SD protocol, the upper limit of the busy period during a write operation, that is, the time from time t4 to time t5 in FIG. 3, is specified as 250 ms or 500 ms depending on the conditions.

[0062] When the host device I / F unit 103 detects that the nonvolatile memory device 110 is not busy, it transmits the next sector data 305 to the nonvolatile memory device controller 111 .

[0063] When writing the next sector data 305 to the physical block, the flash memory control unit 115 controls the sector data 303 so that it is written to consecutive addresses in the logical address space.

[0064] The write command process is repeated until writing of a predetermined amount of data specified by the host device 100 is completed, or until the host device I / F unit 103 transmits a command to stop the write process.

[0065] When writing to a predetermined physical block is completed, the flash memory control unit 115 increments the number of rewrites for that physical block by one.

[0066] FIG. 4 is a timing diagram illustrating the operation of the Read command processing in the memory system according to the first embodiment.

[0067] At time t1, the host device I / F unit 103 transmits a Read command 401 to the nonvolatile memory device I / F unit 114 via the CMD line 124. The Read command 401 includes multiplexed therein a read start logical address in the nonvolatile memory device 110 where the data to be read first by the host device 100 is stored.

[0068] When the nonvolatile memory device I / F unit 114 receives the Read command 401 at time t2, it transmits a response 402 to the Read command 401 to the host device I / F unit 103 via the CMD line 124. Thereafter, the flash memory control unit 115 refers to the flash memory management information expanded in RAM and converts the read start logical address multiplexed in the Read command 401 into a physical address on the flash memory 112.

[0069] Next, the flash memory control unit 115 reads the data and the ECC written together with the data from the physical block on the flash memory 112 corresponding to the physical address calculated when the Read command 401 was received, via the flash memory bus 113, and attempts to correct any errors in the data. If the number of defective bits in the data read from the flash memory 112 exceeds the maximum number of correctable bits of the error correction function implemented in the flash memory control unit 115, the correct read data cannot be sent to the host device 100, and the Read command processing cannot be continued.

[0070] On the other hand, if the number of defective bits in the data read from flash memory 112 is equal to or less than the maximum number of correctable bits, the defective bits can be eliminated by error correction. At this time, nonvolatile storage device I / F unit 114 divides the data that has been error corrected by flash memory control unit 115 into sectors, and begins transmitting the first sector data 403 to host device I / F unit 103 via DAT line 125 at time t3. As with write processing, the SD protocol generally divides data into sectors (512 bytes) and transmits it.

[0071] The transmission start time t3 of the sector data 403 may be before the transmission completion time of the response 402 to the Read command 401.

[0072] After completing the transmission of the first sector data 403 at time t4, the nonvolatile storage device I / F unit 114 starts transmitting the second sector data 404 at time t5.

[0073] The Read command process is repeated until the reading of a predetermined amount of data specified by the host device 100 is completed, or until the host device I / F unit 103 transmits a command to stop the read process.

[0074] In the SD protocol, the busy period during a read operation is defined as the period from the time when the read command 401 is received to the time when the transmission of the first sector data 403 starts (from time t2 to time t3), or from the time when the transmission of the previous sector data is completed to the time when the transmission of the next sector data starts (for example, from time t4 to time t5), with the upper limit of this period being stipulated as 100 ms. During this busy period during a read operation, the flash memory control unit 115 reads data from the flash memory 112 and performs the above-mentioned processes of detecting and correcting the number of defective bits.

[0075] [1-3. Reliability Improvement Process and Problems of Nonvolatile Memory Device] The flash memory 112 constituting the nonvolatile memory device 110 according to the first embodiment has the following physical characteristics.

[0076] First, when data is repeatedly written to a physical block and a certain number of rewrites is reached, a phenomenon occurs in which no further rewrites can be performed. This upper limit on the number of rewrites of a flash memory is called endurance.

[0077] Second, when data is repeatedly read from a certain physical block, the voltage levels of that block and surrounding blocks may change and deviate from the originally recorded values. This phenomenon is called read disturb.

[0078] 5A and 5B are diagrams illustrating the operation of a swap process that avoids an event in which endurance prevents the host device 100 from writing data to the nonvolatile memory device 110, thereby improving the reliability of the nonvolatile memory device 110.

[0079] FIG. 5A is a diagram showing the relationship between each physical block of the flash memory 112 and the number of rewrites before the swap process. The horizontal axis indicates the physical address (P-addr) of each physical block. The vertical axis indicates the number of rewrites (N) of each physical block. When the number of rewrites of a physical block exceeds the swap execution threshold number, the physical block is considered to be a swap execution target. The swap execution threshold number (Tsw) is set in advance in the flash memory control unit 115 to a value lower than the maximum number of rewrites (endurance E) of the normal flash memory 112. The swap execution threshold number can also be changed depending on the state of the flash memory 112.

[0080] 5A, physical blocks A, B, C, and D have significantly higher rewrite counts than the other physical blocks. This is because the host device 100 frequently performs write operations on the logical addresses corresponding to these physical blocks. In particular, the number of rewrites for physical block C exceeds the swap execution threshold number. In this case, physical block C becomes the target for swap execution.

[0081] When executing the swap process for physical block C, a physical block with a low number of rewrites and no logical address assigned is selected as the swap destination physical block. In Fig. 5A, physical block E with no logical address assigned and no rewrites is selected as the swap destination physical block.

[0082] The swap process from physical block C to physical block E is performed in the following procedure: (1) Move (copy) data from physical block C to physical block E; (2) Reassign the logical address that was assigned to physical block C to physical block E, and then make the logical address of physical block C unassigned, and update the logical-physical conversion table; (3) Increase the number of rewrites of physical block E by 1. Figure 5B is a diagram showing the relationship between each physical block and the number of rewrites of the flash memory 112 after the swap process. As a result of the swap process, physical block C becomes unassigned. Furthermore, physical block E is newly assigned the logical address that was assigned to physical block C in Figure 5A, and the number of rewrites is increased by 1 to 1.

[0083] By repeating the above, the number of times each physical block in the flash memory 112 is rewritten is leveled out, thereby extending the usable period of the nonvolatile memory device 110 and improving its reliability.

[0084] 6A and 6B are diagrams illustrating a refresh operation to avoid an event in which, when the host device 100 reads data from a specified physical block, the number of defective bits becomes greater than a specified value due to read disturbance, making correction impossible and preventing the recorded data from being read correctly.

[0085] 6A is a diagram showing the relationship between the physical blocks of the flash memory 112 before the refresh process and the number of faulty bits (NFB) when each physical block is read. The horizontal axis shows the physical address of each physical block. The vertical axis shows the number of faulty bits when each physical block is read. The number of faulty bits is only determined when the flash memory control unit 115 reads the data in each physical block.

[0086] When the number of faulty bits in a physical block exceeds a refresh threshold faulty bit count (RTFBC), the physical block becomes a target for refresh execution. The refresh threshold faulty bit count is set in advance in the flash memory control unit 115 to a value lower than the maximum correctable bit count (MCBC) of the error correction function of the flash memory control unit 115.

[0087] 6A shows that the number of defective bits in physical block a exceeds the refresh execution threshold number of defective bits due to a past read operation, and physical block a is to be subjected to refresh.

[0088] When performing a refresh process on physical block a, a physical block that has been rewritten a small number of times and to which no logical address is assigned is selected as the refresh destination physical block. In Fig. 6A, physical block b to which no logical address is assigned is selected as the refresh destination physical block.

[0089] Unlike the number of rewrites, the number of defective bits changes each time depending on the physical characteristics and usage environment of the flash memory 112, so a physical block with a small number of defective bits in past read processes is not necessarily suitable as a refresh destination physical block. Therefore, a physical block with no logical address assigned and with a relatively small number of rewrites is selected as the refresh destination physical block.

[0090] The refresh process from physical block a to physical block b is performed as follows: (1) Move (copy) data from physical block a to physical block a; (2) Reassign the logical address that was assigned to physical block a to physical block b, and then make the logical address of physical block a unassigned, and update the logical-to-physical conversion table; (3) Increase the number of rewrites of physical block b by 1. Fig. 6B is a diagram showing the relationship between each physical block of the flash memory 112 and the number of bad bits after the refresh process. Note that the number of bad bits in physical block b, which holds the data moved from physical block a, is unknown until the physical block is actually read, but is expected to be less than the number of bad bits in physical block a.

[0091] By repeating the above process, the data in the flash memory 112 is stored in a physical block with a relatively small number of defective bits, and correct data can be sent to the host device 100 in response to a read operation from the host device 100 .

[0092] FIG. 7 is a timing diagram illustrating the operation of the flash memory control unit 115 during the memory system initialization process according to the first embodiment.

[0093] When the nonvolatile memory device 110 receives the first initialization command 203 sent by the host device 100 at time T1, the state of the nonvolatile memory device 110 becomes "initializing", and the flash memory control unit 115 starts a flash memory management information update process 701. The flash memory management information update process 701 includes the reconfiguration of the logical-physical conversion table as well as the extraction of physical blocks to be swapped or refreshed.

[0094] When the flash memory management information update process 701 is completed at time T2, if the number of physical blocks to be swapped or refreshed (hereinafter referred to as Swap Refresh Target - Physical Block Count (SRT-PBC)) is not 0, the swap and refresh process 702 (swap process or refresh process) is repeatedly executed from time T2 onwards. In Figure 7, this operation causes the number of physical blocks to be swapped and refreshed to become 0 at time T3, and the nonvolatile memory device 110 can change its state to "initialization completed".

[0095] Therefore, the value of the Busy flag of the response 208 to the initialization command 207 issued at time T4 after time T3 becomes 1 as explained in FIG.

[0096] At time T3 when the initialization is completed, the number of physical blocks to be swapped and refreshed is 0, so that in principle there is no need to execute the swapping and refreshing process after the initialization process.

[0097] FIG. 8 is a timing diagram illustrating another operation of the flash memory control unit 115 when initializing the memory system according to the first embodiment.

[0098] As in the case of Figure 7, the non-volatile memory device I / F unit 114 receives the first initialization command 203 at time T1, the flash memory control unit 115 executes the flash memory management information update process 701 from time T1 to T2, and executes the swap refresh process 702 from time T2 onwards.

[0099] After time T2, the flash memory control unit 115 executes the swap refresh process, but an upper limit time is set from the start of initialization to the end of initialization, and the nonvolatile memory device 110 cannot continue initialization beyond this upper limit time.

[0100] In Fig. 8, the number of physical blocks to be swapped and refreshed detected at the start of initialization is larger than in Fig. 7. Therefore, even at time T3 when the upper initialization limit time has elapsed since time T1, the number of physical blocks to be swapped and refreshed does not become 0.

[0101] In this case, the flash memory control unit 115 executes the swap / refresh process 702 to the extent possible within the upper initialization time limit, and leaves the swap / refresh process unexecuted for the target physical blocks that could not be executed during initialization.Then, the physical blocks for which the swap / refresh process has not been executed are swapped or refreshed during the busy period of the Write command process or the Read command process.

[0102] FIG. 9 is a diagram illustrating a method for measuring random write performance.

[0103] Random write performance is typically measured by how many times per second the operation of writing 4K bytes of data from a randomly specified address on flash memory 112 can be executed, and is expressed in units of IOPS.

[0104] As shown in Figure 9(a), the Write command processing of 4K bytes of data for measuring IOPS consists of sending a Write command and receiving a response to it, transmitting data in units of sectors (512 bytes), and writing sector data eight times during the accompanying Busy period.

[0105] 9A, the write command processing can be executed M times per second. At this time, the random write performance of the nonvolatile memory device 110 is M [IOPS]. To increase the random write performance of the nonvolatile memory device 110, that is, to increase the IOPS value, it is necessary to make the busy period in each sector data write processing as short as possible.

[0106] 9A is a diagram showing the timing of Write command processing when the required swap / refresh processing is completed within the initialization period described in FIG. 7. In this case, since there is no need to execute the swap / refresh processing during a busy period, it is possible to minimize each busy period, resulting in improved random write performance.

[0107] 9B is a diagram showing the timing of Write command processing when the required swap / refresh processing is not completed within the initialization period described in FIG. 8. In this case, the nonvolatile memory device 110 executes the swap / refresh processing in addition to writing each sector data to the flash memory 112 during the Busy period. Note that since the swap / refresh processing of one physical block often takes longer than the maximum allowable Busy period (250 ms or 500 ms in the SD protocol), the above-mentioned swap / refresh processing is often divided and executed across multiple Busy periods.

[0108] 9B, the number of Write command processes that can be executed per second is N, which is less than M in the case of Fig. 9A, due to the swap refresh process. Therefore, the random Write performance of the nonvolatile memory device 110 in this case is N [IOPS], which is lower than the case of Fig. 9A.

[0109] FIG. 10 is a diagram illustrating a method for measuring random read performance.

[0110] Like random write performance, random read performance is measured in IOPS as the number of times per second a 4K byte data read operation can be performed from a randomly specified address on flash memory 112.

[0111] As shown in Figure 10(a), the Read command processing for 4K byte data consists of sending a Read command and receiving a response to it, a Busy period corresponding to reading data from the flash memory 112, and eight sector data reads each consisting of data transmission in units of sectors (512 bytes).

[0112] 10A, the read command processing can be executed m times per second, and the random read performance of the nonvolatile memory device 110 is m [IOPS].

[0113] Fig. 10A is a diagram showing the timing of Read command processing when the required swap / refresh processing is completed within the initialization period described in Fig. 7. In this case, since there is no need to execute the swap / refresh processing during a busy period, it is possible to minimize each busy period, resulting in improved random read performance.

[0114] 10B is a diagram showing the timing of a Read command process when the required swap / refresh process is not completed within the initialization period described in FIG. 8. In this case, the nonvolatile memory device 110 executes the swap / refresh process in addition to reading the next sector data during the Busy period. As with the Write process, the swap / refresh process of one physical block often takes longer than the maximum allowable Busy period (100 ms), and therefore the above-mentioned swap / refresh process is often executed across multiple Busy periods.

[0115] 10B, the number of Read command processes that can be executed per second is n, which is less than the m in the case of Fig. 10A, due to the swap refresh process. Therefore, the random Read performance of the nonvolatile memory device 110 in this case is n [IOPS], which is lower than the case of Fig. 10A.

[0116] Incidentally, when writing data to a physical block, including in a swap / refresh process, the physical block must be erased. In a swap / refresh process, if a physical block with no logical address assigned cannot be selected, a physical block with a low number of rewrites must be erased and then selected as the swap destination physical block or refresh destination physical block. In this case, the busy period of the Write command process or the Read command process becomes even longer.

[0117] 11 is a diagram illustrating an example of a random access class of the nonvolatile memory device 110. The random access class is an expression obtained by grouping the random write performance and random read performance of each nonvolatile memory device 110. Information indicating the random access class is stored in the register unit 117 and is also written on the surface of the housing of the nonvolatile memory device 110, on the package, or in a paper or electronic instruction manual, etc. In this embodiment, the random access class is an unchanging numerical value defined for each nonvolatile memory device 110.

[0118] 11, a nonvolatile storage device 110 of random access class 1 has a random write performance of 500 IOPS or more and a random read performance of 1,500 IOPS or more. Similarly, a nonvolatile storage device 110 of random access class 4 has a random write performance of 50,000 IOPS or more and a random read performance of 100,000 IOPS or more. Note that, in this embodiment, a random access class is defined for a case where predetermined random write performance and random read performance are simultaneously satisfied, but it is also possible to define a random access class for each of the random write performance and the random read performance.

[0119] A nonvolatile memory device 110 that indicates a random access class with a larger numerical value is considered to have higher performance. Therefore, the random access class to be displayed is often estimated based on the timing shown in FIG. 9(a) or FIG. 10(a).

[0120] However, when the nonvolatile memory device 110 is used for a long period of time, the number of times each physical block in the flash memory 112 is rewritten increases, or the number of defective bits increases when data is read from each physical block. This means that the number of physical blocks to be swap-refreshed increases. There is no problem if the swap-refresh process for eliminating these physical blocks to be swap-refreshed is completed during the initialization process period shown in Figure 2. However, if the number of target blocks is large and the swap-refresh process cannot be completed during the initialization process period, the swap-refresh process must be performed during a busy period in the Write command process or the Read command process, as shown in Figures 9(b) and 10(b).

[0121] At this time, there is a possibility that the performance defined by the random access class held or displayed by the nonvolatile memory device 110 may temporarily not be satisfied.

[0122] In order to realize a predetermined function, the host device 100 may need to use a nonvolatile memory device 110 having a predetermined random access class. However, if such a host device 100 uses a nonvolatile memory device 110 that does not satisfy the performance specified by the random access class, a problem occurs in which the predetermined function cannot be realized.

[0123] [1-4. Operation of Memory System to Solve the Problem] To solve the above problem, the nonvolatile memory device 110 according to the present invention is characterized in that, when the random access performance defined by the random access class is lower than the actual random write performance or random read performance, it notifies the host device 100 of this fact. In this specification, "notifying information" may be described as "sending a notification" or "performing a notification."

[0124] FIG. 12 is a diagram illustrating a method in which the nonvolatile memory device 110 notifies the host device 100 of the random access class and the performance for the random access class.

[0125] 12 , the host device 100 transmits a register data read command 1201 to the nonvolatile memory device 110 via the CMD line 124. At this time, the nonvolatile memory device 110 transmits a response 1202 to the register data read command 1201 to the host device 100 via the CMD line 124.

[0126] Thereafter, the nonvolatile memory device 110 transmits register data 1203 to the host device 100 via the DAT line 125. The data transmitted by the register data 1203 is composed of information held in the register unit 117 of the nonvolatile memory device 110, and at least the random access class 1204 and the performance evaluation flag 1205 described in FIG.

[0127] When the value of the performance evaluation flag 1205 is "0", it means that the random access performance of the nonvolatile memory device 110 maintains the performance specified in the random access class 1204, that is, the acquired random access class is valid. On the other hand, when the value of the performance evaluation flag 1205 is "1", it means that the random access performance of the nonvolatile memory device 110 is lower than the performance specified in the random access class 1204.

[0128] 13 and 14 are diagrams illustrating the relationship between the processing of the memory system and the performance evaluation flag 1205 in this embodiment.

[0129] 13, first, at time T1, initialization command processing 1301 is started. In initialization command processing 1301, flash memory management information update processing 701 is first performed as described in Fig. 7. In this process, physical blocks to be swapped and refreshed are detected, and the number of such physical blocks is stored.

[0130] When the flash memory management information update process 701 is completed at time T2, a swap refresh process 702 is subsequently started. As in the case of Fig. 7, in Fig. 13, the number of physical blocks to be swapped and refreshed detected at the start of the initialization command process 1301 is small, so the necessary swap refresh process 702 can be executed within the initialization command process 1301. Therefore, at time T3 when the initialization command process 1301 is completed, the number of physical blocks to be swapped and refreshed becomes 0.

[0131] As a result, the nonvolatile memory device 110 does not need to perform swap refresh processing while repeatedly executing the write or read command processing 1302 from time T4 onwards. This means that the random write performance and random read performance do not deteriorate, and the value "0" is maintained as the performance evaluation flag 1205.

[0132] Therefore, when the host device 100 sends a register data read command 1303 at time T5 during the Write or Read command processing 1302, the value of the performance evaluation flag 1205 multiplexed on the register data 1304 read after receiving a response (not shown) becomes "0".

[0133] 14, when initialization command processing 1401 is started at time T1, the flash memory management information update processing 701 is performed as described in Fig. 8, and then the swap refresh processing 702 is started at time T2. In Fig. 14, since the number of physical blocks to be swapped and refreshed detected at the start of initialization command processing 1401 is large, the necessary swap refresh processing 702 cannot be completed by the end time T3 of initialization command processing 1401, as described in Fig. 8. Therefore, the number of physical blocks to be swapped and refreshed does not become 0 at time T3.

[0134] In this case, the nonvolatile memory device 110 needs to continue executing the swap / refresh process 702 while executing the write or read command process 1302 from time T4 onwards. As explained in Fig. 8, if the swap / refresh process 702 is executed while executing the write or read command process 1302, the number of write command processes or read command processes that can be processed per unit time (e.g., one second) will decrease. In this case, the performance defined by the random access class indicated by the nonvolatile memory device 110 will no longer be able to be maintained, so when the number of physical blocks to be swapped / refreshed is not 0, the value of the performance evaluation flag 1205 indicates "1", which means that the performance will be below that of the random access class.

[0135] Therefore, when the host device 100 sends a register data read command 1402 at time T5 during the Write or Read command processing 1302, it can obtain register data 1403 in which the value "1" is multiplexed as a performance evaluation flag after receiving a response (not shown).

[0136] Thereafter, at time T6, when the number of physical blocks to be swapped and refreshed becomes 0, the value of the performance evaluation flag 1205 changes from "1" to "0" because there is no need to execute the swap and refresh process 702 any more.

[0137] At time T7 after time T6, the host device 100 sends a register data read command 1404, and after receiving a response (not shown), it is possible to obtain register data 1405 in which the value "0" is multiplexed as a performance evaluation flag.

[0138] FIG. 15 is a diagram illustrating an example of the operation of the host device 100 when the performance evaluation flag 1205 having a value of "1" is received.

[0139] The host device 100 transmits the initialization command processing 1401 shown in Fig. 14. The initialization command processing 1401 includes the flash memory management information update processing 701 and the swap / refresh processing 702 executed by the flash memory control unit 115.

[0140] If the swap / refresh process 702 for all physical blocks to be swapped / refreshed is not completed during the initialization command process 1401, the value of the performance evaluation flag 1205 becomes "1".

[0141] The host device 100 transmits an initial register data read command 1501 to the nonvolatile memory device 110. At this time, the nonvolatile memory device 110 transmits register data 1502 to the host device 100 after a response (not shown). The host device 100 detects the random access class 1204 and performance evaluation flag 1205 multiplexed in the register data 1502.

[0142] Because the value of the performance evaluation flag 1205 multiplexed in the register data 1502 is "1", the host device 100 detects that the nonvolatile memory device 110 cannot currently achieve the random access performance defined in the random access class 1204. When the host device 100 determines that it is unacceptable for the random access performance to fall below the random access performance defined in the random access class, the host device 100 sends a forced swap / refresh execution command 1503 to the nonvolatile memory device 110.

[0143] When the nonvolatile memory device 110 receives the forced swap / refresh execution command 1503, the flash memory control unit 115 executes a swap / refresh process 1504 on the physical blocks that have not yet been subjected to the swap / refresh process. The swap / refresh process 1504 executed by the forced swap / refresh execution command 1503 is regarded as a continuation process of the initialization command process 1401, and therefore does not affect random access performance.

[0144] After the swap / refresh initialization process 1504 is completed for all physical blocks to be swapped / refreshed, the performance evaluation flag 1205 becomes "0." At this time, when the host device 100 sends a second register data read command 1505 to the nonvolatile memory device 110, register data 1506 with the value of the performance evaluation flag 1205 set to "0" is received.

[0145] At this time, the host device 100 detects that the random access performance of the nonvolatile memory device 110 can be guaranteed as specified by the random class, and thereafter starts a write or read command process 1302 .

[0146] As described above, in the first embodiment, if the host device 100 determines from the value of the performance evaluation flag 1205 obtained by transmitting a register data read command that the current random access performance of the nonvolatile memory device 110 is lower than the performance specified by the random access class, the host device 100 transmits a forced swap / refresh execution command 1503 to set the number of physical blocks to be swapped / refreshed in the nonvolatile memory device 110 to zero. This allows the write or read command processing 1302 to be executed while ensuring the random access performance specified by the random access class held by the nonvolatile memory device 110. [2. Host Device and Nonvolatile Memory Device According to the Second Embodiment] FIG. 16 is a diagram illustrating the operation of a memory system including a host device according to the second embodiment and a nonvolatile memory device controlled by the host device. The configuration, basic operation, and reliability improvement process of this memory system are the same as those of the first embodiment, and therefore will not be described here.

[0147] 16, the host device 100 transmits a register data read command 1601 to the nonvolatile memory device 110 via the CMD line 124. At this time, the nonvolatile memory device 110 transmits a response 1602 to the register data read command 1601 to the host device 100 via the CMD line 124.

[0148] Thereafter, the nonvolatile memory device 110 communicates the register data 1603 to the host device 100 via the DAT line 125. The register data 1603 includes at least the random access class 1204 and the performance index 1604 multiplexed therein.

[0149] The value of the figure of merit 1604 can take intermediate values ​​between "0" and "9".

[0150] A value of "0" in the performance index 1604 indicates that the nonvolatile memory device 110 is valid, i.e., that the nonvolatile memory device 110 maintains random access class performance. On the other hand, a value of "9" indicates that there are a predetermined number or more physical blocks that require swap or refresh processing during the Write or Read command processing 1302, which will definitely result in a decrease in access performance. In this case, the value "9" corresponds to the value "1" of the performance evaluation flag in FIG. 12.

[0151] When the value of the performance index 1604 is other than "0" or "9," for example, a value of "1" is defined as meaning that performance will not degrade for the time being, but that performance may degrade if Write or Read command processing is executed continuously for a long period of time. A value of "8" is defined as meaning that, although the swap / refresh processing required during the initialization period can currently be completed as shown in Fig. 7, there is a definite possibility that performance will degrade in a short period of time due to the presence of a physical block whose rewrite count is about to exceed the swap execution threshold count in Fig. 5A or a physical block whose number of defective bits is about to exceed the refresh execution threshold defective bit count in Fig. 6A.

[0152] The performance index 1604 includes a write performance index 1605 and a read performance index 1606 .

[0153] FIG. 17 is a diagram illustrating an example of the operation of the host device 100 when it receives a performance index 1604 other than "0."

[0154] As in the first embodiment, the host device 100 executes an initialization command process 1401. The initialization command process 1401 includes a flash memory management information update process 701 and a swap / refresh process 702, which are executed by the flash memory control unit 115.

[0155] In this embodiment, it is assumed that during the initialization command process 1401, the swap process for all physical blocks to be swapped is completed, but the refresh process for all physical blocks to be refreshed is not completed.

[0156] The normal swap process is performed during the busy period of the write command process as well as during the initialization command process 1401. The refresh process is performed during the busy period of the read command process as well as during the initialization command process 1401.

[0157] Therefore, since the necessary swap processing is completed within the period of the initialization command processing 1401, the value of the Write performance index 1605 becomes "0", while the refresh processing is not completed, so the value of the Read performance index 1606 becomes a value other than "0" (here, "6").

[0158] After the initialization command process 1401 is completed, the host device 100 sends a register data read command 1701. The nonvolatile memory device 110 then sends a response (not shown) followed by register data 1702 to the host device. The register data 1702 has a performance index 1604 multiplexed therein, and the host device 100 detects that the value of the write performance index 1605 is "0" and the value of the read performance index 1606 is "6."

[0159] Upon detecting these values, the host device 100 determines that a refresh process is necessary to improve read performance in order to achieve the desired random access performance. Therefore, the host device 100 sends a forced refresh execution command 1703 to the nonvolatile memory device 110, instructing the flash memory control unit 115 to execute a refresh process 1704. As a result of this refresh process 1704, the value of the read performance index 1606 becomes "0."

[0160] After the refresh process 1704 is completed, the host device 100 sends a register data read command 1705, and receives register data 1706 in which the values ​​of the Write performance index 1605 and the Read performance index 1606 are both "0".

[0161] At this time, the host device 100 detects that the random access performance of the nonvolatile memory device 110 can be guaranteed as specified by the random class, and thereafter starts a write or read process 1302 .

[0162] In this embodiment, the performance index has been described as having 10 values ​​ranging from "0" to "9," but the types of values ​​are not limited to these. The number of types of values ​​that the Write performance index 1605 can take and the number of types of values ​​that the Read performance index 1606 can take may differ.

[0163] Furthermore, the host device 100 can arbitrarily determine the operation to be performed when it detects a performance index 1604 that is not "0."

[0164] For example, if the performance index 1604 is equal to or greater than a predetermined value, for example, "6," it may be determined that a swap refresh process is to be executed.

[0165] Also, as shown in FIG. 18, if the value of the Read performance index 1606 is "6", but the value of the Write performance index 1605 is "0", and the host device 100 will only be writing data from now on, then the Write command processing 1801 may be executed without executing the swap refresh processing.

[0166] As described above, in the second embodiment, by notifying the host device 100 of the performance index 1604 instead of the performance evaluation flag 1205, the host device 100 is able to detect the performance level of the non-volatile memory device 110 in more detail.

[0167] Furthermore, by dividing the performance index 1604 into a write performance index 1605 and a read performance index 1606 and notifying them, it becomes possible to perform only the refresh process of the swap / refresh process, or to decide not to perform the swap / refresh process depending on the operation of the host device 100 in the initialization command process 1401, thereby providing the effect of increasing the degree of freedom in designing the host device 100. [3. Host Device and Nonvolatile Storage Device According to Third Embodiment] Figure 19 is a diagram illustrating the operation of a memory system configured from a host device according to a third embodiment and a nonvolatile storage device controlled by the host device.

[0168] The difference from embodiments 1 and 2 is that when the host device 100 sends a register data read command 1901, the non-volatile memory device 110 sends a response 1902 to the register data read command 1901, followed by register data 1903 with a variable random access class 1904 multiplexed thereon.

[0169] The nonvolatile storage device 110 normally displays a normal random access class based on the performance measured under the conditions of FIG. 9( a ) and FIG. 10( a ) in the variable random access class 1904 .

[0170] On the other hand, if physical blocks to be swapped and refreshed remain even after the initialization command processing is completed and performance degradation occurs, the non-volatile memory device I / F unit 114 notifies the host device I / F unit 103 of the host device controller 102 of a class lower than the normal random access class as the variable random access class 1904.

[0171] When the host device 100 receives a random access class lower than the normal random access class, the random access performance of the nonvolatile memory device 110 is reduced, and therefore the host device 100 executes a swap refresh process as necessary.

[0172] As described above, in the third embodiment, by making the random access class variable, the host device 100 can estimate the degree of degradation in the random access performance of the nonvolatile memory device 110. [4. Host Device and Nonvolatile Memory Device According to the Fourth Embodiment] Figure 20 is a diagram illustrating the operation of a memory system configured from a host device according to the fourth embodiment and a nonvolatile memory device controlled by the host device.

[0173] The difference from the first embodiment is that a performance evaluation flag is multiplexed in the response 2001 of the Write command 301 or the Read command 401 included in the Write or Read command process 1302. This allows the host device 100 to acquire the performance evaluation flag 1205 each time the Write or Read command process 1302 is being executed.

[0174] FIG. 21 is a diagram illustrating an example of the operation of the memory system when the value of the performance evaluation flag 1205 changes from "0" to "1" in this embodiment.

[0175] After completing the initialization command process 1301, the host device 100 detects that the value of the performance evaluation flag 1205 is "0" by a register data read command (not shown).

[0176] Next, the host device 100 executes a Write or Read command process 1302. As described in Fig. 20, in this embodiment, the value of the performance evaluation flag 1205 is multiplexed in the response 2001 of the Write command 301 or the Read command 401, so that the host device 100 can detect the value of the performance evaluation flag 1205 each time.

[0177] As the Write or Read command process 1302 continues, a case may occur in which the number of rewrites to a certain physical block exceeds the swap execution threshold number of times, or the number of defective bits when reading data from a certain physical block exceeds the refresh execution threshold number of defective bits.

[0178] At this time, since a swap refresh process is required to maintain a predetermined random access performance, the value of the performance evaluation flag 1205 changes from "0" to "1."

[0179] For example, after transmitting a Read command 401, the host device 100 receives a response 2001 in which a performance evaluation flag 1205 with a value of "1" is multiplexed. If the host device 100 requires the random access performance defined by the random access class of the nonvolatile memory device 110, it transmits a forced swap / refresh execution command 1503 and causes the flash memory control unit 115 to execute a swap / refresh process 1504.

[0180] In the fourth embodiment, the time required for the swap refresh process 1504 is not so long. When the host device 100 detects that the value of the performance evaluation flag 1205 is again "0", the write or read command process 1302 is resumed.

[0181] As described above, even if the value of the performance evaluation flag 1205 is "0" when the initialization process is completed, the value of the performance evaluation flag 1205 may become "1" as various processes continue. In this embodiment, when it is detected that the value of the performance evaluation flag 1205 multiplexed in the response 2001 of the Write command 301 or the Read command 401 is "1", a swap refresh process is executed during the Write or Read command process 1302, making it possible to maintain the random access performance defined by the random access class of the nonvolatile memory device 110.

[0182] In this embodiment, the performance evaluation flag 1205 is acquired from the response 2001 of the Write command 301 or the Read command 401, but it may be acquired from register data obtained by sending a register data read command.

[0183] The same effect can be obtained by using the performance index 1604 instead of the performance evaluation flag 1205.

[0184] Furthermore, as in the third embodiment, the variable random access class 1904 may be notified.

[0185] Although all of the embodiments have been described using an SD bus, similar effects can be achieved using other buses to which a host device and a nonvolatile storage device can be connected. Examples of such buses include a PCI Express bus and a USB bus. The present invention can also be applied to cases where a host device and a nonvolatile storage device are connected via multiple buses. For example, the present invention can be applied to a memory system configured with an SD Express card, which is a nonvolatile storage device having both an SD bus and a PCI Express bus, and a host device that is compatible with both buses.

[0186] The present disclosure can be applied to nonvolatile storage devices such as SD cards and microSD cards, and to host devices that control the nonvolatile storage devices.

Claims

1. A non-volatile storage device connected to a host device, comprising: a non-volatile memory; a memory control unit that reads and writes data to the non-volatile memory; and an interface unit that notifies the host device, wherein if the read performance or write performance falls below a specified access performance, the interface unit notifies the host device that the read performance or write performance falls below the specified access performance.

2. The nonvolatile storage device according to claim 1, wherein the specified access performance is lowered when the memory control unit is unable to complete a specified data transfer process within the period during which the nonvolatile storage device is initialized as instructed by the host device.

3. The nonvolatile storage device according to claim 1, wherein the access performance falls below the predetermined level when a predetermined data movement process is required during the process of the memory control unit reading or writing data to the nonvolatile memory.

4. A nonvolatile storage device according to claim 2 or claim 3, wherein the nonvolatile memory is divided into physical blocks of a predetermined data size, and the predetermined data movement process is a process of moving data from a physical block that has been rewritten more than a threshold value to a different physical block.

5. A nonvolatile storage device according to claim 2 or claim 3, wherein the nonvolatile memory is divided into physical blocks of a predetermined size, and the predetermined data movement process is a process of moving data from a physical block having a number of defective bits greater than a threshold value when read to a different physical block.

6. The nonvolatile memory device according to any one of claims 1 to 3, wherein the interface unit holds information indicating the predetermined access performance.

7. A nonvolatile memory device according to any one of claims 1 to 3, wherein the interface unit holds information indicating the predetermined access performance, and the interface unit notifies an access performance lower than the predetermined access performance.

8. A host device connected to a nonvolatile storage device, comprising a controller having an interface unit that communicates with the nonvolatile storage device, wherein the controller receives notifications from the nonvolatile storage device via the interface unit and sends instructions to the nonvolatile storage device, and wherein the interface unit instructs the nonvolatile storage device to perform a specified data movement process when it receives a notification that the read performance or write performance of the nonvolatile storage device is below a specified access performance.

9. The host device according to claim 8, wherein when said interface unit receives a notification that the access performance falls below a predetermined level, said interface unit determines whether or not it is necessary to instruct said predetermined data movement processing based on said notification.

10. The host device according to claim 8 or 9, wherein the predetermined data movement process moves data from a physical block in the nonvolatile storage device that has been rewritten more than a threshold value to a different physical block.

11. The host device according to claim 8 or claim 9, wherein the predetermined data movement process moves data from a physical block of the nonvolatile storage device in which the number of defective bits at the time of reading is greater than a threshold value to a different physical block.

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