Light-emitting element, method for manufacturing light-emitting element, and display device comprising light-emitting element

Abstract

A light-emitting device according to an embodiment of the present disclosure comprises: a first semiconductor layer; an auxiliary layer on the first semiconductor layer; an active layer on the auxiliary layer; and a second semiconductor layer on the active layer, wherein the auxiliary layer includes a first auxiliary layer surface adjacent to the first semiconductor layer and a second auxiliary layer surface adjacent to the first auxiliary layer surface, the active layer includes a well layer and a barrier layer, and the auxiliary layer has a superlattice structure, the well layer being disposed on the first auxiliary layer surface without being disposed on the second auxiliary layer surface of the auxiliary layer.

Description

Light-emitting element, method for manufacturing light-emitting element, and display device including light-emitting element

[0001] Embodiments of the present disclosure relate to a light-emitting element, a method for manufacturing a light-emitting element, and a display device including the light-emitting element.

[0002] As information technology advances, the importance of display devices, which serve as a connection medium between users and information, is increasing. Display devices may include light-emitting elements having micro- or nano-scale dimensions, and the light-emitting elements may include active layers comprising p-type semiconductors, n-type semiconductors, and quantum well structures.

[0003] Display devices must have various suitable operating characteristics. For example, the color purity of the display device must be improved to improve the luminous efficiency of the display device.

[0004] One aspect of the embodiments of the present disclosure is to provide a light-emitting element capable of increasing color purity, a method for manufacturing the light-emitting element, and a display device including the light-emitting element.

[0005] However, the purpose of the present disclosure is not limited to the above-described purposes, and may be appropriately expanded in various ways without departing from the spirit and scope of the present disclosure.

[0006] A light-emitting device according to an embodiment of the present disclosure comprises a first semiconductor layer; an auxiliary layer on the first semiconductor layer; an active layer on the auxiliary layer; and a second semiconductor layer on the active layer, wherein the auxiliary layer comprises a first auxiliary layer surface adjacent to the first semiconductor layer and a second auxiliary layer surface that is a side surface adjacent to the first auxiliary layer surface, the active layer comprises a well layer and a barrier layer, the auxiliary layer has a superlattice structure, and the well layer can be disposed on the first auxiliary layer surface without being disposed on the second auxiliary layer surface of the auxiliary layer (e.g., without physical contact).

[0007] In some embodiments, the second auxiliary layer surface may be an inclined surface.

[0008] In some embodiments, the first auxiliary layer surface and the well layer may be in contact with each other, and the second auxiliary layer surface and the well layer may not be in contact with each other (e.g., may not be physically in contact with each other).

[0009] According to an embodiment, the auxiliary layer may have a structure in which InGaN and GaN are alternately stacked.

[0010] In an embodiment, the first semiconductor layer may include a first surface and a second surface adjacent to the first surface, wherein the first surface may be a c-plane and the second surface may be a semipolar surface.

[0011] In some embodiments, the auxiliary layer may entirely cover the first side and the second side.

[0012] In some embodiments, the active layer further includes a cap layer on the well layer, and the cap layer may include at least one selected from AlN and AlxGayNz(0≤x≤1,0≤y≤1,0≤z≤1,0≤x+y+z≤1).

[0013] According to an embodiment, in the AlxGayNz(0≤x≤1,0≤y≤1,0≤z≤1,0≤x+y+z≤1), Al may have a composition of 25 mol% or more and less than 100 mol% with respect to Ga.

[0014] Depending on the embodiment, the cap layer may have a thickness of 0.5 nm to 2.5 nm.

[0015] In some embodiments, the cap layer may have the same diameter as the well layer.

[0016] In some embodiments, the light emitting element may have a truncated pyramid shape.

[0017] A method for manufacturing a light-emitting device according to an embodiment of the present disclosure includes the steps of forming an insulating layer (e.g., an electrical insulating layer) on a base substrate; forming a first semiconductor layer on the base substrate; forming an auxiliary layer on the first semiconductor layer; forming an active layer on the auxiliary layer; and forming a second semiconductor layer on the active layer, wherein the step of forming the auxiliary layer on the first semiconductor layer includes the step of forming the auxiliary layer having a first auxiliary layer surface adjacent to the first semiconductor layer and a second auxiliary layer surface that is a side surface adjacent to the first auxiliary layer surface, and the step of forming the active layer on the auxiliary layer includes the step of forming the active layer including a well layer and a barrier layer, wherein the auxiliary layer has a superlattice structure, and the well layer can be disposed on the first auxiliary layer surface without being disposed on the second auxiliary layer surface of the auxiliary layer.

[0018] In an embodiment, the step of forming a first semiconductor layer on the base substrate includes the step of forming the first semiconductor layer having a first surface and a second surface adjacent to the first surface, wherein the first surface is a c-plane, the second surface is a semipolar surface, and the second auxiliary layer surface may be a surface inclined with respect to the first auxiliary layer surface (for example, the second auxiliary layer surface may be inclined with respect to the first auxiliary layer surface).

[0019] In an embodiment, the step of forming the well layer includes: forming a base well layer on the auxiliary layer, the base well layer including a first portion and a second portion; and etching the second portion, wherein the first portion is in contact with (e.g., physically in contact with) a surface of the first auxiliary layer, the second portion is in contact with (e.g., physically in contact with) a surface of the second auxiliary layer, the second auxiliary layer surface is an inclined surface with respect to the surface of the first auxiliary layer (e.g., the second auxiliary layer surface is inclined with respect to the surface of the first auxiliary layer), and the second portion is etched, so that the well layer may not be in contact with the surface of the second auxiliary layer.

[0020] In an embodiment, the second portion is etched by an etching gas including nitrogen (N2) gas and hydrogen (H2) gas, and the hydrogen gas flows at a flow rate of 5% or more and less than 25% with respect to the flow rates of the nitrogen gas and the hydrogen gas, and the second portion can be removed by an in-situ process.

[0021] A display device according to an embodiment of the present disclosure includes a base layer; and a light-emitting element on the base layer, wherein the light-emitting element includes a first semiconductor layer; an auxiliary layer on the first semiconductor layer; an active layer on the auxiliary layer; and a second semiconductor layer on the active layer, wherein the auxiliary layer includes a first auxiliary layer surface adjacent to the first semiconductor layer and a second auxiliary layer surface that is a side surface adjacent to the first auxiliary layer surface, the active layer includes a well layer and a barrier layer, the auxiliary layer has a superlattice structure, and the well layer can be disposed on the first auxiliary layer surface without being disposed on the second auxiliary layer surface of the auxiliary layer.

[0022] In an embodiment, the first semiconductor layer includes a first surface and a second surface adjacent to the first surface, the first surface is a c-plane, the second surface is a semipolar surface and a non-etching surface, the second auxiliary layer surface is an inclined surface, and the auxiliary layer can entirely cover the first surface and the second surface.

[0023] According to an embodiment, the active layer of the light-emitting device further includes a cap layer on the well layer, and the cap layer may include at least one selected from AlN and AlxGayNz(0≤x≤1,0≤y≤1,0≤z≤1,0≤x+y+z≤1).

[0024] According to an embodiment, the display device includes a pixel, the pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may have different diameters.

[0025] According to an embodiment, the well layer includes well layers, the barrier layer includes barrier layers, and the well layers and the barrier layers may be provided alternately.

[0026] According to an embodiment of the present disclosure, a light-emitting element capable of increasing color purity, a method for manufacturing the light-emitting element, and a display device including the light-emitting element can be provided.

[0027] However, the effects of the embodiments of the present disclosure are not limited to the effects described above, and may be appropriately expanded in various ways without departing from the spirit and scope of the present disclosure.

[0028] The above and other features of the embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail with reference to the accompanying drawings.

[0029] Fig. 1 is a schematic plan view showing a display device according to an embodiment.

[0030] FIGS. 2 to 4 are schematic plan views according to embodiments of the pixels illustrated in FIG. 1.

[0031] Fig. 5 is a schematic cross-sectional view of a display device according to an embodiment.

[0032] Figure 6 is a schematic plan view of the first semiconductor layer.

[0033] Fig. 7 is a schematic cross-sectional view of a display device according to an embodiment.

[0034] Fig. 8 is a schematic cross-sectional diagram of a multi-quantum well layer according to an embodiment.

[0035] Figure 9 is a flowchart schematically showing a method for manufacturing a light-emitting element.

[0036] Figures 10 to 18 are schematic cross-sectional views showing a method for manufacturing a light-emitting element.

[0037] The present disclosure may be modified in various appropriate ways and take various suitable forms. Examples are illustrated in the drawings and described in more detail herein. However, this is not intended to limit the present disclosure to any specific form, but rather to encompass all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present disclosure.

[0038] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present disclosure, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0039] In the present disclosure, terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood to not preemptively exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. In the embodiments, when it is said that a part such as a layer, film, region, or plate is "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. In the embodiments, in the present specification, when it is said that a part such as a layer, film, region, or plate is formed on another part, the direction in which it is formed is not limited to the upper direction, but also includes the case where it is formed in the side or lower direction. In the embodiments, when it is said that a part such as a layer, film, region, or plate is "under" another part, this includes not only the case where it is "directly below" the other part, but also the case where there is another part in between.

[0040] Embodiments of the present disclosure relate to a light-emitting element, a method for manufacturing the light-emitting element, and a display device including the light-emitting element. Hereinafter, a light-emitting element, a method for manufacturing the light-emitting element, and a display device including the light-emitting element according to embodiments will be described with reference to the accompanying drawings.

[0041] First, the display device (DD) will be described with reference to FIGS. 1 to 4.

[0042] Fig. 1 is a schematic plan view showing a display device according to an embodiment. Figs. 2 to 4 are schematic plan views according to an embodiment of the pixel shown in Fig. 1.

[0043] Referring to FIG. 1, a display device (DD) is configured to emit light. The display device (DD) includes a light-emitting element (LD) (see FIG. 5). Depending on the embodiment, the display device (DD) may be a device that displays a moving image and / or a still image. The display device (DD) may be used as a display screen of various suitable products, such as, for example, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, and an Ultra Mobile PC (UMPC), as well as a television, a laptop, a monitor, a billboard, and / or an Internet of Things (IOT) device. However, the application fields of the display device (DD) are not limited to specific examples.

[0044] The display device (DD) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display device (DD) is not limited to a square, and may be formed in a round shape, such as, for example, another polygon, circle, or oval. The display device (DD) may be formed to be flat, but is not limited thereto. For example, the display device (DD) may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device (DD) may be formed to be flexible so as to be bent, curved, folded, or rolled.

[0045] In embodiments of the present disclosure, the first direction (DR1) may be a “horizontal” direction in the row direction of the pixels (PXL). The second direction (DR2) may be a column direction of the pixels (PXL). The third direction (DR3) may be a display direction of the display device (DD) or a normal direction of a plane on which the base layer (BSL) is provided.

[0046] A display device (DD) may include a display area (DA) and a non-display area (NDA). The non-display area (NDA) may refer to an area outside the display area (DA). The non-display area (NDA) may surround at least a portion of the display area (DA).

[0047] The base layer (BSL) may provide a base member of the display device (DD). The base layer (BSL) may be a rigid or flexible substrate and / or film. For example, the base layer (BSL) may be a rigid substrate made of glass and / or tempered glass, a flexible substrate (or thin film) made of plastic and / or metal, and / or at least one insulating layer (e.g., an electrical insulating layer). In some embodiments, the base layer (BSL) may include silicon (Si). The material and / or physical properties of the base layer (BSL) are not particularly limited. In some embodiments, the base layer (BSL) may be substantially transparent. Here, substantially transparent may mean that light (e.g., visible light) can be transmitted with a transmittance of at least one degree. In other embodiments, the base layer (BSL) may be translucent or opaque. In some embodiments, the base layer (BSL) may include a reflective material.

[0048] The display area (DA) may be an area where pixels (PXL) are provided. The non-display area (NDA) may be an area where pixels (PXL) are not provided. In the non-display area (NDA), driving circuits, wires, and pads connected to the pixels (PXL) of the display area (DA) may be arranged.

[0049] In some embodiments, pixels (PXL) (or sub-pixels (SPX)) may be provided in a stripe or pentile (PENTILE®, PENTILE® is a registered trademark of Samsung Display Co., Ltd.) array structure (e.g., RGBG matrix, RGBG structure, or RGBG matrix structure), but the present disclosure is not necessarily limited thereto.

[0050] According to an embodiment, a pixel (PXL) (or sub-pixels (SPX)) may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3). At least one of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may form one pixel unit (PXU) capable of emitting light of various suitable colors. Although FIG. 1 illustrates that each pixel (PXL) is provided with three sub-pixels (SPX1, SPX2, SPX3), for example, a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3), the embodiments of the present specification are not limited thereto.

[0051] According to an embodiment, the sub-pixels (SPX) may have a rectangular, square, or rhombus-shaped planar shape. For example, each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2), as shown in FIG. 1. Alternatively, the sub-pixels (SPX) may have a square or rhombus-shaped planar shape including sides having the same length in the first direction (DR1) and the second direction (DR2).

[0052] In one example, the areas of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be substantially the same, but are not limited thereto. For example, at least one of the areas of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be different from another one. Alternatively, any two of the areas of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be substantially the same, and the remaining one may be different from the two. Alternatively, the areas of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may be different from each other.

[0053] Referring to FIG. 2, the first sub-pixel (SPX1) may be arranged in a first direction (DR1) with one of the second sub-pixels (SPX2) and the third sub-pixel (SPX3) and may be arranged in a second direction (DR2) with the other one. For example, the first sub-pixel (SPX1) may be arranged in the first direction (DR1) with the second sub-pixel (SPX2), and the first sub-pixel (SPX1) may be arranged in the second direction (DR2) with the third sub-pixel (SPX3).

[0054] In one example, the third sub-pixel (SPX3) may be adjacent to the first sub-pixel (SPX1) and the second sub-pixel (SPX2) along the second direction (DR2). In one example, the areas of the first and second sub-pixels (SPX1, SPX2) may be substantially the same, and the area of ​​the third sub-pixel (SPX3) may be different from the areas of the first and second sub-pixels (SPX1, SPX2). For example, the area of ​​the third sub-pixel (SPX3) may be larger than the areas of the first and second sub-pixels (SPX1, SPX2).

[0055] Referring to FIG. 3, each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may have a hexagonal (e.g., regular hexagon) planar shape. In one example, two adjacent sides of the six sides of each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) may face one side of another adjacent sub-pixel (SPX).

[0056] Referring to FIG. 4, the pixel (PXL) may further include a fourth sub-pixel (SPX4). The fourth sub-pixel (SPX4) may be arranged diagonally relative to the first sub-pixel (SPX1). For example, the first sub-pixel (SPX1) may be arranged adjacent to the fourth sub-pixel (SPX4) in a direction crossing between the first direction (DR1) and the second direction (DR2).

[0057] The first sub-pixel (SPX1) may be arranged along the first direction (DR1) with the second sub-pixel (SPX2). The first sub-pixel (SPX1) may be arranged along the second direction (DR2) with the third sub-pixel (SPX3).

[0058] The second sub-pixel (SPX2) may be arranged along the second direction (DR2) with respect to the fourth sub-pixel (SPX4). The second sub-pixel (SPX2) may be arranged along a diagonal direction with respect to the third sub-pixel (SPX3). For example, the second sub-pixel (SPX2) may be arranged adjacent to the fourth sub-pixel (SPX4) in a direction crossing between the opposite direction of the first direction (DR1) and the second direction (DR2).

[0059] The third sub-pixel (SPX3) can be arranged along the third direction (DR3) with the fourth sub-pixel (SPX4).

[0060] In some embodiments, the third sub-pixel (SPX3) may include a plurality of spaced apart sub-pixel portions. For example, the third sub-pixel (SPX3) may include a third_1st sub-pixel (SPX3_1), a third_2nd sub-pixel (SPX3_2), a third_3rd sub-pixel (SPX3_3), and a third_4th sub-pixel (SPX3_4). The third_1st sub-pixel (SPX3_1), the third_2nd sub-pixel (SPX3_2), the third_3rd sub-pixel (SPX3_3), and the third_4th sub-pixel (SPX3_4) may be arranged in a clockwise direction.

[0061] For example, the 3_1st sub-pixel (SPX3_1), the 3_2nd sub-pixel (SPX3_2), the 3_3rd sub-pixel (SPX3_3), and the 3_4th sub-pixel (SPX3_4) can be sequentially arranged along the four sides of the rectangle. For example, the 3_1st sub-pixel (SPX3_1) can be arranged at the upper left of the rectangle, the 3_2nd sub-pixel (SPX3_2) can be arranged at the upper right, the 3_3rd sub-pixel (SPX3_3) can be arranged at the lower right, and the 3_4th sub-pixel (SPX3_4) can be arranged at the lower left.

[0062] In some embodiments, the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) (the third_1st sub-pixel (SPX3_1), the third_2nd sub-pixel (SPX3_2), the third_3rd sub-pixel (SPX3_3), and the third_4th sub-pixel (SPX3_4) respectively) may have different diameters (e.g., the length of the longest diagonal among the lengths of the diagonals of the sub-pixels in FIG. 4). For example, the diameter of the second sub-pixel (SPX2) may be larger than that of the first sub-pixel (SPX1). The diameter of the first sub-pixel (SPX1) may be larger than that of the third sub-pixel (SPX3) (the third_1st sub-pixel (SPX3_1), the third_2nd sub-pixel (SPX3_2), the third_3rd sub-pixel (SPX3_3), and the third_4th sub-pixel (SPX3_4) respectively). The first sub-pixel (SPX1) may have the same diameter as the fourth sub-pixel (SPX4).

[0063] According to an embodiment, the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) (the third_1st sub-pixel (SPX3_1), the third_2nd sub-pixel (SPX3_2), the third_3rd sub-pixel (SPX3_3), and the third_4th sub-pixel (SPX3_4) respectively) may have different areas. The first sub-pixel (SPX1) may have the same area as the fourth sub-pixel (SPX4).

[0064] In some embodiments, the area of ​​the second sub-pixel (SPX2) may be larger than the area of ​​the first sub-pixel (SPX1). In some embodiments, the area of ​​the first sub-pixel (SPX1) may be larger than the areas of each of the 3_1 sub-pixel (SPX3_1), the 3_2 sub-pixel (SPX3_2), the 3_3 sub-pixel (SPX3_3), and the 3_4 sub-pixel (SPX3_4). In some embodiments, the area of ​​the first sub-pixel (SPX1) may be the same as the area of ​​the 4th sub-pixel (SPX4). However, the present disclosure is not limited thereto.

[0065] In the present disclosure, the first to fourth sub-pixels (SPX1 to SPX4) can form one pixel (PXL). According to an embodiment, the first sub-pixel (SPX1) and the fourth sub-pixel (SPX4) can emit first light, the second sub-pixel (SPX2) can emit second light, and the third sub-pixel (SPX3) can emit third light. Here, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band may be a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0066] Each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), the third sub-pixel (SPX3), and the fourth sub-pixel (SPX4) may include an inorganic light-emitting element including an inorganic material that emits light. For example, the light-emitting element (LD) may be an inorganic light-emitting element including an inorganic semiconductor, and may be a micro LED (Light Emitting Diode).

[0067] Hereinafter, a display device (DD) according to an embodiment will be described with reference to FIGS. 5 and 6.

[0068] Fig. 5 is a schematic cross-sectional view of a display device according to an embodiment. Fig. 5 may be a diagram illustrating an embodiment in which an active layer (AL) includes a single quantum well structure. Fig. 6 is a schematic plan view of a first semiconductor layer. Fig. 6 is a schematic diagram illustrating crystal planes of the first semiconductor layer (SCL1).

[0069] Referring to FIG. 5, the display device (DD) may include a pixel circuit layer (PCL) and a light emitting element layer (LEL).

[0070] A pixel circuit layer (PCL) may be a layer including pixel circuits for driving light-emitting elements (LD). The pixel circuit layer (PCL) may include a base layer (BSL), conductive layers (e.g., electrically conductive layers) for forming pixel circuits, and insulating layers (e.g., electrically insulating layers) disposed between the conductive layers.

[0071] According to an embodiment, the pixel circuit may include circuit elements (e.g., driving transistors, etc.) that are electrically connected to light-emitting elements (LD) to provide electrical signals for causing the light-emitting elements (LD) to emit light.

[0072] A light emitting element layer (LEL) may be disposed on a pixel circuit layer (PCL). The light emitting element layer (LEL) may include a light emitting element (LD), an insulating layer (IPL) (e.g., an electrical insulating layer (IPL)), a first electrode (ELT1), a second electrode (ELT2), and an intermediate layer (IL).

[0073] A light emitting element (LD) may be disposed on a pixel circuit layer (PCL) (or base layer (BSL)). According to an embodiment, the light emitting element (LD) may include a first semiconductor layer (SCL1), an auxiliary layer (SL), an active layer (AL), and a second semiconductor layer (SCL2).

[0074] A light emitting element (LD) may have a first end (EP1) and a second end (EP2). In some embodiments, a first semiconductor layer (SCL1) may be adjacent to the first end (EP1) of the light emitting element (LD), and a second semiconductor layer (SCL2) may be adjacent to the second end (EP2).

[0075] The first semiconductor layer (SCL1) is disposed on one surface of the active layer (AL) (or auxiliary layer (SL)) and may include an n-type semiconductor, depending on the embodiment. For example, the first semiconductor layer (SCL1) may include at least one of n-doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer (SCL1) may be doped with an n-type dopant, and for example, the first semiconductor layer (SCL1) may be n-GaN doped with an n-type dopant. However, the present disclosure is not limited thereto, and the first semiconductor layer (SCL1) may include various suitable n-type semiconductor materials in the general technical field.

[0076] The first semiconductor layer (SCL1) may include a first surface (S1) and a second surface (S2) adjacent to the first surface (S1).

[0077] The first side (S1) may be a generally flat side. The first side (S1) may be generally parallel to the base layer (BSL).

[0078] The first surface (S1) is a polar surface on which an n-type semiconductor is grown, and may be a c-plane. In some embodiments, the first surface (S1) may be a {0001} crystal plane. In embodiments of the present disclosure, the first surface (S1) may be defined as a first crystal plane.

[0079] The second surface (S2) may be a surface inclined with respect to the first surface (S1) (for example, inclined with respect to the first surface (S1)). The second surface (S2) may be a surface inclined with respect to the base layer (BSL) (for example, inclined with respect to the base layer (BSL)). For example, the second surface (S2) may be an inclined side wall (or side surface) of the first semiconductor layer (SCL1). The second surface (S2) may be inclined with respect to the first surface (S1), and the width of the first semiconductor layer (SCL1) may decrease as it gets closer to the base layer (BSL) (or as it goes from the first end (EP1) to the second end (EP2). The first semiconductor layer (SCL1) may have a trapezoidal cross-section.

[0080] The second surface (S2) may be a semipolar surface on which an n-type semiconductor is grown. In some embodiments, the second surface (S2) may be a {n -n 0 k} crystal plane. Here, n and k are each integers greater than or equal to 1. For example, the second surface (S2) may be a {1 -1 0 1} crystal plane. However, the present disclosure is not limited thereto. In some embodiments, the second surface (S2) may be a {n 0 -nk} crystal plane or a {nn -2n k} crystal plane. Here, n and k are each integers greater than or equal to 1. In some embodiments of the present disclosure, the second surface (S2) may be defined as a second crystal plane.

[0081] The second surface (S2) is a surface on which the semiconductor is formed by epitaxial growth and may be a non-etched surface. For example, the second surface (S2) may be a crystal surface on which the semiconductor is formed by epitaxial growth.

[0082] Referring to FIG. 6, the first surface (S1) may have a hexagonal shape when viewed in a plan view. When viewed in a plan view, the first surface (S1) may have a hexagonal shape, and the light emitting element (LD) may have a truncated-inverted-pyramid shape. In embodiments, the light emitting element (LD) may have a truncated pyramid shape. For example, the light emitting element (LD) may have a truncated hexagonal column shape. In FIG. 6, the first surface (S1) is illustrated as having a hexagonal shape, but the present disclosure is not limited thereto. The first surface (S1) may have a circular, elliptical, or polygonal shape.

[0083] When the first side (S1) has a hexagonal shape, the second side (S2) may include a second_first side (S2_1), a second_second side (S2_2), a second_third side (S2_3), a second_fourth side (S2_4), a second_fifth side (S2_5), and a second_sixth side (S2_6). Each of the second_first side (S2_1), the second_second side (S2_2), the second_third side (S2_3), the second_fourth side (S2_4), the second_fifth side (S2_5), and the second_sixth side (S2_6) may be sequentially provided clockwise along the six sides of the first side (S1).

[0084] Each of the second_first surface (S2_1), the second_second surface (S2_2), the second_third surface (S2_3), the second_fourth surface (S2_4), the second_fifth surface (S2_5), and the second_sixth surface (S2_6) may be inclined with respect to the first surface (S1). In some embodiments, the angles formed by each of the second_first surface (S2_1), the second_second surface (S2_2), the second_third surface (S2_3), the second_fourth surface (S2_4), the second_fifth surface (S2_5), and the second_sixth surface (S2_6) with respect to the first surface (S1) may be equal to each other. However, the present disclosure is not limited thereto, and the angles formed by each of the second_first surface (S2_1), the second_second surface (S2_2), the second_third surface (S2_3), the second_fourth surface (S2_4), the second_fifth surface (S2_5), and the second_sixth surface (S2_6) with the first surface (S1) may be different from each other.

[0085] The auxiliary layer (SL) may be disposed on the first side (S1) and the second side (S2). The auxiliary layer (SL) may be adjacent to the first side (S1) and the second side (S2). In an embodiment, the auxiliary layer (SL) may be disposed directly on the first side (S1) and the second side (S2). In an embodiment, the auxiliary layer (SL) may be in contact with (e.g., physically in contact with) the first side (S1) and the second side (S2). In an embodiment, the auxiliary layer (SL) may entirely cover the first side (S1) and the second side (S2).

[0086] The auxiliary layer (SL) may be disposed between the first semiconductor layer (SCL1) and the active layer (AL), and may alleviate the stress difference between the first semiconductor layer (SCL1) and the active layer (AL). The auxiliary layer (SL) may have a superlattice structure. The auxiliary layer (SL) may have a superlattice structure.

[0087] For example, the auxiliary layer (SL) may include InGaN and GaN. In some embodiments, the auxiliary layer (SL) may be formed in a structure in which InGaN and GaN are alternately laminated. However, the present disclosure is not limited thereto.

[0088] The auxiliary layer (SL) may include a first auxiliary layer surface (A1) and a second auxiliary layer surface (A2).

[0089] The first auxiliary layer plane (A1) may be a polar plane and may be a c-plane. The first auxiliary layer plane (A1) may be adjacent to the first semiconductor layer (SCL1). The first auxiliary layer plane (A1) may be adjacent to the first plane (S1). The first auxiliary layer plane (A1) may be a substantially flat plane. The first auxiliary layer plane (A1) may be substantially parallel to the base layer (BSL).

[0090] The second auxiliary layer surface (A2) is adjacent to the first auxiliary layer surface (A1) and may be an inclined surface with respect to the second auxiliary layer surface (A2). The second auxiliary layer surface (A2) may be an inclined surface with respect to the base layer (BSL) (for example, may be inclined with respect to the base layer (BSL)). For example, the second auxiliary layer surface (A2) may be an inclined side wall (or side surface) of the auxiliary layer (SL). The second auxiliary layer surface (A2) may be a semi-polar surface.

[0091] An active layer (AL) may be disposed between a first semiconductor layer (SCL1) and a second semiconductor layer (SCL2). The active layer (AL) may include a single-quantum well or a multi-quantum well structure. For example, the active layer (AL) may have a single-quantum well structure including one well layer (QW) and one barrier layer (QB) as illustrated in FIG. 5.

[0092] The active layer (AL) may include a well layer (QW) and a barrier layer (QB) for forming a quantum well structure. In some embodiments, the active layer (AL) may further include a cap layer (CPL).

[0093] The well layer (QW) may be disposed between the first surface (S1) (or the first auxiliary layer surface (A1)) and the second semiconductor layer (SCL2). The well layer (QW) may be disposed on the first surface (S1) (or the first auxiliary layer surface (A1)). In an embodiment, the well layer (QW) may be disposed directly on the first auxiliary layer surface (A1). In an embodiment, the well layer (QW) may be in contact with (e.g., physically in contact with) the first auxiliary layer surface (A1). In an embodiment, the well layer (QW) may entirely cover the first auxiliary layer surface (A1). The well layer (QW) may be in contact with (e.g., physically in contact with) a crystal plane of a c-plane.

[0094] The well layer (QW) may not be disposed between the second surface (S2) and the second semiconductor layer (SCL2) when viewed in the first direction (DR1) or the second direction (DR2). The well layer (QW) may not be in contact with (e.g., may not physically contact) the second surface (S2) (or the second auxiliary layer surface (A2)). The well layer (QW) may not cover the second auxiliary layer surface (A2). The well layer (QW) may not be in contact with (e.g., may not physically contact) a semipolar crystal plane.

[0095] The well layer (QW) may not be in contact with a side surface of the auxiliary layer (SL) (e.g., the second auxiliary layer surface (A2)) and may expose the side surface of the auxiliary layer (SL). The well layer (QW) according to embodiments of the present disclosure may not be disposed on the second auxiliary layer surface (A2), thereby increasing the color purity of the light emitting element (LD).

[0096] In some embodiments, the well layer (QW) may include In. In some embodiments, the well layer (QW) may include InGaN. However, the present disclosure is not limited thereto, and the well layer (QW) may include any suitable well layer material used in the art.

[0097] In an embodiment, the cap layer (CPL) may be disposed on the well layer (QW). In an embodiment, at least a portion of the cap layer (CPL) may be disposed between the well layer (QW) and the barrier layer (QB). In an embodiment, the cap layer (CPL) may be disposed directly on the well layer (QW). In an embodiment, the cap layer (CPL) may be in contact with (e.g., physically in contact with) the well layer (QW). The cap layer (CPL) may cover one surface of the well layer (QW). In an embodiment, the cap layer (CPL) may not be in contact with (e.g., physically in contact with) a side surface of the auxiliary layer (SL) (e.g., a second auxiliary layer surface A2) and may expose the side surface of the auxiliary layer (SL). However, the position of the cap layer (CPL) is not limited to the embodiments of the present disclosure.

[0098] For example, although FIG. 5 illustrates that the active layer (AL) has a structure in which the cap layer (CPL) is disposed between the well layer (QW) and the barrier layer (QB) (e.g., a structure in which the well layer (QW), the cap layer (CPL), and the barrier layer (QB) are sequentially stacked), the structure of the active layer (AL) is not limited thereto. According to an embodiment, the active layer (AL) may have a structure in which the cap layer (CPL) is disposed at the uppermost portion. For example, the active layer (AL) may also have a structure in which the barrier layer (QB), the well layer (QW), and the cap layer (CPL) are sequentially stacked on the auxiliary layer (SL). For example, the barrier layer (QB) may be in full contact with the auxiliary layer (SL) (e.g., in full physical contact), the well layer (QW) may be disposed on the barrier layer (QB), and the cap layer (CPL) may be disposed on the well layer (QW). According to an embodiment, the active layer (AL) may have a structure in which a well layer (QW), a barrier layer (QB), and a cap layer (CPL) are sequentially stacked on an auxiliary layer (SL). For example, at least a portion of the barrier layer (QB) may be disposed between the well layer (QW) and the cap layer (CPL), and the cap layer (CPL) may be disposed on at least a portion of the barrier layer (QB).

[0099] The cap layer (CPL) may include a group III nitride semiconductor. For example, the cap layer (CPL) may include one or more of GaN, AlN, and AlxGayNz(0≤x≤1,0≤y≤1,0≤z≤1,0≤x+y+z≤1). In an embodiment, when the cap layer (CPL) includes AlxGayNz(0≤x≤1,0≤y≤1,0≤z≤1,0≤x+y+z≤1), in the chemical formula of AlxGayNz(0≤x≤1,0≤y≤1,0≤z≤1,0≤x+y+z≤1), Al may have a composition of 25 mol% or more and less than 100 mol% with respect to Ga.

[0100] The cap layer (CPL) may have a thickness of 0.5 nm to 2.5 nm. However, the present disclosure is not limited thereto. Hereinafter, the thickness of a component in the present disclosure may be defined in a direction perpendicular to the plane on which the component is arranged.

[0101] The cap layer (CPL) may have, in a plan view, the same diameter as the barrier layer (QW), depending on the embodiment. The cap layer (CPL) may have, in a plan view, the same area as the barrier layer (QW), depending on the embodiment.

[0102] The barrier layer (QB) may be disposed between the auxiliary layer (SL) and the second semiconductor layer (SCL2). The barrier layer (QB) may be disposed between the first surface (S1) (or the first auxiliary layer surface (A1)) and the second semiconductor layer (SCL2). The barrier layer (QB) may be disposed on the first surface (S1) (or the first auxiliary layer surface (A1)). According to an embodiment, at least a portion of the barrier layer (QB) may be disposed on the cap layer (CPL). The barrier layer (QB) may be disposed between the second surface (S2) (or the second auxiliary layer surface (A2)) and the second semiconductor layer (SCL2) when viewed in the first direction (DR1) or the second direction (DR2). At least a portion of the barrier layer (QB) may be disposed on at least a portion of the auxiliary layer (SL).

[0103] In some embodiments, the barrier layer (QB) may include GaN. However, the present disclosure is not limited thereto, and the barrier layer (QB) may include any suitable barrier layer material used in the art.

[0104] The second semiconductor layer (SCL2) is disposed on the other surface of the active layer (AL) and may include a p-type semiconductor, depending on the embodiment. For example, the second semiconductor layer (SCL2) may include one or more of p-doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer (SCL2) may be doped with a p-type dopant, and for example, the second semiconductor layer (SCL2) may be p-GaN doped with a p-type dopant. However, the present disclosure is not limited thereto, and the second semiconductor layer (SCL2) may include various suitable p-type semiconductor materials used in the art.

[0105] According to an embodiment, at least a portion of the second semiconductor layer (SCL2) may be disposed on the cap layer (CPL). According to an embodiment, the second semiconductor layer (SCL2) may be disposed on the barrier layer (QB). According to an embodiment, the second semiconductor layer (SCL2) may be in contact with (e.g., physically in contact with) the barrier layer (QB). According to an embodiment, the second semiconductor layer (SCL2) may entirely cover the barrier layer (QB). However, the present disclosure is not limited thereto, and an electron blocking layer (EBL) may further be disposed between the barrier layer (QB) and the second semiconductor layer (SCL2).

[0106] An intermediate layer (IL) may be disposed on a pixel circuit layer (PCL). The intermediate layer (IL) may be disposed between light-emitting elements (LD). In some embodiments, the intermediate layer (IL) may be an insulating layer (e.g., an electrical insulating layer). The intermediate layer (IL) may fill at least a portion of the space between the light-emitting elements (LD).

[0107] According to an embodiment, the intermediate layer (IL) may include an organic material and / or an inorganic material. For example, the organic material may include one or more of the group consisting of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, polyester resin, polyphenylenesulfide resin, and benzocyclobutene. For example, the inorganic material may include one or more of the group consisting of silicon nitride (SiNx), aluminum nitride (AlNx), titanium nitride (TiNx), silicon oxide (SiOx), aluminum oxide (AlxOy), titanium oxide (TiOx), silicon oxycarbide (SiOxCy), and silicon oxynitride (SiOxNy). However, the present disclosure is not limited thereto.

[0108] An insulating layer (IPL) may be disposed on the intermediate layer (IL). At least a portion of the insulating layer (IPL) may be in contact with (e.g., physically in contact with) at least a portion of the first semiconductor layer (SCL1). At least a portion of the insulating layer (IPL) may be in contact with (e.g., physically in contact with) at least a portion of the second semiconductor layer (SCL2).

[0109] The insulating layer (IPL) may include an insulating material (e.g., an electrically insulating material). For example, the insulating layer (IPL) may include silicon oxide (SiOx). For example, the insulating layer (IPL) may include silicon dioxide (SiO2). The insulating layer (IPL) may include an insulating material (e.g., an electrically insulating material) and may electrically insulate the second semiconductor layer (SCL2) and the second electrode (ELT2). For example, the insulating layer (IPL) may prevent contact between the second semiconductor layer (SCL2) and the second electrode (ELT2) or reduce contact (e.g., physical contact).

[0110] According to an embodiment, the first electrode (ELT1) may be an anode electrode, and the second electrode (ELT2) may be a cathode electrode. The first electrode (ELT1) may be electrically connected to the first semiconductor layer (SCL2), and the second electrode (ELT2) may be electrically connected to the second semiconductor layer (SCL2).

[0111] According to an embodiment, the first electrode (ELT1) and the second electrode (ELT2) may include a conductive material (e.g., an electrically conductive material). For example, the first electrode (ELT1) may include a conductive material having reflective properties (e.g., an electrically conductive material), and the second electrode (ELT2) may include a transparent conductive material, but the present disclosure is not necessarily limited thereto.

[0112] According to an embodiment, the display device (DD) may further include an encapsulation film. The encapsulation film may be disposed on the light-emitting element (LD) (e.g., the second electrode (ELT2)). The encapsulation film may include a plurality of insulating films (e.g., electrical insulating films) covering the light-emitting element (LD). According to an embodiment, the encapsulation film may have a structure in which inorganic films and organic films are alternately laminated.

[0113] Hereinafter, with reference to FIGS. 7 and 8, a display device (DD) in which an active layer (AL') has a multi-well structure according to an embodiment will be described. The embodiment illustrated in FIGS. 7 and 8 differs from the embodiment illustrated in FIG. 5 in that the active layer (AL') has a multi-well structure. Any content that overlaps with the above will not be described again.

[0114] Fig. 7 is a schematic cross-sectional view of a display device according to an embodiment. Fig. 7 may be a diagram illustrating an embodiment in which an active layer (AL') includes a multi-quantum well structure. Fig. 8 is a schematic cross-sectional view of a multi-quantum well layer according to an embodiment. Fig. 8 is a schematic drawing of an embodiment of the multi-quantum well layer (MQ) of Fig. 7.

[0115] Referring to FIGS. 7 and 8, the active layer (AL') may have a multi-quantum well structure including a multi-quantum well layer (MQ). The multi-quantum well layer (MQ) may be disposed on the auxiliary layer (SL). The multi-quantum well layer (MQ) may be disposed between the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2).

[0116] A multiple quantum well layer (MQ) may include at least two well layers (QW') and at least two barrier layers (QB'). The well layers (QW') and the barrier layers (QB') may be provided alternately.

[0117] Even when the active layer (AL') includes multiple quantum well layers (MQ), as described above, the well layers (QW') may not be in contact with the semipolar crystal plane (e.g., may not be physically in contact). For example, the well layer (QW') may expose a side surface of a plane disposed underneath the well layer (QW').

[0118] In some embodiments, the multi-quantum well layer (MQ) may have a structure in which a well layer (QW') is disposed at the bottom, a barrier layer (QB') is disposed on the well layer (QW'), and the well layers (QW') and the barrier layers (QB') are provided alternately. In some embodiments, the barrier layer (QB') may be disposed directly on the auxiliary layer (SL). However, the present disclosure is not limited thereto.

[0119] In some embodiments, the multi-quantum well layer (MQ) may have a structure in which a barrier layer (QB') is disposed at the bottom, a well layer (QW') is disposed on the barrier layer (QB'), and the well layers (QW') and the barrier layers (QB') are provided alternately. In some embodiments, the well layer (QW') may be disposed directly on the auxiliary layer (SL).

[0120] In some embodiments, the cap layer (CPL') may be disposed on a multi-quantum well layer (MQ). In some embodiments, the cap layer (CPL') may be disposed on top of the active layer (AL'). However, the present disclosure is not limited thereto.

[0121] Hereinafter, a method for manufacturing a light-emitting element (LD) according to embodiments of the present disclosure will be described with reference to FIGS. 9 to 18. FIG. 9 is a flowchart schematically illustrating a method for manufacturing a light-emitting element. FIGS. 10 to 18 are schematic cross-sectional views schematically illustrating a method for manufacturing a light-emitting element.

[0122] Referring to FIG. 9, a method for manufacturing a light emitting element (LD) may include a step of forming an insulating layer (e.g., an electrical insulating layer) on a base substrate (S50), a step of forming a first semiconductor layer (S100), a step of forming an auxiliary layer (S200), a step of forming an active layer (S300), and a step of forming a second semiconductor layer (S400).

[0123] Referring to FIG. 10, in step S50 of forming an insulating layer on a base substrate, a base substrate (SUB) may be prepared. The base substrate (SUB) may include a transparent substrate such as a sapphire substrate or glass. However, the present disclosure is not limited thereto.

[0124] Depending on the embodiment, the base substrate (SUB) may include GaN, SiC, ZnO, Si, GaP and / or GaAs, and the base substrate (SUB) may include a conductive substrate (e.g., an electrically conductive substrate).

[0125] According to an embodiment, a buffer layer (BFL) may be optionally formed on a base substrate (SUB). The buffer layer (BFL) may be disposed on one surface (or upper surface) of the base substrate (SUB).

[0126] The buffer layer (BFL) can play a role in reducing the difference in lattice constant between the first semiconductor layer (SCL1) formed on the buffer layer (BFL) and the base substrate (SUB).

[0127] The buffer layer (BFL) may include an undoped semiconductor. The buffer layer (BFL) may include substantially the same material as the first semiconductor layer (SCL1), but may be a material that is not doped as an n-type or p-type material, or may have a doping concentration lower than that of the first semiconductor material layer (SCL1). For example, the buffer layer (BFL) may include one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. However, the present disclosure is not limited thereto.

[0128] Referring to FIGS. 11 and 12, in the step (S50) of forming an insulating layer on a base substrate, an insulating layer (IPL) may be formed on a buffer layer (BFL) (or base substrate (SUB)).

[0129] The step (S50) of forming an insulating layer on the base substrate may include a step of forming a base insulating layer (B_IPL) on the base substrate (SUB). To form the insulating layer (IPL), the base insulating layer (B_IPL) may be formed (or provided) on the buffer layer (BFL) (or the base substrate (SUB)).

[0130] The base insulating layer (B_IPL) is a base layer for forming an insulating layer (IPL) and may include an insulating material (e.g., an electrical insulating material). For example, the base insulating layer (B_IPL) may include silicon oxide (SiOx). For example, the base insulating layer (B_IPL) may include silicon dioxide (SiO2).

[0131] The base insulating layer (B_IPL) can be deposited on the buffer layer (BFL) (or base substrate (SUB)) by a plasma-enhanced chemical vapor deposition (PECVD) process. The base insulating layer (B_IPL) can be deposited to have a thickness of 100 nm to 500 nm.

[0132] The step (S50) of forming an insulating layer on a base substrate may include a step of etching the base insulating layer (B_IPL). The base insulating layer (B_IPL) may be etched through a photolithography process, an electron-beam lithography process, and / or a nanoimprint lithography (NIL) process.

[0133] The base insulating layer (B_IPL) can be etched to define an opening (H). For example, the base insulating layer (B_IPL) can be etched to expose at least a portion of the buffer layer (BFL). The opening (H) can expose at least a portion of the buffer layer (BFL).

[0134] According to an embodiment, the base insulating layer (B_IPL) can be etched to form a fine pattern having a plurality of openings (H) of micro-scale and / or nano-scale. According to an embodiment, the openings (H) can be 1 μm or less (for example, 1 μm or less in a horizontal direction perpendicular to the third direction (DR3)). However, the present disclosure is not limited thereto, and the size of the openings (H) can be changed depending on the wavelength of light emitted by the light-emitting element (LD). For example, a light-emitting element (LD) that emits green light can be manufactured to have an opening (H) that is wider than a light-emitting element (LD) that emits red light.

[0135] Referring to Fig. 13, in the step of forming a first semiconductor layer (S100), a first semiconductor layer (SCL1) may be formed on a buffer layer (BFL). The first semiconductor layer (SCL1) may be formed in an opening (H).

[0136] The step of forming a first semiconductor layer (S100) may include a step of growing a first semiconductor layer (SCL1) on a buffer layer (BFL). The first semiconductor layer (SCL1) may be formed by growing a seed crystal by an epitaxial method.

[0137] According to an embodiment, the first semiconductor layer (SCL1) may be formed by electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, and / or metal-organic chemical vapor deposition (MOCVD). According to an embodiment, the first semiconductor layer (SCL1) may be formed by metal-organic chemical vapor deposition (MOCVD), but the present disclosure is not necessarily limited thereto.

[0138] Referring to Fig. 14, in the step (S100) of forming the first semiconductor layer, a seed crystal for forming the first semiconductor layer (SCL1) can grow in a direction perpendicular to a plane on which the base substrate (SUB) is provided. The first semiconductor layer (SCL1) can be formed by a selective growth technique (Selective Area Growth). For example, a seed crystal overlapping the opening (H) can grow in a direction perpendicular to a plane on which the base substrate (SUB) is provided, but a seed crystal overlapping the insulating layer (IPL) may not be able to grow in a direction perpendicular to a plane on which the base substrate (SUB) is provided. Accordingly, stress can be relieved during growth of the first semiconductor layer (SCL1).

[0139] The step of forming a first semiconductor layer (S100) may include a step of forming a first semiconductor layer (SCL1) having a first surface (S1) and a second surface (S2). The first semiconductor layer (SCL1) may be grown to form the first surface (S1).

[0140] The first surface (S1) may be a generally flat surface. The first surface (S1) may be generally parallel to the base substrate (SUB).

[0141] The first surface (S1) is a polar surface and may be a c-plane. In some embodiments, the first surface (S1) may be a {0001} crystal plane.

[0142] The first semiconductor layer (SCL1) can be grown to form a second surface (S2) that is inclined with respect to the first surface (S1). The second surface (S2) can be a surface inclined with respect to the base substrate (SUB) (for example, can be inclined with respect to the base substrate (SUB)). For example, the second surface (S2) can be an inclined side wall of the first semiconductor layer (SCL1). The second surface (S2) can be inclined with respect to the first surface (S1), and the width of the first semiconductor layer (SCL1) can decrease as it moves away from the base substrate (SUB) (or in the third direction (DR3)).

[0143] Experimentally, when the first semiconductor layer (SCL1) is formed by a selective growth technique, the seed crystal growth direction can be bent to form a second surface (S2).

[0144] Accordingly, the second surface (S2) may be a semipolar surface having a different crystal growth direction from the first surface (S1). In some embodiments, the second surface (S2) may be a {n -n 0 k} crystal plane. Here, n and k are each integers greater than or equal to 1. For example, the second surface (S2) may be a {1 -1 0 1} crystal plane. However, the present disclosure is not limited thereto. In some embodiments, the second surface (S2) may be a {n 0 -nk} crystal plane or a {nn -2n k} crystal plane. Here, n and k are each integers greater than or equal to 1.

[0145] Referring to FIG. 15, in the step of forming an auxiliary layer (S200), the auxiliary layer (SL) may be formed on the first semiconductor layer (SCL1). The auxiliary layer (SL) may be disposed on the first surface (S1) and the second surface (S2). According to an embodiment, the auxiliary layer (SL) may be directly disposed on the first surface (S1) and the second surface (S2). According to an embodiment, the auxiliary layer (SL) may be in contact with (for example, physically in contact with) the first surface (S1) and the second surface (S2). According to an embodiment, the auxiliary layer (SL) may entirely cover the first surface (S1) and the second surface (S2).

[0146] The step of forming an auxiliary layer (S200) may include a step of forming an auxiliary layer (SL) having a first auxiliary layer surface (A1) and a second auxiliary layer surface (A2).

[0147] The first auxiliary layer surface (A1) may be substantially parallel to the first surface (S1), and may be a polar surface, i.e., a c-plane. The first auxiliary layer surface (A1) may be adjacent to the first surface (S1). The second auxiliary layer surface (A2) may be a surface inclined with respect to the first auxiliary layer surface (A1) (for example, inclined with respect to the first auxiliary layer surface (A1)). The second auxiliary layer surface (A2) may be adjacent to the first auxiliary layer surface (A1). The second auxiliary layer surface (A2) may be a semi-polar surface. The second auxiliary layer surface (A2) may be a side wall of the auxiliary layer (SL).

[0148] The auxiliary layer (SL) may include InGaN and GaN. In some embodiments, the auxiliary layer (SL) may be formed in a structure in which InGaN and GaN are alternately laminated. However, the present disclosure is not limited thereto.

[0149] The step of forming an active layer (S300) may include a step of forming a well layer (QW) and a step of forming a cap layer (CPL).

[0150] In the step of forming an active layer (S300), in order to form a well layer (QW), a base well layer (B_QW) may be formed on an auxiliary layer (SL), and a cap layer (CPL) may be formed on the base well layer (B_QW).

[0151] The base well layer (B_QW) may include a first portion (BQW_1) and a second portion (BQW_2). The first portion (BQW_1) and the second portion (BQW_2) may be deposited and formed in the same process and may include the same material. For example, the first portion (BQW_1) and the second portion (BQW_2) may include In. For example, the first portion (BQW_1) and the second portion (BQW_2) may include InGaN. However, the present disclosure is not limited thereto.

[0152] The first portion (BQW_1) is a portion formed on the first auxiliary layer surface (A1) (or the upper surface of the auxiliary layer (SL)) and may have a first thickness (T1). The second portion (BQW_2) is a portion formed on the second auxiliary layer surface (A2) (or the side surface of the auxiliary layer (SL)) and may have a second thickness (T2). The first thickness (T1) may be thicker than the second thickness (T2). For example, the first thickness (T1) and the second thickness (T2) may have a ratio of 3:1. However, the present disclosure is not limited thereto.

[0153] Experimentally, since In has a long surface diffusion distance, when the base well layer (B_QW) includes In, the base well layer (B_QW) can be deposited more on the c-plane than on the semi-polar plane. Accordingly, the first thickness (T1) can be thicker than the second thickness (T2), and light of different colors can be emitted from the first portion (BQW_1) and the second portion (BQW_2). For example, light with a longer wavelength can be emitted from the first portion (BQW_1) than from the second portion (BQW_2). For example, the first portion (BQW_1) can emit red light, and the second portion (BQW_2) can emit green or blue light. For example, the first portion (BQW_1) can emit green light, and the second portion (BQW_2) can emit blue light.

[0154] When light of different colors is emitted from the first part (BQW_1) and the second part (BQW_2), if the current density applied to the light emitting element (LD) increases when the light emitting element (LD) is driven, there may be a risk that two or more types of light are emitted, resulting in a decrease in the color purity of the light emitting element (LD).

[0155] In the light emitting element (LD) according to embodiments of the present disclosure, the second portion (BQW_2) may not be disposed on the side surface of the auxiliary layer (SL) (or the second auxiliary layer surface (A2)) (or the side surface of the first semiconductor layer (SCL1)) by removing the second portion (BQW_2), and the color purity of the light emitting element (LD) may be increased.

[0156] The cap layer (CPL) may be disposed on the first portion (BQW_1). The cap layer (CPL) may be disposed directly on the first portion (BQW_1). In an embodiment, the cap layer (CPL) may be in contact with (e.g., physically in contact with) the first portion (BQW_1). The cap layer (CPL) may cover one surface of the first portion (BQW_1). In an embodiment, the cap layer (CPL) may not be in contact with (e.g., physically in contact with) a side surface of the auxiliary layer (SL) (e.g., a second auxiliary layer surface (A2)) and may expose the side surface of the auxiliary layer (SL).

[0157] The cap layer (CPL) may include a group III nitride semiconductor. For example, the cap layer (CPL) may include one or more of GaN, AlN, and AlxGayNz (0≤x≤1, 0≤y≤1, 0≤z≤1, 0≤x+y+z≤1).

[0158] Referring to FIG. 16, the step of forming an active layer (S300) (or the step of forming a well layer (QW)) may include a step of removing a second portion (BQW_2). In some embodiments, the second portion (BQW_2) may be removed after forming a cap layer (CPL).

[0159] The second portion (BQW_2) can be etched by an etching process. The second portion (BQW_2) can be etched by dry etching, wet etching, laser etching, or the like.

[0160] The second portion (BQW_2) may have a thinner thickness than the first portion (BQW_1), and thus, even if the second portion (BQW_2) is completely etched, the first portion (BQW_1) may be disposed on at least a portion of the auxiliary layer (SL).

[0161] When the second portion (BQW_2) is removed by dry etching, the second portion (BQW_2) can be removed by an in-situ process. For example, the second portion (BQW_2) can be etched in the same chamber in which the second portion (BQW_2) is formed. When the second portion (BQW_2) is removed by an in-situ process, movement between chambers can be reduced, making the process convenient.

[0162] When the second portion ((BQW_2) is removed by dry etching, an etching gas may be provided within the chamber. When the second portion ((BQW_2) is removed by dry etching, the step of removing the second portion (BQW_2) may include a step of flowing an etching gas within the chamber.

[0163] The etching gas may include nitrogen (N2) gas and hydrogen (H2) gas. In the step of flowing the etching gas within the chamber, the hydrogen (H2) gas may flow at a flow rate of 5% or more and less than 25% of the total flow rate of the nitrogen (N2) gas and hydrogen (H2) gas. For example, when the nitrogen (N2) gas and hydrogen (H2) gas flow at a total of 100 L per hour, the hydrogen (H2) gas may flow at a flow rate of 5 L or more and less than 25 L per hour.

[0164] Hydrogen (H2) gas can remove indium (In). Because indium (In) has a relatively low binding energy, it can be removed by the etching gas before other materials.

[0165] When the hydrogen (H2) gas flows at a flow rate of less than 5% of the gas flow rates of nitrogen (N2) gas and hydrogen (H2) gas, the etching gas may not properly etch the second portion (BQW_2). For example, the etching gas may not completely etch the second portion (BQW_2), and thus the second portion (BQW_2) may remain on the side surface of the auxiliary layer (SL).

[0166] When the hydrogen (H2) gas flows at a gas flow rate of 25% or more compared to the gas flow rates of nitrogen (N2) gas and hydrogen (H2) gas, the etching gas can completely etch the first portion (BQW_1). When the etching gas completely etches the first portion (BQW_1), the well layer (QW) may not be formed, and thus the light emitting element (LD) may not be properly formed.

[0167] When the second portion (BQW_2) is removed by wet etching, the second portion (BQW_2) can be removed by an ex-situ process. For example, the second portion (BQW_2) can be immersed in an etchant and etched in a chamber different from the chamber in which the second portion (BQW_2) is formed.

[0168] When the second portion (BQW_2) is removed by laser etching, the second portion (BQW_2) can be removed by an ex-situ process. For example, a laser can be irradiated to the second portion (BQW_2) in a chamber different from the chamber in which the second portion (BQW_2) is formed, and the second portion (BQW_2) can be etched.

[0169] The light emitting element (LD) according to the present disclosure can emit light from the first portion (BQW_1) by removing the second portion (BQW_2), and the color purity of the light emitting element (LD) can be improved.

[0170] In the step of forming the active layer (S300), after the second portion (BQW_2) is removed, a recovery process may be performed. For example, a heat treatment process may be performed. For example, one side of the cap layer (CPL) (or one side of the first portion (BQW_1)) may be heat treated.

[0171] When the second portion (BQW_2) is etched, the surface of the cap layer (CPL) (or the first portion (BQW_1)) may become uneven. The method for manufacturing a light-emitting device (LD) according to an embodiment of the present disclosure can reduce the surface unevenness of the cap layer (CPL) (or the first portion (BQW_1)) through a heat treatment process, thereby appropriately securing the crystallinity of the first portion (BQW_1).

[0172] Referring to FIG. 17, the step of forming an active layer (S300) may include a step of forming a barrier layer (QB). In the step of forming an active layer (S300), the barrier layer (QB) may be formed on the auxiliary layer (SL). At least a portion of the barrier layer (QB) may cover the cap layer (CPL), and the remaining portion of the barrier layer (QB) may cover a side surface of the auxiliary layer (SL) (e.g., the second auxiliary layer surface (A2)).

[0173] The barrier layer (QB) may include GaN. However, the present disclosure is not limited thereto, and the barrier layer (QB) may include any suitable barrier layer material used in the art.

[0174] Referring to FIG. 7, when the active layer (AL) has a multi-well structure (e.g., the multi-quantum well layer (MQ)), the step of forming the well layer (QW') and the step of forming the barrier layer (QB') may be performed at least twice. For example, the above-described processes may be performed so that the well layer (QW') and the barrier layer (QB') are alternately provided.

[0175] Referring to FIG. 16, in the step of forming a second semiconductor layer (S400), a second semiconductor layer (SCL2) may be formed on the active layer (AL). According to an embodiment, the second semiconductor layer (SCL2) may be directly disposed on the active layer (AL). However, the present disclosure is not limited thereto, and according to an embodiment, an electron blocking layer (EBL) may be further formed between the active layer (AL) and the second semiconductor layer (SCL2).

[0176] According to an embodiment, at least a portion of the second semiconductor layer (SCL2) may be disposed on the cap layer (CPL). According to an embodiment, the second semiconductor layer (SCL2) may be disposed on the barrier layer (QB).

[0177] The second semiconductor layer (SCL2) is disposed on the other surface of the active layer (AL) and may include a p-type semiconductor, depending on the embodiment. For example, the second semiconductor layer (SCL2) may include one or more of p-doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer (SCL2) may be doped with a p-type dopant, and for example, the second semiconductor layer (SCL2) may be p-GaN doped with a p-type dopant. However, the present disclosure is not limited thereto, and the second semiconductor layer (SCL2) may include various appropriate p-type semiconductor materials used in the art.

[0178] After the second semiconductor layer (SCL2) is formed, the light emitting element (LD) can be transferred onto the pixel circuit layer (PCL). The method by which the light emitting element (LD) is transferred onto the pixel circuit layer (PCL) is not particularly limited. For example, the light emitting element (LD) can be picked up by a separate carrier substrate and transferred onto the pixel circuit layer (PCL). In embodiments, for example, the light emitting element (LD) can be separated from the base substrate (SUB) by a mechanical lift-off process.

[0179] According to an embodiment, when separated from the base substrate (SUB) and transferred onto the pixel circuit layer (PCL), the insulating layer (IPL) may remain intact and may be transferred onto the pixel circuit layer (PCL) together with the light emitting element (LD).

[0180] As described above, although the present disclosure has been described with reference to embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes to the present disclosure can be made without departing from the spirit and technical scope of the present disclosure as set forth in the claims to be described below.

[0181] Accordingly, the technical scope of the present disclosure should not be limited to the contents described in the detailed description of the specification, but should be defined by the patent claims.

Claims

1. First semiconductor layer; An auxiliary layer on the first semiconductor layer; an active layer on the auxiliary layer; and A second semiconductor layer is included on the active layer, The auxiliary layer includes a first auxiliary layer surface adjacent to the first semiconductor layer and a second auxiliary layer surface that is a side surface adjacent to the first auxiliary layer surface, The above active layer includes a well layer and a barrier layer, The above auxiliary layer has a superlattice structure, A light emitting element in which the well layer is disposed on the first auxiliary layer surface without being disposed on the second auxiliary layer surface of the auxiliary layer.

2. In paragraph 1, A light emitting element in which the second auxiliary layer surface is an inclined surface.

3. In paragraph 1, The above first auxiliary layer surface and the above well layer are in contact with each other, A light emitting element in which the second auxiliary layer surface and the well layer do not contact each other.

4. In paragraph 1, The above auxiliary layer is a light-emitting device having a structure in which InGaN and GaN are alternately laminated.

5. In paragraph 1, The first semiconductor layer includes a first surface and a second surface adjacent to the first surface, The above first surface is a c-plane, A light emitting element wherein the second surface is a semipolar surface.

6. In paragraph 5, The above auxiliary layer is a light emitting element that entirely covers the first side and the second side.

7. In paragraph 1, The above active layer further includes a cap layer on the well layer, A light emitting device in which the cap layer includes at least one of AlN and AlxGayNz (0≤x≤1, 0≤y≤1, 0≤z≤1, 0≤x+y+z≤1).

8. In paragraph 7, A light emitting element having a composition of 25 mol% or more and less than 100 mol% of Al with respect to Ga in the above AlxGayNz(0≤x≤1,0≤y≤1,0≤z≤1,0≤x+y+z≤1).

9. In paragraph 7, A light emitting element wherein the cap layer has a thickness of 0.5 nm to 2.5 nm.

10. In paragraph 7, A light emitting element in which the cap layer has the same diameter as the well layer.

11. In paragraph 1, The above light-emitting element is a light-emitting element having a truncated pyramid shape.

12. Step of forming an insulating layer on the base substrate; A step of forming a first semiconductor layer on the base substrate; A step of forming an auxiliary layer on the first semiconductor layer; A step of forming an active layer on the auxiliary layer; and comprising a step of forming a second semiconductor layer on the active layer; The step of forming the auxiliary layer on the first semiconductor layer includes the step of forming the auxiliary layer having a first auxiliary layer surface adjacent to the first semiconductor layer and a second auxiliary layer surface that is a side surface adjacent to the first auxiliary layer surface, The step of forming the active layer on the auxiliary layer includes the step of forming the active layer including a well layer and a barrier layer, The above auxiliary layer has a superlattice structure, A method for manufacturing a light emitting element in which the well layer is disposed on the first auxiliary layer surface without being disposed on the second auxiliary layer surface of the auxiliary layer.

13. In paragraph 12, The step of forming the first semiconductor layer on the base substrate includes the step of forming the first semiconductor layer having a first surface and a second surface adjacent to the first surface, The above first surface is a c-plane, The above second side is a semipolar side, A method for manufacturing a light-emitting element in which the second auxiliary layer surface is an inclined surface with respect to the first auxiliary layer surface.

14. In paragraph 12, The step of forming the above well layer is: A step of forming a base well layer including a first portion and a second portion on the auxiliary layer; and Including a step of etching the second part, The above first part is in contact with the first auxiliary layer surface, The above second portion is in contact with the second auxiliary layer surface, The second auxiliary layer surface is an inclined surface with respect to the first auxiliary layer surface, A method for manufacturing a light emitting element in which the second portion is etched so that the well layer does not come into contact with the second auxiliary layer surface.

15. In paragraph 14, The second portion is etched by an etching gas containing nitrogen (N2) gas and hydrogen (H2) gas, Regarding the flow rates of the above nitrogen gas and the above hydrogen gas, the hydrogen gas flows at a flow rate of 5% or more and less than 25%, A method for manufacturing a light-emitting element in which the second part is removed by an in-situ process.

16. Base layer; and A light emitting element is included on the base layer, The above light emitting element, First semiconductor layer; An auxiliary layer on the first semiconductor layer; an active layer on the auxiliary layer; and A second semiconductor layer is included on the active layer, The auxiliary layer includes a first auxiliary layer surface adjacent to the first semiconductor layer and a second auxiliary layer surface that is a side surface adjacent to the first auxiliary layer surface, The above active layer includes a well layer and a barrier layer, The above auxiliary layer has a superlattice structure, A display device in which the well layer is disposed on the first auxiliary layer surface without being disposed on the second auxiliary layer surface of the auxiliary layer.

17. In paragraph 16, The first semiconductor layer includes a first surface and a second surface adjacent to the first surface, The above first surface is a c-plane, The above second side is a semipolar side and a non-etching side, The above second auxiliary layer surface is an inclined surface, A display device in which the auxiliary layer entirely covers the first side and the second side.

18. In paragraph 16, The active layer of the light emitting element further includes a cap layer disposed on the well layer, A display device in which the cap layer includes at least one of AlN and AlxGayNz (0≤x≤1, 0≤y≤1, 0≤z≤1, 0≤x+y+z≤1).

19. In paragraph 16, The display device includes pixels, The above pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, A display device wherein each of the first sub-pixel, the second sub-pixel, and the third sub-pixel has a different diameter.

20. In paragraph 19, The above well layer includes well layers, The above barrier layer includes barrier layers, A display device in which the above well layers and the above barrier layers are provided alternately.

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