Display device

Abstract

This display device comprises: a pixel circuit layer; anodes disposed on the pixel circuit layer so as to be spaced apart from one other in a first diagonal direction and a second diagonal direction intersecting the first diagonal direction; and a cathode and light-emitting diodes disposed on the pixel circuit layer so as to be spaced apart from the anodes. The light-emitting diodes are electrically connected to the respective anodes and the cathode.

Description

display device

[0001] The present invention relates to a display device.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting display devices (OLEDs) is increasing.

[0003] One object of the present invention is to provide a display device capable of improving voltage drop (IR drop) and power consumption.

[0004] However, the purpose of the present invention is not limited to the above purposes, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0005] A display device according to one embodiment of the present invention includes a pixel circuit layer, anodes arranged to be spaced apart from each other in a first diagonal direction and a second diagonal direction intersecting the first diagonal direction on the pixel circuit layer, a cathode arranged to be spaced apart from the anodes on the pixel circuit layer, and light-emitting elements, wherein each of the light-emitting elements can be electrically connected to each of the anodes and the cathode.

[0006] The pixel circuit layer may include transistors, a first passivation layer including first contact holes, conductive patterns extending in a second direction on the first passivation layer and arranged in a first direction intersecting the second direction, and a second passivation layer including second contact holes.

[0007] In each pixel, the first contact holes may have the same position in the second direction and the second contact holes may have different positions in the second direction.

[0008] The above anodes and the above cathode can be arranged in the same plane.

[0009] The above anodes may be arranged in a zigzag shape along the first diagonal direction and the second diagonal direction.

[0010] The above cathode may have a diagonal mesh structure.

[0011] The cathode may include a first wiring portion extending in the first diagonal direction and arranged in the second diagonal direction, and a second wiring portion extending in the second diagonal direction and arranged in a zigzag shape along the first diagonal direction and the second diagonal direction.

[0012] The above cathodes can surround the above anodes in each sub-pixel.

[0013] The above light emitting elements may be of the flip chip type.

[0014] The light emitting elements may be arranged along the first diagonal direction so as to have a constant spacing between the light emitting elements.

[0015] The above light emitting elements can be arranged in a zigzag shape along the first diagonal direction and the second diagonal direction.

[0016] The cathode may surround the anodes in each pixel.

[0017] The light emitting elements included in each pixel may be arranged so as to have a first gap between the light emitting elements included in each pixel along the first diagonal direction, and the light emitting elements included in each of the adjacent pixels may be arranged so as to have a second gap different from the first gap between the light emitting elements included in each of the adjacent pixels along the first diagonal direction.

[0018] The light emitting elements may be arranged so as to have a constant spacing between the light emitting elements along a first direction and a second direction intersecting the first direction.

[0019] It may further include color filters respectively arranged on the above light emitting elements.

[0020] The center of each of the above color filters and the center of each of the above light-emitting elements may coincide.

[0021] The light-emitting elements may include first light-emitting elements that emit light of a first color, second light-emitting elements that emit light of a second color, and third light-emitting elements that emit light of a third color, and the color filters may include first color filters respectively disposed on the first light-emitting elements, second color filters respectively disposed on the second light-emitting elements, and third color filters respectively disposed on the third light-emitting elements.

[0022] The size of the second color filters may be larger than the size of the first color filters, and the size of the first color filters may be larger than the size of the third color filters.

[0023] The above color filters may have a polygonal shape.

[0024] The above light emitting elements may be of the lateral chip type.

[0025] It may further include a reflective electrode arranged in a diagonal mesh structure on the cathode and a transparent electrode arranged in a diagonal mesh structure on the reflective electrode and electrically connected to the light-emitting elements.

[0026] According to embodiments of the present invention, a display device with improved voltage drop (IR drop) and power consumption can be provided.

[0027] However, the effects of the present invention are not limited to the above-described effects, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0028] Figure 1 is a block diagram showing an embodiment of a display device.

[0029] FIG. 2 is a block diagram showing an embodiment of one of the sub-pixels of FIG. 1.

[0030] Fig. 3 is a circuit diagram showing an example of a sub-pixel of Fig. 2.

[0031] FIG. 4 is a plan view showing an embodiment of the display panel of FIG. 1.

[0032] Fig. 5 is a cross-sectional view showing an embodiment of the display panel of Fig. 4.

[0033] Fig. 6 is a plan view showing an embodiment of the display panel of Fig. 4.

[0034] Fig. 7 is a cross-sectional view taken along line II' of Fig. 6.

[0035] Fig. 8 is a cross-sectional view taken along line II-II' of Fig. 6.

[0036] Fig. 9 is a plan view showing an embodiment of a pixel circuit layer.

[0037] Fig. 10 is a cross-sectional view taken along line III-III' of Fig. 9.

[0038] Fig. 11 is a cross-sectional view taken along line IV-IV' of Fig. 9.

[0039] Fig. 12 is a cross-sectional view taken along line VV' of Fig. 9.

[0040] FIG. 13 is a plan view showing another embodiment of the display panel of FIG. 4.

[0041] FIG. 14 is a plan view showing another embodiment of the display panel of FIG. 1.

[0042] Fig. 15 is a plan view showing an embodiment of the display panel of Fig. 14.

[0043] Fig. 16 is a plan view showing an embodiment of a color filter layer.

[0044] Fig. 17 is a plan view showing another embodiment of a color filter layer.

[0045] Fig. 18 is a plan view showing another embodiment of a color filter layer.

[0046] FIG. 19 is a plan view showing another embodiment of the display panel of FIG. 4.

[0047] Figure 20 is a plan view showing the anodes and cathodes illustrated in Figure 19.

[0048] Fig. 21 is a plan view showing the first reflective electrodes and the second reflective electrode illustrated in Fig. 19.

[0049] FIG. 22 is a plan view showing the light-emitting elements, first transparent electrodes, and second transparent electrodes illustrated in FIG. 19.

[0050] Fig. 23 is a cross-sectional view taken along line VI-VI' of Fig. 19.

[0051] Fig. 24 is a block diagram showing an embodiment of a display system.

[0052] Figures 25 to 28 are perspective views showing application examples of the display system of Figure 24.

[0053] Numerous specific details are set forth herein to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, the terms "embodiment" and "implementation" are interchangeable and refer to non-limiting examples of the devices or methods disclosed herein. However, it should be understood that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. It should be understood that the various embodiments are not necessarily exclusive or limiting of the present disclosure. For example, specific features, configurations, and characteristics of an embodiment may be utilized or implemented in other embodiments.

[0054] Unless otherwise specified, the described embodiments are understood to provide features of the invention. Accordingly, unless otherwise specified, features, components, modules, layers, films, panels, regions, and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be otherwise combined, separated, interchanged, and / or rearranged without departing from the scope of the invention.

[0055] The use of crosshatching and / or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. Therefore, the presence or absence of crosshatching or shading does not convey or indicate any preference or requirement for any particular material, material property, dimension, proportion, commonality between the depicted elements, and / or any other characteristic, property, or property of the elements. Furthermore, the dimensions and relative sizes of elements in the accompanying drawings may be exaggerated for clarity and / or illustrative purposes. Where the embodiments can be implemented differently, certain process sequences may be performed differently from the illustrated sequence. For example, two processes depicted in succession may be performed substantially simultaneously or in the reverse order of the illustrated sequence. Furthermore, like reference numerals indicate like elements.

[0056] When an element or layer is referred to as being "over," "connected to," or "coupled to" another element or layer, it may be directly over, connected to, or coupled to the other element or layer, or there may be intervening elements or layers present. However, when an element or layer is referred to as being "directly over," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. For this purpose, the term "connected" may refer to a physical, electrical, and / or fluid connection, with or without intervening elements. Furthermore, the axis in the first direction (DR1), the axis in the second direction (DR2), and the axis in the third direction (DR3) are not limited to the three axes of a Cartesian coordinate system, such as the X, Y, and Z axes, and may be interpreted in a broader sense. For example, the axis in the first direction (DR1), the axis in the second direction (DR2), and the axis in the third direction (DR3) may be perpendicular to one another, or may represent directions other than perpendicular to one another. For the purposes of this disclosure, “at least one of A and B” shall be understood to mean A alone, B alone, or any combination of A and B. Additionally, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” shall be interpreted to mean X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0057] While the terms "first," "second," and the like may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below may be referred to as a second element without departing from the scope of this disclosure.

[0058] Spatially relative terms such as "below," "above," "higher," "side" (as in "side wall"), etc., may be used herein for descriptive purposes to describe one element's relationship to another as depicted in the drawings. Spatially relative terms are intended to encompass various orientations of the device during use, operation, and / or manufacture, in addition to the orientation depicted in the drawings. For example, if the device is turned over in the drawings, an element described as being "below" another element or feature is oriented "above" the other element or feature. Thus, the term "below" can encompass both the above and below orientations. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or placed in other orientations), and spatially relative descriptors used herein should be interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. Furthermore, the terms "comprises," "comprising," and "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, the terms "substantially," "about," and other similar terms as used herein are used as terms of approximation rather than terms of degree, and are therefore used to account for inherent variations in measurements, calculations, and / or values ​​provided that would be recognizable to one of ordinary skill in the art.

[0060] Various embodiments are described with reference to cross-sectional and / or exploded drawings, which are schematic drawings of embodiments and / or intermediate structures. Accordingly, the shapes of the drawings may vary due to manufacturing techniques and / or tolerances, etc. Therefore, the embodiments disclosed herein should not be construed as necessarily limited to the specific depicted shapes of the regions, but rather to include, for example, shape variations that occur during manufacturing. In this way, the regions depicted in the drawings may be schematic in nature, and the shapes of such regions may not reflect the actual shapes of the device regions and are therefore not necessarily intended to be limiting.

[0061] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0062] Figure 1 is a block diagram showing an embodiment of a display device.

[0063] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0064] The display panel (DP) includes sub-pixels (SP). The sub-pixels (SP) can be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) can be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0065] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0066] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. In this way, the pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included therein.

[0067] The gate driver (120) is connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0068] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and the other side of the display panel (DP) opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0069] The data driver (130) is connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, etc.

[0070] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the first to n-th data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0071] In embodiments, the gate driver (120) and data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0072] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) is configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from the outside of the display device (DD) and regulating the received voltage.

[0073] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In other embodiments, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0074] In addition, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). Although FIG. 1 illustrates that the pixel control lines (PXCL) are connected between the voltage generator (140) and the display panel (DP), embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0075] The controller (150) controls all operations of the display device (DD). The controller (150) receives input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0076] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by aligning the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0077] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0078] Fig. 2 is a block diagram showing an embodiment of one of the sub-pixels of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is exemplarily illustrated.

[0079] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0080] A light emitting element (LD) is connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) is connected to one of the power supply lines (PL) of FIG. 1 and receives a first power supply voltage. The second power supply voltage node (VSSN) is connected to another of the power supply lines (PL) of FIG. 1 and receives a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0081] A light emitting element (LD) is connected between an anode (AE) and a cathode (CE). The anode (AE) may be connected to a first power supply voltage node (VDDN) via a sub-pixel circuit (SPC). For example, the anode (AE) may be connected to the first power supply voltage node (VDDN) via one or more transistors included in the sub-pixel circuit (SPC). The cathode (CE) may be connected to a second power supply voltage node (VSSN). The light emitting element (LD) is configured to emit light according to a current flowing from the anode (AE) to the cathode (CE).

[0082] The sub-pixel circuit (SPC) may be connected to the i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and to the j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0083] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0084] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, and the like.

[0085] Fig. 3 is a circuit diagram showing an example of a sub-pixel of Fig. 2.

[0086] Referring to FIG. 3, the sub-pixel (SPij) may include a light-emitting element (LD), a first sub-pixel circuit (SPC1) that controls the light-emitting time of the light-emitting element (LD), and a second sub-pixel circuit (SPC2) that provides a driving current to the light-emitting element (LD).

[0087] For example, the first sub-pixel circuit (SPC1) includes a first transistor (T1) including a control electrode connected to a first node (N1), a first electrode connected to a second node (N2), and a second electrode connected to a third node (N3), a first capacitor (C1) including a first electrode receiving a sweep voltage (SV) and a second electrode connected to the first node (N1), a second transistor (T2) including a control electrode receiving a first write gate signal (GWC1), a first electrode receiving a data voltage (VDATA), and a second electrode connected to a second node (N2), a third transistor (T3) including a control electrode receiving the first write gate signal (GWC1), a first electrode connected to a third node (N3), and a second electrode connected to the first node (N1), a control electrode receiving an emission signal (EM), a first electrode receiving a first-first power voltage (VDD1), and a second capacitor (C1) including a first electrode receiving a first-first power voltage (VDD1), and a second capacitor (C1) connected to the second node (N2). It may include a fourth transistor (T4) including a second electrode to be connected, a fifth transistor (T5) including a control electrode receiving an emission signal (EM), a first electrode connected to a third node (N3), and a second electrode connected to a second sub-pixel circuit (SPC2) (e.g., the fourth node (N4)), and a sixth transistor (T6) including a control electrode receiving a first initialization gate signal (GI1), a first electrode receiving a first initialization voltage (VINT1), and a second electrode connected to the first node (N1).

[0088] For example, the second sub-pixel circuit (SPC2) includes a seventh transistor (T7) including a control electrode connected to the fourth node (N4), a first electrode connected to the fifth node (N5), and a second electrode connected to the sixth node (N6), a second capacitor (C2) including a first electrode receiving a first-second power voltage (VDD2) and a second electrode connected to the fourth node (N4), an eighth transistor (T8) including a control electrode receiving a second write gate signal (GWC2), a first electrode receiving a data voltage (VDATA), and a second electrode connected to the fifth node (N5), a ninth transistor (T9) including a control electrode receiving a second write gate signal (GWC2), a first electrode connected to the sixth node (N6), and a second electrode connected to the fourth node (N4), a control electrode receiving an emission signal (EM), a first electrode receiving a first-second power voltage (VDD2), and a second capacitor (C2) including a second capacitor (C2) receiving a first-second power voltage (VDD2) and a second electrode connected to the fifth node (N5). It may include a tenth transistor (T10) including a second electrode to be connected, an eleventh transistor (T11) including a control electrode receiving an emission signal (EM), a first electrode connected to a sixth node (N6), and a second electrode connected to a seventh node (N7), a twelfth transistor (T12) including a control electrode receiving a second initialization gate signal (GI2), a first electrode receiving a first initialization voltage (VINT1), and a second electrode connected to a fourth node (N4), and a thirteenth transistor (T13) including a control electrode receiving a bias gate signal (BCB), a first electrode receiving a second initialization voltage (VINT2), and a second electrode connected to the seventh node (N7).

[0089] For example, the light emitting element (LD) may include a first electrode (i.e., an anode (AE, see FIG. 2)) connected to a seventh node (N7) and a second electrode (i.e., a cathode (CE, see FIG. 2)) receiving a second power supply voltage (VSS).

[0090] The first, fourth, fifth, seventh, tenth, eleventh, and thirteenth transistors (T1, T4, T5, T7, T10, T11, T13) may be P-type transistors, and the second, third, sixth, eighth, ninth, and twelfth transistors (T2, T3, T6, T8, T9, T12) may be N-type transistors. However, the present invention is not limited thereto, and the P-type transistors may be replaced with N-type transistors, and the N-type transistors may be replaced with P-type transistors.

[0091] In one embodiment, the first transistor (T1) may include a back gate electrode receiving a first-first power supply voltage (VDD1), the second transistor (T2) may include a back gate electrode connected to a control electrode of the second transistor (T2), the third transistor (T3) may include a back gate electrode connected to a control electrode of the third transistor (T3), and the sixth transistor (T6) may include a back gate electrode receiving a first initialization gate signal (GI1).

[0092] In one embodiment, the seventh transistor (T7) may include a back gate electrode receiving the first-second power supply voltage (VDD2), the eighth transistor (T8) may include a back gate electrode connected to the control electrode of the eighth transistor (T8), the ninth transistor (T9) may include a back gate electrode connected to the control electrode of the ninth transistor (T9), and the twelfth transistor (T12) may include a back gate electrode receiving the second initialization gate signal (GI2).

[0093] The sixth transistor (T6) can provide a first initialization voltage (VINT1) to the first node (N1) in response to the first initialization gate signal (GI1). Accordingly, the voltage of the first node (N1) can be initialized to the first initialization voltage (VINT1).

[0094] The second transistor (T2) can provide a data voltage (VDATA) to the second node (N2) in response to the first write gate signal (GWC1). The third transistor (T3) can diode-connect the first transistor (T1) in response to the first write gate signal (GWC1). Accordingly, a voltage compensated for by the threshold voltage of the first transistor (T1) can be provided to the first node (N1).

[0095] The fourth transistor (T4) can provide the first power voltage (VDD1) to the first transistor (T1) in response to the emission signal (EM). The fifth transistor (T5) can provide the current generated by the first transistor (T1) to the fourth node (N4) in response to the emission signal (EM). At this time, the sweep voltage (SV) is reduced, and the point in time at which the first transistor (T1) is turned on may vary depending on the magnitude of the data voltage (VDATA). Accordingly, the point in time at which the voltage of the fourth node (N4) increases may vary, and the point in time at which the seventh transistor (T7) is turned off may vary. That is, the first sub-pixel circuit (SPC1) can control the light-emitting time of the light-emitting element (LD) by adjusting the turn-off point of the seventh transistor (T7) that provides the driving current to the light-emitting element (LD). In addition, the luminance of the light-emitting element (LD) may vary depending on the light-emitting time (i.e., grayscale expression).

[0096] In one embodiment, the sweep voltage (SV), the second write gate signal (GWC2), the emission signal (EM), the bias gate signal (BCB), the first initialization gate signal (GI1), and the second initialization gate signal (GI2) may be pixel control signals. For example, the pixel control signals may be provided equally to the sub-pixels (SP, see FIG. 1).

[0097] In one embodiment, the first write gate signal (GWC1) may be provided to the sub-pixels (SP) through the first to m-th gate lines (GL1 to GLm, see FIG. 1). For example, the first write gate signal (GWC1) may be sequentially provided to each of the gate lines (GL1 to GLm, see FIG. 1).

[0098] FIG. 4 is a plan view showing an embodiment of the display panel of FIG. 1.

[0099] Referring to FIG. 4, the display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) displays an image through the display area (DA). The non-display area (NDA) is arranged around the display area (DA). For example, the display area (DA) (or the non-display area (NDA)) may include a first side (or short side) extending in a first direction (DR1) and a second side (or long side) extending in a second direction (DR2).

[0100] A display panel (DP) includes first to third sub-pixels (SP1 to SP3) in a display area (DA). The first to third sub-pixels (SP1 to SP3) may be arranged along a first diagonal direction (DR4) and a second diagonal direction (DR5) intersecting the first diagonal direction (DR4). For example, the first diagonal direction (DR4) may extend between the first direction (DR1) and the second direction (DR2), and the second diagonal direction (DR5) may extend between the second direction (DR2) and a direction opposite to the first direction (DR1). For example, the first to third sub-pixels (SP1 to SP3) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). That is, the first to third sub-pixels (SP1 to SP3) may be arranged in a diagonal shape. The arrangement of the first to third sub-pixels (SP1 to SP3) may vary depending on the embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0101] The first to third sub-pixels (SP1 to SP3) can constitute one pixel (PXL). In FIG. 4, the pixel (PXL) is illustrated as including three sub-pixels (SP1 to SP3), but embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes the first to third sub-pixels (SP1 to SP3).

[0102] Each of the first to third sub-pixels (SP1 to SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for the sake of clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) generates blue color light.

[0103] Each of the first to third sub-pixels (SP1 to SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate red light, green light, and blue light, respectively.

[0104] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0105] Components for controlling sub-pixels (SP) may be placed in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be placed in the non-display area (NDA).

[0106] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0107] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have the shape of a closed loop including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, circle, semicircle, or ellipse.

[0108] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0109] Fig. 5 is a cross-sectional view showing an embodiment of the display panel of Fig. 4.

[0110] Referring to FIG. 5, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0111] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As yet another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0112] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0113] A pixel circuit layer (PCL) is arranged on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns arranged between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0114] The circuit elements of the pixel circuit layer (PCL) may include a sub-pixel circuit (SPC, see FIG. 2) for each of the sub-pixels (SP, see FIG. 1). In other words, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0115] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0116] A display element layer (DPL) is arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0117] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0118] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or color). In embodiments, the color filter layer may be omitted.

[0119] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0120] Fig. 6 is a plan view showing an embodiment of the display panel of Fig. 4.

[0121] Referring to FIG. 6, anodes (AE) are provided on a pixel circuit layer (PCL, see FIG. 7), and each of the anodes (AE) may be electrically connected to each of the light-emitting elements (LD). The anodes (AE) may include first anodes (AE1), second anodes (AE2), and third anodes (AE3). Each of the first anodes (AE1) may be electrically connected to each of the first light-emitting elements (LD1). In addition, each of the second anodes (AE2) may be electrically connected to each of the second light-emitting elements (LD2). In addition, each of the third anodes (AE3) may be electrically connected to each of the third light-emitting elements (LD3).

[0122] The anodes (AE) may be arranged spaced apart from each other in a first diagonal direction (DR4) and a second diagonal direction (DR5) intersecting the first diagonal direction (DR4). For example, the anodes (AE) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). By arranging the anodes (AE) in the first and second diagonal directions (DR4, DR5), the gap between the anodes (AE) may be widened. For example, the gap between the anodes (AE) may be wider when the anodes (AE) are arranged in the first diagonal direction (DR4) and the second diagonal direction (DR5) (i.e., a diagonal arrangement) than when the anodes (AE) are arranged in the first direction (DR1) and the second direction (DR2) intersecting the first direction (DR1) (i.e., a stripe arrangement). As the spacing between the anodes (AE) increases, a predetermined space can be secured between the anodes (AE) in which the cathodes (CE) can be arranged. In embodiments, the angle (θ) of the first diagonal direction (DR4) may be the angle between the first direction (DR1) and the first diagonal direction (DR4). However, the angle (θ) of the first diagonal direction (DR4) in which the anodes (AE) are arranged is not particularly limited. Hereinafter, for the convenience of explanation, it is assumed that the angle (θ) of the first diagonal direction (DR4) is 45°.

[0123] Each of the anodes (AE) may be electrically connected to the pixel circuit layer (PCL) through each of the second contact holes (CNT2). For example, each of the first anodes (AE1) may be electrically connected to a first conductive pattern (CP1, see FIG. 10) through each of the second contact holes (CNT2). In addition, each of the second anodes (AE2) may be electrically connected to a second conductive pattern (CP2, see FIG. 11) through each of the second contact holes (CNT2). In addition, each of the third anodes (AE3) may be electrically connected to a third conductive pattern (CP3, see FIG. 12) through each of the second contact holes (CNT2).

[0124] The second contact holes (CNT2) may be arranged at regular intervals along the first diagonal direction (DR4). For example, the interval between the second contact holes (CNT2) in the first direction (DR1) may be the same as the interval between the second contact holes (CNT2) in the second direction (DR2). However, the embodiments are not limited thereto.

[0125] A cathode (CE) is provided on a pixel circuit layer (PCL), and the cathode (CE) can be electrically connected to light-emitting elements (LD). For example, the first light-emitting elements (LD1) can be electrically connected to the cathode (CE). In addition, the second light-emitting elements (LD2) can be electrically connected to the cathode (CE). In addition, the third light-emitting elements (LD3) can be electrically connected to the cathode (CE). In one embodiment, the cathode (CE) can be provided on the same plane as the anodes (AE). The cathode (CE) can be spaced apart from the anodes (AE).

[0126] The cathode (CE) may have a diagonal mesh structure. For example, the cathode (CE) may include a first wiring portion (CE1) extending in a first diagonal direction (DR4) and arranged in a second diagonal direction (DR5), and a second wiring portion (CE2) extending in the second diagonal direction (DR5) and arranged in the first diagonal direction (DR4) and the second diagonal direction (DR5). The second wiring portion (CE2) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). The first wiring portion (CE1) may be spaced apart from the light emitting elements (LD) in the second diagonal direction (DR5). The second wiring portion (CE2) may be spaced apart from the light emitting elements (LD) in the first diagonal direction (DR4).

[0127] As a predetermined space is secured between the anodes (AE), a cathode (CE) (or a second wiring portion (CE2)) can be additionally placed between the anodes (AE). In this case, the resistance of the cathode (CE) is reduced, so that the voltage drop (IR drop) can be improved (or reduced) and the power consumption can be reduced. In particular, when applying a PWM (Pulse Width Modulation) pixel circuit (see Fig. 3) that uses a high current, the power consumption can be significantly reduced. In addition, since the voltage drop (IR drop) can be improved (or reduced) by reducing the resistance of the cathode (CE) without adding a wiring layer, the process cost, process efficiency, and integration level can be improved.

[0128] In one embodiment, the cathode (CE) may surround each of the anodes (AE). For example, the cathode (CE) may surround each of the first anodes (AE1). Additionally, the cathode (CE) may surround each of the second anodes (AE2). Additionally, the cathode (CE) may surround each of the third anodes (AE3). The cathode (CE) having a diagonal mesh structure may include openings, and the first to third anodes (AE1 to AE3) may be arranged in each of the openings. The openings may refer to a space formed by the intersection of the first wiring portion (CE1) and the second wiring portion (CE2). That is, the cathode (CE) may surround the anodes (AE) in one sub-pixel (or a single sub-pixel). In this case, each of the first to third sub-pixels (SP1 to SP3, see FIG. 4) may include one second wiring portion (CE2). Accordingly, each of the pixels (PXL, see FIG. 4) may include three second wiring portions (CE2).

[0129] Each of the light-emitting elements (LD) may be provided on each of the anodes (AE) and the cathode (CE). For example, each of the first light-emitting elements (LD1) may be disposed on each of the first anodes (AE1) and the cathode (CE). In addition, each of the second light-emitting elements (LD2) may be disposed on each of the second anodes (AE2) and the cathode (CE). In addition, each of the third light-emitting elements (LD3) may be disposed on each of the third anodes (AE3) and the cathode (CE). The first to third light-emitting elements (LD1 to LD3) may be electrically connected to the first wiring portion (CE1) of the cathode (CE).

[0130] In one embodiment, the light-emitting elements (LD) may be of the flip-chip type. In this case, each of the light-emitting elements (LD) may be electrically connected to each of the anodes (AE) and the cathode (CE) from below. This will be described later with reference to FIG. 7.

[0131] In one embodiment, the light emitting elements (LD) may be arranged to be spaced apart from each other in a first diagonal direction (DR4) and a second diagonal direction (DR5) intersecting the first diagonal direction (DR4). For example, the first light emitting elements (LD1) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). In addition, the second light emitting elements (LD2) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). In addition, the third light emitting elements (LD3) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). That is, the light emitting elements (LD) may be arranged in a diagonal shape similar to the anodes (AE).

[0132] The light emitting elements (LD) may be arranged at regular intervals along the first diagonal direction (DR4) or may be arranged so as to have a regular interval between the light emitting elements (LD). For example, the interval (d) between the first light emitting element (LD1) and the second light emitting element (LD2) in the first diagonal direction (DR4) may be the same as the interval between the second light emitting element (LD2) and the third light emitting element (LD3) and the interval between the third light emitting element (LD3) and the first light emitting element (LD1). The interval between the light emitting elements (LD) in the first direction (DR1) may be the same as the interval between the light emitting elements (LD) in the second direction (DR2). However, the embodiments are not limited thereto.

[0133] Fig. 7 is a cross-sectional view taken along line II' of Fig. 6.

[0134] Referring to FIGS. 6 and 7, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0135] The pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns laminated on a substrate (SUB). This will be described later with reference to FIGS. 10 to 12.

[0136] A first anode (AE1) and a cathode (CE) may be arranged on the pixel circuit layer (PCL).

[0137] The first anode (AE1) can be electrically connected to a transistor (T_SP1, see FIG. 10) of the pixel circuit layer (PCL).

[0138] The cathode (CE) may be spaced apart from the first anode (AE1) in a second diagonal direction (DR5). The cathode (CE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) may be transmitted to the cathode (CE).

[0139] A first bank (BNK1) may be arranged on a first anode (AE1) and a cathode (CE) (or, a first wiring portion (CE1)). The first bank (BNK1) may have a first opening (OP1) exposing portions of the first anode (AE1) and the cathode (CE). A first light-emitting element (LD1) may be arranged in the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines an area where the first light-emitting element (LD1) is positioned.

[0140] The first bank (BNK1) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0141] A first reflective electrode (RFE1) may be disposed on an exposed portion of the first anode (AE1) and a side surface of the first bank (BNK1) adjacent thereto. A second reflective electrode (RFE2) may be disposed on an exposed portion of the cathode (CE) and a side surface of the first bank (BNK1) adjacent thereto. The first and second reflective electrodes (RFE1, RFE2) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1) may be improved. In embodiments, the first and second reflective electrodes (RFE1, RFE2) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0142] The first light-emitting element (LD1) is electrically connected to the first anode (AE1) via the first reflective electrode (RFE1). The first light-emitting element (LD1) is electrically connected to the cathode (CE) via the second reflective electrode (RFE2). The first light-emitting element (LD1) can be bonded to the first and second reflective electrodes (RFE1, RFE2).

[0143] The first light-emitting element (LD1) may include a first semiconductor layer (11), an active layer (12), a second semiconductor layer (13), and an auxiliary layer (15). The first light-emitting element (LD1) includes a light-emitting laminate in which the auxiliary layer (15), the first semiconductor layer (11), the active layer (12), and the second semiconductor layer (13) are sequentially laminated.

[0144] The first light-emitting element (LD1) includes first and second bonding electrodes (BDE1, BDE2) facing the same direction (e.g., opposite to the third direction (DR3)). The first bonding electrode (BDE1) may be connected to the second semiconductor layer (13). The second bonding electrode (BDE2) may be connected to the first semiconductor layer (11) exposed by etching the second semiconductor layer (13) and the active layer (12). In this way, the first light-emitting element (LD1) may be a flip chip type light-emitting element.

[0145] The first semiconductor layer (11) is configured to provide electrons to the active layer (12). The first semiconductor layer (11) may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer (11) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer (11) is not limited thereto, and various other materials may also constitute the first semiconductor layer (11). In one embodiment of the present invention, the first semiconductor layer (11) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). According to an embodiment, the first semiconductor layer (11) may form an n-type semiconductor layer together with the auxiliary layer (15).

[0146] The active layer (12) is disposed on the first semiconductor layer (11) and may be a region where electrons and holes recombine. As electrons and holes recombine in the active layer (12), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The active layer (12) may be formed in a single or multiple quantum well structure. When the active layer (12) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer may be repeatedly stacked to form the active layer (12). However, embodiments of the active layer (12) are not limited thereto.

[0147] The second semiconductor layer (13) is disposed on the active layer (12) and provides holes to the active layer (12). The second semiconductor layer (13) may include a semiconductor layer of a different type from the first semiconductor layer (11). For example, the second semiconductor layer (13) may include at least one p-type semiconductor layer. For example, the second semiconductor layer (13) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the second semiconductor layer (13) is not limited thereto, and various other materials may constituting the second semiconductor layer (13). In one embodiment of the present invention, the second semiconductor layer (13) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0148] The auxiliary layer (15) may include a gallium nitride (GaN) semiconductor material that is not doped with impurities, and may form an n-type semiconductor layer together with the first semiconductor layer (11).

[0149] The first bonding electrode (BDE1) may be electrically connected to the second semiconductor layer (13). The second bonding electrode (BDE2) may be electrically connected to the first semiconductor layer (11). The first and second bonding electrodes (BDE1, BDE2) may include a eutectic metal.

[0150] The first light-emitting element (LD1) may further include an insulating film (16) covering an outer surface of the light-emitting stack. The insulating film (16) may prevent an electrical short circuit that may occur when the active layer (12) comes into contact with a conductive material other than the first and second semiconductor layers (11, 13). The insulating film (16) may include a transparent insulating material. The insulating film (16) is configured to expose the lower surfaces of the first and second bonding electrodes (BDE1, BDE2).

[0151] The lower surface of the first bonding electrode (BDE1) contacts the first reflective electrode (RFE1). Accordingly, the first bonding electrode (BDE1) is electrically connected to the first anode (AE1) via the first reflective electrode (RFE1). The lower surface of the second bonding electrode (BDE2) contacts the second reflective electrode (RFE2). Accordingly, the second bonding electrode (BDE2) is electrically connected to the cathode (CE) via the second reflective electrode (RFE2).

[0152] An overcoat layer (OCL) may be disposed within a first opening (OP1) in which first and second reflective electrodes (RFE1, RFE2) and a first light-emitting element (LD1) are disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1) bonded to the first and second reflective electrodes (RFE1, RFE2) so as not to move. In addition, the overcoat layer (OCL) may protect components disposed thereunder from foreign substances such as dust and moisture. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but embodiments are not limited thereto.

[0153] A third passivation layer (PSV3) is disposed on the first bank (BNK1) and the overcoat layer (OCL). The third passivation layer (PSV3) protects components disposed thereunder and can provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2, see FIG. 10), but embodiments are not limited thereto.

[0154] In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface (LTS) of the first light-emitting element (LD1). The first light-emitting element (LD1) may protrude into the light-functional layer (LFL). The first light-emitting element (LD1) may be at least partially positioned within the second opening (OP2) of the second bank (BNK2). For example, the height of the upper surface (LTS) of the first light-emitting element (LD1) from the substrate (SUB) may be higher than the lowermost end (RBE) of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0155] The capping layer (CPL) is disposed on the third passivation layer (PSV3). The capping layer (CPL) can protect components under the capping layer (CPL), such as the first light-emitting element (LD1), from external moisture and humidity. In embodiments, the capping layer (CPL) may not be disposed on the upper surface of the first light-emitting element (LD1). In other embodiments, the capping layer (CPL) may entirely cover the first light-emitting element (LD1) and the third passivation layer (PSV3). The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the capping layer (CPL) is not limited thereto.

[0156] The pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1, see FIG. 4) have been described. Each of the second and third sub-pixels (SP2, SP3) of FIG. 4 may also be configured similarly to the first sub-pixel (SP1), unless otherwise described herein.

[0157] A light-functional layer (LFL) is disposed on a capping layer (CPL). The light-functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a fourth passivation layer (PSV4), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0158] A second bank (BNK2) is disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have a second opening (OP2) that overlaps the first opening (OP1).

[0159] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0160] A reflective layer (RFL) may be disposed on side surfaces of the second bank (BNK2) adjacent to the second opening (OP2). The reflective layer (RFL) is configured to reflect incident light, thereby improving light emission efficiency. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0161] On the capping layer (CPL), a fourth passivation layer (PSV4) is disposed within the second opening (OP2). The fourth passivation layer (PSV4) protects components disposed thereunder and can provide a flat upper surface. The fourth passivation layer (PSV4) may include the same material as any one of the first to third passivation layers (PSV1 to PSV3), but embodiments are not limited thereto.

[0162] On the fourth passivation layer (PSV4), a first light conversion pattern (CCP1) can be arranged within a second opening (OP2).

[0163] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. Additionally, the color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0164] The first sub-pixel (SP1) may be a red sub-pixel. When the first light-emitting element (LD1) emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. When the first light-emitting element (LD1) emits red light, the first light conversion pattern (CCP1) may include scattering particles. In this way, the particles included in the first light-conversion pattern (CCP1) may be variously changed depending on the first light-emitting element (LD1).

[0165] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) is configured to refract or totally reflect light depending on the incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0166] A color filter layer (CFL) may be disposed on a low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) overlaps the first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0167] Fig. 8 is a cross-sectional view taken along line II-II' of Fig. 6.

[0168] Referring to FIGS. 6 and 8, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0169] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to Fig. 7. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1 to SP3) are provided, respectively.

[0170] In the display element layer (DPL), a cathode (CE) (or, a second wiring portion (CE2)) is provided between the anodes (AE) in the first diagonal direction (DR4). For example, the second wiring portion (CE2) of the cathode (CE) is provided between the first anode (AE1) and the second anode (AE2) in the first diagonal direction (DR4). In addition, the second wiring portion (CE2) of the cathode (CE) is provided between the second anode (AE2) and the third anode (AE3) in the first diagonal direction (DR4). As the anodes (AE) are arranged in the first diagonal direction (DR4), the spacing between the anodes (AE) increases, so that the cathode (CE) can be arranged between the anodes (AE).

[0171] In the display element layer (DPL), first to third light-emitting elements (LD1 to LD3) corresponding to first to third sub-pixels (SP1 to SP3) are provided, respectively. The first to third light-emitting elements (LD1 to LD3) may overlap the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1) is connected between the cathode (CE) (or the first wiring portion (CE1), see FIG. 7) and a transistor (T_SP1, see FIG. 10) included in the sub-pixel circuit of the first sub-pixel (SP1). The second light-emitting element (LD2) is connected between the cathode (CE) and a transistor (T_SP2, see FIG. 11) included in the sub-pixel circuit of the second sub-pixel (SP2). The third light-emitting element (LD3) is connected between the cathode (CE) and the transistor (T_SP3, see Fig. 12) included in the sub-pixel circuit of the third sub-pixel (SP3). Hereinafter, redundant descriptions are omitted.

[0172] A light-functional layer (LFL) is provided on the display element layer (DPL). The light-functional layer (LFL) is described in the same manner as described with reference to Fig. 7. Hereinafter, redundant descriptions are omitted.

[0173] The second bank (BNK2) has second openings (OP2). It can be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1 to SP3) are defined by the second bank (BNK2). The area overlapping the second bank (BNK2) may correspond to (or overlap with) the non-light-emitting area (NEMA). The area overlapping the second openings (OP2) of the second bank (BNK2) may correspond to (or overlap with) the light-emitting area (EMA) of the first to third sub-pixels (SP1 to SP3).

[0174] On the capping layer (CPL), a fourth passivation layer (PSV4) may be disposed within the second openings (OP2). On the fourth passivation layer (PSV4), first and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) may be disposed within the second openings (OP2).

[0175] In embodiments, the first to third light-emitting elements (LD1 to LD3) may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light emission efficiency. Accordingly, the first to third sub-pixels (SP1 to SP3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0176] In embodiments, the first to third light-emitting elements (LD1 to LD3) may be configured to emit red, green, and blue light, respectively. In this case, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may each include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the first to third light-emitting elements (LD1 to LD3).

[0177] In embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0178] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3).

[0179] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1 to CF3) and light blocking patterns (LBP).

[0180] Each of the first to third color filters (CF1 to CF3) can selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1 to CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, embodiments are not limited thereto, and the first to third color filters (CF1 to CF3) may have a refractive index lower than or equal to that of the low-refractive-index layer (LRL).

[0181] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1 to CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1 to SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to (or overlap with) the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to (or overlap with) the light emitting area (EMA).

[0182] In embodiments, the light blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1 to CF3) overlap. For example, each of the light blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1 to CF3). As another example, the light blocking pattern between the first and second color filters (CF1, CF2) among the light blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light blocking pattern between the second and third color filters (CF2, CF3) among the light blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1 to CF3) can extend into the non-emission area (NEMA) to form light blocking patterns (LBP).

[0183] Fig. 9 is a plan view showing an embodiment of a pixel circuit layer. For convenience of explanation, Fig. 9 exemplarily shows a pixel circuit layer (PCL) corresponding to one pixel (PXL, see Fig. 4). Fig. 10 is a cross-sectional view taken along line III-III' of Fig. 9. Fig. 11 is a cross-sectional view taken along line IV-IV' of Fig. 9. Fig. 12 is a cross-sectional view taken along line VV' of Fig. 9.

[0184] Referring to FIGS. 9 to 12, the pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and the conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0185] Semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) can function as transistors and capacitors of a sub-pixel circuit (SPC, see FIG. 2). In addition, the conductive patterns of the pixel circuit layer (PCL) can further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1.

[0186] The pixel circuit layer (PCL) may include a first pixel circuit layer (PCL1), a second pixel circuit layer (PCL2), and a third pixel circuit layer (PCL3). The first pixel circuit layer (PCL1) may correspond to (or overlap) a first sub-pixel (SP1, see FIG. 4), the second pixel circuit layer (PCL2) may correspond to (or overlap) a second sub-pixel (SP2, see FIG. 4), and the third pixel circuit layer (PCL3) may correspond to (or overlap) a third sub-pixel (SP3, see FIG. 4).

[0187] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0188] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may comprise polyimide.

[0189] Transistors (T_SP1 to T_SP3) may be arranged on the buffer layer (BFL). The transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). The transistor (T_SP2) may be any one of the transistors of the sub-pixel circuit (SPC) included in the second sub-pixel (SP2). The transistor (T_SP3) may be any one of the transistors of the sub-pixel circuit (SPC) included in the third sub-pixel (SP3). For example, the transistors (T_SP1 to T_SP3) may be understood as transistors connected to the first to third anodes (AE1 to AE3), respectively.

[0190] Each of the transistors (T_SP1 to T_SP3) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0191] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. As the impurities, for example, a p-type impurity may be used, but embodiments are not limited thereto.

[0192] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0193] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor pattern (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers including an inorganic material. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0194] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL) to cover the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for forming the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0195] A gate electrode (GE) is disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0196] The first and second terminals (ET1, ET2) are disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) can include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0197] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), the embodiments are not limited thereto. In the embodiments, the first terminal (ET1) may be a first contact region adjacent to one side of the channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the light emitting element (LD) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0198] In embodiments, the transistors (T_SP1 to T_SP3) may be formed of low-temperature polysilicon transistors. However, the embodiments are not limited thereto. For example, the transistors (T_SP1 to T_SP3) may also be formed of oxide semiconductor transistors. In embodiments, the sub-pixel circuits of each of the first to third sub-pixels (SP1 to SP3) may include transistors of different types. For example, the transistors (T_SP1 to T_SP3) may be formed of low-temperature polysilicon transistors, and the other transistors may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the transistors (T_SP1 to T_SP3) is formed.

[0199] In the embodiments, the transistors (T_SP1 to T_SP3) are described as transistors having a top gate structure, but the embodiments are not limited thereto. For example, the transistors (T_SP1 to T_SP3) may be transistors having a bottom gate structure. In addition, the structures of the transistors (T_SP1 to T_SP3) may be changed in various ways.

[0200] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0201] A first passivation layer (PSV1) may be disposed on the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed thereunder and may provide a flat upper surface.

[0202] First to third conductive patterns (CP1 to CP3) may be arranged on a first passivation layer (PSV1). The first to third conductive patterns (CP1 to CP3) may be connected to first terminals (ET1) of transistors (T_SP1 to T_SP3) by penetrating the first passivation layer (PSV1), respectively. For example, the first to third conductive patterns (CP1 to CP3) may be connected to first terminals (ET1) of transistors (T_SP1 to T_SP3) by first contact holes (CNT1), respectively. The first to third conductive patterns (CP1 to CP3) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0203] In one embodiment, the first contact holes (CNT1) may have the same position in the second direction (DR2) with respect to the pixel. For example, within one pixel (PXL), the first contact holes (CNT1) may be formed at the same position in the first passivation layer (PSV1) in the second direction (DR2).

[0204] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0205] A second passivation layer (PSV2) is disposed on the first to third challenge patterns (CP1 to CP3) and the first passivation layer (PSV1). The second passivation layer (PSV2) protects components disposed thereunder and can provide a flat upper surface.

[0206] First to third anodes (AE1 to AE3) may be disposed on the second passivation layer (PSV2). The first to third anodes (AE1 to AE3) may be connected to the first to third conductive patterns (CP1 to CP3) by penetrating the second passivation layer (PSV2), respectively. For example, the first to third anodes (AE1 to AE3) may be connected to the first to third conductive patterns (CP1 to CP3) by way of second contact holes (CNT2), respectively.

[0207] In one embodiment, the second contact holes (CNT2) may have different positions in the second direction (DR2) with respect to the pixel. For example, within one pixel (PXL), the second contact holes (CNT2) may be formed at different positions in the second passivation layer (PSV2) in the second direction (DR2). The second contact holes (CNT2) may become closer to the first contact holes (CNT1) as they move from the first pixel circuit layer (PCL1) to the third pixel circuit layer (PC3).

[0208] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0209] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0210] Fig. 13 is a plan view showing another embodiment of the display panel of Fig. 4. With respect to Fig. 13, descriptions of content overlapping with Fig. 6 will be brief or omitted.

[0211] Referring to Fig. 13, the anodes (AE) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). However, the cathodes (CE) may not be arranged between some of the anodes (AE). Therefore, the spacing between the anodes (AE) in the first diagonal direction (DR4) may not be constant. For example, the spacing between the first anode (AE1) and the second anode (AE2) in the first diagonal direction (DR4) may be the same as the spacing between the second anode (AE2) and the third anode (AE3), and may be different from the spacing between the third anode (AE3) and the first anode (AE1). The shapes of the anodes (AE) may be changed to correspond to the positions of the second contact holes (CNT2).

[0212] The cathode (CE) has a diagonal mesh structure and may surround the anodes (AE) in multiple units. For example, the cathode (CE) may surround the first to third anodes (AE1 to AE3). In this case, the cathode (CE) may not be arranged between the first anode (AE1) and the second anode (AE2). In addition, the cathode (CE) may not be arranged between the second anode (AE2) and the third anode (AE3). The cathode (CE) having a diagonal mesh structure may include openings, and the first to third anodes (AE1 to AE3) may be arranged in each of the openings. The openings may refer to a space formed by the intersection of the first wiring portion (CE1) and the second wiring portion (CE2). That is, the cathode (CE) can surround the anodes (AE) in one pixel (or single pixel). In this case, each of the pixels (PXL, see FIG. 4) can include one second wiring portion (CE2).

[0213] The width (w') of the second wiring portion (CE2) of the cathode (CE) illustrated in FIG. 13 may be greater than the width (w) of the second wiring portion (CE2) of the cathode (CE) illustrated in FIG. 6. For example, the width (w') of the second wiring portion (CE2) illustrated in FIG. 13 may be greater than three times (3*w) the width (w) of the second wiring portion (CE2) of the cathode (CE) illustrated in FIG. 6. Accordingly, the voltage drop (IR drop) effect due to the decrease in resistance of the cathode (CE) may be greater.

[0214] Depending on the arrangement of the anodes (AE), the spacing between the light-emitting elements (LD) in the first diagonal direction (DR4) may not be constant. For example, the spacing (d1) between the first light-emitting element (LD1) and the second light-emitting element (LD2) in the first diagonal direction (DR4) may be the same as the spacing between the second light-emitting element (LD2) and the third light-emitting element (LD3), and may be different from the spacing (d2) between the third light-emitting element (LD3) and the first light-emitting element (LD1). The spacing (d2) between the third light-emitting element (LD3) and the first light-emitting element (LD1) may be greater than the spacing (d1) between the first light-emitting element (LD1) and the second light-emitting element (LD2). That is, the spacing (d1) between the first to third light-emitting elements (LD1 to LD3) included in one pixel (PXL, see FIG. 4) and the spacing (d2) between the light-emitting elements (e.g., LD1 and LD3) included in adjacent pixels may be different from each other.

[0215] Fig. 14 is a plan view showing another embodiment of the display panel of Fig. 1. With respect to Fig. 14, descriptions of content overlapping with Fig. 4 will be brief or omitted.

[0216] Referring to FIG. 14, the first sub-pixels (SP1) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). The second sub-pixels (SP2) may be arranged along the first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). The third sub-pixels (SP3) may be arranged along the first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). That is, unlike FIG. 4, the first to third sub-pixels (SP1 to SP3) may be arranged in a stripe shape.

[0217] Fig. 15 is a plan view showing an embodiment of the display panel of Fig. 14. With respect to Fig. 15, descriptions of content overlapping with Fig. 6 will be brief or omitted.

[0218] Referring to FIG. 15, the first light-emitting elements (LD1) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). The second light-emitting elements (LD2) may be arranged along the first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). The third light-emitting elements (LD3) may be arranged along the first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). That is, unlike FIG. 6, the first to third light-emitting elements (LD1 to LD3) may be arranged in a stripe shape. In this case, the arrangement margin of the cathode (CE) can be secured. In response to the changed arrangement of the first to third light-emitting elements (LD1 to LD3), the shapes of the anodes (AE) and the cathode (CE) may be changed. However, the spacing (d) between the light emitting elements (LD) in the first diagonal direction (DR4) and the width (w) of the second wiring portion (CE2) may be substantially the same as in the embodiment illustrated in FIG. 6.

[0219] Fig. 16 is a plan view showing an embodiment of a color filter layer. For convenience of explanation, some color filters (CF1 to CF3) among the color filter layers (CF) are illustrated as examples.

[0220] Referring to FIG. 16, the color filter layer (CF) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3). In one embodiment, the first to third color filters (CF1 to CF3) may be arranged in a first diagonal direction (DR4) and a second diagonal direction (DR5). That is, the first to third color filters (CF1 to CF3) may be arranged in a diagonal shape corresponding to the first to third light-emitting elements (LD1 to LD3).

[0221] In one embodiment, the first to third color filters (CF1 to CF3) may have a rectangular shape. The short side of each of the first to third color filters (CF1 to CF3) may be parallel to the first diagonal direction (DR4), and the long side may be parallel to the second diagonal direction (DR5).

[0222] The first to third color filters (CF1 to CF3) may be disposed on the first to third light-emitting elements (LD1 to LD3), respectively. For example, the first to third color filters (CF1 to CF3) may be disposed to overlap the first to third light-emitting elements (LD1 to LD3), respectively. The center of the first color filter (CF1) may coincide with the center of the first light-emitting element (LD1). The center of the second color filter (CF2) may coincide with the center of the second light-emitting element (LD2). The center of the third color filter (CF3) may coincide with the center of the third light-emitting element (LD3).

[0223] In one embodiment, the sizes of the first to third color filters (CF1 to CF3) may be different from each other. For example, the size of the second color filter (CF2) may be larger than the size of the first color filter (CF1). Additionally, the size of the first color filter (CF1) may be larger than the size of the third color filter (CF3). That is, the size of the second color filter (CF2) may be the largest, and the size of the third color filter (CF3) may be the smallest.

[0224] Fig. 17 is a plan view illustrating another embodiment of a color filter layer. For convenience of explanation, some color filters (CF1 to CF3) among the color filter layer (CF) are illustrated as examples. With respect to Fig. 17, descriptions of content overlapping with Fig. 16 will be omitted or simplified.

[0225] Referring to FIG. 17, the first to third color filters (CF1 to CF3) can be arranged in the first direction (DR1) and the second direction (DR2). That is, unlike the first to third light-emitting elements (LD1 to LD3), the first to third color filters (CF1 to CF3) can be arranged in a stripe shape.

[0226] The first to third color filters (CF1 to CF3) may have a rectangular shape, and the short side of each of the first to third color filters (CF1 to CF3) may be parallel to the first direction (DR1), and the long side may be parallel to the second direction (DR2). Similarly to FIG. 16, the first to third color filters (CF1 to CF3) may be arranged to overlap the first to third light-emitting elements (LD1 to LD3), respectively, and the centers of the first to third color filters (CF1 to CF3) may coincide with the centers of the first to third light-emitting elements (LD1 to LD3), respectively.

[0227] Fig. 18 is a plan view illustrating another embodiment of a color filter layer. For convenience of explanation, some color filters (CF1 to CF3) among the color filter layer (CF) are illustrated as examples. With respect to Fig. 18, descriptions of content overlapping with Fig. 16 will be omitted or simplified.

[0228] Referring to FIG. 18, the first to third color filters (CF1 to CF3) are arranged in a diagonal shape, and the first to third color filters (CF1 to CF3) may each have a polygonal shape. For example, the first and third color filters (CF1, CF3) may have a triangular shape, and the second color filter (CF2) may have a hexagonal shape. However, the embodiments are not limited thereto.

[0229] As illustrated in FIGS. 16 to 18, the size, shape, arrangement, etc. of the first to third color filters (CF1 to CF3) can be designed in various ways in consideration of the characteristics (efficiency, lifespan, etc.) of the first to third light-emitting elements (LD1 to LD3).

[0230] Fig. 19 is a plan view showing another embodiment of the display panel of Fig. 4. With respect to Fig. 19, descriptions of contents overlapping with Fig. 6 will be brief or omitted. Fig. 20 is a plan view showing the anodes and cathodes shown in Fig. 19. Fig. 21 is a plan view showing the first reflective electrodes and the second reflective electrode shown in Fig. 19. Fig. 22 is a plan view showing the light-emitting elements, the first transparent electrodes, and the second transparent electrode shown in Fig. 19.

[0231] Referring to FIGS. 19 and 20, the anodes (AE) can be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). Unlike FIG. 6, the shape of the anodes (AE) can be changed to correspond to the positions of the second contact holes (CNT2).

[0232] The cathode (CE) has a diagonal mesh structure and may include a first wiring portion (CE1) extending in a first diagonal direction (DR4) and a second wiring portion (CE2) extending in a second diagonal direction (DR5). Since the anodes (AE) and the cathode (CE) are the same as those described in Fig. 6, a detailed description thereof will be omitted.

[0233] Referring to FIGS. 19 and 21, first reflective electrodes (RFE1) are respectively provided on the anodes (AE). For example, the first reflective electrodes (RFE1) may be respectively disposed on the first anodes (AE1). In addition, the first reflective electrodes (RFE1) may be respectively disposed on the second anodes (AE2). In addition, the first reflective electrodes (RFE1) may be respectively disposed on the third anodes (AE3). The first reflective electrodes (RFE1) may be respectively formed to cover the anodes (AE).

[0234] The first reflective electrodes (RFE1) may be arranged spaced apart from each other in a first diagonal direction (DR4) and a second diagonal direction (DR5) intersecting the first diagonal direction (DR4). For example, the first reflective electrodes (RFE1) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5).

[0235] A second reflective electrode (RFE2) may be provided on the cathode (CE). In one embodiment, the second reflective electrode (RFE2) may be provided on the same plane as the first reflective electrodes (RFE1). The second reflective electrode (RFE2) may be spaced apart from the first reflective electrodes (RFE1). The second reflective electrode (RFE2) may be formed to cover the cathode (CE).

[0236] The second reflective electrode (RFE2) may have a diagonal mesh structure. For example, the second reflective electrode (RFE2) may include a first electrode portion (RFE21) extending in a first diagonal direction (DR4) and arranged in a second diagonal direction (DR5), and a second electrode portion (RFE22) extending in a second diagonal direction (DR5) and arranged in the first diagonal direction (DR4) and the second diagonal direction (DR5). The second electrode portion (RFE22) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). The first electrode portion (RFE21) may be spaced apart from the light emitting elements (LD) in the second diagonal direction (DR5). The second electrode portion (RFE22) may be spaced apart from the light emitting elements (LD) in the first diagonal direction (DR4). The second reflective electrode (RFE2) can surround each of the first reflective electrodes (RFE1).

[0237] The light-emitting elements (LD') may be of the lateral chip type. In this case, each of the light-emitting elements (LD') may be electrically connected to each of the anodes (AE) and the cathode (CE) from above. This will be described later with reference to FIG. 23.

[0238] Referring to FIGS. 19 and 22, each of the first transparent electrodes (ITO1) may be provided on each of the light-emitting elements (LD') and each of the first reflective electrodes (RFE1). Each of the first transparent electrodes (ITO1) may be electrically connected to each of the first reflective electrodes (RFE1) through each of the third contact holes (CNT3). In addition, each of the first transparent electrodes (ITO1) may be electrically connected to each of the light-emitting elements (LD') through each of the fourth contact holes (CNT4). For example, each of the first transparent electrodes (ITO1) provided on each of the first anodes (AE1) may be electrically connected to each of the first light-emitting elements (LD1') through each of the fourth contact holes (CNT4). The first transparent electrodes (ITO1) provided on the second anodes (AE2) may be electrically connected to the second light-emitting elements (LD2') through the fourth contact holes (CNT4), respectively. The first transparent electrodes (ITO1) provided on the third anodes (AE3) may be electrically connected to the third light-emitting elements (LD3') through the fourth contact holes (CNT4), respectively.

[0239] A second transparent electrode (ITO2) may be provided on the light-emitting elements (LD') and the second reflective electrode (RFE2). The second transparent electrode (ITO2) may be provided on the same plane as the first transparent electrodes (ITO1). The second transparent electrode (ITO2) may be spaced apart from the first transparent electrodes (ITO1).

[0240] The second transparent electrode (ITO2) may have a diagonal mesh structure. For example, the second transparent electrode (ITO2) may include a first transparent electrode portion (ITO21) extending in a first diagonal direction (DR4) and arranged in a second diagonal direction (DR5), and a second transparent electrode portion (ITO22) extending in a second diagonal direction (DR5) and arranged in the first diagonal direction (DR4) and the second diagonal direction (DR5). The second transparent electrode portion (ITO22) may be arranged in a zigzag shape along the first diagonal direction (DR4) and the second diagonal direction (DR5). The second transparent electrode (ITO2) may surround each of the first transparent electrodes (ITO1).

[0241] The second transparent electrode (ITO2) can be electrically connected to the light-emitting elements (LD') through the fifth contact holes (CNT5). For example, the second transparent electrode (ITO2) can be electrically connected to the first to third light-emitting elements (LD1' to LD3') through the fifth contact holes (CNT5). In addition, the second transparent electrode (ITO2) can be electrically connected to the second reflective electrode (RFE22) through the sixth contact holes (CNT6, see FIG. 23).

[0242] Fig. 23 is a cross-sectional view taken along line VI-VI' of Fig. 19. With respect to Fig. 23, descriptions of content overlapping with Fig. 7 will be brief or omitted.

[0243] Referring to FIGS. 19 and 23, the first light-emitting element (LD1') may include a first semiconductor layer (21), an active layer (22), a second semiconductor layer (23), and an auxiliary layer (25). The first light-emitting element (LD1') includes a light-emitting laminate in which the auxiliary layer (25), the first semiconductor layer (21), the active layer (22), and the second semiconductor layer (23) are sequentially laminated.

[0244] The first light-emitting element (LD1') includes first and second bonding electrodes (BDE1, BDE2) facing the same direction (e.g., the third direction (DR3)). The first bonding electrode (BDE1) may be connected to the second semiconductor layer (23). The second bonding electrode (BDE2) may be connected to the first semiconductor layer (21) exposed by etching the second semiconductor layer (23) and the active layer (22). The first light-emitting element (LD1') may be a lateral chip type light-emitting element.

[0245] A third passivation layer (PSV3) is disposed on the first and second reflective electrodes (RFE1, RFE2), the first light-emitting element (LD1'), and the overcoat layer (OCL). The third passivation layer (PSV3) protects components disposed thereunder and can provide a flat upper surface.

[0246] The third passivation layer (PSV3) may have third to sixth contact holes (CNT3 to CNT6). The third contact hole (CNT3) exposes a portion of the first reflective electrode (RFE1). The fourth contact hole (CNT4) exposes the top surface of the first bonding electrode (BDE1). The fifth contact hole (CNT5) exposes a portion of the second reflective electrode (RFE2). The sixth contact hole (CNT6) exposes the top surface of the second bonding electrode (BDE2).

[0247] First and second transparent electrodes (ITO1, ITO2) are disposed on a third passivation layer (PSV3). The first transparent electrode (ITO1) can electrically connect a first reflective electrode (RFE1) exposed through a third contact hole (CNT3) to a first bonding electrode (BDE1) exposed through a fourth contact hole (CNT4). The second transparent electrode (ITO2) can electrically connect a second reflective electrode (RFE2) exposed through a sixth contact hole (CNT6) to a second bonding electrode (BDE2) exposed through a fifth contact hole (CNT5). Accordingly, the first bonding electrode (BDE1) can be electrically connected to the first anode (AE1) through the first transparent electrode (ITO1) and the first reflective electrode (RFE1). The second bonding electrode (BDE2) can be electrically connected to the cathode (CE) via the second transparent electrode (ITO2) and the second reflective electrode (RFE2).

[0248] In embodiments, the first and second transparent electrodes (ITO1, ITO2) may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In embodiments, the first and second transparent electrodes (ITO1, ITO2) may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the first and second transparent electrodes (ITO1, ITO2) is not limited thereto.

[0249] The capping layer (CPL) is disposed on the third passivation layer (PSV3). The capping layer (CPL) can protect components under the capping layer (CPL), such as the first and second transparent electrodes (ITO1, ITO2), the first light-emitting element (LD1'), etc., from external moisture and humidity. The capping layer (CPL) can include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the capping layer (CPL) is not limited thereto.

[0250] The pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1, see FIG. 4) have been described. Each of the second and third sub-pixels (SP2, SP3) of FIG. 4 may also be configured similarly to the first sub-pixel (SP1), unless otherwise described herein.

[0251] Fig. 24 is a block diagram showing an embodiment of a display system.

[0252] Referring to FIG. 24, the display system (1000) may include a processor (1100) and a display device (1200).

[0253] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0254] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0255] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0256] Figures 25 to 28 are perspective views showing application examples of the display system of Figure 24.

[0257] Referring to FIG. 25, the display system (1000) of FIG. 24 can be applied to a smart watch (2000) including a display portion (2100) and a strap portion (2200).

[0258] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0259] Referring to FIG. 26, the display system (1000) of FIG. 24 can be applied to an automotive display system (3000). Here, the automotive display system (3000) can include a computing system provided inside and / or outside a vehicle to provide image data.

[0260] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0261] Referring to FIG. 27, the display system (1000) of FIG. 24 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0262] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0263] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0264] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0265] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0266] Referring to FIG. 28, the display system (1000) of FIG. 24 can be applied to a head-mounted display device (5000).

[0267] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0268] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0269] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0270] Those skilled in the art will appreciate that numerous modifications and variations can be made to the embodiments without significantly departing from the principles, technical concepts, and scope of the present invention. Therefore, the disclosed embodiments are intended to be used solely for general and illustrative purposes, not for limiting purposes.

Claims

1. Pixel circuit layer; Anodes arranged spaced apart from each other in a first diagonal direction and a second diagonal direction intersecting the first diagonal direction on the pixel circuit layer; A cathode disposed spaced apart from the anodes on the pixel circuit layer; and A display device comprising light-emitting elements, each of said light-emitting elements being electrically connected to each of said anodes and said cathode.

2. In paragraph 1, The above pixel circuit layer, transistors; A first passivation layer including first contact holes; Conductive patterns extending in a second direction on the first passivation layer and arranged in a first direction intersecting the second direction; and A display device comprising a second passivation layer including second contact holes.

3. In paragraph 2, A display device in which, in each pixel, the first contact holes have the same position in the second direction and the second contact holes have different positions in the second direction.

4. In paragraph 1, A display device in which the anodes and the cathode are arranged on the same plane.

5. In paragraph 1, A display device in which the anodes are arranged in a zigzag shape along the first diagonal direction and the second diagonal direction.

6. In paragraph 1, The above cathode is a display device having a diagonal mesh structure.

7. In paragraph 6, The above cathode is, A first wiring portion extending in the first diagonal direction and arranged in the second diagonal direction; and A display device including a second wiring portion extending in the second diagonal direction and arranged in a zigzag shape along the first diagonal direction and the second diagonal direction.

8. In paragraph 6, The above cathode is a display device that surrounds the anodes in each sub-pixel.

9. In paragraph 6, The above light emitting elements are a display device of the flip chip type.

10. In paragraph 9, A display device in which the light emitting elements are arranged along the first diagonal direction so as to have a constant interval between the light emitting elements.

11. In paragraph 10, A display device in which the light emitting elements are arranged in a zigzag shape along the first diagonal direction and the second diagonal direction.

12. In paragraph 6, The above cathode is a display device that surrounds the anodes in each pixel.

13. In paragraph 12, The light emitting elements included in each pixel are arranged along the first diagonal direction so as to have a first gap between the light emitting elements included in each pixel, A display device in which light emitting elements included in adjacent pixels are arranged along the first diagonal direction so as to have a second interval different from the first interval between the light emitting elements included in the adjacent pixels.

14. In paragraph 9, A display device in which the light emitting elements are arranged with a constant spacing between the light emitting elements along a first direction and a second direction intersecting the first direction.

15. In paragraph 1, A display device further comprising color filters respectively arranged on the light-emitting elements.

16. In paragraph 15, A display device in which the center of each of the color filters and the center of each of the light-emitting elements are aligned.

17. In paragraph 15, The light emitting elements include first light emitting elements emitting light of a first color, second light emitting elements emitting light of a second color, and third light emitting elements emitting light of a third color, A display device in which the color filters include first color filters each disposed on the first light-emitting elements, second color filters each disposed on the second light-emitting elements, and third color filters each disposed on the third light-emitting elements.

18. In paragraph 17, A display device wherein the size of the second color filters is larger than the size of the first color filters, and the size of the first color filters is larger than the size of the third color filters.

19. In paragraph 15, The above color filters are a display device having a polygonal shape.

20. In paragraph 6, The above light emitting elements are a display device of the lateral chip type.

21. In paragraph 20, A reflective electrode arranged in a diagonal mesh structure on the cathode; and A display device further comprising a transparent electrode arranged in a diagonal mesh structure on the reflective electrode and electrically connected to the light-emitting elements.

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