Driver circuit

Abstract

The invention provides a driver circuit (class-DE driver) for driving a line having a circuit inductance (Lac) and a circuit impedance (C), the driver circuit adapted for generating, when operating at a cryogenic temperature, a current (Icoil, ac) for generating a set magnetic field to control a quantum system (not shown close to Lac), The circuit inductance (Lac) and the circuit impedance (C) defining a resonance frequency matching the control frequency of the quantum system for optimizing an output power of the driver circuit.

Description

[0001]P100929PC00 Driver circuit Field of the invention The invention relates to a driver circuit, a method for producing a driver currenton a line of a quantum computing system, and a quantum computing device. Background of the invention US11683026 According in its abstract discloses: “Techniques are provided forcalibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.” In this proposal, the circuit drives a 50 ohm load, which was found to be inefficientfor magnetic field driving. Long lines are needed for bridging temperature gap, bymoving to the same temperature stage the lines can be reduced, resulting in a line with a specific inductance and impedance that can be used to optimize for the efficient current driving at the qubit frequencies. US20240022248 according to its abstract relates to “Apparatus and methods forinterfacing an integrated qubit control chip and a solid state qubit; detecting a qubit state with a transition pulse histogram; high resolution and high speed rectangular pulse generation; large-scale spin qubit state readout; and activity-based clock control.” Again, it shows 50 Ohm driving to generate the fluctuating magnetic field. Alsothe CMOS are at 4K, but the qubit are at mK, meaning intermediate cabling is required.WO2019164638 according to its abstract relates to: “The Zeeman shift of electronic spins in nitrogen-vacancy (NV) centers in diamond has been exploited in lab- scale instruments for ultra-high-resolution, vector-based magnetic sensing. A quantum magnetometer in CMOS utilizing a diamond-nanocrystal layer with NVs or NV-doped bulk diamond on a chip-integrated system provides vector-based magnetic sensing in a compact package. The system performs two functions for the quantum magnetometry:(1) strong generation and efficient delivery of microwave for quantum-state control and(2) optical filtering / detection of spin-dependent fluorescence for quantum-state readout. The microwave delivery can be accomplished with a loop inductor or array of wires integrated into the chip below the nanodiamond layer or diamond. And the wire array can also suppress excitation light using a combination of plasmonic and (optionally) Talbot effects.” S. Pezzagna et al., “Quantum computer based on color centers in diamond,” Applied Physics Review, Feb. 2021, in its abstract states “Artificial atoms like the nitrogen vacancy (NV) centers in diamond enable the realization of fully functional qubits in a solid at room temperature. The functionalities of all the parts needed to createa quantum computer, such as quantum error correction, couplings, quantumteleportation, and a quantum repeater, have already been experimentally demonstrated. These achievements are expected to influence the industrial development of quantum information technology as well as quantum sensing. Whereas quantum sensing has been established and a large number of organizations are working on new developments in this area, a quantum computer itself remains elusive due to technical reasons and limitations of the available materials. For example, only in recent months has it become possible to electrically readout the NV spin state at the level of a single center and significantly improve the scalability of NV center production. A number of ideas have been proposed to overcome the above-mentioned limitations. This paper summarizes the status of research in the area, details the most promising concepts for development, and discusses factors limiting progress as well as the most recent developments in the field.” R. Ishihara et al., “3D Integration Technology for Quantum Computer based onDiamond Spin Qubits,” IEDM, Dec. 2021, in its abstract states: “Quantum computerchip based on spin qubits in diamond uses modules that are entangled with on-chip optical links. This enables an increased connectivity and a negligible crosstalk and error- rate when the number of qubits increases on-chip. Here, 3D integration is the key enabling technology for a large-scale integration of the diamond spin qubits with photonic circuits and CMOS electronics for routing, control and readout of qubits. Several engineering challenges exist in order to integrate the large number of spins in diamond with the on-chip circuits operating at a cryogenic temperature. We will review trends, address challenges and discuss future outlook of the integration technology for realization of a scalable quantum computer based on diamond spin qubits.” J. Yoo et al., “34.2 A 28-nm Bulk-CMOS IC for Full Control of a Superconducting Quantum Processor Unit-Cell,” ISSCC, pp. 506-508, Feb. 2023, in its abstract states: “While large-scale fault-tolerant quantum computers promise to enable the solution to certain classes of problems for which no other efficient approach is known, such a machine is believed to require over a million performant qubits. Scaling today's 0(100) qubit superconducting (SC) quantum computers to this extent while also improving performance carries many daunting challenges, including control of such a large quantum processor (QP). Integrating the control electronics at an intermediate temperature stage within the cryostat is an attractive option, e.g., due to the inherent thermal stability of the cryogenic environment and the feasibility of connecting to the QP via dense low-loss / high-thermal-isolation SC lines [1], [2]. Several cryo-CMOS quantum controllers have been reported, with examples used to control spin [3] and transmon [1], [2] qubits. To date, IC-based quantum control experiments have focused on resonant RF control, but baseband signals are often central to the execution of gates. Here, we report the design and system characterization of a cryo-CMOS IC for generating both the RF and baseband signals required for full control of a SC QP unit- cell, and show its ability to implement the components of a high-fidelity gate set that is universal for quantum computing.” D. J. Frank et al., “A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology,” ISSCC, pp.360-361, Feb.2022, in its abstractstates: “Error-corrected quantum computing is expected to require at least 105 to 106physical qubits. Superconducting transmons, which are promising qubit candidates for scaled quantum computing systems, typically require individually tailored RF pulses in the 4-to-6 GHz range to manipulate their states, so scaling to 106 qubits presents an enormous challenge. Providing a control line for every qubit from room temperature (RT) to the 10mK environment does not appear to be viable for a 106 qubit system due to multiple factors, including RF loss, mechanical congestion, heat load, and connector unreliability. TDM cannot be used to reduce the number of control lines since all of the qubits may need to be activated at once (e.g., during quantum error correction (QEC) cycles). FDM has been proposed but is undesirable because extra tones can give rise to unwanted qubit excitations.” J. S. Park, et al., “A fully integrated cryo-CMOS SoC for qubit control in quantum computers capable of state manipulation, readout and high-speed gate pulsing of spin qubits in Intel 22nm FFL FinFET technology,” ISSCC, pp. 208-209, Feb. 2021, in itsabstract states: “Quantum computing promises exponential speed-up in solving certaincomplex problems that would be intractable by classical computers. However, thousands or millions of qubits might be required to solve useful problems. High-precision and low-noise electrical signals are required to manipulate and read the state of a qubit and to control qubit-to-qubit interactions. Current systems use room temperature electronics with many coax cables routed to the qubit chip inside a dilution refrigerator. This approach does not scale to large number of qubits, due to form factor, cost, power consumption and thermal load to the fridge. To address this challenge, a cryogenic qubit controller has been proposed [1]. The first integrated implementation of a cryogenic pulse modulator has been presented in [2], demonstrating the capability of manipulating (drive) the state of superconducting qubits. The work in [3] extends the capability of the controller with 3 main features: frequency-multiplexing to reduce the number of RF cables per qubit, an arbitrary I / Q pulse generation for improved control fidelity and a digitally-intensive architecture with integrated instruction set to enable integration in existing quantum control stacks. This work further advances the prior art by integrating the capability of reading the qubit state and generating the voltage pulses required for drive, readout, 2-qubit operations and qubit characterization. The SoC can drive up to 16 spin qubits by frequency multiplexing over a single RF line, read the state of up to 6 qubits simultaneously and control up to 22 gate potentials. The SoC also integrates a \mu-controller for increased flexibility in implementing the control instruction set. The proposed cryogenic controller can replace all the high-speed control electronics used in conventional solutions today, paving the way towards scalable quantum computers.” P. A. ‘t Hart et al., “Characterization and Modeling of Mismatch in Cryo-CMOS,”JEDS, pp 263-273, Feb. 2020, in its abstract states: “This paper presents a devicematching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge- effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.” JOSEPH C. BARDIN ET AL: "Design andCharacterization of a 28-nm Bulk-CMOS Cryogenic Quantum Controller Dissipating Less Than 2 mW at 3 K", IEEEJOURNAL OF SOLID-STATE CIRCUITS, part 54, no. 11, 23 Oktober 2019, pp 3043-3060, relates to a cryogenic CMOS quantum controller for transmon qubits.DEVIN L UNDERWOOD ET AL: "Using Cryogenic CMOS Control ElectronicsTo Enable A Two-Qubit Cross-Resonance Gate", ARXIV.ORG, CORNELLUNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA,NY 14853, 9 December 2023, relates to qubit control electronics composed of CMOScircuits in FinFET technology for transmon qubits. Summary of the invention Adisadvantage of prior art is that known drivers for operation under cooledconditions often dissipate heat, which in turn requires higher power input for cooling. Known drivers cannot be integrated at millikelvin cooling plates (necessary for certain types of qubits), since the available cooling power is limited to a few mW. Also there is a cable needed to cover the physical distance between the driver located at the 4K plate and the qubit located at the mK plate. Hence, it is an aspect of the invention to provide a driver circuit which preferablyfurther at least partly obviates one or more of above-described drawbacks. There is provide a driver circuit for driving a line having a circuit inductance and a circuit impedance, the driver circuit adapted for generating, when operating at a cryogenic temperature, a current for generating a set magnetic field to control a quantum system, The circuit inductance and the circuit impedance defining a resonance frequency matching the control frequency of the quantum system for optimizing an output power of the driver circuit. There is furthermore provided a method for producing a driver current on a line of a quantum computing system, comprising selecting a driver resonance of a driver circuit to match the control frequency of the quantum system while minimizing the power dissipation of the driver. There is furthermore provided a quantum computing device comprising a series ofqubits operating at a qubit temperature and a driver circuit according to any one of the preceding claims for at least one of driving and controlling the qubits, the driver circuit operating at the qubit temperature. Generating large current amplitude using a driver circuit in cryogenic temperaturesthat drive a 50-Ohm transmission line into a 50-Ohm load would require a largeimpedance transfer ratio and consume significant power. However, the proposed drivercircuit it is located much closer to the quantum system, for instance closer to the qubits.Thus long lines can be omitted, and the driver circuit comprises or provides a resonatorconsisting of a capacitor and an inductor with a quality factor of Q and a series resistancer = ωL / Q where ω = 2π f0 is the resonator’s angular resonant frequency.Since the driver must now provide the required current to a low-ohmic resistorinstead of 50 Ohm, power consumption is significantly reduced.In general, the current device and circuit(s) operate(s) or is / are designed to operate at a low temperature. In the current application, “low temperature” is defined as a temperature of below -55^C (218K). In physics, cryogenics relates to the production and behaviour of materials at very low temperatures. The 13th IIR International Congress of Refrigeration (held in Washington DC in 1971) a universal definition of "cryogenics" and "cryogenic" was set by accepting a threshold of 120 K (or –153 °C) to distinguish these terms from the conventional “refrigeration”. The U.S. National Institute of Standards and Technology considers the field of cryogenics to involve temperatures below 120K. In particular embodiments, reference is made to circuits operating at cryogenic temperature. In some applications, even lower temperatures are required. For instance, this low cryogenic operation is below 10 K. In particular, low cryogenic is below 4.2 K. Color-center quantum bits (qubits), such as the Nitrogen-Vacancy center (NV) in diamond, have demonstrated entanglement between remote (>1.3km) qubits and excellent coherence times, all while operating at a few Kelvins. Compared to other qubit technologies typically operating at mK temperatures, the higher operating temperature of NVs enables scalable 3D integration with cryo-CMOS control electronics, provides significantly more cooling power, and removes the interconnect bottleneck between the qubits and the electronics in prior art. Yet, no cryo-CMOS controller for NV-based quantum computers (QC) has been demonstrated. An operating temperature difference between components of a quantum computing device limits scalability. For instance by moving a qubit to a higher operatingtemperature, such as 1-4K for NV centers, more cooling power is available and theelectronics can be co-integrated at the same temperature plate. This makes cablesbetween components obsolete and allows for resonant driving.In general, the following is used to define a class D and class DE amplifier / driver. A class-D amplifier or switching amplifier is an electronic amplifier in which the amplifying devices (transistors, usually MOSFETs) operate as electronic switches, and not as linear gain devices as in other amplifiers. They operate by rapidly switching backand forth between a supply rails, using pulse-width modulation, pulse-densitymodulation, or related techniques to produce a pulse train output. A simple low-pass filter may be used to attenuate their high-frequency content to provide analog output current and voltage. Little energy is dissipated in the amplifying transistors because they are always either fully on or fully off, so efficiency can exceed 90%. In general, The Class DE RF switching-mode power amplifier, also called theClass D ZVS RF power amplifier, has two transistors, series-resonant circuit, and shuntcapacitors connected in parallel with the transistors. It combines the properties of low voltage stress of the Class D power amplifier and zero-voltage switching (ZVS) of the Class E power amplifier. Switching losses are zero in the Class DE power amplifier, yielding high current efficiency. In the Class DE power amplifier, the transistors are driven in such a way that there are time intervals (dead times) when both transistors are OFF. The nitrogen-vacancy center (N-V center or NV center) is one of numerous photoluminescent point defects in diamond. Its most explored and useful properties include its spin-dependent photoluminescence (which enables measurement of theelectronic spin state using optically detected magnetic resonance), and its relatively long(millisecond) spin coherence at room temperature. The NV center energy levels aremodified by magnetic fields, electric fields, temperature, and strain. This for instanceallows it to serve as a sensor of a variety of physical phenomena. Its atomic size and spin properties can form the basis for useful quantum sensors. It has also been explored for applications in quantum computing (e.g. for entanglement generation) and spintronics. The NV center has a ground-state triplet (3A), an excited-state triplet (3E) and two intermediate-state singlets (1A and 1E). Both 3A and 3E contain ms= ±1 spin states, in which the two electron spins are aligned (either up, such that ms = +1 or down, such that ms = -1), and an ms = 0 spin state where the electron spins are antiparallel. Due to the magnetic interaction, the energy of the ms= ±1 states is higher than that of the ms= 0 state.1A and 1E only contain a spin state singlet each with ms= 0. If an external magnetic field is applied along the defect axis (the axis which aligns with the nitrogen atom and the vacancy) of the NV center, it does not affect the ms = 0 states, but it splits the ms = ±1 levels (Zeeman effect). Similarly the following other properties of the environment influence the energy level diagram (further discussed under #Effects of external fields) The energy difference between the ms= 0 and ms= ±1 states corresponds to the microwave regime. Population can be transferred between the states by applying a resonant magnetic field perpendicular to the defect axis. Numerous dynamic effects (spin echo, Rabi oscillations, etc.) can be exploited by applying a carefully designed sequence of microwave pulses. Such protocols are rather important for the practical realization of quantum computers. By manipulating the population, it is possible to shift the NV center into a more sensitive or stable state. Its own resulting fluctuating fields may also be used to influence the surrounding nuclei or protect the NV center itself from noise. This is typically done using a wire loop (microwave antenna) which creates anoscillating magnetic field. (Free according to Wikipedia)Detailed description of the inventionIn the description in this part, various embodiments are discussed. In an embodiment, the driver circuit comprises a CMOS structure. In an embodiment, the driver circuit comprises a DC current regulator comprisingat least two transistors biased in triode. In a particular embodiment, this enables drivingcurrents of between -12.5 mA and +12.5 mA. In particular, the DC current regulator isbased on CMOS. In an embodiment, the DC current regulator comprises transistors biased in triode. In a particular embodiment thereof, it comprises a triode H-bridge with reduced supply to control the polarity of the current for driving positive and negative currents in the coil. In an embodiment, the driver further comprises a feedback loop designed tooperate with the nominal supply to regulate the current inside the H-bridge, allowing for improved supply rejection at low frequencies without dissipating significant amounts of power. In an embodiment, he driver circuit further comprises a high resolution currentDAC, wherein the feedback loop mirrors and amplifies the current from the high resolution current DAC, enabling a high resolution control of the current in the H-bridge, while the high resolution DAC dissipates less power and can benefit from supply rejection as it operates in saturation. In an embodiment, the high resolution DAC comprises two DACs, a first one with a coarse structure, and a second one with a Fine structure, i.e. fine with respect to the coarse structure, where overlap in the most significant bit (MSB) codes and the first and second Coarse / Fine DAC are is implemented to ensure that no missing codes are presentand the an entire range can be covered with an least significant bit (LSB) step. The DACare selected for LSB=420pA, in particular in view of the future for strong coil-to-qubit coupling. In an embodiment, the feedback loop comprising a trimming element to mitigate the influence of offset and maximize the operating range of the loop. In a particularembodiment thereof, the feedback loop comprises a chopper stabilizer designed tofurther reduce the offset and 1 / f noise. More in particular the feedback loop furthercomprises a switched capacitor notch filter that further reduces the ripple at the choppingfrequency. In an embodiment, the driver circuit further comprises a shunt path designed to setthe voltage across the H-bridge, allowing stacking of the driver circuit. In an embodiment, the driver circuit comprises a class-DE voltage-mode driveradapted to drive a low impedance series resonant tank. In particular the class-DEvoltage-mode driver is adapted to drive the low impedance series resonant tank adaptedto drive the low impedance series resonant tank at high frequencies higher than 1GHz. In an embodiment the class DE voltage-mode driver comprises a resonant tank in series adapted to achieve a Q (quality factor of resonator)-times larger current swing. In an embodiment, the class-DE voltage-mode driver comprises NMOS and PMOS transistors in a final output stage and is adapted for class-DE operation by applying 25% duty-cycle rail-to-rail input pulses to the gates of the NMOS and PMOStransistors of the final output stage. In a particular embodiment, the class-DE voltage-mode driver comprising a shunt and series capacitances designed with the coil inductance to achieve zero-voltage-switching (ZVS) operation. In an embodiment, the shunt capacitor is partially implemented by the parasitic capacitance of the output stage transistors. In particular, the rest of the capacitance can be implemented with additional metal capacitors. In an embodiment of the driver circuit with the class-DE voltage-mode driver aseries capacitance of the resonator is provided before or after a coil that is driven. Inparticular, it is implemented as metal capacitor or the parasitic switch capacitance of thetransistors implementing a coil sharing switch. In an embodiment, the class-DE voltage-mode driver further comprising a multi- bit output stage, for driving a load with a varying output current amplitude. In an embodiment, the driver circuit comprises a class D stage for driving an ACcurrent. In particular, it is adapted for driving at low frequencies below 50 MHz. In aparticular embodiment, the low frequency is below 10 MHz. In a particular embodimentthe class D stage has a lowered supply voltage. In a particular embodiment thereof, theclass D stage driving an AC current of >10mApk. More in particular, the class D stage driving at frequencies adapted to drive operations on nuclear spins. In an embodiment, the class D stage is a CMOS-based stage. In an embodiment, the class D stage comprises a class D output stage adapted to operate with a low positive and negative supply set to only enable the transistors to operate in triode. In a further embodiment the class D output stage further comprises switches that are sized to reduce the on resistance below 1 Ω and forward back biasing can be used to reduce the on resistance. In a particular embodiment the class D outputstage directly drives the low impedance coil and forms a first order low-pass filter withthe low impedance coil. In an embodiment, the class D output stage comprises a digital loopfilter for enabling low quantization noise in a preselected frequency band, i.e., where the Larmorfrequencies of the nuclear spin qubits are located. In a particular embodiment thereof,the digital loop filter comprises a programmable resonator.In an embodiment, the driver circuit further comprising an analogue to digitalconverter for sensing the coil voltage. In a particular embodiment, the sensed coilvoltage is fed back into the loopfilter to provide supply rejection with transistors operating in triode. In an embodiment, the class D stage comprises an analog-to-digital converter (ADC), a loopfilter and an output stage, with a clock gating designed to freeze, allowingthe circuit to resume operation and track a quantization error once the circuit restarts.In an embodiment, a input of the class D stage is provided by at least one numerically controlled oscillator (NCO)’s that outputs a digital rising sawtooth waveform that wrap around at a midpoint to form a triangle waveform. In an embodiment, phase and amplitude modulation is performed by adding phase to the NCO and by multiplying the NCO output with the amplitude code word, for removing second order harmonics. In an embodiment, the driver circuit further comprises a back-to-back thick oxideNMOS switch, that allows for reverse current blocking, and providing a coil-sharing switch for coupling a first driver for operating a coil and a second driver for operatingthe coil. In particular, the coil-sharing switch comprises a back-to-back NMOS switch.In a particular embodiment, the first driver comprises a class DE voltage-mode driver asdescribed herein, and the second driver comprises a class D stage as described herein.In an embodiment, the coil-sharing switch has an ON-state in which gates of atleast one thick oxide NMOS device is tied to a supply, for providing a low-impedancepath to ground, optimal for the low-frequency operation. In particular, the at least onethick oxide NMOS device provided for handling larger voltages than regular oxideNMOS. More at least one thick oxide NMOS device has a gate width >1mm.In an embodiment, the coil-sharing switch has an OFF-state, in which the gatesare tied to shared sources of NMOS devices, for forcing the gate-source voltage to 0, and hence turning off the switch. In a particular embodiment, the gates are tied to shared sources of NMOS devices for re-using the parasitic capacitance of the drain to source as series capacitance for the resonator for the high-frequency operation. In an embodiment the coil-sharing switch comprising at least one back-to-back thick oxide NMOS device. In an embodiment, the at least one back-to-back thick oxide NMOS device is sized sufficiently large to minimize on-resistance to optimize low-frequency operation. In an embodiment, it is not larger than the maximum parasitic capacitance of 3pF to reach thetanks’ resonance for the high-frequency operation. In an embodiment of the quantumcomputing device, the qubits are color-center quantum bits (qubits), such as the Nitrogen-Vacancy center (NV) in diamond. The terms “upstream” and “downstream” relate to an arrangement of items or features relative to the propagation of the light from a light generating means (here the especially the first light source), wherein relative to a first position within a beam of light from the light generating means, a second position in the beam of light closer to the light generating means is “upstream”, and a third position within the beam of light further away from the light generating means is “downstream”. The term “substantially” herein, such as in “substantially consists”, will be understood by the person skilled in the art. The term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. Hence, in embodiments the adjective substantially may also be removed. Where applicable, the term “substantially” may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, even more especially 99.5% or higher, including 100%. The term “comprise” includes also embodiments wherein the term “comprises” means “consists of”. The term "functionally" will be understood by, and be clear to, a person skilled in the art. The term “substantially” as well as “functionally” may also include embodiments with “entirely”, “completely”, “all”, etc. Hence, in embodiments the adjective functionally may also be removed. When used, for instance in “functionally parallel”, a skilled person will understand that the adjective “functionally” includes the term substantially as explained above. Functionally in particular is to be understood to include a configuration of features that allows these features to function as if the adjective “functionally” was not present. The term “functionally” is intended to cover variations in the feature to which it refers, and which variations are such that in the functional use of the feature, possibly in combination with other features it relates to in the invention, that combination of features is able to operate or function. For instance, if an antenna is functionally coupled or functionally connected to a communication device, received electromagnetic signals that are receives by the antenna can be used by the communication device. The word “functionally” as for instance used in “functionally parallel” is used to cover exactly parallel, but also the embodiments that are covered by the word “substantially” explained above. For instance, “functionally parallel” relates to embodiments that in operation function as if the parts are for instance parallel. This covers embodiments for which it is clear to a skilled person that it operates within its intended field of use as if it were parallel. Furthermore, the terms first, second, third and the like in the description and in theclaims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms soused are interchangeable under appropriate circumstances and that the embodiments ofthe invention described herein are capable of operation in other sequences than describedor illustrated herein.The devices or apparatus herein are amongst others described during operation.As will be clear to the person skilled in the art, the invention is not limited to methods of operation or devices in operation. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "to comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements. In thedevice or apparatus claims enumerating several means, several of these means may beembodied by one and the same item of hardware. The mere fact that certain measuresare recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. The invention further applies to an apparatus or device comprising one or more of the characterising features described in the description and / or shown in the attached drawings. The invention further pertains to a method or process comprising one or more of the characterising features described in the description and / or shown in the attached drawings. The various aspects discussed in this patent can be combined in order to provide additional advantages. Furthermore, some of the features can form the basis for one or more divisional applications. Brief description of the drawings Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which: Figure 1 relates to a scalable NV-based QC, showing a design for a modularquantum computer based on NV-centers with AC and DC coils connected to the 3D-integrated cryo-CMOS chip, showing a inhomogeneity of the permanent magnetic fieldB0 (illustrated in the top-left drawing) which induces a shift in the Larmor frequency f0(shown in the top-right graph) to be compensated in each individual module.Figure 2A-2C To maximize the generated AC magnetic field, a series resonanttank (temporary power storage) is preferred over its parallel counterpart, as the inductor current is Q (resonator’s quality factor) times higher for the same voltage across the driving transistor, which is limited by reliability. The drawings show a comparison between series and parallel tank to maximize coil current (Figure 2A); Issues associatedwith class-D and class-E switched-mode amplifiers (Figure 2B), and a block diagram ofthe AC controller, including a proposed class-DE current driver and its waveforms(Figure 2C). Figures 3A-3E show a DC current regulator for locally adjusting the DC magneticfield by running a DC current (Icoil, DC up to 10mA) through a low–resistance coil (Rcoil,DC ~1Ω) close to the NV to locally actuate the magnetic field. The drawings show acomparison between a current regulator utilizing a transistor operating in saturation(Figure 3A) and triode (Figure 3B). To tune the qubit Larmor frequency f0, the DCcurrent regulator exploits a triode-biased H-bridge and a chopped regulation loop to achieve low power and robustness to supply variation. Voltages For the H-bridge,voltage drops for Icoil,DC=10mA, Rcoil=1Ω and R4b =1Ω are annotated in Figure 3C, alsothe timing diagram describing the operation of the chopping circuit is disclosed (Figure3D), and an additional shunt arrangement is illustrated in figure 3E (dotted), with a shuntpath that allows modulating the H-bridge supply (when multiple H-bridges are arrangedin series), in particular when multiple H-bridges are voltage-stacked, VL,H-bridge is notshorted to VSS. Figures 4A-4F show a characterization at room temperature (RT) and 4.2K (CT)of a MW AC controller and DC current regulator that have been fabricated in a 40-nmCMOS process, Illustrated in figures 4A-4C are measured spectrum of Icoil,AC, Icoil,AC transient waveform and Icoil,AC / Idriver,DCover frequency of the AC controller at cryogenictemperature (CT), and illustrated in figures 4D-4F are measured PSD of Icoil,DC, supplyrejection of Icoil,DC versus VH-bridge and VDD of the DC current regulator at CT.Figures 5A-5D show in figure 5A characteristics of a Rabi oscillation of a NVcenter electron spin, showing a comparison between driving by RT electronic setup andan integrated CMOS AC controller, figure 5B the Rabi frequency (fR) vs driver DCcurrent (Idriver, DC) of the AC controller, figure 5C the tuning of Larmor frequency (f0)with DC current regulator, and figure 5D is illustrated, using both chips, the calibratingf0 for largest Rabi oscillation amplitude by sweeping DDC. Figure 6 shows a comparison of the currently proposed cryo-CMOS controller toa state-of-the-art cryo-CMOS controller, where the current cryo-CMOS controller is the first targeting color centers, with the AC controller demonstrating a more effective way of generating high AC current levels with respect to prior cryo-CMOS controllers, thusshowing a benchmark of the currently proposed AC controller with prior art cryo-CMOScontrollers, and performance of the currently proposed DC current regulator. Figure 7 shows, in order to demonstrate functionality, the currently proposed cryo-CMOS chips that have been integrated with a NV center qubit. Two striplines, LDCand LAC, are used; LDC is here bonded to a bias-T, which combines the DC current regulator with RT electronics, used for comparison; LAC here is directly bonded to the AC driver. Figures 8A-8C Qubit measurement setup (figure 8A), which highlights the sampleholder containing the qubit sample and cryo-CMOS chips on a single PCB, and in figure 8B the setup schematically. In figure 8C a side cross-section of the diamond details the integration of striplines with the NV centers, demonstrating the coils introducing both parallel and perpendicular magnetic fields at the qubit location. Figure 9A illustrates how a class D output stage is used that operates with a lowersupply and has big switches to reduce the power dissipated in the coil, showing a system overview of the MW and RF controller, where both output stages connect to a commoncoil. The coil is connected to back-to-back thick oxide switches. Figure 9B illustrates aninput of the class D stage by at least one numerically controlled oscillator (NCO) that outputs a digital rising sawtooth waveform that wrap around at a midpoint to form atriangle waveform, and phase and amplitude modulation is performed by adding phaseto the NCO and by multiplying the NCO output with the amplitude code word, for removing second order harmonics.Figure 10 shows a digital loopfilter used in the class D RF driver to provide supplyrejection and reconfigurability, where the loopfilter enables reducing the quantizationnoise in the qubit band while allowing it to pass outside the qubit band, where the different digital blocks are highlighted and the digital loopfilter allows either providing internal or external feedback. Figure 11 illustrates how to allow the class D and class DE driver to both drive thesame coil, where both output stages are connected to one side of the coil, while the other is connected to a back-to-back thick oxide NMOS switch, where the Class D outputstage with configuration on the left is connected to the low impedance coil and the back-to-back thick oxide NMOS switches illustrated on the right that allow a floating configuration for MW driving or a low impedance path to ground for RF driving. The drawings are not necessarily on scale. Description of preferred embodiments In order to explain the current circuit, four examples will be presented below: A -A DC current regulator B-A class DE voltage-mode driverC -A class D RF amplifier D -A coil sharing switch These four examples / building blocks can be combined, examples of which are illustrated. Two open challenges in the unit cells must be addressed. First, due to the hybridco-integration, it is physically difficult to place the coils generating the AC magneticfield close to the color centers, requiring the efficient generation of significant currentamplitudes (>10 mAp) for driving qubit operations. Second, while the Larmor frequencyof a 10 × 10 unit cell quantum processor can be set by a global permanent magnet, theinhomogeneity of the permanent magnet and integration inaccuracies can cause asignificant deviation in Larmor frequency f0 (>13 MHz), leading to infidelity whendriving qubit operations. In fact, the following is suggested. 1) introducing an AC controller with a class-DE switch-mode driver thatefficiently delivers large AC to a low-impedance coil via a series resonator and2) accurately correcting for deviations in Larmor frequency f0 using a DC currentregulator that locally tunes the static magnetic field by driving a DC coil close to thecolor center. With respect to the DC current regulator, in an embodiment it can be implementedusing transistors biased in triode. This enables driving large currents into a lowimpedance coil that can control the magnetic field with low power dissipation. By tuning the magnetic field, the Larmor frequency of the qubit can be tuned such that it can beefficiently driven by an AC controller, which drives the qubit gates by generating ACcontrol pulses with the Larmor frequency.With respect to the class DE voltage-mode driver, using this driver is the optimalway to drive a low impedance coil load with a large current at higher (>1GHz) frequencies. As a counterpart to the class-DE stage to drive a large AC current for lower (up to10 MHz) frequencies, the class D driver with lowered supply voltage is most suitable,as it is inherently linear and offers supply rejection. The lower frequencies are needed to drive operations on nuclear spins. In an embodiment, the coil sharing switch comprises a back-to-back NMOSswitch. This switch allows for dual use of the coil, in an optimal manner for both low-frequency operation with the class-D driver and high-frequency operation with the class- DE driver. The current circuits specifically provide an efficient operation and design freedom when used in so called “color-center quantum bits (qubits)”. Color-center quantum bits (qubits), such as the Nitrogen-Vacancy center (NV) in diamond, have demonstrated entanglement between remote (>1.3km) qubits and excellent coherence times, all while operating at a few Kelvins. Compared to other qubittechnologies typically operating at mK temperatures, in an embodiment the higheroperating temperature of NVs enables scalable 3D integration with cryo-CMOS control electronics, provides significantly more cooling power, and removes the interconnectbottleneck between the qubits and the electronics in prior art (cited above) J. Yoo et al.,D. J. Frank et al., J. S. Park, et al.. Yet, no cryo-CMOS controller for NV-based quantumcomputers (QC) has been demonstrated. In the drawing discussed, specific design values are included as an example. It should be evident that rather specific design parameters can be used in other designs. In a scalable NV-based QC (Fig.1), a chip hosting the NV qubits and the photoniccircuitry is 3D-integrated with a cryo-CMOS chip. In such a QC, a permanent magneticfield (B0) biases the qubits and roughly sets the qubits’ Larmor frequency (f0). In this scheme, optical signals with waveguides are used for initialization, readout, and entanglement, whereas the cryo-CMOS controller drives the AC coil, generating oscillating magnetic fields perpendicular to B0 for qubit control. Thanks to the NV’s remote-entanglement capabilities, the qubits can be conveniently organized in identical unit cells that are kept small to maximize scalability, thus requiring corresponding area- efficient cryo-CMOS. With a ~1 mm spacing between unit cells, the crosstalk ofneighbouring NV’s coils is negligible. Consequently, frequency spacing, i.e., FDMA, isnot required, allowing each unit cell to operate at the same f0, thereby reducing the total system complexity and power by sharing only a single frequency generator. However, two main challenges must be addressed to realize this QC architecture: (1) compared to other qubits, the coils that couple the microwave signals to the qubits are further away, requiring significantly larger currents (>10mApk) from the AC controller, and (2) the inhomogeneity of the permanent magnetic field causes variability in f0 (up to 20 MHz) among the unit cells, leading to inefficiency of the cryo-CMOS controller. This application addresses both challenges by(1) introducing a class-DE switching amplifier that delivers large currents to a low- impedance AC coil via a series resonator, and (2) compensating the inhomogeneity in f0 (with an accuracy <16kHz) using a DC current regulator that locally tunes the DC magnetic field by driving a DC coil. Since a large AC coil current enables fast qubit gates and the AC controller is veryclose to the qubits, 50-Ω matching and load driving that is currently proposed in the stateof the art can be omitted. To maximize the generated AC magnetic field, a seriesresonant tank is preferred over its parallel counterpart, see Fig.2A. The inductor currentis Q (the resonators’ quality factor) times higher for the same voltage across the drivingtransistor, which is limited by reliability. Therefore, a voltage-mode driver with a series resonant tank is chosen. Using a typical class-D as a voltage-mode driver in the AC controller was foundinefficient. It was found that parasitic capacitances of the large transistors need to becharged and discharged each cycle, and crowbar currents may occur due to simultaneous conduction of switches, see Fig.2B. A class-E topology would resolve the former problem by using the transistors’ shunt capacitance to achieve zero voltage switching (ZVS). A embodiment is illustrated at figure 2C. However, it requires a large choke inductor and its theoretical current efficiency, defined as the ratio of the coil current (Icoil,AC) to the driver DC supply current (Idriver,DC), is relatively low (~2.86). To improvethe power and current efficiency, a class-DE topology is proposed, see figure 2C. Thisis to drive the input of the amplifier with 25% duty-cycle pulses to avoid crowbarcurrents. Furthermore, it uses the parasitic capacitance of the transistors together withadded shunt capacitors CS1, 2 to achieve ZVS (see graphs right side of figure 2C).Compared to class-D amplifiers, the shunt capacitors provide the coil current for 50% of the time, thus doubling its theoretical current efficiency to 2π. To control the qubitX / Y-gates, a phase-demultiplexer indicated [2b] in figure 2C selects the quadratureclocks generated from an external clock (fclk). Furthermore, in an embodiment these are then converted to 25% pulses by a cascaded AND structure. In an embodiment, theduration of qubit-gates is controlled by a programmable counter indicated 12b in figure2C, and running at fclk / 2.To tune each qubit’s Larmor frequency f0, the DC current regulator in Figure 3Clocally adjusts the DC magnetic field by running a DC current (Icoil,DC up to 10mA) through a low–resistance coil (Rcoil,DC ~1Ω) close to the NV. As the generated field is directly proportional to the current, the power dissipation can only be reduced by lowering the supply voltage. Using transistors in saturation (Figure 3A) would make the circuit robust against supply and Rcoil,DC variations, but would require excessive headroom. Transistors in triode would allow for a lower VDSand hence require less power, but would suffer from worse supply rejection. As an alternative, this current work uses a triode H-bridge (illustrated in figure 3B) supplied with a low voltage (~50mV), which is combined with a current regulation loop to achieve both robustness and low power dissipation. The DC current regulator is illustrated in figure 3C. There, (as indicated in the drawing) the current IDAC is mirrored from M3 to M4a / b. Although M3 and M4a / b work in triode, the feedback loop consisting of Afband M5a / bensures an accurate current ratioIcoil,DC / IDAC=WM4a / b / WM3 by setting Vref=Vset. Transistors M3 and M4a / b are nominallysized for 1000x current gain, such that IDAC can be generated with low current levels (0-12μA) without degrading noise performance. Limiting the infidelity due to detuningplaces tight requirements on the frequency accuracy (Δf0<2kHz); hence, IDAC isgenerated with a coarse (IDACc) and fine (IDACf) DAC to achieve LSB=420pA, asrequired in the future for strong coil-to-qubit coupling. In this context, a coarse DAC isdefines as providing IADC steps of between 0.06-14µA, and a coarse DAC is definedas providing IADC steps of between 0.4-80nA. A larger mismatch at cryogenictemperatures (CT) was found. Missing codes , i.e. digital input that does not lead to ananalogue output, are prevented by range overlaps, which can be compensated during thestart-up qubit calibration. Switches M4a / b are optimized for power, area, and noise, sincea lower Ron contributes a lower voltage drop. It also increases the area and amplifiesAfb's input-referred voltage noise. Finally, M4a / band M5a / bset the polarity of Icoil,DC,thereby doubling the tuning range of f0 for the same Icoil,DC. In an embodiment to extendthe output-current range, the voltage range at the gate of M5a / b is maximized by adopting a 2-stage folded-cascode with a rail-to-rail common-source output stage for Afb. Chopper-stabilization avoids Afb's offset limiting the range of Icoil,DCand 1 / f noise affecting the qubit coherence. The resulting chopping ripple (250kHz) is reduced by trimming Afb's offset via a digitally selectable input pair, lowering the upmodulated offset, and by using a switched-capacitor notch filter (SC-filter) with a quadrature clock. All switches used for chopping and filtering are thick-oxide transistors, preventing improper mid-rail switching at CT due to increased Vth. To enable setting the H-bridge current independently in each unit cell, anadditional feedback loop is introduced that regulates the voltage drop across the H-bridge, as shown in Fig. 3E, and allows for an alternative current path Ishunt. Thefeedback loop drives a transistor M6 that shunts the residual current not used to drivethe coil. Hence, this transistor needs to have a sufficiently low ON-resistance, such thata maximum current of 12 mA can be shunted with a maximum drop equal to VH-bridgeto avoid an increase in power dissipation. The shunt transistor is driven by a differentialdifference amplifier, implemented as a folded-cascode amplifier consuming 3 µW witha gain bandwidth (GBW) of 200 kHz. The two input branches compare the voltage dropacross the H-bridge to a reference voltage and the gate of M6 is regulated to equalizethe two. At low frequencies, the current regulation loop determines the supply rejectionand the noise at lower frequencies. As a result, the voltage regulation does not requirehigh accuracy and only noise at higher frequencies could be introduced due to theregulator. It is expected that up to ten cells can be stacked with Vcell voltages between30 and 50 mV, which enables reducing interconnect dissipation significantly due to theI2 DC term. The amount of H-bridges that can be stacked is limited since for H-bridgesthat are close to the supply side, the fixed VDD of 1.1 V limits the overdrive voltage onthe transistors, increasing the resistances and power dissipation.Measurement results DC current regulator & Class DE MW amplifier Both MW AC controller (figure 2C) and DC current regulator (figure 3C) have been fabricated in a 40-nm CMOS process and characterized at room temperature (RT) and 4.2K (Figures 4A-4F). A magnetic-field probe located ~20-μm above an on-chip test coil (Ltest,AC=2.28nH) in a cryogenic probe station measures the AC controller’s performance. At 2.7GHz, the AC controller reaches a magnetic flux density of 2.17 (2.05)G, corresponding to an extrapolated current Icoil,ACof 30.7 (28.9)mAp, while Idriver,DC is 10.7 (13.4)mA from a 1.1V supply at 4.2K (RT). Over the 2.6-3.0GHz range, an signal-to-noise ratio SNR of >47 (>48)dB for a 5MHz bandwidth is achieved. The DC current regulator is characterized using a dipstick setup with liquid helium. Icoil,DCis measured on an external resistor Rcoil,DC=1Ω with VH-bridge=50mV and VDD=1.1V. The DC current regulator, including the H-bridge, dissipates 906 (812)μW with chopping enabled and can set currents up to 12.5 (10.5)mA at 4.2K (RT). The power spectraldensity (PSD) at 10Hz improves from 2400 (460)fA2 / Hz to 305 (25)fAs / Hz whenactivating chopping, while Icoil,DC has a DC power supply rejection ratio (PSRR) of -87.4(88.5)μA / V versus VH-bridgeand 297 (58)μA / V versus VDD. To demonstrate functionality, the cryo-CMOS chips have been integrated with a NV center qubit as illustrated in Figure 7. The ensemble is placed in a Montana cryostatwith optical access and cooled to <4.5K (see figure 8A). figure 8B shows the setup offigure 8A schematically. In figure 8C a side cross-section of the diamond details the integration of striplines with the NV centers, demonstrating the coils introducing both parallel and perpendicular magnetic fields at the qubit location. Permanent magnets bias the qubit at f0=2.66GHz. As illustrated in figure 7, two thin gold coils, LAC and LDC, are patterned on diamond: LAC (~2.4nH) is directly bonded to the AC controller, whereas LDC is bonded to a bias-T, which combines the signals from the DC current regulator and the RT electronics, used for comparison. Figure 5A shows a Rabi oscillation using both the RT setup and the AC controller, both yielding similar results. The Rabi frequency (fR) of the AC controller is plotted versus the driver’s DC supply current and shows that a maximum fR=2.5MHz can be achieved with Idriver,DC=6.5mA. In this case the entire AC controller consumes 16.8mW. The DC current regulator achieves a tuning range of + / -8MHz for f0 using currents up to 20mA with VH-bridge=100mV, increased to compensate for the larger Rcoil,DC due to the bias-T. Lastly, by using both chips, and keeping the driving frequency of the AC controller fixed, f0is calibrated for the maximum contrast of the Rabi oscillation by sweeping the DC-regulator’s digital input (DDC), highlighting the functionality of the proposed system. Compared to state-of-the-art cryo-CMOS controllers (Figure 6), the cryo-CMOS controller is the first targeting color centers, with the AC controller demonstrating a more effective way of generating high AC current levels with respect to prior cryo- CMOS controllers, and with no comparable work for the DC current regulator. Although3D integration might facilitate further power saving by reducing the parasitic losses andimproving the coil-to-qubit coupling, the reported experimental performance combined with the few-Watt cooling power readily available in 4K refrigerators enables the cryo- CMOS control of hundreds of unit cells, thus advancing scalable color-center-based quantum computers. Class D RF amplifier The DC current regulator and the AC controller with class DE amplifier can becombined, in particular to drive operations on the electron spin qubit of a vacancy center.For operations on nuclear spin qubits, lower Larmor frequencies are driven, which also have a lower Rabi frequency. Nevertheless, similarly large currents (>10mApk) are needed to have relatively high Rabi frequency. To create a resonator similar to the Class DE driver resonator would require very large inductance and capacitance values for Land C at RF frequencies (below 10 MHz), hence requiring a very large area. Similar tothe DC driver, the current needs to be continuously on the nuclear spins at RFfrequencies. Hence, a class D output stage is used that operates with a lower supply and has big switches (>1mm gate width) to reduce the power dissipated in the coil (Fig.9A). A digital loopfilter (Fig.10) is used in the class D stage to provide supply rejection and reconfigurability. The loopfilter enables reducing the quantization noise in the qubit band while allowing it to pass outside the qubit band. By adding a resonator in the loopfilter, a notch can be created and it can be moved by reprogramming the coefficients. An ADC senses the voltage at the output of the class D and feeds it back into the loopfilter to improve supply rejection. In this respect, a notch is a reversed spike,allowing dampening of distantion on selected frequencies. In other words, it allowsimproving the signal to noise ratio on selected frequencies. A numerically controlledoscillator (NCO) provides an input to the loopfilter, the resonator is inside the loopfilter.Coil Sharing Switch To allow the class D stage and class DE voltage-mode driver to both drive the same coil, both these output stages are connected to one side of the coil, while the other side of the coil is connected to a back-to-back thick oxide NMOS switch, as illustratedin figure 11). When the switch is open, it provides a capacitive connection to ground(for the class DE MW driving). When the switch is closed, it provides a low impedancepath to ground (for the class D RF driving). The switches need to be connected back to back such that it allows a large voltage swing without becoming conductive. The devicesshould be sized wide (>1mm gate width) to enable a sufficiently low resistive path toground, but not too much parasitic capacitance, yielding an optimum. It will also be clear that the above description and drawings are included to illustrate some embodiments of the invention, and not to limit the scope of protection. Starting from this disclosure, many more embodiments will be evident to a skilled person. These embodiments are within the scope of protection and the essence of this invention and are obvious combinations of prior art techniques and the disclosure of this patent.

Claims

Claims1. A driver circuit for driving a line having a circuit inductance and a circuitimpedance, the driver circuit adapted for generating, when operating at a cryogenic temperature, a current for generating a set magnetic field to control a quantumsystem, the circuit inductance and the circuit impedance selected to define aresonance frequency matching a control frequency of the quantum system foroptimizing an output power of the driver circuit.

2. The driver circuit of claim 1, wherein the circuit inductance and the circuitimpedance are selected to define the resonance frequency matching the controlfrequency of the quantum system and set to maximize the current with minimal power dissipation of the driver circuit.

3. The driver circuit of any one of the preceding claims, adapted for operating at aquantum system temperature, in particular said quantum system comprising qubits operating at a qubit working temperature, and said driver circuit adapted foroperating at said qubit working temperature.

4. The driver circuit of any one of the preceding claims, wherein the driver circuitcomprises a CMOS structure.

5. The driver circuit of any one of the preceding claims, comprising a DC currentregulator comprising at least two transistors biased in triode, in particular to enabledriving currents of between -12.5 mA and +12.5 mA, in particular the DC currentregulator based on CMOS.

6. The driver circuit of claim 5, wherein the DC current regulator comprisestransistors biased in triode, in particular a triode H-bridge with reduced supply to control the polarity of the current for driving positive and negative currents in thecoil.

7. The driver circuit of any one of the preceding claims, further comprising afeedback loop designed to operate with the nominal supply to regulate the current inside the H-bridge, allowing for improved supply rejection at low frequencies without dissipating significant amounts of power.

8. The driver circuit of claim 7, further comprising a high resolution current DAC,wherein the feedback loop mirrors and amplifies the current from the highresolution current DAC, enabling a high resolution control of the current in the H- bridge, while the high resolution DAC dissipates less power and can benefit from supply rejection as it operates in saturation.

9. The driver circuit of claim 8, wherein the high resolution DAC comprises twoDACs, a first one with a coarse structure, and a second one with a fine structure,i.e. fine with respect to the coarse structure, where the output range of the fine DAC structure is implemented to be larger than the LSB code output of the coarseDAC to ensure that no missing codes are present and an entire range can be covered with an LSB step of the fine DAC.

10. The driver circuit of any one of the preceding claims 7-9, wherein the feedbackloop comprising a trimming element to mitigate the influence of offset andmaximize the operating range of the loop, in particular comprising a chopper stabilizer designed to further reduce the offset and 1 / f noise and more in particularfurther comprising a switched capacitor notch filter that further reduces the ripple at the chopping frequency.

11. The driver circuit of any one of the preceding claims 7-10, further comprising ashunt path designed to set the voltage across the H-bridge, allowing stacking of thedriver circuit.

12. The driver circuit according to any one of the preceding claims, comprising a class-DE voltage-mode driver adapted to drive a low impedance series resonant tank, in particular adapted to drive the low impedance series resonant tank at highfrequencies higher than 1GHz.

13. The driver circuit according to claim 12, wherein the class DE voltage-mode drivercomprises a resonator as a tank in series adapted to achieve a Q (quality factor ofresonator)-times larger current swing.

14. The driver circuit according to any one of the preceding claims 12-13, wherein theclass-DE voltage-mode driver comprises NMOS and PMOS transistors in a finaloutput stage and is adapted for class-DE operation by applying 25% duty-cyclerail-to-rail input pulses to the gates of the NMOS and PMOS transistors of the final output stage, in particular the class-DE voltage-mode driver comprising a shuntand series capacitances designed with the coil inductance to achieve zero-voltage- switching (ZVS) operation.

15. The driver circuit according to claim 14, wherein the shunt capacitor is partiallyimplemented by the parasitic capacitance of the output stage transistors, while the rest of the capacitance can be implemented with additional metal capacitors.

16. The driver circuit according to any one of the preceding claims 13-15, wherein aseries capacitance of the resonator is provided before or after a coil that is driven,and is implemented as metal capacitor or the parasitic switch capacitance of the transistors implementing a coil sharing switch.

17. The driver circuit according to any one of the preceding claims 13-16, the class-DEvoltage-mode driver further comprising a multi-bit output stage, for driving a loadwith a varying output current amplitude.

18. The driver circuit according to any one of the preceding claims, comprising a classD stage for driving an AC current, in particular at low frequencies below 50 MHz,more in particular below 10 MHz, in particular a class D stage with lowered supplyvoltage, more in particular driving an AC current of >10mApk, more in particular driving at frequencies adapted to drive operations on nuclear spins.

19. The driver circuit of the previous claim, wherein the class D stage is a CMOS-based stage.

20. The driver circuit of the previous claim 18 or 19, wherein the class D stagecomprises a class D output stage adapted to operate with a low positive and negative supply set to only enable the transistors to operate in triode, In particular further comprising switches that are sized to reduce the on resistance below 1 Ω, and forward back biasing can be used to reduce the on resistance, in particular the class D output stage directly driving the low impedance coil and forms a first orderlow-pass filter with the low impedance coil.

21. The driver circuit of the previous claims 18-20, wherein the class D output stagecomprises a digital loopfilter for enabling low quantization noise in a preselectedfrequency band, i.e., where the Larmor frequencies of the nuclear spin qubits are located, in particular comprising a programmable resonator.

22. The driver circuit of the previous claim 21, wherein further comprising an analogto digital converter for sensing the coil voltage, in particular wherein the sensed coil voltage is fed back into the loopfilter to provide supply rejection with transistors operating in triode.

23. The driver circuit of the previous claims 21-22, wherein the class D stagecomprises an analog-to-digital converter (ADC), a loopfilter and an output stage,with a clock gating designed to freeze, allowing the circuit to resume operation andtrack the quantization error once the circuit restarts.

24. The driver circuit of the previous claims 18-23, wherein a input of the class D stageis provided by at least one numerically controlled oscillator (NCO) that outputs adigital rising sawtooth waveform that wrap around at a midpoint to form a trianglewaveform, wherein phase and amplitude modulation is performed by adding phaseto the NCO and by multiplying the NCO output with the amplitude code word, for removing second order harmonics.

25. The driver circuit according to any one of the preceding claims, further comprisinga back-to-back thick oxide NMOS switch, that allows for reverse current blocking, and providing a coil-sharing switch for coupling a first driver for operating a coil and a second driver for operating the coil, in particular wherein the first driver comprises a class DE voltage-mode driver according to any one of the preceding claims 12-17, and wherein the second driver comprises a class D stage according to any one of the preceding claims 18-24.

26. The driver circuit according to claim 25, the coil-sharing switch having an ON-state in which gates of at least one thick oxide NMOS device is tied to a supply, forproviding a low-impedance path to ground, optimal for the low-frequency operation, in particular the at least one thick oxide NMOS device provided for handling larger voltages than regular oxide NMOS, more in particular having agate width >1mm.

27. The driver circuit according to any one of the preceding claims 25-26, the coil-sharing switch having an OFF-state, in which the gates are tied to shared sources ofNMOS devices , for forcing the gate-source voltage to 0, and hence turning off theswitch, in particular re-using the parasitic capacitance of the drain to source as series capacitance for the resonator for the high-frequency operation.

28. The driver circuit according to any one of the preceding claims, wherein the atleast one back-to-back thick oxide NMOS device is sized sufficiently large tominimize on-resistance to optimize low-frequency operation, in particular not larger than the maximum parasitic capacitance of 3pF to reach the resonators’(tanks’) resonance frequency for the high-frequency operation.

29. A method for producing a driver current on a line of a quantum computing system,comprising selecting a driver resonance of a driver circuit to match the control frequency of the quantum system while minimizing the power dissipation of the driver.

30. A quantum computing device comprising a series of qubits operating at a qubittemperature and a driver circuit according to any one of the preceding claims for atleast one of driving and controlling the qubits, the driver circuit operating at the qubit temperature.

31. The quantum computing device of claim 30, wherein the qubits are color-centerquantum bits (qubits), such as the Nitrogen-Vacancy center (NV) in diamond. -o-o-o-o-o-

Images