Irregularly-shaped display panel and display apparatus

Abstract

An irregularly-shaped display panel (100). A display area (AA) of the irregularly-shaped display panel (100) comprises a first sub-boundary (S11), and the first sub-boundary (S11) extends along a non-straight line, or the first sub-boundary (S11) is not perpendicular to a boundary of the display area (AA) adjacent to the first sub-boundary. At a position corresponding to the first sub-boundary (S11) of the display area (AA), extension directions of a plurality of clock signal lines (31) are consistent with the extension direction of the first sub-boundary (S11); and each clock signal line (31) is connected to a shift register (20) by means of a corresponding adapter line (40). In the extension direction of the adapter line (40), the adapter line (40) comprises a first line segment (41) and a second line segment (42); the first line segment (41) and the second line segment (42) are connected to form a corner; the first line segment (41) is connected to a shift register (20), and the second line segment (42) is connected to a clock signal line (31); the orthographic projection of the second line segment (42) on a substrate overlaps the orthographic projection of a first part (311) of the clock signal line (31), which is connected to the second line segment (42), on the substrate; and the extension direction of the second line segment (42) is parallel to the line-width extension direction of the first part (311) of the clock signal line (31).

Description

Special-shaped display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a special-shaped display panel and display device. BACKGROUND

[0002] At present, liquid crystal display devices (English: Liquid Crystal Display, English: LCD) have been widely used in mobile phones, computers and other electronic products.

[0003] SUMMARY

[0004] In one aspect, a special-shaped display panel is provided. The special-shaped display panel has a display area and a peripheral area surrounding the display area. The display area includes a first sub-boundary, and at least two segments in the first sub-boundary have different extension directions, or the first sub-boundary is not perpendicular to a boundary of the display area adjacent to the first sub-boundary. The special-shaped display panel includes a substrate, a plurality of pixel units, at least one gate drive circuit, and a plurality of clock signal lines. The plurality of pixel units are located on one side of the substrate, and the plurality of pixel units are arranged in multiple rows and multiple columns in the display area. The pixel units include a plurality of sub-pixels. The at least one gate drive circuit is located in the peripheral area, and the gate drive circuit includes a plurality of shift registers connected in cascade. One shift register is connected to a plurality of sub-pixels arranged in a row. In a position corresponding to the first sub-boundary of the display area, the extension direction of the middle line connection of the plurality of shift registers is consistent with the extension direction of the first sub-boundary. The plurality of clock signal lines are located in the peripheral area and on a side of the gate drive circuit away from the display area. In a position corresponding to the first sub-boundary of the display area, the extension direction of the plurality of clock signal lines is consistent with the extension direction of the first sub-boundary. Each clock signal line is connected to the shift register through a corresponding adapter line. Along the extension direction of the adapter line, the adapter line includes a first line segment and a second line segment. The first line segment and the second line segment are connected to form a corner. The first line segment is connected to the shift register, and the second line segment is connected to the clock signal line. The orthogonal projection of the second line segment on the substrate overlaps the orthogonal projection of the first part of the clock signal line connected to the second line segment on the substrate. The extension direction of the second line segment is parallel to the line width extension direction of the first part of the clock signal line.

[0005] In some embodiments, the extension direction of a first edge of the shift register is parallel to the tangent line of the first sub-boundary or consistent with the extension direction of the first sub-boundary. The first edge is an inner edge of the shift register close to the first sub-boundary.

[0006] In some embodiments, the extension direction of the first edge of the shift register is perpendicular to the row direction.

[0007] In some embodiments, the line width of any two adjacent clock signal lines is equal, and among the plurality of clock signal lines, the clock signal line farthest from the display area is defined as a first target clock signal line, and the remaining clock signal lines are second target clock signal lines. The orthogonal projection of the second segment of each of the transfer lines on the substrate passes through all the second target clock signal lines and overlaps with the orthogonal projection of the first target clock signal line on the substrate.

[0008] In some embodiments, the peripheral area further comprises a frame area, at least one of the clock signal lines is located in the frame area, and each of the clock signal lines comprises a plurality of openings. The orthogonal projection of the transfer line on the substrate is equal to the area of the overlapping region formed by the orthogonal projection of the openings on at least two of the clock signal lines on the substrate.

[0009] In some embodiments, the display panel further comprises a gate metal layer and a source-drain metal layer, the gate metal layer is located between the substrate and the source-drain metal layer, and the plurality of clock signal lines are located in the gate metal layer. The plurality of transfer lines are located in the source-drain metal layer. The display panel further comprises a plurality of first connection portions, and the plurality of first connection portions are located on the side of the source-drain metal layer away from the gate metal layer. The first connection portion comprises a first connection sub-portion and a second connection sub-portion. The orthogonal projection of the first connection sub-portion of the first connection portion on the substrate overlaps with the orthogonal projection of the transfer line on the substrate, and the first connection sub-portion of the first connection portion is connected to the transfer line. The orthogonal projection of the second connection sub-portion of the first connection portion on the substrate overlaps with the clock signal line, and the second connection sub-portion of the first connection portion is connected to the clock signal line.

[0010] In some embodiments, the display panel further comprises a transparent electrode layer located on the side of the source-drain metal layer away from the gate metal layer. The sub-pixel comprises a pixel electrode located on the transparent electrode layer. The first connection portion is in the same layer as the pixel electrode.

[0011] In some embodiments, the display panel further comprises a plurality of data signal lines and a plurality of scan signal lines. The plurality of data signal lines are located in the display area, extend along the column direction, are arranged along the row direction, and are located in the source-drain metal layer. The plurality of scan signal lines are located in the display area, extend along the row direction, are arranged along the column direction, and are located in the gate metal layer. The gate metal layer is located between the substrate and the source-drain metal layer. The peripheral area is divided into two sub-peripheral areas and the display area is divided into two sub-display areas along a first reference line, which is an extension of the center connecting line of the plurality of scan signal lines. In the column direction, the sub-peripheral areas include a first frame area and a second frame area, and the display panel further comprises a binding area. In the column direction, the first frame area, the plurality of data signal lines, and the binding area are arranged in sequence. The first frame area includes a first area and a second area. The first area overlaps the gate drive circuit, and the second area does not overlap the gate drive circuit. Each of the two first short-circuit rings is located in one of the sub-peripheral areas. The first short-circuit ring comprises a first sub-section, a second sub-section, and a third sub-section. In one short-circuit ring: the second sub-section is located in the first frame area, and the second sub-section is located between the gate drive circuit and the display area. The second sub-section is connected to one end of all the data signal lines in the corresponding sub-display area away from the binding area. The third sub-section is located in the second area of the first frame area. The first sub-section is located on the side of the clock signal line away from the gate drive circuit, and the first sub-section extends from the binding area to the second area of the first frame area and is connected to the second sub-section through the third sub-section.

[0012] In some embodiments, the display panel further comprises a plurality of output signal lines, and one of the shift registers is connected to one of the scan signal lines through one of the output signal lines. The output signal line, the second sub-section, and the data signal line are in the same layer.

[0013] In some embodiments, the display panel further comprises a gate metal layer and a source-drain metal layer, the gate metal layer is between the substrate and the source-drain metal layer, a plurality of clock signal lines are on the gate metal layer, and a plurality of transfer lines are on the source-drain metal layer. The display panel further comprises a plurality of scan signal line extensions and a plurality of second connection portions. The plurality of scan signal line extensions are on the peripheral area, the plurality of scan signal line extensions are in the same layer as the scan signal lines, the scan signal line extensions are consistent with the extension direction of the scan signal lines, and in the row direction, one scan signal line extension is on one side of one scan signal line and connected to the scan signal line. The plurality of second connection portions are on the peripheral area, and the plurality of second connection portions are on the side of the source-drain metal layer away from the gate metal layer. The second connection portion comprises a third connection sub-portion and a fourth connection sub-portion, the third connection sub-portion of the second connection portion has an overlapping projection on the substrate with the output signal line, and the third connection sub-portion of the second connection portion is connected to the output signal line, and the fourth connection sub-portion of the second connection portion has an overlapping projection on the substrate with the scan signal line extension, and the fourth connection sub-portion of the second connection portion is connected to the scan signal line extension.

[0014] In some embodiments, the display panel further comprises a transparent electrode layer on the side of the source-drain metal layer away from the gate metal layer. The sub-pixel comprises a pixel electrode on the transparent electrode layer. The second connection portion is in the same layer as the pixel electrode.

[0015] In some embodiments, the display panel further comprises a plurality of switch units and two second short-circuit rings. The plurality of switch units are between the second sub-section and the display area, the first end of the switch unit is connected to the first short-circuit ring, the second end of the switch unit is connected to the data signal line, and the control end of the switch unit is connected to the second short-circuit ring. The second short-circuit ring comprises a fourth sub-section, a fifth sub-section, and a sixth sub-section. The fifth sub-section is in the first frame area, and the fifth sub-section is between the gate drive circuit and the second sub-section, and the control end of all the switch units in the same one of the peripheral areas is connected to the fifth sub-section. The sixth sub-section is in the second area of the first frame area. The fourth sub-section is between the first sub-section and the clock signal line, and the fourth sub-section extends from the binding area to the second area of the first frame area and is connected to the fifth sub-section through the sixth sub-section.

[0016] In some embodiments, the second shorting ring and the scan signal line are in the same layer, and a normal projection of the second connecting portion on the substrate is between normal projections of the first shorting ring and the second shorting ring on the substrate.

[0017] In some embodiments, the pixel unit includes three sub-pixels. In a plurality of rows of the pixel units corresponding to a first sub-boundary of the display area, in a direction along which the first frame area points to the second frame area, two adjacent rows of the pixel units are included, the two adjacent rows of the pixel units are an nth row of pixel units and an (n+1)th row of pixel units respectively, a number of the pixel units in the nth row of pixel units is less than a number of the pixel units in the (n+1)th row of pixel units. n is a positive integer. The (n+1)th row of pixel units includes at least one (n+1)th target pixel unit, in a column direction, the (n+1)th target pixel unit does not overlap with the nth row of pixel units, and the (n+1)th target pixel unit and the nth row of pixel units form an nth step area. A switch unit connected to a same data signal line as one of the sub-pixels in the (n+1)th target pixel unit is defined as an (n+1)th target switch unit, a plurality of the (n+1)th target switch units are located in the nth step area and are in the same row as the nth row of pixel units, and the plurality of (n+1)th target switch units are arranged in a row direction.

[0018] In some embodiments, the (n+1)th target switch unit is away from a side edge of the (n+1)th row of pixel units, overlaps with the nth row of pixel units in a row direction, and overlaps with the (n+1)th row of pixel units in a column direction.

[0019] In some embodiments, the pixel unit comprises three sub-pixels. In the multiple rows of pixel units corresponding to the first sub-boundary of the display area, in the direction along the first frame area pointing to the second frame area, three rows of pixel units are sequentially arranged, which are the nth row of pixel units, the (n+1)th row of pixel units and the (n+2)th row of pixel units. The number of pixel units in the nth row of pixel units, the (n+1)th row of pixel units and the (n+2)th row of pixel units gradually increases. The (n+2)th row of pixel units comprises at least one (n+2)th target pixel unit, which does not overlap with the (n+1)th row of pixel units in the column direction, and forms an (n+1)th step area with the (n+1)th row of pixel units. The (n+1)th row of pixel units comprises at least one (n+1)th target pixel unit, which does not overlap with the nth row of pixel units in the column direction, and forms an nth step area with the nth row of pixel units. A switching unit connected to the same data signal line as one of the sub-pixels in the (n+2)th target pixel unit is defined as an (n+2)th target switching unit, and the sub-pixels in multiple (n+2)th target switching units are arranged in two rows and multiple columns. The first row of (n+2)th target switching units is located in the (n+1)th step area and is in the same row as the (n+1)th row of pixel units, and the second row of (n+2)th target switching units is in the same row as the nth row of pixel units and is located on the side of the nth step area away from the nth row of pixel units.

[0020] In some embodiments, a switching unit connected to the same data signal line as one of the sub-pixels in the (n+1)th target pixel unit is defined as an (n+1)th target switching unit, and the sub-pixels in multiple (n+1)th target switching units are arranged in two rows and multiple columns. The first row of (n+1)th target switching units is located in the nth step area and is in the same row as the second row of (n+2)th target switching units and the nth row of pixel units.

[0021] In some embodiments, the ratio of the number of the first row of (n+2)th target switching units to the number of the second row of (n+2)th target switching units is 1:2.

[0022] In some embodiments, the display panel further comprises a third connecting portion and a fourth connecting portion. The third connecting portion is in the same layer as the second sub-section of the first short-circuit ring, one end of the third connecting portion is connected to the second sub-section of the first short-circuit ring in one of the sub-display areas, and the other end of the third connecting portion is connected to the second sub-section of the first short-circuit ring in another of the sub-display areas. The fourth connecting portion is in the same layer as the fifth sub-section of the second short-circuit ring, one end of the fourth connecting portion is connected to the fifth sub-section of the second short-circuit ring in one of the sub-display areas, and the other end of the fourth connecting portion is connected to the fifth sub-section of the second short-circuit ring in another of the sub-display areas.

[0023] In some embodiments, the third sub-section of the first short-circuit ring comprises a first part and a second part, the first part of the third sub-section is in the same layer as and connected to the first sub-section of the first short-circuit ring, and the second part of the third sub-section is in the same layer as and connected to the second sub-section of the first short-circuit ring. The second part of the third sub-section has an overlapping projection on the substrate with the fourth connecting portion.

[0024] In another aspect, a display device is provided. The display device comprises a cover plate and the display panel as in any of the above embodiments, the cover plate is located at the light-out side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present disclosure.

[0026] FIG. 1 is a cross-sectional view of a display device according to some embodiments;

[0027] FIG. 2 is a cross-sectional view of a display panel according to some embodiments;

[0028] FIG. 3 is a structural diagram of a display panel according to some embodiments;

[0029] FIG. 4 is a structural diagram of a display panel according to some other embodiments;

[0030] FIG. 5 is a structural diagram of a display panel according to yet some other embodiments;

[0031] FIG. 6 is a partial enlarged view of a target subspace of a shaped display panel according to some embodiments;

[0032] FIG. 7 is a partial enlarged view of C1 in FIG. 6;

[0033] FIG. 8 is a structural diagram of a display panel according to yet other embodiments;

[0034] FIG. 9 is a cross-sectional view of a shaped display panel according to some embodiments;

[0035] FIG. 10 is a structural diagram of a shaped display panel according to yet other embodiments;

[0036] FIG. 11 is a partial enlarged view of C2 in FIG. 10;

[0037] FIG. 12 is a layout view of C2 in FIG. 10;

[0038] FIG. 13 is an equivalent circuit diagram of FIG. 12;

[0039] FIG. 14 is a structural diagram of a shaped display panel according to yet other embodiments;

[0040] FIG. 15 is a partial enlarged layout view of C3 in FIG. 14;

[0041] FIG. 16 is a structural diagram of a shaped display panel according to yet other embodiments;

[0042] FIG. 17 is another layout view of C2 in FIG. 10;

[0043] FIG. 18 is an equivalent circuit diagram of FIG. 17;

[0044] FIG. 19 is yet another layout view of C2 in FIG. 10. DETAILED DESCRIPTION

[0045] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present disclosure.

[0046] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive in a manner consistent with the term's plain meaning, namely, "including but not limited to." In describing the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example" or "some examples," and the like, mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the disclosure, but that it can not be included in other embodiments or examples. The illustrative appearance of the foregoing terms in various places in the description are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0047] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and should not be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0048] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0049] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0050] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0051] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected," is, optionally, interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0052] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0053] Additionally, the use of "based on" means open and inclusive, as the process, step, calculation, or other action that is based on one or more recited conditions or values can in practice be based on additional conditions or values beyond those recited.

[0054] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the recited value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0055] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable deviation of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable deviation of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable deviation of, for example, less than or equal to 5% of either of the two quantities being compared.

[0056] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In this regard, the dimensions of the layers shown in the figures can be exaggerated relative to other layers to help improve understanding of embodiments. Accordingly, the exemplary embodiments should not be considered as limited to the particular shapes of regions illustrated herein, but include deviations in shapes that result from, for example, manufacturing. For example, an etched region illustrated as a rectangle will generally have rounded corners and / or irregular edges due to manufacturing techniques. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region that would be formed by a given manufacturing technique. The shapes should be understood to be schematic and not intended to limit the scope of exemplary embodiments.

[0058] FIG. 1 is a cross-sectional view of a display device according to some embodiments. As shown in FIG. 1, some embodiments of the present disclosure provide a display device 200 including a cover plate 210 and a display panel 100. The cover plate 210 is located on the light-out side of the display panel 100.

[0059] The cover plate 210 can be used for the display panel 100 to prevent the display panel 100 from being scratched and improve the service life of the display device 200.

[0060] In some examples, the material of the cover plate 210 includes at least one of inorganic glass, thermoplastic polyester, transparent polyimide, or organic glass. Among them, the inorganic glass can include ordinary glass that cannot be bent and ultra-thin glass (English full name: Ultra Thin Glass, abbreviation: UTG) that can be bent.

[0061] Embodiments of the present disclosure provide a display device 200, which can be a liquid crystal display device (LCD). The display device can also be an electroluminescent display device or a photoluminescent display device. In the case of an electroluminescent display device, the electroluminescent display device can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). In the case of a photoluminescent display device, the photoluminescent display device can be a quantum dot photoluminescent display device.

[0062] In the case of a liquid crystal display device, in some embodiments, the display panel 100 in the display device 200 is a liquid crystal display panel. The display device 200 can also include a backlight assembly located on the side of the liquid crystal display panel 100 away from the cover plate 210, and the backlight assembly is used to provide a light source for the liquid crystal display panel 100.

[0063] In some embodiments, the display panel 100 in the display device 200 can be an electrophoretic display panel or a photochromic display panel.

[0064] In some embodiments, the display panel 100 in the display device 200 can be an electrophoretic display panel or a photochromic display panel.

[0065] In some embodiments, the display panel 100 in the display device 200 can be an electrophoretic display panel or a photochromic display panel.

[0066] With the development of display panel technology, display panels with various shapes are also increasing. Based on this, the display panel 100 in the display device 200 described above can be a display panel 100 with a special shape.

[0067] FIG. 2 is a cross-sectional view of a display panel according to some embodiments.

[0068] In some embodiments, as shown in FIG. 2, the display panel 100 is a special-shaped liquid crystal display panel, and the main structure of the special-shaped liquid crystal display panel 100 includes an array substrate 110, a counter substrate 120, and a liquid crystal layer 130 disposed between the array substrate 110 and the counter substrate 120. In some examples, the counter substrate 120 can be a color filter (CF) substrate.

[0069] It can be understood that the light can be emitted through the backlight assembly and irradiate to the liquid crystal layer 130. By adjusting the arrangement of the liquid crystal molecules in the liquid crystal layer 130, the intensity of the light passing through the liquid crystal layer 130 can be adjusted, thereby adjusting the intensity of the light irradiating to the color film substrate 120. Since the color film substrate 120 is the color filter substrate, by adjusting the intensity of the light irradiating to the light blocking units of different colors, the special-shaped display panel 100 can realize the display function of color images.

[0070] In some examples, as shown in FIG. 2, the peripheral area SA further includes a frame area F, and the frame area F is arranged around the display area AA. The special-shaped display panel 100 can further include a frame sealant F1, and the frame sealant F1 is located in the frame area F and between the array substrate 110 and the color film substrate 120, and is arranged around the liquid crystal layer 130 to prevent the liquid crystal in the liquid crystal layer 130 from leaking and maintain the peripheral cell gap of the special-shaped display panel 100.

[0071] FIG. 3 is a structural diagram of a display panel according to some embodiments, and FIG. 4 is a structural diagram of a display panel according to other embodiments.

[0072] As shown in FIGS. 3 and 4, some embodiments of the present disclosure provide a special-shaped display panel 100, which includes a display area (English full name: Active Area, referred to as AA area for short; also referred to as effective display area) AA and a peripheral area SA around the display area AA.

[0073] In some examples, as shown in FIG. 3, the first boundary S1 of the display area AA includes a first sub-boundary S11 and a second sub-boundary S12, and the first sub-boundary S11 and the second sub-boundary S12 are adjacent and connected, and the first sub-boundary S11 is not perpendicular to the second sub-boundary S12. That is, the display area AA in the special-shaped display panel 100 includes at least two adjacent and non-perpendicular boundaries. Wherein, the side of the second sub-boundary S12 away from the first sub-boundary S11 can be perpendicular or non-perpendicular to the adjacent other boundary.

[0074] In other examples, as shown in FIG. 4, the first boundary S1 of the display area AA includes a first sub-boundary S11, and at least two segments in the first sub-boundary S11 extend in different directions. That is, the first sub-boundary S11 is not straight. For example, the first sub-boundary S11 can be an arc line, a broken line, a wavy line, etc.

[0075] In yet other examples, the first boundary S1 of the display area AA can be the first sub-boundary S11. At this time, the shape of the first boundary S1 of the display area AA can be a circle, an ellipse, etc.

[0076] Any of the above special-shaped display panels 100 can include a substrate 10 and a plurality of pixel units P located on the substrate 10.

[0077] In some examples, the substrate 10 can be a flexible substrate. For example, the material of the substrate 10 can be an organic material. For example, the material of the substrate 10 can be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0078] In other examples, the substrate 10 can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0079] The plurality of pixel units P are arranged in the display area AA, and the plurality of pixel units P are arranged in a plurality of rows and a plurality of columns. A row of pixel units P is defined as a pixel unit row, and a column of pixel units P is defined as a pixel unit column. Since the first sub-boundary S11 is present in the boundary of the display area AA of the special-shaped display panel 100, the shape of the display area AA is not a regular shape, and thus the number of pixel units P in at least two pixel unit rows arranged in the display area AA is different, and the number of pixel units P in at least two pixel unit columns is different.

[0080] It should be noted that the first boundary S1 of the display area AA can coincide with the second boundary S2 of the peripheral area SA on the side close to the display area AA. That is, the first boundary S1 of the display area AA or the second boundary S2 of the peripheral area SA can be understood as the boundary line between the display area AA and the peripheral area SA. The third boundary S3 of the peripheral area SA on the side away from the display area AA can be arranged opposite to the second boundary S2 of the peripheral area SA or the first boundary S1 of the display area AA. That is, the trend of the third boundary S3 of the peripheral area SA can be consistent with the trend of the second boundary S2 of the peripheral area SA or the trend of the first boundary of the display area AA.

[0081] The third boundary S3 of the peripheral area SA includes a third sub-boundary S31, the third sub-boundary S31 of the peripheral area SA is arranged opposite to the first sub-boundary S11 of the display area AA, and the space between the third sub-boundary S31 of the peripheral area SA and the first sub-boundary S11 of the display area AA is the target sub-space SA0 of the peripheral area.

[0082] In some examples, as shown in FIG. 4, one pixel unit P includes a plurality of sub-pixels P0. Light emitted by the plurality of sub-pixels P0 can be used by the special-shaped display panel 100 to display a predetermined image in the display area AA. Specifically, the plurality of sub-pixels P0 can include a plurality of sub-pixels that emit light of different colors. For example, the plurality of sub-pixels P0 can include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can emit light of three primary colors, respectively. For example, the first sub-pixel P1 can emit red light, the second sub-pixel P2 can emit green light, and the third sub-pixel P3 can emit blue light.

[0083] In some other examples, the special-shaped display panel 100 can further include a white sub-pixel.

[0084] In some examples, as shown in FIG. 4, the plurality of sub-pixels P0 in each pixel unit P are arranged in a plurality of rows and a plurality of columns in the display area AA. One row of the plurality of sub-pixels P0 arranged in a row is defined as a sub-pixel row, and one column of the plurality of sub-pixels P0 arranged in a column is defined as a sub-pixel column.

[0085] FIG. 5 is a structural diagram of a display panel according to yet some examples. In FIG. 5, the first sub-boundary S11 is taken as an example and is not straight.

[0086] In some examples, as shown in FIGS. 4 and 5, the special-shaped display panel 100 can further include a plurality of scan signal lines G1 and a plurality of data signal lines Data. The plurality of data signal lines Data and the plurality of scan signal lines G1 can be arranged in a cross manner to define the plurality of sub-pixels P0. One data signal line Data can be connected to one sub-pixel column, and one scan signal line G1 can be connected to one sub-pixel row.

[0087] The special-shaped display panel 100 can further include at least one gate drive circuit G located in the peripheral area SA. The gate drive circuit G is configured to output a scan signal to the pixel drive circuit in the plurality of sub-pixels P. Since the gate drive circuit G is arranged on the special-shaped display panel 100, the gate drive circuit G can also be referred to as a GOA (Gate Driver on Array, gate drive circuit arranged on an array substrate).

[0088] In some examples, as shown in FIG. 4, one pixel unit P includes a plurality of sub-pixels P0. Light emitted by the plurality of sub-pixels P0 can be used by the special-shaped display panel 100 to display a predetermined image in the display area AA. Specifically, the plurality of sub-pixels P0 can include a plurality of sub-pixels that emit light of different colors. For example, the plurality of sub-pixels P0 can include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can emit light of three primary colors, respectively. For example, the first sub-pixel P1 can emit red light, the second sub-pixel P2 can emit green light, and the third sub-pixel P3 can emit blue light.

[0089] In some examples, the gate driving circuit G includes a plurality of transistors. In some embodiments, the structure of the gate driving circuit G in the present disclosure includes multiple types, which can be selected and arranged according to actual needs. For example, the structure of the gate driving circuit G can include "3T1C", "8T2C", or "12T1C", etc. Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C.

[0090] In the column direction Y (the direction in which the data signal line Data extends), the peripheral area SA includes a first bezel area SA1 (upper bezel) and a second bezel area SA2 (lower bezel). In the row direction X (the direction in which the scan signal line G1 extends), the peripheral area SA includes a third bezel area SA3 (left bezel) and a fourth bezel area SA4 (right bezel).

[0091] In some examples, the special-shaped display panel 100 includes one gate driving circuit G, which is located in the third bezel area SA3 or the fourth bezel area SA4 of the peripheral area SA.

[0092] In other examples, the special-shaped display panel 100 includes two gate driving circuits G, one of which is located in the third bezel area SA3 of the peripheral area SA, and the other is located in the second bezel area SA2 of the peripheral area SA.

[0093] The special-shaped display panel 100 further includes a plurality of input signal lines 30 for providing driving signals to the gate driving circuit G. Among them, the input signal line 30 can include a plurality of clock signal lines 31, and the input signal line 30 can also include other signal lines. The types of other signal lines will be described in detail below.

[0094] Among them, the plurality of input signal lines 30 can be located in the peripheral area SA, and the plurality of input signal lines 30 are located on the side of the gate driving circuit G away from the display area AA. Specifically, the plurality of clock signal lines 31 can be located on the side of the other signal lines away from the display area AA. Specifically, the plurality of input signal lines 30 and the gate driving circuit G connected thereto are located in the same bezel area, the extension direction of the plurality of input signal lines 30 is consistent with the extension direction of the bezel area, and the plurality of input signal lines 30 are arranged in the direction of the bezel area pointing to the display area AA.

[0095] That is, the plurality of clock signal lines 31 and the gate driving circuit G connected thereto are located in the same bezel area, the extension direction of the plurality of clock signal lines 31 is consistent with the extension direction of the bezel area, and the plurality of clock signal lines 31 are arranged in the direction of the bezel area pointing to the display area AA.

[0096] The special-shaped display panel 100 can further include a plurality of transfer lines 40, one transfer line 40 being used to connect one clock signal line 31 and its corresponding shift register 20.

[0097] In some implementable manners, the transfer lines 40 extend along the row direction X to connect the clock signal lines 31 and the corresponding shift registers 20. However, due to the existence of the first boundary S1 of the display area AA, an overlapping problem can occur in part of the frame area in the peripheral area SA. For example, the first boundary S1 of the display area AA1 is the boundary of the first frame area SA1 close to the display area AA. That is, the first frame area SA1 includes the target sub-space SA0. As a result, the first frame area SA1 extends into the third frame area SA3 and the fourth frame area SA4. Therefore, the first frame area SA1 can have an overlapping area with the third frame area SA3 and / or an overlapping area with the fourth frame area SA4. Thus, the shift registers 20 located in the third frame area SA3 or the fourth frame area SA4 can be located in the target sub-space SA0. Therefore, the clock signal lines 31 also need to extend into the target sub-space SA0 to connect the clock signal lines 31 and the shift registers 20.

[0098] In the position (target sub-space SA0) corresponding to the first sub-boundary S11 of the display area AA, the extension direction of the middle line U of the plurality of shift registers 20 is consistent with the extension direction of the first sub-boundary S11, and the extension direction of the plurality of clock signal lines 31 is consistent with the extension direction of the first sub-boundary S11, so as to connect the clock signal lines 31 and the shift registers 20, without the need to design the fan-shaped layout for the transfer lines 40, which is beneficial to reduce the space occupation of the transfer lines 40 in the peripheral area SA and to realize a narrow frame.

[0099] However, as set forth above, the orthogonal projection of the transfer line 40 extending along the row direction X on the substrate 10 intersects the orthogonal projection of the clock signal line 31 connected thereto on the substrate 10, and the included angle formed by the intersection is an obtuse angle. On the one hand, due to the large area of the overlapping region formed by the orthogonal projection of the transfer line 40 on the substrate 10 and the orthogonal projection of the clock signal line 31 connected thereto on the substrate 10, an overlapping capacitance is formed between the two, which increases the load of the clock signal line 31. In addition, when the first sub-boundary S11 does not extend linearly, the orthogonal projections of at least two transfer lines 40 on the substrate 10 intersect the orthogonal projections of the clock signal lines 31 connected thereto on the substrate 10 to form included angles of different sizes. Thus, the areas of the overlapping regions formed between different transfer lines 40 and the clock signal lines 31 connected thereto are different, and the overlapping capacitances formed between the two are also different, which causes the loads of at least two clock signal lines 31 to be different, affecting the display effect of the special-shaped display panel 100.

[0100] It should be noted that the orthographic projection of one shift register 20 on the substrate 10 can be a rectangle. That is, the orthographic projection of all the transistors in one register 20 on the substrate 10 can combine to form a rectangle. The center line of the plurality of shift registers 20 can be understood as the line connecting the center points of the plurality of rectangles corresponding to the plurality of shift registers 20. The extension direction of the center line of the shift register 20 is consistent with the extension direction of the first sub-boundary S11. That is, at the position (target sub-space SA0) corresponding to the first sub-boundary S11 of the display area AA, the plurality of shift registers 20 are arranged along the extension direction of the first sub-boundary S11.

[0101] FIG. 6 is a partial enlarged view of a target sub-space of a shaped display panel according to some embodiments, and FIG. 7 is a partial enlarged view of C1 in FIG. 6.

[0102] Based on this, in some embodiments, in combination with FIGS. 5-7, along the extension direction of the jumper wire 40, the jumper wire 40 includes a first segment 41 and a second segment 42, the first segment 41 and the second segment 42 are connected to form a corner J, the first segment 41 is connected to the shift register 20, and the second segment 42 is connected to the clock signal line 31. The orthographic projection of the second segment 42 on the substrate 10 overlaps the orthographic projection of the first part 311 of the clock signal line 31 connected thereto on the substrate 10, and the extension direction of the second segment 42 is parallel to the line width extension direction of the first part 311 of the clock signal line 31.

[0103] That is, by dividing each jumper wire 40 into two parts, the extension direction of the second segment 42 of each jumper wire 40 connected to the clock signal line 31 can be adjusted so that the orthographic projection of the second segment 42 of each jumper wire 40 on the substrate 10 is substantially perpendicular to the orthographic projection of the first part 311 of the clock signal line 31 connected thereto on the substrate 10.

[0104] In other words, the shape of the overlapping area formed by the orthographic projection of the second segment 42 of each jumper wire 40 on the substrate 10 and the orthographic projection of the first part 311 of the clock signal line 31 connected thereto on the substrate 10 can be approximately a rectangle, and the area of this rectangle can be approximately the product of the line width of the second segment 42 of the jumper wire 40 and the line width of the clock signal line 31. Therefore, not only can the area of the overlapping area formed by the orthographic projection of the jumper wire 40 on the substrate 10 and the orthographic projection of the clock signal line 31 connected thereto on the substrate 10 be small, but also the overlapping capacitance formed therebetween can be small, thereby reducing the load of the clock signal line 31; in addition, the area of the overlapping area formed between different jumper wires 40 and the clock signal line 31 connected thereto can be approximately equal, so that the load of each jumper wire 40 is approximately the same and the load of each clock signal line 31 is approximately the same, which is conducive to improving the display effect of the shaped display panel 100.

[0105] In some embodiments, the plurality of input signal lines 30 can include other lines in addition to the clock signal line 31, for example, a first power signal line VDD1, a second power signal line VDD2, a start trigger signal line STV, a first gate control signal line Vgl, and a second gate control signal line Lvgl. The voltage of the signal transmitted by the second gate control signal line Lvgl is less than or equal to the voltage of the signal transmitted by the first gate control signal line Vgl.

[0106] The other lines in the plurality of input signal lines 30 in addition to the clock signal line 31 can be located between the clock signal line 31 and the gate drive circuit G. That is, the first power signal line VDD1 (not shown in the figure), the second power signal line VDD2, the start trigger signal line STV (not shown in the figure), the first gate control signal line Vgl (not shown in the figure), and the second gate control signal line Lvgl (not shown in the figure) are all located between the clock signal line 31 and the gate drive circuit G.

[0107] Specifically, in the direction along the clock signal line 31 pointing to the gate drive circuit G, the first power signal line VDD1, the second power signal line VDD2, the second gate control signal line Lvgl, the start trigger signal line STV, and the first gate control signal line Vgl are arranged in sequence.

[0108] In addition, the first power signal line VDD1, the second power signal line VDD2, the start trigger signal line STV, the first gate control signal line Vgl, and the second gate control signal line Lvgl have the same trend as the clock signal line 31, so as to improve the regularity of the wiring in the peripheral area SA and facilitate the full use of the space in the peripheral area SA.

[0109] In the case where the first power signal line VDD1, the second power signal line VDD2, the start trigger signal line STV, the first gate control signal line Vgl, and the second gate control signal line Lvgl have the same trend as the clock signal line 31, the second segment 42 of each transition line 40 can have a rectangular shape in the intersection area formed by the intersection of the orthogonal projection of the first power signal line VDD1, the second power signal line VDD2, the start trigger signal line STV, the first gate control signal line Vgl, and the second gate control signal line Lvgl on the substrate 10 and the orthogonal projection of the second segment 42 of the transition line 40 on the substrate 10. Therefore, the parasitic capacitance between the transition line 40 and any one of the first power signal line VDD1, the second power signal line VDD2, the start trigger signal line STV, the first gate control signal line Vgl, and the second gate control signal line Lvgl can be reduced, which is beneficial to reducing the load.

[0110] In some embodiments, as shown in FIGS. 5-7, along the row direction X, each shift register 20 in the gate drive circuit G at least partially overlaps with one sub-pixel row connected thereto.

[0111] Based on this, the length of the gate drive circuit G in the column direction Y is approximately equal to the length of the sub-pixel column with the largest number of sub-pixels P0. Furthermore, when the shift register is connected to the scan signal line G1, there is no need to fan out the wiring for connection, which is beneficial to reduce the space occupied by such wiring in the peripheral area SA and facilitate the realization of a narrow frame.

[0112] In some embodiments, as shown in FIGS. 5-7, along the row direction X, each shift register 20 in the gate drive circuit G at least partially overlaps with one sub-pixel row connected thereto.

[0113] The first type is that, along the row direction X, the shift register 20 partially overlaps with the sub-pixel row connected thereto.

[0114] The second type is that, along the row direction X, the shift register 20 completely overlaps with the sub-pixel row connected thereto. That is, at this time, along the Y direction, the width of the shift register 20 is approximately equal to the width of the sub-pixel row.

[0115] In this way, the multiple shift registers 20 are arranged corresponding to the sub-pixel rows connected thereto, so as to facilitate the connection of the shift register 20 to the scan signal line G1 connected by the sub-pixel row, and facilitate the realization of a narrow frame.

[0116] In some examples, as shown in FIGS. 5-7, the first line segment 41 of each transition line 40 can be approximately perpendicular to the extension direction of the first edge 21 of the shift register 20, which is the inner edge of the shift register 20 close to the first sub-boundary. Based on this, the first line segment 41 of each transition line 40 can be connected to the transistor in the shift register 20 to which it needs to be connected, so as to improve the problem of winding of the first line segment 41.

[0117] In some embodiments, as shown in FIGS. 5-7, along the row direction X, each shift register 20 in the gate drive circuit G at least partially overlaps with one sub-pixel row connected thereto.

[0118] The first type is that, as shown in FIG. 7, the extension direction of the first line segment 41 intersects the extension direction of the second line segment 42, and the included angle (corner J) formed by the intersection of the two can be an obtuse angle.

[0119] The second type is that, in the same transition line 40, the first line segment 41 and the second line segment 42 can be connected by an arc line.

[0120] No matter which relative position relationship between the first line segment 41 and the second line segment 42, the structure of the transition line 40 can be changed to achieve that the extending direction of the second line segment 42 of the transition line 40 is parallel to the extending direction of the line width of the first part 311 of the clock signal line 31, and the first line segment 41 of the transition line 40 is substantially perpendicular to the extending direction of the first edge 21 of the shift register 20.

[0121] Based on this, the overlapping capacitance formed between the transition line 40 and the clock signal line 31 can be reduced, and the load of the two can be reduced at the same time, and the first line segment 41 of the transition line 40 can be connected to the transistor in the shift register 20 which needs to be connected.

[0122] In addition, the first line segment 41 and the second line segment 42 in the transition line 40 are consistent in other data parameters except that the extending directions are different, for example, the line widths of the first line segment 41 and the second line segment 42 are consistent, and the line thicknesses of the first line segment 41 and the second line segment 42 are consistent. In this way, the difference between the two can be reduced to reduce the difference at different positions in the same transition line 40, which is conducive to improving the display effect of the special-shaped display panel 100.

[0123] It should be noted that the orthographic projection of one shift register 20 on the substrate 10 can be a rectangle. That is, the orthographic projection of all transistors in one register 20 on the substrate 10 can be combined into a rectangle. The first edge 21 of the shift register 20 can be understood as the edge of the rectangle corresponding to the shift register 20 close to the display area AA. Alternatively, the first edge 21 of the shift register 20 can be understood as the connecting line of the side edge of the plurality of transistors in the shift register 20 adjacent to the display area AA close to the display area AA. Wherein, the "first edge 21 of the shift register 20" involved in the text is the same as the above explanation.

[0124] FIG. 8 is a structural diagram of a display panel according to still some embodiments. In FIG. 8, the first sub-boundary S11 is taken as an example to be non-linearly extended.

[0125] In some embodiments, as shown in FIGS. 4 and 8, any two adjacent shift registers 20 are rotationally arranged relative to each other, the extending direction of the first edge 21 of the shift register 20 is parallel to the tangent line of the first sub-boundary S11 or consistent with the extending direction of the first sub-boundary S11, and the first edge 21 is the inner edge of the shift register 20 close to the first sub-boundary.

[0126] In this way, the position of each shift register 20 located in the target subspace SA0 is adjusted, so that the first edge 21 of the shift register 20 is arranged opposite to the corresponding first sub-boundary S11 of the display area AA. That is, the gap between the first edge 21 of the shift register 20 and the first sub-boundary S11 of the display area AA is approximately equal in width at any two positions.

[0127] Therefore, the plurality of shift registers 20 arranged in the target subspace SA0 are arranged in a rotating manner around the first sub-boundary S11 of the display area AA, so as to reduce the occupation of the peripheral area SA space by the gate drive circuit G, and facilitate the realization of a narrow frame.

[0128] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), when the difference in gap width between any two positions in the gap between the first edge 21 of the shift register 20 and the first sub-boundary S11 of the display area AA is within 10% of any gap, it can also be considered that the gap width between any two positions in the gap between the first edge 21 of the shift register 20 and the first sub-boundary S11 of the display area AA is equal.

[0129] In some embodiments, as shown in FIGS. 5-7, any two adjacent shift registers 20 are arranged in parallel, and the extension direction of the first edge 21 of the shift register 20 is perpendicular to the row direction X.

[0130] In this way, the position of each shift register 20 located in the target subspace SA0 is adjusted, and the extension direction of the first edge 21 of the shift register 20 is perpendicular to the row direction X, so that each shift register 20 is arranged approximately in parallel. That is, the plurality of shift registers 20 arranged in the target subspace SA0 are arranged in a stepped manner. Based on this, the arrangement direction of the plurality of transistors in the shift register 20 can be made consistent, which is beneficial to improving the uniformity of the channel etching process of the transistors.

[0131] It should be noted that the extension direction of the first edge 21 of the shift register 20 is arranged approximately perpendicular to the row direction X, and at this time, the included angle between the extension direction of the first edge 21 of the shift register 20 and the row direction X is approximately equal to 90°. For example, the included angle between the extension direction of the first edge 21 of the shift register 20 and the row direction X can be 85°, 90°, or 95°.

[0132] In some embodiments, as shown in FIGS. 5-7, in the plurality of clock signal lines 31: the clock signal line 31 farthest from the display area AA is defined as the first target clock signal line 31A, and the remaining clock signal lines 31 are the second target clock signal lines 31B. The orthogonal projection of the second segment 42 of each switching line 40 on the substrate 10 passes through all the second target clock signal lines 31B, and overlaps with the orthogonal projection of the first target clock signal line 31A on the substrate 10.

[0133] In this way, the orthogonal projection of any one switching line 40 on the substrate 10 overlaps with the orthogonal projection of all the clock signal lines 31 (one first target clock signal line 31A and all the second target clock signal lines 31B) on the substrate 10. Therefore, the orthogonal projection of each switching line 40 on the substrate 10 overlaps with the orthogonal projection of the same number of clock signal lines 31 on the substrate 10. Further, the overlapping capacitance formed between each switching line 40 and all the clock signal lines 31 is approximately equal, which indirectly also makes the overlapping capacitance formed between each clock signal line 31 and all the switching lines 40 approximately equal.

[0134] Based on this, the load of each switching line 40 is approximately the same, and the load of each clock signal line 31 is approximately the same, which is beneficial to improve the display effect of the special-shaped display panel 100.

[0135] In some examples, the special-shaped display panel 100 can include 8 clock signal lines 31. In the direction from the display area AA to the peripheral area SA, the 8 clock signal lines 31 are respectively the first clock signal line 311, the second clock signal line 312, the third clock signal line 313, the fourth clock signal line 314, the fifth clock signal line 315, the sixth clock signal line 316, the seventh clock signal line 317, and the eighth clock signal line 318. At this time, the eighth clock signal line 318 is the first target clock signal line 31A, and the first clock signal line 311, the second clock signal line 312, the third clock signal line 313, the fourth clock signal line 314, the fifth clock signal line 315, the sixth clock signal line 316, and the seventh clock signal line 317 belong to the second target clock signal line 31B.

[0136] Among them, the number of clock signal lines 31 can be set according to the needs of actual application scenarios, for example, the number of clock signal lines 31 can be 4, 6, or 8, etc. The embodiments of the present disclosure are not limited thereto.

[0137] The orthogonal projection of the connection line 40 connected with the first clock signal line 311 (the second target clock signal line 31B) closest to the display area AA on the substrate 10 passes through the remaining second target clock signal lines 31B (the second clock signal line 312, the third clock signal line 313, the fourth clock signal line 314, the fifth clock signal line 315, the sixth clock signal line 316, and the seventh clock signal line 317), and overlaps with the orthogonal projection of the eighth clock signal line 318 (the first target clock signal line 31A) on the substrate 10.

[0138] That is, the orthogonal projection of the connection line 40 on the substrate 10 overlaps with the orthogonal projections of the first clock signal line 311, the second clock signal line 312, the third clock signal line 313, the fourth clock signal line 314, the fifth clock signal line 315, the sixth clock signal line 316, the seventh clock signal line 317, and the eighth clock signal line 318 on the substrate 10. The same applies to other connection lines 40. In this way, the overlapping capacitances between each connection line 40 and all the clock signal lines 31 are approximately equal, and the overlapping capacitances between each clock signal line 31 and all the connection lines 40 are also approximately equal.

[0139] Based on this, the loads of each connection line 40 and the loads of each clock signal line 31 are approximately equal, which is conducive to improving the display effect of the special-shaped display panel 100.

[0140] In addition, the line widths of any two adjacent clock signal lines 31 can be approximately equal, and the gap widths at any two positions in the gap between any two adjacent clock signal lines 31 can be approximately equal. That is, the plurality of clock signal lines 31 can be arranged in equal widths and equal distances. In this way, the differences between the clock signal lines 31 can be reduced, which is conducive to improving the display effect of the special-shaped display panel 100.

[0141] Since the orthogonal projection of the second line segment 42 of each connection line 40 on the substrate 10 is approximately perpendicular to the first part 311 of the clock signal line 31 connected thereto. In the case of the above layout of the plurality of clock signal lines 31, the orthogonal projection of the second line segment 42 of any connection line 40 on the substrate 10 can be approximately perpendicular to the first part 311 of all the clock signal lines 31 (one first target clock signal line 31A and all the second target clock signal lines 31B).

[0142] Based on this, the shape of the overlapping area formed by the second line segment 42 of each transfer line 40 in the orthographic projection on the substrate 10 and the first part 311 of all clock signal lines 31 in the orthographic projection on the substrate 10 can be a rectangle, and the area of the rectangle is approximately the product of the line width of the second line segment 42 of the transfer line 40 and the line width of the clock signal line 31. Therefore, not only can the overlapping area formed by the orthographic projection of the transfer line 40 on the substrate 10 and the orthographic projection of all clock signal lines 31 on the substrate 10 be small, and the overlapping capacitance formed between them can be small, thereby reducing the load of all clock signal lines 31, but also the areas of the overlapping areas formed between different transfer lines 40 and all clock signal lines 31 are approximately equal, so that the load of each transfer line 40 is approximately the same, and the load of each clock signal line 31 is approximately the same, which is beneficial to improve the display effect of the special-shaped display panel 100.

[0143] In some embodiments, as shown in FIG. 7, the second line segment 42 of each transfer line 40 is approximately coincident with the orthographic projection on the substrate 10 of the edge of the second target clock signal line 31B away from the first target clock signal line 31A.

[0144] In this way, any one of the transfer lines 40 can extend to approximately coincide with the side of the first target clock signal line 31A away from the second target clock signal line 31B, and thus the orthographic projection on the substrate 10 of each transfer line 40 can form an overlapping area with the orthographic projection on the substrate 10 of the first target clock signal line 31A, and the shape of the overlapping area is approximately a rectangle, and the area of the rectangle is approximately the product of the line width of the second line segment 42 of the transfer line 40 and the line width of the first target clock signal line 31A.

[0145] Based on this, the orthographic projection on the substrate 10 of each transfer line 40 can extend to the position of the orthographic projection on the substrate 10 of the side of the first target clock signal line 31A away from the second target clock signal line 31B. Thus, the orthographic projection on the substrate 10 of each transfer line 40 can form an overlapping area with the orthographic projection on the substrate 10 of the first target clock signal line 31A, and the area of the overlapping area is approximately equal, so that the load of each transfer line 40 is approximately the same, and the load of each clock signal line 31 is approximately the same, which is beneficial to improve the display effect of the special-shaped display panel 100.

[0146] In some embodiments, as shown in FIG. 7, in the case that the orthogonal projection of the second line segment 42 of each transition line 40 on the substrate 10 has an overlap with the orthogonal projection of the first target clock signal line 31A on the substrate 10, the orthogonal projection of the edge of the second line segment 42 of each transition line 40 away from the first line segment 41 on the substrate 10 can be located outside the boundary of the orthogonal projection of the first target clock signal line 31A on the substrate 10.

[0147] In this way, each transition line 40 can pass through the first target clock signal line 31A, so that the area of the overlap region formed by the orthogonal projection of each transition line 40 on the substrate 10 and the orthogonal projection of the first target clock signal line 31A on the substrate 10 is approximately equal, so that the load of each transition line 40 is approximately equal, and the load of each clock signal line 31 is approximately equal, which is conducive to improving the display effect of the special-shaped display panel 100.

[0148] In some examples, the first interval between the orthogonal projection of the edge of the second line segment 42 of each transition line 40 away from the first line segment 41 on the substrate 10 and the orthogonal projection of the edge of the first target clock signal line 31 away from the second target clock signal line 31B on the substrate 10 is in the range of 1 μm to 3 μm.

[0149] When the first interval is in the range of 1 μm to 3 μm, it can not only ensure that each transition line 40 can pass through the first target clock signal line 31, so that the area of the overlap region formed by the orthogonal projection of each transition line 40 on the substrate 10 and the orthogonal projection of the first target clock signal line 31A on the substrate 10 is approximately equal, so that the load of each transition line 40 is approximately equal, and the load of each clock signal line 31 is approximately equal, but also can reduce the size of the transition line 40 protruding from the first target clock signal line 31, so as to reduce the length of the transition line 40, reduce the resistance of the transition line 40, and also reduce the occupation of the size of the peripheral area SA by the transition line 40, which is conducive to the layout of other devices and lines in the peripheral area SA.

[0150] In other examples, the first interval is in the range of 1 μm to 2 μm.

[0151] When the first interval is in the range of 1 μm to 2 μm, it can not only ensure that each transition line 40 can pass through the first target clock signal line 31, so that the load of each transition line 40 is approximately equal, and the load of each clock signal line 31 is approximately equal, but also can better reduce the length of the transition line 40, reduce the resistance of the transition line 40, and reduce the occupation of the size of the peripheral area SA by the transition line 40.

[0152] For example, the first distance is about any one of 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm. However, the embodiments of the present disclosure are not limited thereto.

[0153] It should be noted that the first distance is about 1.5 μm for illustration. Due to the existence of certain uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), when the first distance floats within the range of ±10% × 1.5 μm, the first distance can also be considered to satisfy the condition that the first distance is equal to 1.5 μm.

[0154] The above embodiments mainly introduce how to layout the plurality of transfer lines 40 and the plurality of clock signal lines 31 to achieve that the load of each transfer line 40 is substantially the same and the load of each clock signal line 31 is substantially the same, so as to improve the display effect of the shaped display panel 100. Among them, the above embodiments can be applied to electroluminescent display panel 100 or photoluminescent display panel 100, and can also be applied to shaped liquid crystal display panel 100. Hereinafter, the structure of the shaped liquid crystal display panel 100 is mainly introduced, and the arrangement of the devices and wires in the peripheral area SA is introduced.

[0155] In some embodiments, as shown in FIGS. 2 and 7, at least one clock signal line 31 is located in the frame area F. The clock signal line 31 located in the frame area F can include a plurality of openings K, so that the UV light can pass through the plurality of openings K to irradiate the frame adhesive F1, and the curing treatment of the frame adhesive F1 is realized.

[0156] In addition, when any one or more clock signal lines in the plurality of clock signal lines 31 are provided with a plurality of openings K, all the clock signal lines 31 can be provided with a plurality of openings K synchronously, so as to reduce the difference between the clock signal lines 31 and the difference in load between the clock signal lines 31, and improve the display effect of the shaped display panel 100.

[0157] It should be noted that the shape, size and position of the opening K in each clock signal line 31 can be the same, so as to realize the reduction of the difference between the clock signal lines 31.

[0158] In the case where each clock signal line 31 includes a plurality of openings K, the orthogonal projection of the transfer line 40 on the substrate 10 is equal to the area of the overlapping region formed by the orthogonal projection of the openings K on the substrate 10 of at least two clock signal lines 31. That is, the orthogonal projection of the transfer line 40 on the substrate 10 is equal to the area of the overlapping region formed by the orthogonal projection of the part of at least two clock signal lines 31 which is not provided with the opening K on the substrate 10.

[0159] Specifically, the area of the overlapping region formed by the orthographic projection of the adapter line 40 on the substrate 10 and the orthographic projection of the opening K on each clock signal line 31 on the substrate 10 can be set to be equal.

[0160] In this way, the difference in the area of the overlapping region formed by the orthographic projection of each adapter line 40 on the substrate 10 and the orthographic projection of each clock signal line 31 on the substrate 10 can be reduced, the difference in the coupling capacitance formed between each adapter line 40 and each clock signal line 31 can be reduced, the difference in the load between each adapter line 40 can be reduced, and the display effect of the special-shaped display panel 100 can be improved.

[0161] In addition, in the case where each clock signal line 31 includes a plurality of openings K, the area of the overlapping region formed by the orthographic projection of at least two adapter lines 40 on the substrate 10 and the orthographic projection of the openings K on all clock signal lines 31 on the substrate 10 can also be set to be equal. That is, the area of the overlapping region formed by the orthographic projection of at least two adapter lines 40 on the substrate 10 and the orthographic projection of the part of all clock signal lines 31 on which no opening K is provided on the substrate 10 can be set to be equal.

[0162] Specifically, the area of the overlapping region formed by the orthographic projection of each adapter line 40 on the substrate 10 and the orthographic projection of the openings K on all clock signal lines 31 on the substrate 10 can be set to be equal.

[0163] In this way, the difference in the area of the overlapping region formed by the orthographic projection of each adapter line 40 on the substrate 10 and the orthographic projection of each clock signal line 31 on the substrate 10 can be reduced, the difference in the coupling capacitance formed between each adapter line 40 and each clock signal line 31 can be reduced, the difference in the load between each adapter line 40 can be reduced, and the display effect of the special-shaped display panel 100 can be improved.

[0164] In some embodiments, the adapter line 40 and the clock signal line 31 are in different layers to prevent the adapter line 40 from being short-circuited with the clock signal line 31 with which the adapter line 40 is not required to be connected.

[0165] In some examples, since the adapter line 40 and the clock signal line 31 are in different layers, the adapter line 40 can be directly connected to the clock signal line 31 with which the adapter line 40 is required to be connected through a via.

[0166] In other examples, as shown in FIG. 7, since the adapter line 40 and the clock signal line 31 are in different layers, the special-shaped display panel 100 further includes a plurality of first connection portions W1, the plurality of first connection portions W1 are located on the side of the plurality of adapter lines 40 away from the plurality of clock signal lines 31, one end of the first connection portion W1 is connected to the clock signal line 31, and the other end of the first connection portion W1 is connected to the adapter line 40, so as to realize the connection between the adapter line 40 and the clock signal line 31 with which the adapter line 40 is required to be connected.

[0167] Specifically, the first connection portion W1 can include a first sub-connection portion W11 and a second sub-connection portion W12. A normal projection of the first sub-connection portion W11 of the first connection portion W1 on the substrate 10 overlaps with a normal projection of the transition line 40 to be connected on the substrate 10, so that the first sub-connection portion W11 of the first connection portion W1 is connected with the transition line 40. For example, the first sub-connection portion W11 of the first connection portion W1 can be connected with the transition line 40 through a via hole.

[0168] A normal projection of the second sub-connection portion W12 of the first connection portion W1 on the substrate 10 overlaps with a normal projection of the clock signal line 31 to be connected on the substrate 10, so that the second sub-connection portion W12 of the first connection portion W1 is connected with the clock signal line 31. For example, the second sub-connection portion W12 of the first connection portion W1 can be connected with the clock signal line 31 through a via hole.

[0169] FIG. 9 is a cross-sectional view of a shaped display panel according to some embodiments. In FIG. 9, the shaped display panel 100 is taken as an example of a shaped liquid crystal display panel, and FIG. 9 mainly introduces a structure of an array substrate in the shaped liquid crystal display panel.

[0170] In some embodiments, as shown in FIGS. 4, 7 and 9, each sub-pixel P0 in the shaped liquid crystal display panel 100 is provided with a driving circuit Q and a pixel electrode 51 on the substrate 10. The driving circuit Q can include a first transistor T1 including an active layer, a source, a drain, a gate and a gate insulating layer, the source and the drain being in contact with the active layer, the source of the first transistor T1 being electrically connected with a data signal line Data, and the drain of the first transistor T1 being electrically connected with the pixel electrode 51, for transmitting a data signal on the data signal line Data to the pixel electrode 51.

[0171] In some examples, the first transistor T1 can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and the drain of the transistor can be interchangeable under certain conditions, the source and the drain are not distinguished in terms of connection relationship. In addition, the transistor can be divided into N-type and P-type according to the characteristics of the transistor. In this embodiment, the transistor is taken as an N-type transistor. When the N-type transistor is adopted, the source and the drain of the second transistor T2 are turned on when the gate input is high, and the P-type is opposite, which will not be described here.

[0172] In some examples, the pixel electrode 51 is a transparent electrode. For example, the material of the pixel electrode 51 can be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or fluorine-doped tin oxide (FTO).

[0173] In addition, the array substrate 110 of the shaped liquid crystal display panel 100 further includes a common electrode 61 disposed on the substrate 10. The pixel electrode 51 and the common electrode 61 can be disposed on the same layer. In this case, the pixel electrode 51 and the common electrode 61 are both comb structures including a plurality of strip sub-electrodes. The pixel electrode 51 and the common electrode 61 can also be disposed on different layers. The common electrode 61 can be a surface electrode. In this case, a first insulating layer V1 is disposed between the pixel electrode 51 and the common electrode 61. In the case where the common electrode 61 is disposed between the first transistor T1 and the pixel electrode 51, a second insulating layer V2 is further disposed between the common electrode 61 and the first transistor T1. In other embodiments, the cell substrate 120 includes the common electrode 61.

[0174] Based on this, the electric field formed between the pixel electrode 51 and the common electrode 61 can be used to deflect the liquid crystal in the liquid crystal layer of the display panel 100 to realize picture display.

[0175] In some embodiments, as shown in FIGS. 5 and 9, the array substrate 110 of the shaped liquid crystal display panel 100 further includes a gate metal layer Gate, a source-drain metal layer SD, and a transparent electrode layer 50 in the direction away from the substrate 10. The pixel electrode 51 in the plurality of sub-pixels P0 is located in the pixel electrode layer 50.

[0176] The gate metal layer Gate is located between the substrate 10 and the source-drain metal layer SD. The gate metal layer Gate can include the gate of the first transistor T1 of the driving circuit, and the gate metal layer Gate can also be used to form a scan signal line G1. In addition, the gate metal layer Gate can also include the gate of the transistor in the shift register.

[0177] In some examples, a plurality of clock signal lines 31 are located in the gate metal layer Gate. That is, the plurality of clock signal lines 31 are disposed in the same layer as the gates of the transistors in the shift register and the scan signal line G1. This does not require the formation of an additional metal layer in the shaped display panel 100, which not only facilitates the electrical connection of the clock signal lines 31 and the transistors in the shift register, but also facilitates the simplification of the manufacturing process of the shaped display panel 100.

[0178] In some examples, the material of the gate metal layer Gate includes a conductive metal. The conductive metal can include at least one of aluminum, copper, and molybdenum, and the present disclosure is not limited thereto.

[0179] The source-drain metal layer SD is located between the gate metal layer Gate and the transparent electrode layer 50. The source-drain metal layer SD can include the source and the drain of the first transistor T1, and the source-drain metal layer can also be used to form the data signal line Data. In addition, the gate metal layer Gate can also include the source and the drain of the transistors in the shift register.

[0180] In some examples, the plurality of transfer lines 40 are located in the source-drain metal layer SD. That is, the plurality of transfer lines 40 can be arranged in the same layer as the data signal line Data, without the need to form an additional metal layer in the special-shaped display panel 100, which is conducive to simplifying the manufacturing process of the special-shaped display panel 100.

[0181] In some examples, the material of the source-drain metal layer SD includes a conductive metal. The conductive metal can include at least one of aluminum, copper, and molybdenum, and the present disclosure is not limited thereto. In other examples, the material of the source-drain metal layer SD can include a molybdenum (Mo)-aluminum (Al)-molybdenum (Mo) multi-layer layered composite material.

[0182] In some examples, a planarization layer (English full name: Planarization Layer, English abbreviation: PLN) is provided between the source-drain metal layer SD and the gate metal layer Gate. The planarization layer PLN can electrically insulate the source-drain metal layer SD and the gate metal layer Gate.

[0183] For example, the material of the planarization layer PLN can include at least one of a polyimide (English full name: Polyimide, English abbreviation: PI), an acrylic-based polymer, or a silicon-based polymer.

[0184] Based on this, when the transfer line 40 and the clock signal line 31 are directly connected through the via, the via is provided on the planarization layer PLN, and the via exposes the clock signal line 31 located on the gate metal layer Gate, so as to electrically connect the transfer line 40 located on the source-drain metal layer SD and the clock signal line 31.

[0185] When the transfer line 40 and the clock signal line 31 are electrically connected through the first connection part W1, the first connection part W1 can be arranged in the same layer as the pixel electrode 51. Further, without the need to form an additional conductive layer in the special-shaped display panel 100, which is conducive to simplifying the manufacturing process of the special-shaped display panel 100.

[0186] In the present application, the "same layer" refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form the specific pattern by one-time patterning process. Depending on the specific pattern, the one-time patterning process can include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous, and the specific pattern can also be at different heights or have different thicknesses.

[0187] In some examples, as shown in FIG. 7, the jumper wire 40 can further include a jumper wire connecting portion 40a, which is located on one side of the second line segment 42 of the jumper wire 40 along the extension direction of the clock signal line 31, and the extension direction of the jumper wire connecting portion 40a can be consistent with the extension direction of the clock signal line 31.

[0188] At this time, the normal projection of the first sub-connection portion W11 of the first connection portion W1 on the substrate 10 can overlap with the normal projection of the jumper wire connecting portion 40a of the jumper wire 40 on the substrate 10, so as to connect the first sub-connection portion W11 of the first connection portion W1 with the jumper wire connecting portion 40a of the jumper wire 40.

[0189] In addition, since the jumper wire connecting portion 40a of the jumper wire 40 is located on one side of the second line segment 42 of the jumper wire 40 along the extension direction of the clock signal line 31, and the extension direction of the jumper wire connecting portion 40a is consistent with the extension direction of the clock signal line 31, it is equivalent to increasing the contact area between the first connection portion W1 and the jumper wire 40 by using the jumper wire connecting portion 40a, which is beneficial to reduce the contact resistance therebetween.

[0190] In some examples, the normal projection of the jumper wire connecting portion 40a of the jumper wire 40 on the substrate 10 can be located within the boundary of the normal projection of the first sub-connection portion W11 of the first connection portion W1 on the substrate 10, and the first sub-connection portion W11 of the first connection portion W1 has a larger size, which can further reduce the contact resistance between the first connection portion W1 and the jumper wire 40. In addition, since the first sub-connection portion W11 of the first connection portion W1 has a larger size, it is also convenient to connect the first sub-connection portion W11 of the first connection portion W1 with the jumper wire 40 through a via.

[0191] The above embodiments in combination with the related drawings mainly introduce the relative position relationship between the clock signal line 31 and the jumper wire 40 in the peripheral area SA, so as to reduce the load therebetween and improve the display effect of the special-shaped display panel 100. In the following, how to test all the data signal lines Data in the special-shaped display panel 100 (Array test, AT) will be introduced in combination with the related drawings, so as to improve the yield of the special-shaped display panel 100.

[0192] Specifically, the following mainly introduces a special-shaped display panel 100 adopting a COG (Chip On Glass) binding process. When the special-shaped display panel 100 is detected, the array substrate has not yet bound the driving chip (IC).

[0193] At this time, the substrate 10 (glass substrate) is provided with a first pad PAD1 for connecting the driving chip IC. When the special-shaped display panel 100 binds the driving chip IC, the input end of the driving chip IC can be connected with the first pad PAD1, and the output end of the driving chip IC can be connected with the plurality of data signal lines Data, so as to transmit the driving signal to the data signal lines Data.

[0194] Since the number of the first pads PAD1 is far less than the number of the data signal lines Data, it is necessary to adopt a design scheme of a short-circuit ring, so as to match the number of the first pads PAD1 with the number of the short-circuit ring.

[0195] FIG. 10 is a structural diagram of a special-shaped display panel according to still another embodiment, and FIG. 11 is a partial enlarged view of C2 in FIG. 10.

[0196] In some embodiments, as shown in FIGS. 5, 10 and 11, along the first reference line O1, the peripheral area SA is divided into two sub-peripheral areas SA0, and the display area AA is divided into two sub-display areas AA0. The first reference line O1 is an extension line of the center connecting line of the plurality of scan signal lines G1.

[0197] Along the column direction Y, the sub-peripheral area SA0 includes a first frame area SA1 (upper frame) and a second frame area SA2 (lower frame), and the special-shaped display panel 100 further includes a binding area BB. Along the column direction Y, the first frame area, the plurality of data signal lines Data and the binding area BB are arranged in sequence.

[0198] The first frame area SA1 includes a first area SA11 and a second area SA12. The first area SA11 overlaps the gate driving circuit G, and the second area SA12 does not overlap the gate driving circuit G. That is, part of the shift register 20 in the gate driving circuit G is located in the first area SA11 of the first frame area SA1, but the gate driving circuit G does not extend into the second area SA12 of the first frame area SA1.

[0199] Two first short-circuit rings H1 can be arranged in the special-shaped display panel 100, one first short-circuit ring H1 is located in one sub-peripheral area SA0, and one first short-circuit ring H1 is used for electrically connecting all data signal lines Data in the corresponding sub-display area AA0. In order to facilitate the detection (Array test, AT) of all data signal lines Data in the special-shaped display panel 100 by using the two first short-circuit rings H1, the data line disconnection (Data Open, DO) is detected, and corresponding maintenance is performed, so as to improve the yield of the special-shaped display panel 100.

[0200] Specifically, the first short-circuit ring H1 includes a first sub-section H01, a second sub-section H02 and a third sub-section H03. In one first short-circuit ring H1: the second sub-section H02 is located in the first frame area SA1, and the second sub-section H02 is connected to one end of all data signal lines Data in the corresponding sub-display area AA0 away from the binding area BB; the third sub-section H03 is located in the second area SA12 of the first frame area SA1; the first sub-section H01 extends from the binding area BB through the second frame area SA2, the third frame area SA3 / the fourth frame area SA4, the first area SA11 of the first frame area SA1 to the second area SA12 of the first frame area SA1, and the first sub-section H01 is connected to the second sub-section H02 through the third sub-section H03.

[0201] That is, the first short-circuit ring H1 extending from the first pad PAD1 of the binding area BB first extends to the second area SA12 of the first frame area SA1, then bends towards the display area AA side, extends to the position of the first frame area SA1 close to the edge of the display area AA, and then the first short-circuit ring H1 is folded back and connected to one end of all data signal lines Data in the corresponding sub-display area AA0 away from the binding area BB.

[0202] Based on this, the first sub-section H01 of the first short-circuit ring H1 is located on the side of the gate drive circuit G away from the display area AA, the second sub-section H02 is located on the side of the gate drive circuit G close to the display area AA, and the third sub-section H03 is formed by using the space outside the gate drive circuit G to connect the first sub-section H01 and the second sub-section H02. In addition, the second sub-section H02 extends to the position of the outermost (closest to the gate drive circuit G) data signal line Data, and does not extend to between the gate drive circuit G and the scanning signal line G1.

[0203] For example, the first sub-section H01 of the first short-circuit ring H1 is located on the side of the clock signal line 31 away from the gate drive circuit G, and the second sub-section H02 of the first short-circuit ring H1 is located on the side of the gate drive circuit G away from the clock signal line 31, between the gate drive circuit G and the display area AA.

[0204] In this way, the space of the surrounding area SA can be fully utilized to realize that the first short-circuit ring H1 can be connected to all the data signal lines Data in the corresponding sub-display area AA0 away from the one end of the binding area BB, without affecting the electrical connection between the gate driving circuit G and the plurality of scanning signal lines G1, so as to prevent the short circuit problem between the first short-circuit ring H1, the gate driving circuit G and the scanning signal line G1.

[0205] In some examples, after the special-shaped display panel 100 is boxed, Cell Test detection needs to be performed. At this time, although the driving chip IC is located at the first pad PAD1 for binding. However, since the spacing between the pins on the corresponding lighting device for performing the Cell Test detection (is larger), the spacing of the plurality of first pads PAD1 does not match.

[0206] Based on this, the second pad can be arranged at the binding area BB, and the second pad can be arranged at the edge position of the binding area BB along the row direction X. At this time, the spacing between the plurality of second pads PAD2 can match the spacing between the pins on the corresponding lighting device for performing the Cell Test detection. Therefore, the first short-circuit ring H1 and the second short-circuit ring H2 are connected to the external lighting device by using the plurality of second pads PAD2 to perform the Cell Test detection.

[0207] FIG. 12 is a layout view of C2 in FIG. 10, and FIG. 13 is an equivalent circuit diagram of FIG. 12.

[0208] In some embodiments, as shown in FIGS. 10-13, the special-shaped display panel 100 further includes a plurality of output signal lines OUT, and the output signal line OUT is located between the shift register 20 and the display area AA, so that one shift register 20 is connected to one scanning signal line G1 in the display area AA through one output signal line OUT.

[0209] The second sub-section H02 of the first short-circuit ring H1 can also be arranged in the same layer as the data signal line Data. That is, an additional metal layer does not need to be formed in the special-shaped display panel 100 to manufacture the second sub-section H02 of the first short-circuit ring H1, which is beneficial to simplify the manufacturing process of the special-shaped display panel 100. In addition, since the second sub-section H02 of the first short-circuit ring H1 can also be arranged in the same layer as the data signal line Data, the second sub-section H02 of the first short-circuit ring H1 can be formed integrally with the data signal line Data, and an additional connection part does not need to be formed between the two, which can simplify the structure of the special-shaped display panel 100.

[0210] In some examples, the first sub-section H01 of the first short-circuit ring H1 can be arranged in the same layer as the scan signal line G1. That is, the first sub-section H01 of the first short-circuit ring H1 does not need to be formed by forming an additional metal layer in the special-shaped display panel 100, which is conducive to simplifying the manufacturing process of the special-shaped display panel 100.

[0211] In other examples, the first sub-section H01 of the first short-circuit ring H1 can be arranged in the same layer as the data signal line Data. That is, the first sub-section H01 of the first short-circuit ring H1 does not need to be formed by forming an additional metal layer in the special-shaped display panel 100, which is conducive to simplifying the manufacturing process of the special-shaped display panel 100.

[0212] In the above, two arrangement modes of the first sub-section H01 of the first short-circuit ring H1 are introduced. The resistivity of the gate metal layer Gate and the source-drain metal layer SD can be selected to form the first sub-section H01 of the first short-circuit ring H1. The film layer with smaller resistivity is selected to form the first sub-section H01 of the first short-circuit ring H1, which is conducive to reducing the resistance of the first short-circuit ring H1.

[0213] It should be noted that "in the same layer" means that the film layer used to form a specific pattern is formed by using the same film forming process, and then the layer structure is formed by using the same mask plate through one patterning process. According to different specific patterns, the one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous. These specific patterns can also be at different heights or have different thicknesses.

[0214] In some examples, the output signal line OUT can be arranged in the same layer as the data signal line Data. That is, the second sub-section H02 of the first short-circuit ring H1, the output signal line OUT and the data signal line Data are arranged in the same layer.

[0215] The output signal line OUT does not need to be formed by forming an additional metal layer in the special-shaped display panel 100, which can further simplify the manufacturing process of the special-shaped display panel 100. At this time, the output signal line OUT is equivalent to being arranged in the source-drain metal layer SD, which can also facilitate crossing other lines located in the gate metal layer Gate to prevent short circuit between them, or the problem that the output signal line OUT cannot be extended to be connected with the scan signal line G1. The lines located in the gate metal layer Gate can include common electrode lines and the like.

[0216] As shown in the above structure, the output signal line OUT is located in the source-drain metal layer SD, and the scan signal line G1 is located in the gate metal layer Gate. That is, the output signal line OUT and the scan signal line G1 are arranged in different layers.

[0217] In some examples, as shown in FIGS. 10-13, a scan signal line extension G2 can be provided, which is in the same layer as the scan signal line G1, is located in the peripheral area SA, has the same extension direction as the scan signal line G1, and is connected to the scan signal line G1 on one side of the scan signal line G1 along the row direction X (the extension direction of the scan signal line G1). That is, the scan signal line extension G2 can extend the scan signal line G1, so that the scan signal line G1 can be connected to the output signal line OUT located in the peripheral area SA. The scan signal line extension G2 can be understood as the part of the scan signal line G1 extending to the peripheral area SA.

[0218] In some examples, the scan signal line G1 and the output signal line OUT can be connected by a via. The scan signal line G1 can be connected to the output signal line OUT by the scan signal line extension G2. Specifically, the end of the scan signal line extension G2 away from the scan signal line G1 has a projection on the substrate 10 that overlaps with the projection of the end of the output signal line OUT away from the shift register 20 on the substrate 10. A via is provided on the planarization layer PLN between the two, which exposes the scan signal line extension G2 on the gate metal layer Gate, so that the output signal line OUT on the source-drain metal layer SD is electrically connected to the scan signal line extension G2.

[0219] In other examples, as shown in FIG. 12, the special-shaped display panel 100 further includes a plurality of second connection portions W2, which are located on the side of the source-drain metal layer SD away from the gate metal layer Gate, one end of each second connection portion W2 is connected to the output signal line OUT, and the other end of each second connection portion W2 is connected to the scan signal line G1. That is, the output signal line OUT and the scan signal line G1 can be connected by the second connection portion W2.

[0220] For example, the third sub-connection portion W21 of the second connection portion W2 can be connected to the output signal line OUT by a via.

[0221] The fourth sub-connection portion W22 of the second connection portion W2 has an overlapping projection on the substrate 10 with the projection on the substrate 10 of the one end of the scan signal line G1 away from which the scan signal line extension G2 is connected, so as to connect the fourth sub-connection portion W22 of the second connection portion W2 with the scan signal line extension G2. For example, the fourth sub-connection portion W22 of the second connection portion W2 can be connected with the scan signal line extension G2 through a via hole.

[0222] Based on this, the fourth sub-connection portion W22 of the second connection portion W2 is connected with the scan signal line G1, and the output signal line OUT and the scan signal line G1 are connected by the second connection portion W2.

[0223] In some examples, the second connection portion W2 can be arranged in the same layer as the pixel electrode 51. Further, there is no need to form an additional conductive layer in the special-shaped display panel 100, which is conducive to simplifying the manufacturing process of the special-shaped display panel 100.

[0224] It should be noted that in FIG. 12, in order to clearly show the structure of each pixel electrode 51, the structure of the pixel electrode 51 is not filled with a pattern. That is, the pixel electrode 51 is not filled with a pattern filled in the second connection portion W2, but it does not mean that the second connection portion W2 is not arranged in the same layer as the pixel electrode 51.

[0225] In some embodiments, in combination with FIGS. 10-13, the special-shaped display panel 100 further includes a plurality of switch units R and two second short-circuit rings H2, one second short-circuit ring H2 is arranged corresponding to one first short-circuit ring H1. The plurality of switch units R are located between the second sub-section H02 of the first short-circuit ring H1 and the display area AA, the first end of the switch unit R is connected with the second sub-section H02 of the first short-circuit ring H1, the second end of the switch unit R is connected with the data signal line Data, and the control end of the switch unit R is connected with the second short-circuit ring H2.

[0226] Based on this, the second short-circuit ring H2 can be used to control the switch unit R to be turned on or turned off. When the second short-circuit ring H1 controls the switch unit R to be turned on, the detection signal transmitted by the first short-circuit ring H1 can be transmitted to the corresponding data signal line Data through the switch unit R, so as to detect whether the data signal line Data has a problem of breakage.

[0227] The second short circuit ring H2 comprises a fourth sub-section H04, a fifth sub-section H05 and a sixth sub-section H06. The fifth sub-section H05 is located in the first frame area SA1 and between the first sub-section H01 and the second sub-section H02, and the fifth sub-section H05 is connected with the control terminals of all the switch units R in the same sub-peripheral area SA0. The sixth sub-section H06 is located in the second area SA12 of the first frame area SA1. The fourth sub-section H04 is located between the first sub-section H01 and the fifth sub-section H05, and the fourth sub-section H04 extends from the binding area BB to the second area SA12 of the first frame area SA1 and is connected with the fifth sub-section H05 through the sixth sub-section H06.

[0228] That is, the second short circuit ring H2 extending from the binding area BB first extends to the second area SA12 of the first frame area SA1, then bends towards the display area AA side, extends to the position of the first frame area SA1 close to the edge of the display area AA, and then the second short circuit ring H2 is folded back to be connected with the end of the data signal line Data in the corresponding sub-display area AA0 away from the binding area BB.

[0229] Therefore, the fourth sub-section H04 of the second short circuit ring H2 is located between the first sub-section H01 of the first short circuit ring H1 and the gate drive circuit G, the fifth sub-section H05 of the second short circuit ring H2 is located between the gate drive circuit G and the second sub-section H02 of the first short circuit ring H1, and the sixth sub-section H06 of the second short circuit ring H2 is formed by using the space outside the gate drive circuit G to connect the fourth sub-section H04 and the fifth sub-section H05. The sixth sub-section H06 of the second short circuit ring H2 is located between the third sub-section H03 of the first short circuit ring H1 close to the gate drive circuit G to prevent the second short circuit ring H2 and the first short circuit ring H1 from overlapping. In addition, the end of the fifth sub-section H05 away from the sixth sub-section H06 extends to the position of the outermost data signal line Data (closest to the gate drive circuit G) and does not extend between the gate drive circuit G and the scanning signal line G1.

[0230] For example, the fourth sub-section H04 of the second short circuit ring H2 is located between the first sub-section H01 of the first short circuit ring H1 and the clock signal line 31, and the fifth sub-section H05 of the second short circuit ring H2 is located on the side of the gate drive circuit G away from the clock signal line 31 and between the gate drive circuit G and the second sub-section H02 of the first short circuit ring H1.

[0231] In this way, the space of the peripheral area SA can be fully utilized to realize that the second short circuit ring H2 can be electrically connected with the switch unit R without affecting the electrical connection between the gate drive circuit G and the plurality of scanning signal lines G1, so as to prevent the short circuit problem between the second short circuit ring H2, the gate drive circuit G and the scanning signal line G1.

[0232] In some examples, the switch unit R can include a second transistor T2 including an active layer, a source, a drain, a gate, and a gate insulating layer, the source and the drain are in contact with the active layer respectively, the source of the second transistor T2 is the first end of the switch unit R, and is electrically connected with the second sub-section H02 of the first short-circuit ring H1, the drain of the second transistor T2 is the second end of the switch unit R, and is electrically connected with the data signal line Data, and the gate of the second transistor T2 is the control end of the switch unit R, and is electrically connected with the fifth sub-section H05 of the second short-circuit ring H2. In the switch unit R, the source and the drain of the second transistor T2 can be located in the source-drain metal layer SD, and the gate of the second transistor T2 can be located in the gate metal layer Gate.

[0233] Based on this, the second short-circuit ring H2 can be used to transmit the scan signal to the gate of the second transistor T2 to control the second transistor T2 to be turned on, and the detection signal transmitted by the first short-circuit ring H1 can be transmitted to the corresponding data signal line Data through the switch unit R to detect whether the data signal line Data has a breakage problem. That is, in the detection stage, the second short-circuit ring H2 can control the second transistor T2 to be turned on, and the detection signal transmitted by the first short-circuit ring H1 can be transmitted to the corresponding data signal line Data through the switch unit R. When the subsequent special-shaped display panel 100 is in the display stage, the second short-circuit ring H2 can control the second transistor T2 to be turned off.

[0234] In some examples, the second transistor T2 can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and the drain of the transistor can be interchangeable under certain conditions, the source and the drain are not distinguished in terms of connection relationship. In addition, the transistor can be divided into N-type and P-type according to the characteristics of the transistor. In this embodiment, the transistor is an N-type transistor. When the N-type transistor is used, the source and the drain of the second transistor T2 are turned on when the gate input is high. The P-type is opposite, which will not be described here.

[0235] In some embodiments, as shown in FIGS. 10-13, the second short-circuit ring H2 and the scan signal line G1 are in the same layer. Based on this, no additional conductive layer needs to be formed in the special-shaped display panel 100 for manufacturing the second short-circuit ring H2, which is beneficial to simplify the manufacturing process of the special-shaped display panel 100.

[0236] In this way, the fifth sub-section H05 of the second short-circuit ring H2 and the second sub-section H02 of the first short-circuit ring H1 are arranged in different layers. Therefore, the problem of short circuit caused by the intersection of the fifth sub-section H05 of the second short-circuit ring H2 and the second sub-section H02 of the first short-circuit ring H1 can be prevented.

[0237] In addition, since the gate of the second transistor T2 in the switch unit R can be located on the gate metal layer Gate, the second short circuit ring H2 and the scan signal line G1 are arranged in the same layer, which is equivalent to arranging the second short circuit ring H2 and the gate of the second transistor T2 in the same layer, facilitating the electrical connection between the second short circuit ring H2 and the gate of the second transistor T2, and simplifying the structure of the peripheral area SA of the special-shaped display panel 100.

[0238] In some examples, the second short circuit ring H2 can further include a plurality of connection sub-segments H07, the connection sub-segments H07 extend along the row direction X, and the connection sub-segments H07 are located between the fifth sub-segment H05 of the second short circuit ring H2 and the display area AA, so that the fifth sub-segment H05 of the second short circuit ring H2 can be connected to the second transistor T2 of the switch unit R through the connection sub-segments H07.

[0239] In some examples, the connection sub-segments H07 can include a plurality of conductive parts, and the conductive parts can be reused as the gate of the second transistor T2. Based on this, there is no need to separately manufacture the gate of the second transistor T2, and the manufacturing process of the special-shaped display panel 100 can be simplified.

[0240] In some embodiments, as shown in FIGS. 10-13, since the second sub-segment H02 of the first short circuit ring H1 is located on the source-drain metal layer SD, the output signal line OUT is also located on the source-drain metal layer SD, and the scan signal line extension G2 is located on the gate metal layer Gate.

[0241] The scan signal line extension G2 can be arranged to extend on the substrate 10 to between the normal projection of the fifth sub-segment H05 of the second short circuit ring H2 and the normal projection of the second sub-segment H02 of the first short circuit ring H1 on the substrate 10, so as to prevent the problem of short circuit between the output signal line OUT and the second sub-segment H02 of the first short circuit ring H1.

[0242] Based on this, the second connection part W2 can be arranged to extend on the substrate 10 to between the normal projection of the fifth sub-segment H05 of the second short circuit ring H2 and the normal projection of the second sub-segment H02 of the first short circuit ring H1 on the substrate 10. In order to prevent the problem of short circuit between the second connection part W2 and the second sub-segment H02 of the first short circuit ring H1 located on the source-drain metal layer SD when connected through the via on the scan signal line extension G2 located on the gate metal layer Gate.

[0243] In some examples, the normal projection of the second connection part W2 on the substrate 10 is between the normal projection of the fifth sub-segment H05 of the second short circuit ring H2 on the substrate 10, so as to prevent the problem of short circuit between the two.

[0244] In some examples, the normal projection of the second connection part W2 on the substrate 10 is between the normal projection of the second sub-segment H02 of the first short circuit ring H1 on the substrate 10, so as to prevent the problem of short circuit between the two.

[0245] FIG. 14 is a structural diagram of a shaped display panel according to yet some embodiments, and FIG. 15 is a partial enlarged plan view of C3 in FIG. 14.

[0246] In some embodiments, as shown in FIGS. 14 and 15, the shaped display panel 100 further includes a third connecting portion W3, the third connecting portion W3 is in the same layer as the second sub-section H02 of the first shorting ring H1, one end of the third connecting portion W3 is connected to the second sub-section H02 of the first shorting ring H1 in one sub-display area AA0, and the other end of the third connecting portion W3 is connected to the second sub-section H02 of the first shorting ring H1 in another sub-display area AA0. That is, the second sub-section H02 of the first shorting ring H1 located in two sub-peripheral areas SA0 are connected by one third connecting portion W3, so as to jointly control the first shorting ring H1 in the two sub-peripheral areas SA0.

[0247] In some embodiments, as shown in FIGS. 14 and 15, the shaped display panel 100 further includes a fourth connecting portion W4, the fourth connecting portion W4 is in the same layer as the fifth sub-section H05 of the second shorting ring H2, one end of the fourth connecting portion W4 is connected to the fifth sub-section H05 of the second shorting ring H2 in one sub-display area AA0, and the other end of the fourth connecting portion W4 is connected to the fifth sub-section H05 of the second shorting ring H2 in another sub-display area AA0. That is, the fifth sub-section H05 of the second shorting ring H2 located in two sub-peripheral areas SA0 are connected by one fourth connecting portion W4, so as to jointly control the second shorting ring H2 in the two sub-peripheral areas SA0.

[0248] In some embodiments, as shown in FIGS. 14 and 15, the third sub-section H03 of the first shorting ring H1 includes a first part H031 and a second part H032, the first part H031 of the third sub-section H03 is in the same layer as the first sub-section H01 of the first shorting ring H1, and the second part H032 of the third sub-section H03 is in the same layer as the second sub-section H02 of the first shorting ring H1.

[0249] In this way, the first part H031 of the third sub-section H03 can be connected to the first sub-section H01 of the first shorting ring H1, and the second part H032 of the third sub-section H03 can be connected to the second sub-section H02 of the first shorting ring H1. The third sub-section H03 of the first shorting ring H1 including the first part H031 and the second part H032 can be connected by a via hole.

[0250] In some embodiments, as shown in Figures 14 and 15, the orthographic projection of the second portion H032 of the third sub-segment H03 on the substrate 10 overlaps with the orthographic projection of the fourth connecting portion W4 on the substrate 10. That is, the orthographic projection of the first portion H031 of the third sub-segment H03 on the substrate 10 does not overlap with the orthographic projection of the third connecting portion W3 on the substrate 10, to prevent short circuits between the first portion H031 of the third sub-segment H03 and the fourth connecting portion W4 located in the same layer.

[0251] Figure 16 is a structural diagram of an irregularly shaped display panel according to some other embodiments.

[0252] In some embodiments, as shown in FIG16, the irregularly shaped display panel 100 can realize split-screen control. That is, the two sub-display areas AA0 in the irregularly shaped display panel 100 are controlled independently. For example, each scan signal line G1 in the irregularly shaped display panel 100 is disconnected at the position of the first reference line O1, and if the common electrode is a surface electrode, the common electrode is also disconnected at the position of the first reference line O1, so as to realize independent control of the two sub-display areas AA0.

[0253] At this time, the irregularly shaped display panel 100 may not have the third and fourth connecting parts. That is, the two first short-circuit rings H1 located in the two sub-peripheral areas SA0 are independently set, and the two second short-circuit rings H2 located in the two sub-peripheral areas SA0 are independently set, so as to facilitate the detection of the data signal lines Data in the two sub-display areas AA0 respectively.

[0254] In some embodiments, as shown in Figures 10 and 12, a pixel unit P includes three sub-pixels P0. In the pixel unit rows corresponding to the first boundary S1 of the display area AA, at least two rows of pixel units have different numbers of pixel units P.

[0255] Along the direction from the first border area SA1 to the second border area SA2 (from top to bottom in Figure 12), there are two adjacent rows of pixel units P. These two adjacent rows are the nth pixel unit row and the (n+1)th pixel unit row, respectively. The number of pixel units P in the nth pixel unit row is less than the number of pixel units P in the (n+1)th pixel unit row, where n is a positive integer. The (n+1)th pixel unit row includes at least one (n+1)th target pixel unit P. n+1 Along the column direction Y, the (n+1)th target pixel unit P n+1 The nth pixel unit does not overlap with the n+1th pixel unit row, and the target pixel unit P n+1 Forming the nth step region E with the nth pixel unit row n .

[0256] In other words, the number of pixel units P in the (n+1)th pixel unit row is more than the number of pixel units P in the nth pixel unit row, and the pixel units P that are in excess of the nth pixel unit row relative to the (n+1)th pixel unit row are defined as the (n+1)th target pixel units P of the (n+1)th pixel unit row n+1 The (n+1)th target pixel units P of the (n+1)th pixel unit row n+1 project out of the nth pixel unit row and form the nth step region E with the nth pixel unit row n .

[0257] The switching units R connected to the same data signal line Data with a sub-pixel P0 in the (n+1)th target pixel unit P are defined as the (n+1)th target switching units R n+1 The plurality of (n+1)th target switching units R n+1 are located in the nth step region E n . That is, the plurality of (n+1)th target switching units R n+1 are in the same row as the nth pixel unit row, and the plurality of (n+1)th target switching units R are arranged along the row direction X.

[0258] In other words, the (n+1)th target switching units R corresponding to the sub-pixels P0 in the (n+1)th target pixel units P n+1 are arranged in the nth step region E n to make full use of the step region outside the first sub-boundary S11 of the display region AA and improve the space utilization of the peripheral region SA. Moreover, it is equivalent to arranging the switching units R on one side of the data signal line Data along the column direction Y, which facilitates the connection of the data signal line Data and the switching units R.

[0259] In some embodiments, as shown in FIG. 12, the (n+1)th target pixel units P n+1 overlap the nth pixel unit row in the row direction X, and the (n+1)th target pixel units P n+1 overlap the (n+1)th pixel unit row in the column direction Y away from the side edge of the nth pixel unit row.

[0260] In other words, along the column direction Y, the plurality of (n+1)th target pixel units P do not project out of the nth step region E n , and along the row direction X, the plurality of (n+1)th target pixel units P do not project out of the nth step region E n . That is, the plurality of (n+1)th target pixel units P are arranged in the nth step region E n to prevent affecting the layout of the output signal line OUT connected to the scanning signal line G1 corresponding to the nth pixel unit row and reduce the problem of short circuit between the output signal line OUT and the switching units R.

[0261] In some examples, the width of the sub-pixel P0 is approximately px in the row direction X, and the length of the sub-pixel is approximately py in the column direction Y. Based on this, when the number of the (n+1)th target pixel unit P is 2, i.e., corresponding to 6 sub-pixels P0. At this time, the nth step area E n The length of the first short circuit ring H1 in the row direction X is approximately 6px.

[0262] The minimum distance between the second sub-section H01 of the first short circuit ring H1 and the pixel unit row in the row direction X is bx, and the minimum distance between the second sub-section H01 of the first short circuit ring H1 and the pixel unit row in the column direction Y is by. Wherein, bx < px, by < py.

[0263] Based on this, the plurality of (n+1)th target pixel units P can be made to protrude out of the nth step area E n in the column direction Y, and the plurality of (n+1)th target pixel units P can be made to protrude out of the nth step area E n in the row direction X. That is, the plurality of (n+1)th target pixel units P are arranged in the nth step area E n to prevent affecting the layout of the output signal line OUT connected to the scanning signal line G1 corresponding to the nth pixel unit row, and to reduce the problem of short circuit between the output signal line OUT and the switching unit R.

[0264] In some examples, the width of the second connecting part W2 is approximately cx in the row direction X, and the length of the second connecting part W2 is approximately cy in the column direction Y.

[0265] The minimum distance between the fifth sub-section H05 of the second short circuit ring H2 and the step area in the row direction X is ax, and the minimum distance between the fifth sub-section H05 of the second short circuit ring H2 and the step area in the column direction Y is ay. Wherein, ax ≥ bx+b, ay > by+b+cy.

[0266] Based on this, there is a gap between the second sub-section H02 of the first short circuit ring H1 and the fifth sub-section H05 of the second short circuit ring H2 in the direction of the display area AA from the peripheral area SA, so as to prevent the formation of parasitic capacitance between the two and increase the load of the two.

[0267] FIG. 17 is another layout of C2 in FIG. 10, and FIG. 18 is an equivalent circuit diagram of FIG. 17.

[0268] In some embodiments, as shown in FIG. 10, FIG. 17 and FIG. 18, the pixel unit P includes three sub-pixels P0. In the pixel unit row corresponding to the first boundary S1 of the display area AA, in the direction along which the first frame area SA1 points to the second frame area SA2 (the direction from top to bottom in FIG. 17), three rows of pixel units P are included in sequence, which are the nth pixel unit row, the nth+1 pixel unit row and the nth+2 pixel unit row respectively. The number of pixel units P in the nth+1 pixel unit row is greater than the number of pixel units P in the nth pixel unit row, and the number of pixel units P in the nth+1 pixel unit row is less than the number of pixel units P in the nth+2 pixel unit row. Specifically, the number of pixel units P in the nth pixel unit row, the nth+1 pixel unit row and the nth+2 pixel unit row gradually increases.

[0269] The nth+1 pixel unit row includes at least one nth+1 target pixel unit P n+1 , along the column direction Y, the nth+1 target pixel unit P n+1 does not overlap with the nth pixel unit row, and the nth+1 target pixel unit P forms an nth step area E n with the nth pixel unit row.

[0270] In other words, the number of pixel units P in the nth+1 pixel unit row is greater than the number of pixel units P in the nth pixel unit row, and the pixel units P in the nth+1 pixel unit row that are more than the nth pixel unit row are defined as the nth+1 target pixel unit P n+1 of the nth+1 pixel unit row. The nth+1 target pixel unit P n+1 of the nth+1 pixel unit row protrudes from the nth pixel unit row and forms an nth step area E n with the nth pixel unit row.

[0271] The switch unit R connected to the same data signal line Data in one sub-pixel P0 in the nth+1 target pixel unit P n+1 is defined as the nth+1 target switch unit R n+1 .

[0272] The nth+2 pixel unit row includes at least one nth+2 target pixel unit P n+2 , along the column direction Y, the nth+2 target pixel unit P n+2 does not overlap with the nth+1 pixel unit row, and the nth+2 target pixel unit P forms an nth+1 step area E n+1 with the nth+1 pixel unit row.

[0273] In other words, the number of pixel units P in the (n+2)th pixel unit row is greater than the number of pixel units P in the (n+1)th pixel unit row, and the extra pixel units P in the (n+2)th pixel unit row relative to the (n+1)th pixel unit row is defined as the (n+2)th target pixel unit P in the (n+2)th pixel unit row. n+2 The (n+2)th target pixel unit P in the (n+2)th pixel unit row. n+2 It protrudes from the (n+1)th pixel row and forms the (n+1)th step region E with the (n+1)th pixel row. n+1 .

[0274] With the (n+2)th target pixel unit P n+2 The switching unit R of an inner sub-pixel P0 connected to the same data signal line Data is defined as the (n+2)th target switching unit R. n+2 .

[0275] Among them, multiple n+2th target switching units R n+2 The sub-pixels P0 are arranged in two rows and multiple columns, with the target switching unit R in the (n+2)th row. n+2 Located in the (n+1)th step region E n+1 Inside, in the same row as the (n+1)th pixel unit, the (n+2)th target switch unit R in the second row. n+2 It is in the same row as the nth pixel unit and located in the nth step region E. n The side furthest from the row of the nth pixel unit.

[0276] Based on this, multiple n+2th target switching units R n+2 The sub-pixel P0 is divided into two parts, the first part (the (n+2)th target switching unit R in the first row) n+2 ) Set in the (n+1)th step region E n+1 Inside, the second part (the (n+2)th target switch unit R in the second row) n+2 ) Set in the (n+1)th step region E n+1 Far from the (n+2)th target switch unit R n+2 On one side, and the second part (the n+2nd target switch unit R in the second row) n+2 ) and the nth step region E n They are in the same row and adjacent to each other. That is, the second part (the (n+2)th target switch unit R in the second row). n+2 It was not directly set in the nth step region E n Inside, the nth step area E needs to be reserved. n The space is used to place the (n+1)th target switch unit R n+1 .

[0277] This configuration, relative to all (n+2)th target switching units R n+2 All are set in the (n+1)th step region E n+1The internal method can prevent the (n+2)th target switch unit R from being affected. n+2 The number is too large to be fully set in the (n+1)th step region E. n+1 Within this, the n+2th target switch unit R can be laid out more rationally. n+2 This is to make full use of the space in the surrounding area SA and facilitate the arrangement of cables within the surrounding area SA.

[0278] In some embodiments, as shown in Figures 17 and 18, a plurality of (n+1)th target switching units R n+1 The sub-pixel P0 in the image can correspond to multiple (n+2)th target switching units R. n+2 The sub-pixel P0 is set. That is, multiple (n+1)th target switching units R can be configured. n+1 The sub-pixels P0 are arranged in two rows and multiple columns, and the target switching unit R in the (n+1)th row is... n+1 Located in the nth step region E n Inside, with the (n+2)th target switch unit R in the second row n+2 It is in the same row as the nth pixel unit.

[0279] That is, the (n+1)th target switch unit R in the first row n+1 Target switch unit R located in the second row (n+2th position) n+2 Between the nth pixel unit row and the (n+2)th target switch unit R in the second row. n+2 It can be adjacent to the (n+1)th target switch unit R in the first row. n+1 This is configured to fully utilize the space of the surrounding area SA. Additionally, the (n+1)th target switch unit R in the second row... n+1 The setting method is the same as the target switch unit R in the second row (n+2). n+2 The setting method is similar, and it is also set in the (n+1)th target switch unit R in the first row. n+1 It is located on the side furthest from the (n+1)th pixel row, but can be in the same row as the (n-1)th pixel row. Here, n is a positive integer greater than 1.

[0280] In some examples, due to the (n+2)th target switch unit R in the second row n+2 It can be adjacent to the (n+1)th target switch unit R in the first row. n+1 The configuration can utilize the same connection sub-segment H07, and the target switch unit R in the (n+2)th row of the second line. n+2 and the (n+1)th target switch unit R in the first row n+1 Connection. That is, the (n+2)th target switch unit R set in the branch line. n+2 There is no need to add a separate connection sub-segment H07; the target switch unit R in the (n+1)th row can be shared. n+1 The required connection segment H07 can save space in the surrounding area SA.

[0281] In some embodiments, as shown in FIGS. 17 and 18, the number of the first row of the n+2th target switch unit R n+2 is greater than the number of the second row of the n+2th target switch unit R n+2 .

[0282] Therefore, the number of the first row of the n+2th target switch unit R n+2 is greater than the number of the second row of the n+2th target switch unit R n+2 , which is equivalent to setting a greater number of the second target switch unit R n+2 on the side close to the second sub-section H02 of the first short-circuit ring H1, so as to facilitate the connection of the n+2th target switch unit R n+2 and the second sub-section H02 of the first short-circuit ring H1. In addition, since each pixel unit P includes three sub-pixels P0, and the number of the first row of the n+2th target switch unit R n+2 is set to 1:2 with the number of the second row of the n+2th target switch unit R n+2 , the data signal line Data of the n+2th target switch unit R n+2 and the corresponding sub-pixel column can be electrically connected.

[0283] FIG. 19 is another layout of C2 in FIG. 10.

[0284] In some embodiments, there are other wirings between the gate driving circuit and the fifth sub-section H05 of the second short-circuit ring H2. For example, the gate driving circuit and the fifth sub-section H05 of the second short-circuit ring H2 are further provided with a common electrode line Cm, which can be electrically connected with the common electrode layer.

[0285] Therefore, the output signal line OUT has an overlapping area with the common electrode line Cm on the substrate 10, and the overlapping area is prone to form a parasitic capacitance, thereby increasing the load of the output signal line OUT and the common electrode line Cm. Thus, the common electrode line Cm can be provided with a plurality of hollow areas, and the output signal line OUT has an overlapping area with at least one of the hollow areas on the substrate 10, which can reduce the overlapping area between the output signal line OUT and the common electrode line Cm, thereby reducing the parasitic capacitance formed by the output signal line OUT and the common electrode line Cm, reducing the load of the output signal line OUT and the common electrode line Cm, and improving the display effect of the special-shaped display panel 100.

[0286] The above embodiments mainly introduce that the target switch units corresponding to the target pixel units are arranged in one row or two rows. In the case that the number of target pixel units is large, resulting in a large number of target switch units, a plurality of target switch units can also be arranged in three rows. The principle of arranging a plurality of target switch units in three rows is similar to the principle of arranging a plurality of target switch units in two rows, and can refer to the description of the above embodiments, which will not be described here.

[0287] The above merely describes specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art who thinks of changes or replacements within the technical range disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An irregularly shaped display panel having a display area and a peripheral area surrounding the display area, the display area including a first sub-boundary, wherein at least two segments within the first sub-boundary have different extending directions, or the first sub-boundary is not perpendicular to the boundary of the adjacent display area; The irregularly shaped display panel includes: Substrate; Multiple pixel units are located on one side of the substrate, and the multiple pixel units are arranged in multiple rows and columns in the display area. Each pixel unit includes multiple sub-pixels. At least one gate driving circuit is located in the peripheral area. The gate driving circuit includes a plurality of cascaded shift registers, one of the shift registers being connected to a plurality of sub-pixels arranged in a row. At a position corresponding to a first sub-boundary of the display area, the extension direction of the line connecting the centerlines of the plurality of shift registers is consistent with the extension direction of the first sub-boundary. Multiple clock signal lines are located in the peripheral area and on the side of the gate driving circuit away from the display area. At the position corresponding to the first sub-boundary of the display area, the extension direction of the multiple clock signal lines is consistent with the extension direction of the first sub-boundary. Each of the clock signal lines is connected to the shift register via a corresponding adapter cable; Along the extension direction of the adapter line, the adapter line includes a first segment and a second segment. The first segment and the second segment are connected to form a corner. The first segment is connected to the shift register, and the second segment is connected to the clock signal line. The orthographic projection of the second segment on the substrate overlaps with the orthographic projection of the first part of the clock signal line connected to it on the substrate. The extension direction of the second segment is parallel to the linewidth extension direction of the first part of the clock signal line.

2. The irregularly shaped display panel according to claim 1, wherein, The first edge of the shift register extends in a direction that is parallel to or consistent with the extension direction of the first sub-boundary. The first edge is the inner edge of the shift register that is close to the first sub-boundary.

3. The irregularly shaped display panel according to claim 1, wherein, The first edge of the shift register extends in a direction perpendicular to the row direction.

4. The irregularly shaped display panel according to any one of claims 1 to 3, wherein, Any two adjacent clock signal lines have the same line width. Among the multiple clock signal lines: the clock signal line furthest from the display area is defined as the first target clock signal line, and the remaining clock signal lines are the second target clock signal lines. The orthographic projection of the second segment of each of the adapter lines onto the substrate passes through all the second target clock signal lines and overlaps with the orthographic projection of the first target clock signal line onto the substrate.

5. The irregularly shaped display panel according to any one of claims 1 to 4, wherein, The surrounding area also includes a frame area, where at least one clock signal line is located within the frame area, and each clock signal line includes multiple openings; The area of ​​the orthographic projection of the adapter cable onto the substrate is equal to the area of ​​the overlapping region formed by the orthographic projection of the openings on at least two of the clock signal lines onto the substrate.

6. The irregularly shaped display panel according to any one of claims 1 to 5, further comprising: A gate metal layer and a source / drain metal layer, wherein the gate metal layer is located between the substrate and the source / drain metal layer; Multiple clock signal lines are located in the gate metal layer, and multiple adapter lines are located in the source-drain metal layer; The irregularly shaped display panel further includes a plurality of first connection portions, which are located on the side of the source / drain metal layer away from the gate metal layer. Each first connection portion includes a first connection sub-part and a second connection sub-part. The orthographic projection of the first connection sub-part on the substrate overlaps with the orthographic projection of the adapter line on the substrate, and the first connection sub-part is connected to the adapter line. The orthographic projection of the second connection sub-part on the substrate overlaps with the clock signal line, and the second connection sub-part is connected to the clock signal line.

7. The irregularly shaped display panel according to claim 6, wherein, The irregularly shaped display panel further includes a transparent electrode layer, which is located on the side of the source / drain metal layer opposite to the gate metal layer. The sub-pixel includes a pixel electrode, which is located in the transparent electrode layer; wherein the first connection portion is in the same layer as the pixel electrode.

8. The irregularly shaped display panel according to any one of claims 1 to 7, wherein, Also includes: Multiple data signal lines are located in the display area. The multiple data signal lines extend along the column direction and are arranged in the row direction. The multiple data signal lines are located in the source and drain metal layers. Multiple scan signal lines are located in the display area, extending along the row direction and arranged in the column direction, and located in the gate metal layer; wherein, the gate metal layer is located between the substrate and the source / drain metal layer; Along the first reference line, the peripheral area is divided into two sub-peripheral areas, and the display area is divided into two sub-display areas. The first reference line is the extension of the center line connecting the multiple scanning signal lines. Along the column direction, the sub-peripheral area includes a first border area and a second border area, and the irregular display panel also includes a bonding area. Along the column direction, the first border area, the multiple data signal lines and the bonding area are arranged in sequence. The first border area includes a first area and a second area. The first area overlaps with the gate driving circuit, and the second area does not overlap with the gate driving circuit. Two first short-circuit rings, one of which is located in one of the sub-peripheral regions; the first short-circuit ring includes: a first sub-segment, a second sub-segment, and a third sub-segment; In a short-circuit loop: the second sub-segment is located in the first bezel area and between the gate driving circuit and the display area, and the second sub-segment is connected to the end of all the data signal lines in its corresponding sub-display area away from the bonding area; the third sub-segment is located in the second area of ​​the first bezel area; the first sub-segment is located on the side of the clock signal line away from the gate driving circuit and extends from the bonding area to the second area of ​​the first bezel area, and is connected to the second sub-segment through the third sub-segment.

9. The irregularly shaped display panel according to claim 8 further includes multiple output signal lines, and one of the shift registers is connected to one of the scan signal lines through one of the output signal lines; the output signal lines, the second sub-segment, and the data signal lines are on the same layer.

10. The irregularly shaped display panel according to claim 8 or 9, further comprising: A gate metal layer and a source / drain metal layer, wherein the gate metal layer is located between the substrate and the source / drain metal layer; Multiple clock signal lines are located in the gate metal layer, and multiple adapter lines are located in the source-drain metal layer; The irregularly shaped display panel also includes: Multiple scan signal line extensions are located in the peripheral area. The multiple scan signal line extensions are on the same layer as the scan signal lines, and the extension directions of the scan signal line extensions are consistent with those of the scan signal lines. Along the row direction, one scan signal line extension is located on one side of a scan signal line and is connected to the scan signal line. A plurality of second connection portions are located in the peripheral region, and the plurality of second connection portions are located on the side of the source / drain metal layer opposite to the gate metal layer; the second connection portion includes a third connection sub-portion and a fourth connection sub-portion, the orthographic projection of the third connection sub-portion of the second connection portion on the substrate overlaps with the orthographic projection of the output signal line on the substrate, and the third connection sub-portion of the second connection portion is connected to the output signal line; the orthographic projection of the fourth connection sub-portion of the second connection portion on the substrate overlaps with the orthographic projection of the scan signal line extension on the substrate, and the fourth connection sub-portion of the second connection portion is connected to the scan signal line extension.

11. The irregularly shaped display panel according to claim 10, wherein, The irregularly shaped display panel further includes a transparent electrode layer, which is located on the side of the source / drain metal layer opposite to the gate metal layer. The sub-pixel includes a pixel electrode located in the transparent electrode layer; wherein the second connection portion is in the same layer as the pixel electrode.

12. The irregularly shaped display panel according to any one of claims 8 to 11, further comprising a plurality of switching units and two second short-circuit rings; Multiple switching units are located between the second sub-segment and the display area. The first end of each switching unit is connected to the first short-circuit ring, the second end of each switching unit is connected to the data signal line, and the control end of each switching unit is connected to the second short-circuit ring. The second short-circuit loop includes: The fourth, fifth, and sixth sub-segments; The fifth sub-segment is located in the first border area, and the fifth sub-segment is located between the gate driving circuit and the second sub-segment. The fifth sub-segment is connected to the control terminals of all the switching units in the same sub-peripheral area. The sixth sub-segment is located in the second area of ​​the first border area; the fourth sub-segment is located between the first sub-segment and the clock signal line, and the fourth sub-segment extends from the bonding area to the second area of ​​the first border area, and is connected to the fifth sub-segment through the sixth sub-segment.

13. The irregularly shaped display panel according to claim 12, wherein, The second short-circuit ring and the scan signal line are on the same layer, and the second connection portion is projected onto the substrate and is located between the projections of the first short-circuit ring and the second short-circuit ring onto the substrate.

14. The irregularly shaped display panel according to claim 12 or 13, wherein, The pixel unit includes three sub-pixels; In the multiple rows of pixel units corresponding to the first sub-boundary of the display area, along the direction from the first border area to the second border area, there are two adjacent rows of pixel units, which are the nth pixel unit row and the (n+1)th pixel unit row, respectively. The number of pixel units in the nth pixel unit row is less than the number of pixel units in the (n+1)th pixel unit row; n is a positive integer. The (n+1)th pixel unit row includes at least one (n+1)th target pixel unit. Along the column direction, the (n+1)th target pixel unit does not overlap with the nth pixel unit row. The (n+1)th target pixel unit and the nth pixel unit row form the nth step area. A switch unit connected to the same data signal line as one of the sub-pixels in the (n+1)th target pixel unit is defined as the (n+1)th target switch unit. Multiple (n+1)th target switch units are located in the nth step area, in the same row as the nth pixel unit, and are arranged along the row direction.

15. The irregularly shaped display panel according to claim 14, wherein, The (n+1)th target switch unit has one side edge away from the (n+1)th pixel unit row and overlaps with the nth pixel unit row in the row direction. The (n+1)th target switch unit has one side edge away from the nth pixel unit row and overlaps with the (n+1)th pixel unit row in the column direction.

16. The irregularly shaped display panel according to claim 12 or 13, wherein, The pixel unit includes three sub-pixels; In the multiple rows of pixel units corresponding to the first sub-boundary of the display area, along the direction from the first border area to the second border area, there are three rows of pixel units arranged in sequence, namely: the nth pixel unit row, the (n+1)th pixel unit row and the (n+2)th pixel unit row. The number of pixel units in the nth pixel unit row, the (n+1)th pixel unit row, and the (n+2)th pixel unit row gradually increases; The (n+2)th pixel unit row includes at least one (n+2)th target pixel unit. Along the column direction, the (n+2)th target pixel unit does not overlap with the (n+1)th pixel unit row, and the (n+2)th target pixel unit and the (n+1)th pixel unit row form the (n+1)th step area. The (n+1)th pixel unit row includes at least one (n+1)th target pixel unit. Along the column direction, the (n+1)th target pixel unit does not overlap with the nth pixel unit row. The (n+1)th target pixel unit and the nth pixel unit row form the nth step area. A switching unit that is connected to the same data signal line as one of the sub-pixels in the (n+2)th target pixel unit is defined as the (n+2)th target switching unit, and the sub-pixels in the multiple (n+2)th target switching units are arranged in two rows and multiple columns. The (n+2)th target switch unit in the first row is located within the (n+1)th step area and is in the same row as the (n+1)th pixel unit. The (n+2)th target switch unit in the second row is in the same row as the nth pixel unit and is located on the side of the nth step area away from the nth pixel unit row.

17. The irregularly shaped display panel according to claim 16, wherein, A switch unit connected to the same data signal line as one of the sub-pixels in the (n+1)th target pixel unit is defined as the (n+1)th target switch unit. Sub-pixels in multiple (n+1)th target switch units are arranged in two rows and multiple columns. The (n+1)th target switch units in the first row are located in the nth step area and are in the same row as the (n+2)th target switch units and the nth pixel unit in the second row.

18. The irregularly shaped display panel according to claim 16 or 17, wherein, The ratio of the number of the (n+2)th target switch unit described in the first row to the number of the (n+2)th target switch unit described in the second row is 1:

2.

19. The irregularly shaped display panel according to any one of claims 10 to 16, further comprising: The third connection part is on the same layer as the second sub-segment of the first short-circuit ring. One end of the third connection part is connected to the second sub-segment of the first short-circuit ring in one of the sub-display areas, and the other end of the third connection part is connected to the second sub-segment of the first short-circuit ring in another sub-display area. The fourth connection part is on the same layer as the fifth sub-segment of the second short-circuit ring. One end of the fourth connection part is connected to the fifth sub-segment of the second short-circuit ring in one of the sub-display areas, and the other end of the fourth connection part is connected to the fifth sub-segment of the second short-circuit ring in another sub-display area.

20. The irregularly shaped display panel according to claim 19, wherein, The third sub-segment of the first short-circuit ring includes a first part and a second part. The first part of the third sub-segment is on the same layer as the first sub-segment of the first short-circuit ring and is connected to the first sub-segment of the first short-circuit ring. The second part of the third sub-segment is on the same layer as the second sub-segment of the first short-circuit ring and is connected to the second sub-segment of the first short-circuit ring. The orthographic projection of the second part of the third sub-segment onto the substrate overlaps with the orthographic projection of the fourth connecting part onto the substrate.

21. A display device, comprising: The cover plate and the irregularly shaped display panel as described in claims 1 to 20, wherein the cover plate is located on the light-emitting side of the irregularly shaped display panel.

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