Display driver chip, display control method, and related device

Abstract

The present application relates to the field of display, and discloses a display driver chip, a display control method, and a related device. The display driver chip comprises: an interface unit, which is used for receiving input data signals transmitted from a first quantity of input ends; a plurality of data processing units, wherein each data processing unit is connected to the interface unit, and each data processing unit comprises a data decompressor and a decoder; a plurality of data storage units, wherein each data storage unit is connected to one corresponding data processing unit, and each data storage unit is used for storing decoded signals of a second quantity of input ends; and a plurality of output units, wherein the second quantity of output units are connected to one data storage unit by means of respective corresponding data transmission units, respectively, each output unit is used for outputting output data signals of a plurality of display columns or display rows, and the first quantity is greater than the second quantity.

Description

A display driver chip, display control method and related equipment Technical Field

[0001] The present disclosure relates to the field of display, and in particular to a display driver chip, a display control method, and related devices. Background Art

[0002] To meet the demand for narrow bezels, display driver chips must be as low as possible. Ultra-high output channel chips require more area than conventional chips to accommodate output ports and related analog designs, and the chip is also longer. This shape poses significant challenges to digital automatic layout, routing, and memory placement.

[0003] Current display driver chips have a limited number of output channels. In order to increase the number of channels, the length of the chip must be increased, resulting in a significant decrease in winding efficiency in the design. As the chip length increases, not only does the design complexity increase, but the power consumption and the area required for the chip also increase. In related chips, the larger the width, the more prone to voltage drop problems, requiring designers to use more power and ground pins for optimization, but the optimization effect is limited. At the same time, existing chips generally lack partition refresh functions. Due to the above limitations, current display driver chips are difficult to adapt to a wider range of resolution usage scenarios, which limits their application in diverse display needs, especially in the fields of ultra-high resolution and flexible display functions. Summary of the Invention

[0004] In order to solve the problem that current display driver chips are difficult to adapt to a wider range of resolution usage scenarios, the first aspect of the present disclosure provides a display driver chip, comprising:

[0005] an interface unit, the interface unit being configured to receive input data signals transmitted from a first number of input terminals;

[0006] a plurality of data processing units, each of the data processing units being connected to the interface unit, each of the data processing units comprising a data decompressor and a decoder, each of the data processing units being configured to perform decompression and decoding operations on the input data signals of the second number of input terminals and generate decoded signals of the second number of input terminals;

[0007] A plurality of data storage units, each of which is connected to a corresponding data processing unit, and each of which is used to store the decoded signal of the second number of input terminals

[0008] Multiple output units, a second number of the output units are respectively connected to one of the data storage units through their respective corresponding data transmission units, each of the output units is used to output output data signals for multiple display columns or display rows, wherein the first number is greater than the second number.

[0009] In some embodiments, the display driver chip further includes:

[0010] A logic integrated circuit core unit is connected to the interface unit, each of the data processing units, each of the data storage units and each of the output units respectively, and the logic integrated circuit core unit is used to control the data transmission operation of the display driver chip.

[0011] In some embodiments, the orthographic projections of each of the data transmission units in the thickness direction of the display driver chip do not overlap.

[0012] In some embodiments, each of the data storage units, each of the data processing units, the second number of the output units, and the second number of the data transmission units constitute a regional display function module, and any two of the regional display function modules have no overlap in the orthographic projection in the thickness direction of the display driver chip, and each of the regional display function modules is used to process display data of a partial display area of ​​the display unit.

[0013] In some embodiments, a distance between the data storage unit and a center line of the area display function module in a width direction is less than a preset distance.

[0014] In some embodiments, the data transmission unit includes a first data transmission unit and a second data transmission unit, the first data transmission unit is connected to the output unit and the second data transmission unit, the second data transmission unit is also connected to the data storage unit, and the second data transmission unit includes a compensation circuit, which is used for impedance matching.

[0015] In some embodiments, the first data transmission unit and the logic integrated circuit core unit do not overlap in the thickness direction of the display driver chip, and the second data transmission unit and the logic integrated circuit core unit at least partially overlap in the thickness direction of the display driver chip.

[0016] In some embodiments, the first number is twice the second number, the number of the data processing units and the number of the data storage units are 2, and each of the data storage units and each of the output units is used to process display data of 1 / 2 display area of ​​the display unit.

[0017] In some embodiments, the interface unit includes a first interface unit and a second interface unit, the first interface unit is connected to the first data processing unit, and the second interface unit is connected to the second data processing unit, the first interface unit is used to receive input data signals transmitted by a second number of input terminals, and the second interface unit is used to receive input data signals transmitted by the remaining input terminals, the distance between the interface unit and the center line of the display driver chip in the width direction is less than a preset distance, and the first interface unit and the second interface unit have no overlap in their orthographic projections in the thickness direction of the display driver chip.

[0018] In a second aspect of the present disclosure, a display control method is provided, which is used for the display driver chip according to any one of the first aspects. The method comprises:

[0019] Controlling the interface unit to receive input data signals from a first number of input terminals;

[0020] Controlling the interface unit to distribute the received input data signals of the first number of input terminals to the plurality of data processing units, so that each of the data processing units performs data decompression and decoding operations to generate decoded signals of the second number of input terminals;

[0021] controlling each of the data processing units to transmit the decoded signals of each group of the second number of input terminals to the corresponding data storage unit for data storage;

[0022] Each of the data transmission units is controlled to transmit the decoded signal stored in the data storage unit to the output unit, so that the output unit outputs output data signals of a plurality of display columns or display rows.

[0023] In some real-time implementations, the above method includes:

[0024] When the interface unit receives input data signals from a third number of input terminals, the output units corresponding to the third number of input terminals are controlled to be in a working state, and the remaining output units are controlled to be in a closed state or a dormant state, wherein the third number is smaller than the first number.

[0025] The third aspect of the present disclosure proposes an electronic device, comprising: a memory, a processor, and a computer program stored in the above-mentioned memory and executable on the above-mentioned processor, wherein the above-mentioned processor is configured to implement the steps of the display control method as described in any one of the above-mentioned second aspects when executing the computer program stored in the memory.

[0026] A fourth aspect of the present disclosure provides a display module, comprising the display driver chip according to any one of the first aspects, wherein the display module further comprises a display unit.

[0027] A fifth aspect of the present disclosure provides a display device comprising the display module described in the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 shows a schematic structural diagram of a display driver chip according to the present disclosure;

[0029] FIG2 shows a schematic structural diagram of a display driver chip in the related art;

[0030] FIG3 shows a schematic structural diagram of another display driver chip according to the present disclosure;

[0031] FIG4 shows a structural schematic diagram of another display driver chip according to the present disclosure;

[0032] FIG5 shows a structural schematic diagram of another display driver chip according to the present disclosure;

[0033] FIG6 shows a flow chart of a display control method according to the present disclosure;

[0034] FIG7 shows a schematic structural diagram of an electronic device according to the present disclosure;

[0035] FIG8 shows a schematic diagram of a display module structure according to the present disclosure;

[0036] FIG9 shows a schematic structural diagram of a display device according to the present disclosure;

[0037] The corresponding relationship between the component names and the reference numerals in Figures 1 to 5 is as follows:

[0038] 100 display driver chip; 101 interface unit; 102 data processing unit; 103 data storage unit; 104 data transmission unit; 105 output unit; 106 logic integrated circuit core unit;

[0039] 1041 first data transmission unit, 1042 second data transmission unit, 1011 first interface unit, 1012 second interface unit; 10 area display function module. DETAILED DESCRIPTION

[0040] Current display driver chips are limited by the upper limits of resolution and conventional packaging. The maximum output channel is limited to 4,000 pins, with a total length of approximately 20,000 microns, which is unable to meet the market's growing demand for resolution. Increasing the number of channels increases chip length. When the chip width reaches ~30,000 microns, the traditional data transmission architecture, which centrally processes data before transmitting it in blocks, significantly reduces digital wiring efficiency, increasing area and power consumption.

[0041] Current display driver chips support fewer than 4,000 channels. To achieve ultra-high-resolution applications, multiple chips must be cascaded to work together. This cascaded implementation increases system complexity and coordination requirements. To support more channels, the chip length increases. This increase not only results in a larger physical footprint but also creates inefficient data transmission architectures. Traditional data transmission methods in such long chip designs result in extremely low wiring efficiency, increasing the overall chip area. The increased chip width introduces significant IR drop (voltage drop). This requires designers to optimize numerous GND / POWER pins and networks. However, even with these efforts, the results may not be particularly significant, posing challenges to chip stability and performance. Furthermore, conventional chips generally lack partitioning capabilities, meaning that when partial refresh is required, all data must be updated using a full-frame refresh method. This approach not only consumes high power but also consumes a large amount of data bandwidth. Due to these limitations, current display driver chips struggle to support a wide range of resolution scenarios. This limits their application in diverse display applications, particularly in modern display technology, which demands ultra-high resolution and flexible display functionality.

[0042] Based on this, and to address some of the aforementioned issues, the present disclosure proposes a new display driver chip data transmission architecture. This architecture divides the chip into two parts, each processing and displaying data in its own block. While ensuring complete data transmission, it achieves high winding efficiency and reduces chip size. Please refer to Figure 1, which is a schematic diagram of the structure of a display driver chip 100 disclosed in the present disclosure, including:

[0043] An interface unit 101, configured to receive input data signals transmitted from a first number of input terminals;

[0044] a plurality of data processing units 102, each data processing unit 102 being connected to the interface unit 101, each data processing unit 102 comprising a data decompressor and a decoder, each data processing unit 102 being configured to perform decompression and decoding operations on the input data signals of the second number of input terminals and generate decoded signals of the second number of input terminals;

[0045] a plurality of data storage units 103, each of the data storage units 103 being connected to a corresponding data processing unit 102, and each of the data storage units 103 being configured to store decoded signals of the second number of input terminals;

[0046] Multiple output units 105, the second number of output units 105 are respectively connected to one of the data storage units 103 through their respective corresponding data transmission units 104, each of the output units 105 is used to output output data signals for multiple display columns or display rows, wherein the first number is greater than the second number.

[0047] For example, the present application proposes a display driver chip 100, which includes an interface unit 101, multiple data processing units 102, multiple data storage units 103, and multiple output units 105. The interface unit 101 is responsible for receiving data signals from a first number of input terminals. These signals may include images, videos, or other types of data, and the signal source may be a camera, media file, etc. The function of the interface unit 101 is to ensure that all input data can smoothly enter the display driver for subsequent processing.

[0048] Input data received from interface unit 101 flows to multiple data processing units 102. Each data processing unit 102 is connected to interface unit 101 and is responsible for performing preliminary processing on the received data. Each data processing unit 102 is equipped with a data decompressor and decoder for decompressing and decoding data from the second input terminal. Data processing units 102 can perform a variety of operations, ranging from compression format conversion and format parsing to color space adjustment. After processing, they generate a decoded signal for the second input terminal. The decoded signal is a more optimized and streamlined data format than the original input signal.

[0049] It should be noted that since the display driver chip 100 proposed in the present disclosure includes multiple data processing units 102, each data processing unit 102 can process data signals transmitted by the second number of input terminals. That is, each data processing unit 102 can process the data signals transmitted by some of the input terminals, and the multiple data processing units 102 can jointly complete the data signals transmitted by all of the first number of input terminals. The number of input terminals processed by different data processing units 102 can be the same or different.

[0050] The decoded data is then passed to the data storage unit 103 corresponding to each data processing unit 102. These units' primary function is to temporarily store processed data in preparation for final output. This allows the chip to effectively manage data flow, ensuring that data is securely and completely stored before output. Each data storage unit 103 is associated with a corresponding data processing unit 102, and every two data storage units 103 are used to store the decoded signals corresponding to the second number of input ports.

[0051] Each output unit 105 is connected to a specific data storage unit 103 via a data transmission unit 104 to ensure accurate data transmission, and multiple output units 105 are connected to one data storage unit 103. The task of the output unit 105 is to convert this data into a signal suitable for driving a display device, such as a TV screen or smartphone display.

[0052] As shown in Figure 2, it is a structural diagram of a display chip in the related art. The traditional data transmission architecture solution is to transmit the data corresponding to the entire chip from the middle part and then transmit it to the left and right sides in sequence. The problem brought about by this is that the chip output unit 105 needs to reserve a very wide line for routing. In addition, due to the difference in distance between the two ends and the middle, timing matching needs to be performed in the line. Timing matching requires impedance matching, which increases the difficulty of wiring and has limited adjustable accuracy. This will cause the overall height of the chip to increase, that is, the distance in the L direction increases.

[0053] FIG1 is a schematic structural diagram of a display chip proposed in the present disclosure, taking as an example a case where there are two data storage units 103 and two data processing units 102, and N output units 105, each of which is used to output an input data signal transmitted from an input terminal:

[0054] Data transmission requires that the front-end AP (Application Processor) system chip can decompose the input data signal transmitted from the first input terminal into multiple groups and transmit them separately to the display driver chip 100. After the display driver chip 100 receives the data, it enters the left and right sides of the chip according to the input ports corresponding to the parts of the picture. Multiple sets of independent data processing units 102 and data storage units 103 are placed inside the chip. The output processing unit includes a data decompressor and decoder. The decompressor can be equipped with multiple sets of decoder addresses. The number of decoder addresses depends on the amount of data. Multiple sets of independent data storage units 103 are used for the decompressor and for the interaction of image quality optimization IP data.

[0055] On the output side, the entire chip is also divided into multiple sections. The number of input terminals is divided into multiple output units 105. The number of output units 105 can be equal to or less than the number of input terminals. When the entire display is required, all output units 105 are used for display. However, when only part of the display is required, such as when the local display / resolution is compatible, the output units 105 corresponding to the unneeded portion are disabled, and only the output units 105 corresponding to the modules requiring display are enabled for data transmission, which can reduce the digital power consumption of these modules.

[0056] Because the chip's internal data architecture has broken the chip into multiple components with minimal interaction, digital APR (Automatic Place and Route) routing eliminates the need for back-and-forth routing of traces in the middle, significantly reducing the chip's height (or L dimension). This back-and-forth routing increases trace width and distance, necessitating multiple buffers to increase thrust.

[0057] In summary, the display driver chip 100 proposed in the present disclosure transmits the input data signal transmitted from the first number of input terminals to multiple functional areas for data processing, and each functional area corresponds to a data processing unit 102, a data storage unit 103 and multiple output units 105. By processing part of the input signal respectively by different functional areas, the winding efficiency can be improved, the area and power consumption can be reduced, and the overall data transmission efficiency can be improved. Through the above-mentioned area functions, the display driver chip 100 proposed in the present application can allow local refresh rather than full frame refresh by setting multiple output units 105, each or more input terminals corresponding to an output unit 105, which can reduce power consumption and the demand for data bandwidth. The display driver chip 100 proposed in the present disclosure can adapt to a wider range of resolutions, thereby providing greater flexibility and applicability, and can improve winding efficiency while maintaining data integrity, which helps to reduce the overall size of the chip, making it more suitable for compact design needs and meeting narrow frame and thin design requirements.

[0058] In some examples, the display driver chip 100 further includes:

[0059] The logic integrated circuit core unit 106 is respectively connected to the interface unit 101, each of the data processing units 102, each of the data storage units 103 and each of the output units 105. The logic integrated circuit core unit 106 is used to control the data transmission operation of the display driver chip 100.

[0060] For example, as shown in FIG3 , another structural schematic diagram of a display driver chip is disclosed. The logic integrated circuit core unit 106 is connected to the interface unit 101, each of the data processing units 102, each of the data storage units 103, and each of the output units 105. The logic core unit is responsible for coordinating and controlling all data flows and processing operations. It manages the data received from the interface unit 101, ensures that the data is effectively distributed to the various data processing units 102, and flows correctly from these units to the data storage unit 103. In the data processing unit 102, the logic core unit controls the decompression and decoding process of the data to ensure that each unit effectively performs its assigned task. At the same time, it monitors and manages the storage of data in the storage unit to ensure the security and integrity of the data. In the output stage, the logic core unit controls how the data flows from the storage unit to the output unit 105, and is ultimately converted into a signal for driving the display device.

[0061] In some examples, the orthographic projections of each of the data transmission units 104 in the thickness direction of the display driver chip 100 do not overlap.

[0062] For example, the data transmission units 104 are arranged so that they do not overlap across the thickness of the chip. This ensures that the data transmission units 104 do not overlap across the thickness of the chip, reducing electrical interference and improving data transmission efficiency and reliability. This layout helps maximize the use of limited space, making the chip thinner and lighter. Avoiding overlap improves thermal management, as the space between units serves as a channel for heat dissipation, preventing overheating.

[0063] In some examples, each of the data storage units 103, each of the data processing units 102, the second number of the output units 105, and the second number of the data transmission units 104 constitute a regional display function module 10, and any two of the regional display function modules 10 have no overlap in the orthographic projection in the thickness direction of the display driver chip 100, and each of the regional display function modules 10 is used to process display data of a partial display area of ​​the display unit.

[0064] Exemplarily, as shown in FIG4 , it is a structural schematic diagram of another display driver chip provided by the present disclosure. The regional display function module 10 includes a data storage unit 103, a data processing unit 102, an output unit 105 and a data transmission unit 104. The display unit can be divided into multiple areas, and each regional display function module 10 is responsible for processing the display data of a part of the display area of ​​the display unit. In the thickness direction of the display driver chip 100, there is no overlap in the projections of any two regional display function modules 10, which ensures that the space inside the chip is efficiently utilized while avoiding electrical interference between modules. Each regional display function module 10 can correspond to the corresponding display area in space to avoid large-scale wiring of the regional display function module 10.

[0065] In some examples, the distance between the data storage unit 103 and the center line of the area display function module 10 in the width direction is less than a preset distance.

[0066] For example, as shown in Figure 4, the data on one side will be transmitted from the middle interface to both sides, and then evenly dispersed from the middle parts of both sides to the upper output module. The data flow can be evenly distributed in the chip, and there will be no situation where a certain area requires most of the computing power, which effectively reduces the local voltage drop caused by uneven digital power consumption.

[0067] Taking Figure 4 as an example, the regional display function module 10 can be 2, and the regional display function module 10 can be symmetrically arranged about the center of the display driver chip in the W direction. The distance between the data storage unit 103 and the midline of the regional display function module 10 in the width direction W is less than the preset distance. The data storage unit 103 can be set at about 1 / 4 of the chip in the W direction. Compared with the conventional architecture, the required impedance matching length is shortened by nearly half, and there is no need to concentrate the lines corresponding to all the transmission units 104 in the output module, which greatly reduces the height of the chip and reduces the chip cost and stability.

[0068] In some examples, the data transmission unit 104 includes a first data transmission unit 1041 and a second data transmission unit 1042, the first data transmission unit 1041 is connected to the output unit 105 and the second transmission unit 1042, the second transmission unit 1042 is also connected to the data storage unit 103, and the second data transmission unit 1042 includes a compensation circuit, which is used for impedance matching.

[0069] For example, as shown in Figure 5, the first data transmission unit 1041 is connected to the output unit 105 and the second data transmission unit 1042. The second data transmission unit 1042 is responsible for transmitting the processed data to the first data transmission unit 1041, and the first data transmission unit 1041 is responsible for transmitting the data to the output unit 105, which then transmits the data to the corresponding display unit. The second data transmission unit 1042 is connected to the first data transmission unit 1041 and the data storage unit 103. It not only performs the task of data transmission, but also includes a compensation circuit. The main function of the compensation circuit is to perform impedance matching, which can reduce signal reflection and loss, and improve the quality and stability of signal transmission.

[0070] In some examples, the first data transmission unit 1041 does not overlap with the logic integrated circuit core unit 106 in the thickness direction of the display driver chip 100 , and the second data transmission unit 1042 at least partially overlaps with the logic integrated circuit core unit 106 in the thickness direction of the display driver chip 100 .

[0071] For example, the orthographic projection of the first data transmission unit 1041 in the chip thickness direction does not overlap with the logic core unit, optimizing the use of internal space, thereby improving signal integrity and layout efficiency. The second data transmission unit 1042 at least partially overlaps with the logic core unit in the thickness direction. In a certain area of ​​the chip, the two units share the same space in the vertical direction. This can make rational use of space. By adjusting the overlapping and non-overlapping layout of the units in the thickness direction, the internal space of the chip can be more effectively utilized.

[0072] In some examples, the first number is twice the second number, the number of the data processing units 102 and the number of the data storage units 103 are 2, and each of the data storage units 103 and each of the output units 105 is used to process display data of the display area of ​​the display unit 1 / 2.

[0073] For example, FIG1 is a schematic structural diagram of a display chip proposed in the present disclosure, taking the case where there are two data storage units 103 and two data processing units 102, and N output units 105, each of which is used to output an input data signal transmitted from an input terminal as an example:

[0074] Data transmission requires that the front-end AP system chip split the input data signals transmitted from the first number of input terminals into evenly distributed data and transmit them to the display driver chip 100. (The data input from the first to the N / 2th input terminals represents the display screen in the left image of the display device, and the data input from the N / 2+1th to the Nth input terminals represents the display screen in the right image of the display device.) After receiving the data, the display driver chip 100 enters the left and right sides of the chip according to the corresponding input ports in the left and right images. Two separate data processing units 102 and data storage units 103 are placed inside the chip. The output processing unit includes a data decompressor and decoder. The decompressor can contain multiple sets of decoder addresses, and the number of decoder addresses depends on the data volume. The two separate data storage units 103 are used for the decompressor and for interactive use of image quality optimization IP data.

[0075] On the output side, the entire chip is also divided into two parts, left and right. Each side is further divided into multiple output modules (output modules 1 to N) based on the number of input terminals. Each sub-module corresponds to a display resolution of 1 / A of the total number. When full display is required, all input terminals are output to the sub-modules as required for display. However, when only a portion of the modules need to be displayed, such as when local display / resolution compatibility is required, the output units 105 corresponding to the unneeded portions are disabled, leaving only the output units 105 corresponding to the modules requiring display open for data transmission, reducing the digital power consumption of these modules.

[0076] Because the chip's internal data architecture splits the left and right halves, interaction between the two is minimal. Automatic Place and Route (APR) routing eliminates the need for back-and-forth routing of the middle portion, significantly reducing the chip's height (or L dimension). This back-and-forth routing increases trace width and distance, necessitating multiple buffers to increase thrust.

[0077] In some examples, the interface unit 101 includes a first interface unit 1011 and a second interface unit 1012, the first interface unit 1011 is connected to the first data processing unit 1021, and the second interface unit 1012 is connected to the second data processing unit 1022, the first interface unit 1011 is used to receive input data signals transmitted from the second number input end, and the second interface unit 1012 is used to receive the remaining input data signals, the distance between the interface unit 101 and the center line of the display driver chip 100 in the width direction is less than a preset distance, and the first interface unit 101 and the second interface unit 101 have no overlap in their orthographic projections in the thickness direction of the display driver chip 100.

[0078] Exemplarily, as shown in FIG5 , a structural schematic diagram of a display driver chip is provided for the present disclosure. The interface unit 101 includes a first interface unit 101 and a second interface unit 101. The first interface unit 101 is directly connected to the first data processing unit 102 and receives a portion of the input data signal. The second interface unit 101 is connected to the second data processing unit 102 and receives the remaining input data signal. The distance between the interface unit 101 and the midline of the display driver chip 100 in the width direction (W direction in the figure) is less than the preset distance, that is, the interface unit 101 is close to the center of the chip. Such a layout helps to minimize the signal transmission distance, thereby possibly reducing delay and signal attenuation. In the thickness direction of the chip, the orthographic projections of the first interface unit 1011 and the second interface unit 1012 do not overlap. Such a design ensures that each interface unit occupies an independent position in the vertical space of the chip, reduces physical interference in the design, improves signal integrity, and reduces chip thickness.

[0079] In some embodiments, the two data processing units are symmetrically arranged with respect to the interface unit in the width direction of the display chip, and the two data storage units are symmetrically arranged with respect to the interface unit in the width direction of the display chip.

[0080] For example, two data processing units and two data storage units are arranged symmetrically across the width of the display chip around the interface unit. This layout can balance the data processing load, improving processing efficiency and speed. For the data storage units, the same symmetrical arrangement helps balance storage access, reduce data access latency, and improve overall performance. This symmetrical arrangement ensures a more balanced distribution of processing and storage tasks on the chip, thereby improving overall performance. It helps reduce the distance data must travel within the chip, thereby reducing latency. This balanced load distribution enables the chip to process and store data more efficiently. The symmetrical layout also helps achieve even heat distribution on the chip, reducing the risk of overheating.

[0081] In the second aspect, please refer to FIG6 , which is a flow chart of a display control method proposed in the present disclosure. The method is used in the display driver chip 100 according to any one of the first aspects. The method includes:

[0082] S210, controlling the interface unit 101 to receive input data signals from a first number of input terminals;

[0083] Exemplarily, the control unit activates the interface unit 101 to receive input data signals from the first number of input terminals. These data signals may include video, image or other graphic data, and the input data signals are used to display a picture.

[0084] S220, controlling the interface unit 101 to distribute the received input data signals of the first number of input terminals to the plurality of data processing units 102, so that each of the data processing units 102 performs data decompression and decoding operations to generate decoded signals of the second number of input terminals;

[0085] Exemplarily, the interface unit 101 distributes the received data signal to a plurality of data processing units 102. Each data processing unit 102 is responsible for processing a portion of the data, utilizing the advantages of parallel processing to improve the efficiency of data processing and perform data decompression and decoding.

[0086] S230, controlling each of the data processing units 102 to transmit the decoded signals of each group of the second number of input terminals to the corresponding data storage unit 103 for data storage;

[0087] Exemplarily, each data processing unit 102 transmits the decoded signals of the second number of input terminals it is responsible for to the corresponding data storage unit 103 for storage. The decoded data signals are stored to prepare for the next output and provide a data buffer to balance the speed difference between processing and output.

[0088] S240 , controlling each of the data transmission units 104 to transmit the decoded signal stored in the data storage unit 103 to the output unit 105 , so that the output unit 105 outputs output data signals for a plurality of display columns or display rows.

[0089] Exemplarily, each data transmission unit 104 is controlled to transmit the decoded signal stored in the data storage unit 103 to the output unit 105. The output unit 105 generates an output data signal for controlling the display screen, such as display columns or display rows, according to the received decoded signal.

[0090] In summary, the control method of the display driver chip 100 proposed in the present disclosure transmits the input data signal transmitted from the first number of input terminals to multiple functional areas for data processing, each functional area corresponds to a data processing unit 102, a data storage unit 103 and multiple output units 105, and processes part of the input signal respectively through different functional areas, which can improve the winding efficiency, reduce the area and power consumption, and thus improve the overall data transmission efficiency. Through the above-mentioned zone functions, the display driver chip 100 proposed in the present application can allow local refresh rather than full frame refresh by setting multiple output units 105, each one or more input terminals corresponding to an output unit 105, which can reduce power consumption and the demand for data bandwidth. The control method of the display driver chip 100 proposed in the present disclosure can adapt to a wider range of resolutions, thereby providing greater flexibility and applicability.

[0091] In some examples, the above method includes:

[0092] When the interface unit 101 receives input data signals from a third number of input terminals, the output units 105 corresponding to the third number of input terminals are controlled to be in a working state, and the remaining output units 105 are controlled to be in a closed state or a dormant state, wherein the third number is smaller than the first number.

[0093] For example, when the interface unit 101 receives input data signals from a third number of input terminals, that is, only part of the input terminals input data signals, only local display is required, and the output units 105 corresponding to the parts that do not need to be displayed are closed. Only the output units 105 corresponding to the modules that need to be displayed are opened for data transmission, which can reduce the digital power consumption corresponding to these modules.

[0094] As shown in Figure 7, the present disclosure also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor. When the processor 320 executes the computer program 311, the steps of any of the above-mentioned display control methods are implemented.

[0095] The devices used to implement the methods disclosed herein fall within the scope of protection to be provided by this application.

[0096] During the specific implementation process, when the computer program 311 is executed by the processor, any implementation method of the embodiments corresponding to the second aspect can be implemented.

[0097] As shown in FIG. 8 , the present disclosure further provides a display module 1000 . The display module 1000 further includes the display driver chip 100 described in the first aspect, and further includes a display unit 200 .

[0098] As shown in FIG. 9 , the present disclosure further provides a display device 2000 , and the display module 2000 further includes the display module 1000 .

[0099] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0100] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0101] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0102] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0103] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0104] The present disclosure also provides a computer program product comprising computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the product identification process in the industrial production line in the corresponding embodiment.

[0105] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)).

[0106] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0107] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0108] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0109] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0110] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0111] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display driver chip, comprising: an interface unit, the interface unit being configured to receive input data signals transmitted from a first number of input terminals; a plurality of data processing units, each of the data processing units being connected to the interface unit, each of the data processing units comprising a data decompressor and a decoder, each of the data processing units being configured to perform decompression and decoding operations on the input data signals of the second number of input terminals and generate decoded signals of the second number of input terminals; a plurality of data storage units, each of the data storage units being connected to a corresponding data processing unit, and each of the data storage units being used to store decoded signals of the second number of input terminals; Multiple output units, a second number of the output units are respectively connected to one of the data storage units through their respective corresponding data transmission units, each of the output units is used to output output data signals for multiple display columns or display rows, wherein the first number is greater than the second number.

2. The display driver chip according to claim 1, further comprising: A logic integrated circuit core unit is connected to the interface unit, each of the data processing units, each of the data storage units and each of the output units respectively, and the logic integrated circuit core unit is used to control the data transmission operation of the display driver chip. 3 . The display driver chip according to claim 1 , wherein the orthographic projections of each of the data transmission units in the thickness direction of the display driver chip have no overlap.

4. The display driver chip according to claim 1, each of the data storage units, each of the data processing units, the second number of the output units, and the second number of the data transmission units constitute a regional display function module, and any two of the regional display function modules have no overlap in the orthographic projection in the thickness direction of the display driver chip, and each of the regional display function modules is used to process display data of a partial display area of ​​the display unit. 5 . The display driver chip according to claim 4 , wherein a distance between the data storage unit and a center line of the regional display function module in a width direction is less than a preset distance.

6. The display driver chip according to claim 2, wherein the data transmission unit comprises a first data transmission unit and a second data transmission unit, the first data transmission unit is connected to the output unit and the second data transmission unit, the second data transmission unit is further connected to the data storage unit, and the second data transmission unit comprises a compensation circuit, and the compensation circuit is used for impedance matching.

7. The display driver chip according to claim 6, wherein the first data transmission unit and the logic integrated circuit core unit do not overlap in a thickness direction of the display driver chip, and the second data transmission unit and the logic integrated circuit core unit at least partially overlap in the thickness direction of the display driver chip.

8. The display driver chip according to claim 1, wherein the first number is twice the second number, the number of the data processing units and the number of the data storage units are both 2, and each of the data storage units and each of the output units is used to process display data of 1 / 2 display area of ​​the display unit.

9. According to the display driver chip of claim 8, the interface unit includes a first interface unit and a second interface unit, the first interface unit is connected to the first data processing unit, and the second interface unit is connected to the second data processing unit, the first interface unit is used to receive input data signals transmitted by the second number of input terminals, and the second interface unit is used to receive input data signals transmitted by the remaining input terminals, the distance between the interface unit and the center line of the display driver chip in the width direction is less than a preset distance, and the first interface unit and the second interface unit have no overlap in their orthographic projections in the thickness direction of the display driver chip. 10 . The display driver chip according to claim 8 , wherein the two data processing units are symmetrically arranged with respect to the interface unit in a width direction of the display chip, and the two data storage units are symmetrically arranged with respect to the interface unit in the width direction of the display chip.

11. A display control method, used in the display driver chip according to any one of claims 1 to 8, the method comprising: Controlling the interface unit to receive input data signals from a first number of input terminals; Controlling the interface unit to distribute the received input data signals of the first number of input terminals to the plurality of data processing units, so that each of the data processing units performs data decompression and decoding operations to generate decoded signals of the second number of input terminals; controlling each of the data processing units to transmit the decoded signals of each group of the second number of input terminals to the corresponding data storage unit for data storage; Each of the data transmission units is controlled to transmit the decoded signal stored in the data storage unit to the output unit, so that the output unit outputs output data signals of a plurality of display columns or display rows.

12. The display control method according to claim 11, further comprising: When the interface unit receives input data signals from the third number of input terminals, the output units corresponding to the third number of input terminals are controlled to be in a working state, and the remaining output units are controlled to be in a closed state or a dormant state.

13. An electronic device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the display control method according to claim 11 or 12 when executing the computer program stored in the memory.

14. A display module, comprising the display driver chip according to any one of claims 1 to 10, the display module further comprising a display unit.

15. A display device comprising the display module according to claim 14.

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