Display panel and display device

Abstract

The present disclosure relates to the technical field of display and provides a display panel and a display device. The display panel comprises a base substrate (SBT), a first gate layer (GT1), a second gate layer (GT2), a third gate layer (GT3) and a first source-drain metal layer (SD1) which are sequentially stacked. The second gate layer (GT2) is provided with a first lower scanning signal wire (GNLA). The third gate layer (GT3) is provided with a first upper scanning signal wire (GNLB). The first source-drain metal layer (SD1) has a first metal structure (MA1). An overlapping area of the orthographic projection of the first lower scanning signal wire (GNLA) on the base substrate (SBT) and the orthographic projection of the first metal structure (MA1) on the base substrate (SBT) is a first area (B1). An overlapping area of the orthographic projection of the first upper scanning signal wire (GNLB) on the base substrate and the orthographic projection of the first metal structure (MA1) on the base substrate (SBT) is a second area (A1). The second area (A1) covers the first area (B1). The display panel and the display device using the display panel can improve display uniformity.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202410185874.2, filed on February 19, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] With the development of display technology, higher requirements have been placed on the display uniformity of display panels. In existing technologies, due to the limitations of film preparation processes, key nodes of display panels have certain parasitic capacitances. Deviations in the parasitic capacitances of key nodes in the display panel affect the capacitance deviations of the overall capacitance of the display panel, affecting the display uniformity of the display panel.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] An object of the present disclosure is to provide a display panel and a display device, wherein improving the display panel helps to improve the uniformity of display.

[0007] According to a first aspect of the present disclosure, a display panel is provided, comprising a base substrate, a first gate layer, a second gate layer, a third gate layer, and a first source / drain metal layer stacked in sequence;

[0008] The second gate layer is provided with a first down-scan signal line extending in the row direction; the third gate layer is provided with a first up-scan signal line extending in the row direction; the first source-drain metal layer has a first metal structure; two ends of the first metal structure are electrically connected to the second electrode of the threshold compensation transistor and the gate of the driving transistor through vias respectively;

[0009] The gate of the threshold compensation transistor includes a bottom gate of the threshold compensation transistor located on the first lower scan signal line and a top gate of the threshold compensation transistor located on the first upper scan signal line;

[0010] An overlapping area of ​​the orthographic projection of the first down-scan signal trace on the base substrate and the orthographic projection of the first metal structure on the base substrate is a first area;

[0011] An overlapping area of ​​the orthographic projection of the first upper scan signal trace on the base substrate and the orthographic projection of the first metal structure on the base substrate is a second area;

[0012] The second area covers the first area.

[0013] According to one embodiment of the present disclosure, the display panel further includes a polysilicon semiconductor layer;

[0014] The polysilicon semiconductor layer includes a first polysilicon structure; the first polysilicon structure is located between the channel region of the data writing transistor and the first electrode of the driving transistor;

[0015] An overlapping area of ​​the orthographic projection of the first down-scan signal line on the substrate and the orthographic projection of the first polysilicon structure on the substrate is a fourth area;

[0016] An overlapping area of ​​the orthographic projection of the first upper scan signal line on the substrate and the orthographic projection of the first polysilicon structure on the substrate is a third area;

[0017] The fourth area covers the third area.

[0018] According to an embodiment of the present disclosure, the first down scan signal trace includes a first extension portion and a second extension portion;

[0019] The first extension portion is electrically connected to the second extension portion; and an orthographic projection of the second extension portion intersects an orthographic projection of the first metal structure on the substrate;

[0020] An orthographic projection of the first extension portion on the base substrate intersects with an orthographic projection of the first polysilicon structure on the base substrate, and a width of the first extension portion along a column direction is greater than a width of the second extension portion along the column direction.

[0021] According to an embodiment of the present disclosure, the display panel further includes an initialization voltage trace and a control signal trace extending along a row direction;

[0022] The orthographic projection of at least part of the control signal lines on the substrate overlaps with the orthographic projection of at least part of the initialization voltage lines on the substrate.

[0023] According to an embodiment of the present disclosure, the initialization voltage routing includes a first initialization voltage routing, a second initialization voltage routing, and a third initialization voltage routing; the first initialization voltage routing, the second initialization voltage routing, and the third initialization voltage routing are respectively used to load the first initialization voltage, the second initialization voltage, and the third initialization voltage;

[0024] The control signal routing includes a second reset signal routing, a first reset signal routing and a light emitting signal routing; the second reset signal routing is used to load the second reset signal, the first reset signal routing is used to load the first reset signal, and the light emitting signal routing is used to load the enable signal;

[0025] The orthographic projection of at least one of the second reset signal line, the first reset signal line and the light-emitting signal line on the base substrate overlaps with the orthographic projection of at least one of the first initialization voltage line, the second initialization voltage line and the third initialization voltage line on the base substrate.

[0026] According to an embodiment of the present disclosure, an orthographic projection of the second reset signal line on the substrate and an orthographic projection of the first initialization voltage line on the substrate overlap in an area;

[0027] An orthographic projection of the first reset signal line on the substrate and an orthographic projection of the second initialization voltage line on the substrate overlap each other;

[0028] An orthographic projection of the light emitting signal line on the base substrate and an orthographic projection of the third initialization voltage line on the base substrate have an overlapping area.

[0029] According to one embodiment of the present disclosure, the first gate layer is provided with a light-emitting signal trace extending in a row direction; the third gate layer is provided with a third initialization voltage trace extending in a row direction; the first source-drain metal layer has a second metal structure; and two ends of the second metal structure are electrically connected to the second electrode of the first light-emitting transistor and the second electrode of the second reset transistor through vias, respectively;

[0030] An overlapping area of ​​the orthographic projection of the third initialization voltage trace on the substrate and the orthographic projection of the second metal structure on the substrate is a sixth area;

[0031] The overlapping area of ​​the orthographic projection of the light emitting signal trace on the substrate and the orthographic projection of the second metal structure on the substrate is the fifth area;

[0032] The sixth area covers the fifth area.

[0033] According to one embodiment of the present disclosure, the polysilicon semiconductor layer includes a second polysilicon structure; the second polysilicon structure is located in the channel region of the first light emitting transistor;

[0034] An overlapping area of ​​the orthographic projection of the light emitting signal trace on the substrate and the orthographic projection of the second polysilicon structure on the substrate is an eighth area;

[0035] An overlapping area of ​​the orthographic projection of the third initialization voltage trace on the substrate and the orthographic projection of the second polysilicon structure on the substrate is a seventh area;

[0036] The eighth area covers the seventh area.

[0037] According to an embodiment of the present disclosure, the light emitting signal trace includes a third extension portion and a fourth extension portion;

[0038] The third extension portion is electrically connected to the fourth extension portion; and an orthographic projection of the fourth extension portion on the base substrate intersects with an orthographic projection of the second metal structure on the base substrate;

[0039] An orthographic projection of the third extension portion on the base substrate intersects with an orthographic projection of the second polysilicon structure on the base substrate, and a width of the third extension portion along a column direction is greater than a width of the fourth extension portion along the column direction.

[0040] According to one embodiment of the present disclosure, the polysilicon semiconductor layer includes a third polysilicon structure; the third polysilicon structure is located in the channel region of the first reset transistor;

[0041] The first gate layer is provided with a first reset signal line extending along the row direction; the third gate layer is provided with a second initialization voltage line extending along the row direction;

[0042] An overlapping area of ​​the orthographic projection of the first reset signal trace on the substrate and the orthographic projection of the third polysilicon structure on the substrate is a tenth area;

[0043] An overlapping area of ​​the orthographic projection of the second initialization voltage trace on the substrate and the orthographic projection of the third polysilicon structure on the substrate is a ninth area;

[0044] The tenth area covers the ninth area.

[0045] According to an embodiment of the present disclosure, the first reset signal trace includes a fifth extension portion and a sixth extension portion;

[0046] The orthographic projection of the fifth extension portion on the substrate intersects with the orthographic projection of the third polysilicon structure on the substrate, and the width of the fifth extension portion along the column direction is greater than the width of the sixth extension portion along the column direction.

[0047] According to one embodiment of the present disclosure, the polysilicon semiconductor layer includes a fourth polysilicon structure; the fourth polysilicon structure is located in the channel region of the second light emitting transistor;

[0048] An overlapping area of ​​the orthographic projection of the light emitting signal trace on the substrate and the orthographic projection of the fourth polysilicon structure on the substrate is a twelfth area;

[0049] An overlapping area of ​​the orthographic projection of the third initialization voltage trace on the substrate and the orthographic projection of the fourth polysilicon structure on the substrate is an eleventh area;

[0050] The twelfth area covers the eleventh area.

[0051] According to an embodiment of the present disclosure, the light-emitting signal trace includes a seventh extension portion and an eighth extension portion;

[0052] An orthographic projection of the seventh extension portion on the base substrate intersects with an orthographic projection of the fourth polysilicon structure on the base substrate, and a width of the seventh extension portion along a column direction is greater than a width of the eighth extension portion along the column direction.

[0053] According to an embodiment of the present disclosure, the first gate layer includes a second reset signal trace extending in a row direction; the third gate layer includes a first initialization voltage trace extending in a row direction;

[0054] The polysilicon semiconductor layer includes a fifth polysilicon structure; the fifth polysilicon structure is located in the channel region of the electrode reset transistor;

[0055] An overlapping area of ​​the orthographic projection of the second reset signal trace on the substrate and the orthographic projection of the fifth polysilicon structure on the substrate is a fourteenth area;

[0056] An overlapping area of ​​the orthographic projection of the first initialization voltage trace on the substrate and the orthographic projection of the fifth polysilicon structure on the substrate is a thirteenth area;

[0057] The fourteenth area covers the thirteenth area.

[0058] According to another aspect of the present disclosure, a display device is provided, comprising the display panel.

[0059] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0061] FIG1 is a schematic diagram of a film layer structure of a display panel in one embodiment of the present disclosure.

[0062] FIG2 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0063] FIG3 is a schematic diagram of a partial structure of a polysilicon semiconductor layer in one embodiment of the present disclosure.

[0064] FIG4 is a schematic diagram of a partial structure of a first gate layer in one embodiment of the present disclosure.

[0065] FIG5 is a schematic diagram of a partial structure of a second gate layer in one embodiment of the present disclosure.

[0066] FIG6 is a schematic structural diagram of a metal oxide semiconductor layer in one embodiment of the present disclosure.

[0067] FIG7 is a schematic diagram of a partial structure of a third gate layer in one embodiment of the present disclosure.

[0068] 8 is a schematic diagram of the partial structure of a polysilicon semiconductor layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer in one embodiment of the present disclosure.

[0069] FIG9 is a schematic diagram of the partial structure of the second gate layer, the metal oxide semiconductor layer, the third gate layer, and the first source-drain metal layer in one embodiment of the present disclosure.

[0070] FIG10 is a schematic diagram of the partial structure of a polysilicon semiconductor layer, a second gate layer, a metal oxide semiconductor layer, a third gate layer and a first source-drain metal layer in one embodiment of the present disclosure.

[0071] FIG11 is a schematic diagram of the partial structure of a polysilicon semiconductor layer, a first gate layer, a third gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0072] FIG12 is a schematic diagram of the partial structure of a polysilicon semiconductor layer, a first gate layer, a third gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0073] FIG13 is a schematic diagram of the partial structure of a polysilicon semiconductor layer, a first gate layer, a third gate layer, and a first source-drain metal layer in one embodiment of the present disclosure.

[0074] FIG14 is a schematic diagram showing the distribution of initialization voltage wiring and scan signal wiring in one embodiment of the present disclosure.

[0075] FIG15 is a cross-sectional view of the local structure of the second gate layer, the third gate layer and the first source-drain metal layer in one embodiment of the present disclosure.

[0076] FIG16 is a cross-sectional view of the local structure of the first gate layer, the third gate layer, and the first source-drain metal layer in one embodiment of the present disclosure.

[0077] FIG17 is a cross-sectional view of the local structure of the polysilicon semiconductor layer, the first gate layer, and the third gate layer in one embodiment of the present disclosure.

[0078] FIG18 is a cross-sectional view of the local structure of the polysilicon semiconductor layer, the first gate layer, and the third gate layer in one embodiment of the present disclosure.

[0079] FIG19 is a cross-sectional view of the local structure of the polysilicon semiconductor layer, the second gate layer, and the third gate layer in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0080] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0081] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0082] A transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), through which current can flow. The channel region is the area where current primarily flows.

[0083] The first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0084] In related technologies, the widths of the various film layers of a display panel vary due to the manufacturing process. This is manifested as parasitic capacitance deviations at key nodes of the display panel. While such parasitic capacitance deviations are unavoidable during display panel manufacturing, large deviations at key nodes can increase the overall capacitance deviation of the display panel, leading to uneven display.

[0085] Based on this, an embodiment of the present disclosure provides a display panel, referring to Figures 1 and 2, wherein the display panel includes a substrate SBT, a first gate layer GT1, a second gate layer GT2, a third gate layer GT3, and a first source / drain metal layer SD1 stacked in sequence; wherein the second gate layer GT2 is provided with a first down scan signal trace GNLA extending along a row direction DH (see Figure 5); the third gate layer GT3 is provided with a first up scan signal trace GNLB extending along a row direction DH (see Figure 7); the first source / drain metal layer SD1 has a first metal structure MA1 (see Figure 8); both ends of the first metal structure MA1 are connected to the second electrode T2D and the driver T2D of the threshold compensation transistor through vias, respectively. The gate T3G of the threshold compensation transistor is electrically connected; the gate T2G of the threshold compensation transistor includes a bottom gate T2GA of the threshold compensation transistor located on the first lower scanning signal line GNLA and a top gate T2GB of the threshold compensation transistor located on the first upper scanning signal line GNLB; the area where the orthographic projection of the first lower scanning signal line GNLA on the substrate substrate SBT overlaps with the orthographic projection of the first metal structure MA1 on the substrate substrate SBT is the first area B1; the area where the orthographic projection of the first upper scanning signal line GNLB on the substrate substrate SBT overlaps with the orthographic projection of the first metal structure MA1 on the substrate substrate SBT is the second area A1; the second area A1 covers the first area B1 (see Figure 9).

[0086] In the example of Figure 9, the second area A1 is enclosed by a dotted line; the first area B1 is also enclosed by a dotted line. The dotted line used to identify the second area A1 is a short-dashed line, while the dotted line used to identify the first area B1 is a long-dashed line. To more clearly distinguish between the first and second areas B1, the first and second areas B1 are filled with a solid gray color (the fill pattern of the first area B1 is darker than that of the second area A1).

[0087] In the embodiment of the present disclosure, the dimension of the overlapping portion of the first upper scan signal line GNLB and the first metal structure MA1 along the column direction DV is set to be larger than the dimension of the overlapping portion of the first lower scan signal line GNLA and the first metal structure MA1 along the column direction DV, so that the overlapping region of the first upper scan signal line GNLB and the first metal structure MA1 can cover the overlapping region of the first lower scan signal line GNLA and the first metal structure MA1, thereby preventing the capacitance at the first metal structure MA1 from being affected by the first lower scan signal line GNLA, so that the capacitance of the first metal structure MA1 here is only related to the first upper scan signal line GNLB, which helps to reduce the deviation of the parasitic capacitance of the first metal structure MA1 (first node N1), and further helps to reduce the deviation of the total capacitance of the display panel, thereby helping to improve the display uniformity of the display panel.

[0088] Optionally, the base substrate SBT may be an inorganic material base substrate SBT or an organic material base substrate SBT; of course, it may also be a composite substrate formed by laminating an inorganic material base substrate SBT and an organic material base substrate SBT. For example, in some embodiments of the present disclosure, the base substrate SBT may be made of a glass material such as soda-lime glass, quartz glass, or sapphire glass.

[0089] In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0090] Optionally, referring to FIG1 , in the driving layer DRL, any pixel driving circuit may include a thin film transistor and a storage capacitor CST (not shown in the drawings of this application). Furthermore, the thin film transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0091] It is understandable that, among the transistors in the pixel driving circuit, the types of any two transistors may be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again for example, in other embodiments, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0092] Optionally, referring to FIG1 , the driving layer DRL may include a semiconductor layer (e.g., a polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL) stacked between the substrate SBT and the pixel layer PIXL, a gate insulating layer (e.g., a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3), a gate layer (e.g., a first gate layer GT1, a second gate layer GT2, and a third gate layer GT3), an interlayer dielectric layer ILD, a source / drain metal layer (e.g., a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3), a planarization layer (e.g., a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3), etc. Each thin film transistor and storage capacitor CST may be formed by film layers such as a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer ILD, a source / drain metal layer, and of course, other film layers may also be used. The positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor. Furthermore, the semiconductor layer can be used to form the active layer of the transistor (including the first electrode, the second electrode and the channel region of the transistor), and can also be formed into partial wiring or conductive structure by conductorization when necessary. The first source-drain metal layer SD1 can be used to form a scan signal wiring; the gate layer can be used to form one or more gate layer wirings such as a reset control wiring and a light-emitting control wiring, and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plates of the storage capacitor CST. The source-drain metal layer can be used to form source-drain metal layer wirings such as data wiring and drive power supply voltage wiring, and can also be used to form part of the electrode plates of the storage capacitor CST.

[0093] Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may further include a metal light shielding layer BSM located between the semiconductor layer and the substrate SBT. As needed, any of the above-mentioned semiconductor layers, gate layers, source / drain metal layers and other film layers may also be multi-layered. For example, the driving layer DRL may include two different semiconductor layers, or two or three source / drain metal layers, or two or three gate layers. Accordingly, the insulating film layers in the driving layer DRL (such as a gate insulating layer, an interlayer dielectric layer ILD, a planarization layer, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0094] Optionally, the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer organic EL and a common electrode layer COML that are stacked in sequence. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of ​​the display panel. The pixel definition layer PDL has a plurality of through pixel openings that are arranged in a one-to-one correspondence with the plurality of pixel electrodes PE, and any pixel opening exposes at least a portion of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal area of ​​the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer organic EL), and thus define the light-emitting area and light-emitting area of ​​the sub-pixel. The common electrode layer COML covers the light-emitting functional layer organic EL as a common electrode. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer organic EL, so that the light-emitting functional layer organic EL emits light. The portion of the light-emitting functional layer organic EL located between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element as a sub-pixel, wherein one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel and the other serves as a cathode of the sub-pixel.

[0095] In this example, the display panel is an OLED (organic light-emitting diode) display panel. The organic EL light-emitting functional layer may include an organic light-emitting layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Furthermore, the organic light-emitting layer may include a light-emitting layer host material and a light-emitting layer guest material. The light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material.

[0096] It is understandable that the display panel may also be other types of display panels, for example, a QLED display panel, a QD-OLED display panel or other types of display panels.

[0097] Referring to Figure 1, the display panel may further include a thin film encapsulation layer TFE, which may be provided on the surface of the pixel layer PIXL away from the substrate SBT, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the pixel layer PIXL and causing aging of the material in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.

[0098] Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer (not specifically shown in this figure) stacked in sequence on the side of the pixel layer PIXL away from the substrate SBT. The first inorganic encapsulation layer covers the display area and extends to the outside of the retaining wall; the organic encapsulation layer covers the display area and extends to the inside of the retaining wall; the second inorganic encapsulation layer covers the organic encapsulation layer and extends to the outside of the retaining wall. On the outside of the retaining wall, the second inorganic encapsulation layer is in contact with the first inorganic encapsulation layer. In this way, the organic encapsulation layer is enclosed by the first inorganic encapsulation layer and the second inorganic encapsulation layer, balancing the stresses of the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first inorganic encapsulation layer and the second inorganic encapsulation layer encapsulate the organic encapsulation layer to isolate the organic encapsulation layer from contact with water and oxygen. Of course, in other embodiments of the present disclosure, the display panel may not be provided with a thin film encapsulation layer TFE, but may use other methods to encapsulate and protect the pixel layer.

[0099] In the display panel provided by the present disclosure, the pixel driving circuit includes a storage capacitor CST and multiple transistors, some of which are polysilicon transistors and others are metal oxide transistors. The pixel driving circuit may include a core module for providing a driving current. The core module may include a storage capacitor CST, a threshold compensation transistor T2, and a driving transistor T3; wherein the second electrode of the threshold compensation transistor T2, the gate of the driving transistor T3, and the first electrode plate CP1 of the storage capacitor CST are electrically connected to a first node N1, and the first electrode of the threshold compensation transistor T2 and the second electrode of the driving transistor T3 are electrically connected to a second node N2. The threshold compensation transistor T2 is a metal oxide transistor and is used to compensate for the threshold voltage of the driving transistor T3 in response to a threshold compensation signal. The driving transistor T3 is a polysilicon transistor and can generate a driving current under the control of the first node N1.

[0100] At the initial moment of the data writing phase of the pixel driving circuit, the first node N1 has been pre-reset (for example, to a negative voltage), causing the driving transistor T3 to be turned on. After entering the data writing phase, the data signal Data is written to the first node N1. The threshold compensation transistor T2 is turned on under the control of the threshold compensation signal, so that the first node N1 and the second node N2 are electrically connected. At this time, the third node N3 can be charged to the first node N1 through the driving transistor T3 and the threshold compensation transistor T2, so that the voltage of the first node N1 is pulled up to the point that the driving transistor T3 is turned off. The voltage difference between the voltage of the first node N1 and the voltage of the third node N3 is the threshold voltage of the driving transistor T3. In this way, after the data writing phase, the voltage of the first node N1 is related to the threshold voltage of the driving transistor T3 and the data signal Data, overcoming the problem of uneven threshold voltage of the driving transistor T3 due to process reasons. Of course, in the display panel of the present disclosure, in addition to the core module mentioned above, the pixel driving circuit also needs to include other transistors to realize functions such as resetting the pixel driving circuit, writing the data signal Data, and controlling the light emission of sub-pixels.

[0101] FIG2 illustrates an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure. It is understood that the pixel driving circuit according to an embodiment of the present disclosure may also be a pixel driving circuit with other structures. When the structure of the pixel driving circuit is changed, the structure of each film layer according to the embodiment of the present disclosure may also be adaptively adjusted.

[0102] In the example of FIG2 , the pixel driving circuit may include a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting transistor T5, a second light-emitting transistor T6, an electrode reset transistor T7, a second reset transistor T8, and a storage capacitor CST. The threshold compensation transistor T2 is an N-type thin film transistor, such as a metal oxide thin film transistor; the remaining thin film transistors are P-type thin film transistors, such as low-temperature polysilicon thin film transistors.

[0103] A first electrode of the first reset transistor T1 is connected to the eighth node N8. The first electrode of the first reset transistor T1 is used to apply a first initialization voltage Vinit1. The gate of the first reset transistor T1 is used to apply a first reset signal RP. A second electrode of the first reset transistor T1 is connected to the third node N3. The first reset transistor T1 is used to apply the first initialization voltage Vinit1 to the third node N3 in response to the first reset signal RP.

[0104] A first electrode of the threshold compensation transistor T2 is electrically connected to the third node N3, a second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, and a gate of the threshold compensation transistor T2 is configured to apply the first scan signal GN. The threshold compensation transistor T2 is configured to be turned on in response to the first scan signal GN and write the first initialization voltage Vinit1 applied to the first electrode of the first reset transistor T1 into the first node N1.

[0105] The first electrode of the driving transistor T3 is connected to the second node N2, the second electrode of the driving transistor T3 is connected to the third node N3, and the gate of the driving transistor T3 is connected to the first node N1. The driving transistor T3 is configured to output a driving current under the control of the voltage on the first node N1.

[0106] A first electrode of the data write transistor T4 is connected to the seventh node N7. The first electrode of the data write transistor T4 is used to load the data signal Data. A second electrode of the data write transistor T4 is electrically connected to the second node N2. A gate of the data write transistor T4 is used to load the second scan signal GP. The data write transistor T4 is used to load the data signal Data to the second node N2 in response to the second scan signal GP.

[0107] The first electrode of the first light emitting transistor T5 is connected to the fifth node N5, the first electrode of the first light emitting transistor T5 is used to load the power supply voltage VDD, the second electrode of the first light emitting transistor T5 is connected to the second node N2, and the gate of the first light emitting transistor T5 is used to load the enable signal EM.

[0108] The first electrode of the second light emitting transistor T6 is connected to the third node N3, the second electrode of the second light emitting transistor T6 is connected to the fourth node N4, and the gate of the second light emitting transistor T6 is used to load the enable signal EM. The first light emitting transistor T5 and the second light emitting transistor T6 are used to be turned on in response to the enable signal EM.

[0109] In the above-described exemplary embodiment, the first light-emitting transistor T5 and the second light-emitting transistor T6 operate in response to the same enable signal EM. In this example, the gates of the first light-emitting transistor T5 and the second light-emitting transistor T6 can be connected to the same enable light-emitting signal trace EML. It will be appreciated that in other embodiments of the present disclosure, the gates of the first light-emitting transistor T5 and the second light-emitting transistor T6 can also be connected to different light-emitting signal traces EML. In this embodiment, the light-emitting signal traces EML to which the gates of the first light-emitting transistor T5 and the second light-emitting transistor T6 are respectively connected can each be loaded with the enable signal EM, for example, at different times. This allows the first light-emitting transistor T5 and the second light-emitting transistor T6 to be turned on at different times. Of course, in other embodiments of the present disclosure, the gates of the first light-emitting transistor T5 and the second light-emitting transistor T6 can also be connected to different light-emitting signal traces EML, and both light-emitting signal traces EML can be loaded with the enable signal EM simultaneously.

[0110] A first electrode of the electrode reset transistor T7 is connected to the ninth node N9. The first electrode of the electrode reset transistor T7 is used to apply the second initialization voltage Vinit2. The gate of the electrode reset transistor T7 is used to apply the second reset signal RH. The second electrode of the electrode reset transistor T7 is connected to the fourth node N4. The electrode reset transistor T7 is used to apply the second initialization voltage Vinit2 to the fourth node N4 in response to the second reset signal RH.

[0111] A first electrode of the second reset transistor T8 is connected to the sixth node N6. The first electrode of the second reset transistor T8 is used to apply the third initialization voltage Vinit3. The gate of the second reset transistor T8 is used to apply the second reset signal RH. The second electrode of the second reset transistor T8 is connected to the second node N2. The second reset transistor T8 is used to apply the third initialization voltage Vinit3 to the second node N2 in response to the second reset signal RH.

[0112] The pixel electrode PE of the light-emitting element (not specifically shown in the drawings of this specification) is electrically connected to the pixel driving circuit, the common electrode is used to load the reference voltage VSS, one end of the storage capacitor CST is connected to the first node N1, and the other end is connected to the fifth node N5.

[0113] It should be noted that in the display panel of the present disclosure, the pixel driving circuit can reduce the leakage of the first node N1 by setting the threshold compensation transistor T2 as a metal oxide transistor, thereby improving the voltage holding capability of the pixel driving circuit, reducing the risk of flickering of the display panel under low-frequency driving, and reducing the power consumption of the display panel. However, in actual tests, it was found that during the display process of some display panels, the threshold compensation transistor T2 was easily affected by the negative or positive bias of the threshold compensation voltage, resulting in large fluctuations in the organic EL current of the organic light-emitting functional layer and deterioration of the display image quality of the display panel. The present disclosure optimizes the capacitance of the first node N1, thereby reducing the sensitivity of the voltage of the first node N1 to the change in the threshold voltage of the threshold compensation transistor T2, thereby improving the display quality of the display panel.

[0114] 8 shows a schematic diagram of a partial stacking structure of a polysilicon semiconductor layer PSCL, a second gate layer GT2, a metal oxide semiconductor layer OSCL, a third gate layer GT3, and a first source / drain metal layer SD1 in a display panel according to an example of the present disclosure. 7 and 8 , the third gate layer GT3 includes a first upper scan signal line GNLB extending along the row direction DH, and the first upper scan signal line GNLB serves as the top gate T2GB of the threshold compensation transistor T2; the second gate layer GT2 includes a first lower scan signal line GNLA extending along the row direction DH, and the first lower scan signal line GNLA serves as the bottom gate T2GA of the threshold compensation transistor T2; the first source and drain metal layer SD1 includes a first metal structure MA1 extending along the column direction DV, one end of the first metal structure MA1 is electrically connected to the second electrode T2D of the threshold compensation transistor through a first via H1, and the other end of the first metal structure MA1 is electrically connected to the gate T3G of the driving transistor through a second via H2 (see FIG8 ), and the first via H1 and the second via H2 are located on both sides of the first upper scan signal line GNLB and the first lower scan signal line GNLA, that is, the first metal structure MA1 can serve as part of the first node N1, so that the second electrode T2D of the threshold compensation transistor and the gate T3G of the driving transistor are electrically connected. The orthographic projection of the first metal structure MA1 extending along the column direction DV on the substrate SBT crosses the orthographic projections of the first lower scan signal line GNLA and the first upper scan signal line GNLB. In other words, a portion of the first metal structure MA1 is located on one side of the first upper scan signal line GNLB and the first lower scan signal line GNLA, and another portion of the first metal structure MA1 is located on the other side of the first upper scan signal line GNLB and the first lower scan signal line GNLA.

[0115] Referring to Figure 9, the first upper scanning signal line GNLB has a first protrusion SA1 on at least one side along the row direction DH, and at least a portion of the first protrusion SA1 is arranged to overlap with the first metal structure MA1; that is, by setting the first protrusion SA1 on the first upper scanning signal line GNLB, the coverage effect of the first upper scanning signal line GNLB on the first lower scanning signal line GNLA can be improved (see Figure 15).

[0116] Optionally, a first protrusion SA1 may be provided on one side of the first upper scan signal line GNLB along the row direction DH. Providing the first protrusion SA1 on one side of the first upper scan signal line GNLB may increase the width of the first upper scan signal line GNLB at the intersection with the first metal structure MA1 in the column direction DV, thereby achieving better coverage of the first lower scan signal line GNLA, thereby helping to reduce the deviation of the parasitic capacitance of the first metal structure MA1 (first node N1), thereby helping to improve the display uniformity of the display panel. Of course, the first protrusion SA1 may be provided on both sides of the first upper scan signal line GNLB along the row direction DH. The first protrusion SA1 provided on both sides may also reduce the deviation of the parasitic capacitance of the first metal structure MA1 (first node N1), thereby helping to improve the display uniformity of the display panel. In the embodiments of the present disclosure, there is no specific limitation on the number of first protrusions SA1 provided.

[0117] It can be understood that the first protrusion SA1 can be rectangular, trapezoidal or other shapes, and is not limited to the description and combination of the above embodiments.

[0118] Figure 3 shows a partial schematic diagram of the polysilicon semiconductor layer PSCL in a display panel. Referring to Figure 3 , the polysilicon pattern forms a channel region T3A of a driver transistor with semiconductor characteristics, as well as a first polysilicon strip PL1 and a second polysilicon strip PL2, which are conductive. The first polysilicon strip PL1 and the second polysilicon strip PL2 are located on either side of the driver transistor's channel region T3A. The second polysilicon strip PL2 forms part of a third node N3 and simultaneously serves as the second electrode of the data write transistor T4, the first electrode of the driver transistor T3, and the second electrode of the first light-emitting transistor T5. The first polysilicon strip PL1 forms part of a second node N2 and simultaneously serves as the second electrode of the driver transistor T3 and the second electrode of the first reset transistor T1. The driver transistor's channel region T3A is bent to extend its length.

[0119] FIG4 shows a schematic diagram of a partial structure of the first gate layer GT1 in the display panel. Referring to FIG4 , the first gate layer GT1 is provided with a first electrode plate CP1 of a storage capacitor CST and a second scan signal trace GPL extending along the row direction DH for carrying a second scan signal GP. The first electrode plate CP1 of the storage capacitor CST completely covers the channel region T3A of the drive transistor T3; that is, the orthographic projection of the channel region T3A of the drive transistor T3 on the first gate layer GT1 is located within the range of the first electrode plate CP1 of the storage capacitor CST. In this way, the first electrode plate CP1 of the storage capacitor CST can serve as the gate of the drive transistor T3.

[0120] FIG5 shows a schematic diagram of a partial structure of the second gate layer GT2 in the display panel. Referring to FIG5 , the second gate layer GT2 is provided with a second electrode plate CP2 of a storage capacitor CST corresponding to each pixel driving circuit, and a first down-scan signal trace GNLA for loading a threshold compensation signal and extending along the row direction DH. The second electrode plate CP2 overlaps with the first electrode plate CP1 of the storage capacitor CST to form the storage capacitor CST. The second electrode plate CP2 of the storage capacitor CST has an opening CP2G of the notched second electrode plate, and the opening CP2G of the notched second electrode plate exposes a portion of the first electrode plate CP1 of the storage capacitor CST, so that the first electrode plate CP1 of the storage capacitor CST can be connected to the first source-drain metal layer SD1 through a via located in the opening CP2G of the notched second electrode plate.

[0121] Figure 6 shows a schematic diagram of a partial structure of the metal oxide semiconductor layer (OSCL) in a display panel. Referring to Figure 6 , the metal oxide semiconductor layer (OSCL) has a metal oxide pattern corresponding to each pixel driver circuit. The orthographic projections of the metal oxide pattern of the pixel driver circuit and the polysilicon pattern on the substrate (SBT) do not overlap. The metal oxide pattern includes a channel region (T2A) of a threshold compensation transistor (T2) that maintains semiconductor characteristics, and a first metal oxide portion (OL1) and a second metal oxide portion (OL2) that are conductive. The first metal oxide portion (OL1) is electrically connected to the first metal structure (MA1) via a first via (H1) and serves as part of the first node (N1).

[0122] In one embodiment of the present disclosure, FIG10 shows a schematic diagram of a partial stacking structure of a polysilicon semiconductor layer PSCL, a second gate layer GT2, a third gate layer GT3, and a first source / drain metal layer in an example display panel of the present disclosure. Referring to FIG10 , the display panel further comprises a driving layer DRL provided on a base substrate SBT; the driving layer DRL comprises a pixel driving circuit for driving a sub-pixel PIX; the pixel driving circuit comprises a polycrystalline silicon semiconductor layer PSCL and a data writing transistor T4; the polycrystalline silicon semiconductor layer PSCL comprises a first polycrystalline silicon structure PLA; the first polycrystalline silicon structure PLA is located between a channel region T4A of the data writing transistor and a first electrode T3S of the driving transistor (see FIG8 ); an overlapping area of ​​an orthographic projection of the first lower scanning signal line GNLA on the base substrate SBT and an orthographic projection of the first polycrystalline silicon structure PLA on the base substrate SBT is a fourth area A2; an overlapping area of ​​an orthographic projection of the first upper scanning signal line GNLB on the base substrate SBT and an orthographic projection of the first polycrystalline silicon structure PLA on the base substrate SBT is a third area B2; the fourth area A2 covers the third area B2 (see FIG10 ). That is, the first down scan signal line GNLA can be locally widened at the intersection with the first polysilicon structure PLA, so that the first down scan signal line GNLA covers the first polysilicon structure PLA, thereby reducing the parasitic capacitance between the first polysilicon structure PLA and the first up scan signal line GNLB (see FIG19 ). Specifically, referring to FIG5 , the first down scan signal line GNLA can include a first extension portion X1 and a second extension portion X2; the first extension portion X1 is electrically connected to the second extension portion X2; the orthographic projection of the second extension portion X2 intersects with the orthographic projection of the first metal structure MA1 on the substrate SBT; the orthographic projection of the first extension portion X1 on the substrate SBT intersects with the orthographic projection of the first polysilicon structure PLA on the substrate SBT, and the width of the first extension portion X1 along the column direction DV is greater than the width of the second extension portion X2 along the column direction DV.

[0123] Optionally, the fourth region A2 includes a first side edge and a second side edge extending along the row direction DH (this is not specifically labeled in the drawings of this application), and the third region B2 includes a first inner side edge extending along the row direction DH and on the same side as the first side edge, and a second inner side edge extending along the row direction DH and on the same side as the second side edge; the first side edge and the first inner side have a first distance along the column direction DV, and the second side edge and the second inner side have a second distance along the column direction DV. The first distance can be greater than the second distance. In this configuration, the second side edge and the second inner side edge may overlap, but the first lower scan signal trace GNLA can still cover the first upper scan signal trace GNLB, reducing the impact of the first upper scan signal trace GNLB on the first polysilicon structure PLA. Similarly, the first distance can be smaller than the second distance. In this configuration, the first side edge may overlap the first inner side edge, but the first lower scan signal trace GNLA can still cover the first upper scan signal trace GNLB, reducing the impact of the first upper scan signal trace GNLB on the first polysilicon structure PLA. Of course, the first distance can be equal to the second distance. In this configuration, the first upper scan signal trace GNLB can maximize coverage of the first lower scan signal trace GNLA, thereby improving display uniformity of the display panel.

[0124] 5 and 8 , the first down-scan signal line GNLA may further include a connecting portion X21 of the second extension portion, the connecting portion X21 of the second extension portion being electrically connected to a side of the second extension portion X2 away from the first extension portion X1. Because the first metal structure MA1 is located at the first node N1, the first up-scan signal line GNLB covers the first down-scan signal line GNLA, thereby reducing the impact of the first down-scan signal line GNLA on the first metal structure MA1 within the second extension portion X2. When the first down-scan signal line GNLA is at the position corresponding to the connection portion X21 of the second extension portion, although there is an influence of the connection portion X21 of the second extension portion and the metal structure corresponding to the first source / drain metal layer SD1, its influence on the overall capacitor is relatively small. Therefore, at the position of the first down-scan signal line GNLA corresponding to the connection portion X21 of the second extension portion, the first up-scan signal line GNLB can be used to cover the first down-scan signal line GNLA. Of course, the first up-scan signal line GNLB corresponding to the connection portion X21 of the second extension portion may also not cover the first down-scan signal line GNLA corresponding to the connection portion X21 of the second extension portion.

[0125] It can be understood that the first down-scan signal line GNLA and the first up-scan signal line GNLB arranged along the row direction DH, at the position where they overlap with the first metal structure MA1, adopt a method where the first up-scan signal line GNLB partially covers the first down-scan signal line GNLA, thereby reducing the influence between the first metal structure MA1 and the first down-scan signal line GNLA. At the position where the first down-scan signal line GNLA and the first up-scan signal line GNLB overlap, the first down-scan signal line GNLA can cover the corresponding polysilicon structure to reduce the influence of the first up-scan signal line GNLB on the polysilicon semiconductor layer PSCL. The remaining portions of the first down-scan signal line GNLA and the first up-scan signal line GNLB can be adjusted according to the specific requirements of the restriction panel, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0126] In one embodiment of the present disclosure, referring to FIG. 14 , the display panel further includes an initialization voltage trace VL and a control signal trace GL extending along a row direction DH; wherein the orthographic projection of at least a portion of the control signal trace GL on the substrate substrate SBT overlaps with the orthographic projection of at least a portion of the initialization voltage trace VL on the substrate substrate SBT. It is understood that the orthographic projection of a portion of the initialization voltage trace VL on the substrate substrate SBT may overlap with a portion of the control signal trace GL on the substrate substrate SBT, and the orthographic projection of the remaining portion of the initialization voltage trace VL on the substrate substrate SBT may not overlap with the remaining portion of the control signal trace GL on the substrate substrate SBT. Of course, the orthographic projection of all traces of the initialization voltage trace VL on the substrate substrate SBT may overlap with the orthographic projection of all traces corresponding to the control signal trace GL on the substrate substrate SBT. The orthographic projection of the initialization voltage trace VL on the substrate SBT and the orthographic projection of the control signal trace GL on the substrate SBT have an overlapping area, which helps to reduce the size of the pixel driving circuit along the column direction DV, helps to improve the pixel density PPI of the display panel, and at the same time reduces the parasitic capacitance deviation of the key nodes in the display panel, thereby improving the display uniformity of the display panel.

[0127] The pixel driving circuit further includes a first reset transistor T1, an electrode reset transistor T7, a first light-emitting transistor T5, and a second reset transistor T8; the first reset transistor T1 is configured to apply a first initialization voltage Vinit1 to a first electrode of the threshold compensation transistor T2 in response to a first reset signal RP; the electrode reset transistor T7 is configured to apply a second initialization voltage Vinit2 to a pixel electrode in response to a second reset signal RH; the first light-emitting transistor T5 is configured to apply a power supply voltage VDD to a first electrode T3S of the driving transistor T3 in response to an enable signal EM; the second electrode of the driving transistor T3 is electrically connected to the first electrode T2S of the threshold compensation transistor T2; the first electrode T8S of the second reset transistor is configured to apply a third initialization voltage Vinit3, and the second electrode T8D of the second reset transistor is electrically connected to the first electrode T3S of the driving transistor T3;

[0128] The initialization voltage line VL includes a first initialization voltage line VL1, a second initialization voltage line VL2 and a third initialization voltage line VL3; the first initialization voltage line VL1, the second initialization voltage line VL2 and the third initialization voltage line VL3 are used to load the first initialization voltage Vinit1, the second initialization voltage Vinit2 and the third initialization voltage Vinit3 respectively.

[0129] The control signal line GL includes a second reset signal line RHL, a first reset signal line RPL and a light-emitting signal line EML; the second reset signal line RHL is used to load the second reset signal RH, the first reset signal line RPL is used to load the first reset signal RP, and the light-emitting signal line EML is used to load the enable signal EM.

[0130] As an example, the orthographic projection of the second reset signal line RHL on the substrate SBT and the orthographic projection of the first initialization voltage line VL1 on the substrate SBT have an overlapping area; the orthographic projection of the first reset signal line RPL on the substrate SBT and the orthographic projection of the second initialization voltage line VL2 on the substrate SBT have an overlapping area; the orthographic projection of the light-emitting signal line EML on the substrate SBT and the orthographic projection of the third initialization voltage line VL3 on the substrate SBT have an overlapping area.

[0131] In one embodiment of the present disclosure, FIG13 shows a schematic diagram of the stacked structure of the first gate layer GT1, the third gate layer GT3, and the first source and drain metal layer SD1 in the display panel of the present disclosure. Referring to FIG13, the pixel driving circuit includes a first light-emitting transistor T5 and a second reset transistor T8 (see FIG11); wherein the first gate layer GT1 is provided with a light-emitting signal trace EML extending along the row direction DH, and the light-emitting signal trace EML serves as the gate of the first light-emitting transistor T5; the third gate layer GT3 is provided with a third initialization voltage trace VL3 extending along the row direction DH; the first source and drain metal layer SD1 has a second metal structure MA2; the second metal structure One end of MA2 is electrically connected to the second electrode T5D of the first light-emitting transistor through a third via H3, and the other end of the second metal structure MA2 is electrically connected to the second electrode T8D of the second reset transistor through a fourth via H4 (see FIG13 ). The orthographic projection of the second metal structure MA2, which extends along the column direction DV, on the substrate SBT crosses the orthographic projections of the light-emitting signal trace EML and the third initialization voltage trace VL3. In other words, a portion of the second metal structure MA2 is located on one side of the light-emitting signal trace EML and the third initialization voltage trace VL3, and another portion of the second metal structure MA2 is located on the other side of the light-emitting signal trace EML and the third initialization voltage trace VL3. The overlapping area of ​​the orthographic projection of the third initialization voltage trace VL3 on the substrate SBT and the orthographic projection of the second metal structure MA2 on the substrate SBT is a sixth area A3. The overlapping area of ​​the orthographic projection of the light-emitting signal trace EML on the substrate SBT and the orthographic projection of the second metal structure MA2 on the substrate SBT is a fifth area B3. The sixth area A3 covers the fifth area B3.

[0132] The third initialization voltage trace VL3 has a second protrusion SA2 on at least one side (see FIG. 12 ), with at least a portion of the second protrusion SA2 overlapping the second metal structure MA2. In other words, providing the second protrusion SA2 on the third initialization voltage trace VL3 improves coverage of the light-emitting signal trace EML by the third initialization voltage trace VL3. Alternatively, the second protrusion SA2 may be provided on either side of the third initialization voltage trace VL3 along the row direction DH. Providing the second protrusion SA2 on one side of the third initialization voltage trace VL3 provides better coverage of the light-emitting signal trace EML, helping to reduce deviations in parasitic capacitance at the second metal structure MA2 and thereby improving display uniformity of the display panel. Of course, a second protrusion SA2 can be set on both sides of the third initialization voltage line VL3 along the row direction DH. The second protrusion SA2 set on both sides can also reduce the deviation of the parasitic capacitance at the second metal structure MA2, which helps to improve the display uniformity of the display panel. In the embodiment of the present disclosure, there is no specific restriction on the number of second protrusions SA2 (see Figure 16).

[0133] It can be understood that the second protrusion SA2 can be rectangular, trapezoidal or other shapes, and is not limited to the description and combination of the above embodiments.

[0134] In one embodiment of the present disclosure, referring to Figure 13, the polycrystalline silicon semiconductor layer PSCL includes a second polycrystalline silicon structure PLB; the second polycrystalline silicon structure PLB is located in the channel region T5A of the first light-emitting transistor; the overlapping area of ​​the orthographic projection of the light-emitting signal line EML on the substrate substrate SBT and the orthographic projection of the second polycrystalline silicon structure PLB on the substrate substrate SBT is the eighth area A4; the overlapping area of ​​the orthographic projection of the third initialization voltage line VL3 on the substrate substrate SBT and the orthographic projection of the second polycrystalline silicon structure PLB on the substrate substrate SBT is the seventh area B4; the eighth area A4 covers the seventh area B4.

[0135] In this embodiment, the light-emitting signal trace EML includes a third extension portion X3 and a fourth extension portion X4 (see Figure 4); the third extension portion X3 is electrically connected to the fourth extension portion X4; and the orthographic projection of the fourth extension portion X4 on the substrate substrate SBT intersects with the orthographic projection of the second metal structure MA2 on the substrate substrate SBT; the orthographic projection of the third extension portion X3 on the substrate substrate SBT intersects with the orthographic projection of the second polysilicon structure PLB on the substrate substrate SBT, and the width of the third extension portion X3 along the column direction DV is greater than the width of the fourth extension portion X4 along the column direction DV.

[0136] Optionally, the eighth region A4 includes a third side and a fourth side extending along the row direction DH, and the seventh region B4 includes a third inner side extending along the row direction DH and coexisting with the first side, and a fourth inner side extending along the row direction DH and coexisting with the fourth side; a third distance is defined between the third side and the third inner side along the column direction DV, and a fourth distance is defined between the fourth side and the fourth inner side along the column direction DV. The third distance may be greater than the fourth distance. In this configuration, the third side and the third inner side may overlap, but the light emitting signal trace EML can still cover the third initialization voltage trace VL3, and the coverage of the second polysilicon structure PLB by the light emitting signal trace EML can still reduce the impact of the third initialization voltage trace VL3 on the second polysilicon structure PLB. Similarly, the third distance can be smaller than the fourth distance. In this configuration, the fourth side edge may overlap the fourth inner side edge, but the light-emitting signal trace EML can still cover the third initialization voltage trace VL3. Covering the polysilicon semiconductor layer PSCL by the light-emitting signal trace EML can still reduce the impact of the third initialization voltage trace VL3 on the first polysilicon structure PLA. Of course, the third distance can be equal to the fourth distance. In this configuration, shielding of the third initialization voltage trace VL3 by the light-emitting signal trace EML can be maximized, thereby improving the display uniformity of the display panel. Furthermore, this configuration can reduce the impact of manufacturing errors during production.

[0137] In one embodiment of the present disclosure, referring to Figure 12, the pixel driving circuit includes a second light-emitting transistor T6; the polycrystalline silicon semiconductor layer PSCL includes a fourth polycrystalline silicon structure PLD; the fourth polycrystalline silicon structure PLD is located in the channel region T6A of the second light-emitting transistor; the overlapping area of ​​the orthographic projection of the light-emitting signal line EML on the substrate substrate SBT and the orthographic projection of the fourth polycrystalline silicon structure PLD on the substrate substrate SBT is the twelfth area A6; the overlapping area of ​​the orthographic projection of the third initialization voltage line VL3 on the substrate substrate SBT and the orthographic projection of the fourth polycrystalline silicon structure PLD on the substrate substrate SBT is the eleventh area B6; the twelfth area A6 covers the eleventh area B6.

[0138] In one embodiment of the present disclosure, the light-emitting signal trace EML includes a seventh extension portion X7 and an eighth extension portion X8 (see Figure 4); the orthographic projection of the seventh extension portion X7 on the substrate SBT intersects with the orthographic projection of the fourth polysilicon structure PLD on the substrate SBT, and the width of the seventh extension portion X7 along the column direction DV is greater than the width of the eighth extension portion X8 along the column direction DV.

[0139] Specifically, the light-emitting signal trace EML has a third protrusion SA3 on at least one side along the row direction DH, and at least a portion of the third protrusion SA3 is arranged to overlap with the fourth polysilicon structure PLD; that is, by providing the third protrusion SA3 on the light-emitting signal trace EML, the coverage effect of the light-emitting signal trace EML on the fourth polysilicon structure PLD is improved (see Figure 17).

[0140] Optionally, a third protrusion SA3 may be provided on one side of the light-emitting signal trace EML. Providing the third protrusion SA3 on one side of the light-emitting signal trace EML can achieve better coverage of the fourth polysilicon structure PLD by the light-emitting signal trace EML, thereby helping to reduce deviations in the parasitic capacitance of the fourth node N4, thereby helping to improve the display uniformity of the display panel. Of course, the third protrusion SA3 may be provided on both sides of the light-emitting signal trace EML along the row direction DH. Providing the third protrusion SA3 on both sides can also reduce deviations in the parasitic capacitance of the fourth node N4, thereby helping to improve the display uniformity of the display panel. In the embodiments of the present disclosure, there is no specific limitation on the number of third protrusions SA3 provided.

[0141] In one embodiment of the present disclosure, referring to Figure 8, the polycrystalline silicon semiconductor layer PSCL includes a third polycrystalline silicon structure PLC; the third polycrystalline silicon structure PLC is located in the channel region T1A of the first reset transistor; the first gate layer GT1 is provided with a first reset signal line RPL extending along the row direction DH; the third gate layer GT3 is provided with a second initialization voltage line VL2 extending along the row direction DH; the area where the orthographic projection of the first reset signal line RPL on the substrate substrate SBT overlaps with the orthographic projection of the third polycrystalline silicon structure PLC on the substrate substrate SBT is the tenth area A5; the area where the orthographic projection of the second initialization voltage line VL2 on the substrate substrate SBT overlaps with the orthographic projection of the third polycrystalline silicon structure PLC on the substrate substrate SBT is the ninth area B5; the tenth area A5 covers the ninth area B5.

[0142] In this embodiment, the first reset signal line RPL includes a fifth extension portion X5 and a sixth extension portion X6 (see Figure 4); wherein, the orthographic projection of the fifth extension portion X5 on the substrate substrate SBT intersects with the orthographic projection of the third polysilicon structure PLC on the substrate substrate SBT, and the width of the fifth extension portion X5 along the column direction DV is greater than the width of the sixth extension portion X6 along the column direction DV.

[0143] Optionally, the tenth region A5 includes a fifth side and a sixth side extending along the row direction DH, and the eleventh region B6 includes a fifth inner side extending along the row direction DH and on the same side as the fifth side, and a sixth inner side extending along the row direction DH and on the same side as the sixth side; the dimension between the fifth side and the fifth inner side along the column direction DV is a fifth distance, and the dimension between the sixth side and the sixth inner side along the column direction DV is a sixth distance. The fifth distance may be greater than the sixth distance. Under such a setting, the sixth side and the sixth inner side may overlap, but the first reset signal line RPL can still cover the second initialization voltage line VL2, and can still cover the third polysilicon structure PLC through the first reset signal line RPL to reduce the influence of the second initialization voltage line VL2 on the third polysilicon structure PLC. Similarly, the size of the fifth distance can be smaller than the size of the sixth distance. Under such a setting, there may be a situation where the fifth side and the fifth inner side overlap, but the first reset signal line RPL can still cover the second initialization voltage line VL2, and can still reduce the impact of the first reset signal line RPL on the third polysilicon structure PLC by covering the third polysilicon structure PLC through RPL. Of course, the size of the fifth distance can be equal to the size of the sixth distance. Under such a setting, the shielding of the third polysilicon structure PLC by the first reset signal line RPL can be maximized, and the deviation of the parasitic capacitance of the third node N3 node can be reduced to improve the display uniformity of the display panel. At the same time, under such a setting, the impact of manufacturing errors can be reduced during manufacturing.

[0144] In one embodiment of the present disclosure, referring to Figure 11, the pixel driving circuit includes an electrode reset transistor T7; the first gate layer GT1 includes a second reset signal line RHL extending along the row direction DH; the third gate layer GT3 includes a first initialization voltage line VL1 extending along the row direction DH; the polycrystalline silicon semiconductor layer PSCL includes a fifth polycrystalline silicon structure PLE; the fifth polycrystalline silicon structure PLE is located in the channel region T7A of the electrode reset transistor; the overlapping area of ​​the orthographic projection of the second reset signal line RHL on the substrate substrate SBT and the orthographic projection of the fifth polycrystalline silicon structure PLE on the substrate substrate SBT is the fourteenth area A7; the overlapping area of ​​the orthographic projection of the first initialization voltage line VL1 on the substrate substrate SBT and the orthographic projection of the fifth polycrystalline silicon structure PLE on the substrate substrate SBT is the thirteenth area B7; the fourteenth area A7 covers the thirteenth area B7.

[0145] The second reset signal trace RHL may include a ninth extension portion X9 and a tenth extension portion X10 (see FIG4 ), the orthographic projection of the ninth extension portion X9 on the substrate SBT intersecting with the orthographic projection of the fifth polysilicon structure PLE on the substrate SBT, and the width of the ninth extension portion X9 along the column direction DV being greater than the width of the tenth extension portion X10 along the column direction DV.

[0146] Specifically, the second reset signal line RHL has a fourth protrusion SA4 on at least one side along the row direction DH, and at least a portion of the fourth protrusion SA4 overlaps with the fifth polysilicon structure PLE. In other words, by providing the fourth protrusion SA4 on the second reset signal line RHL, the coverage of the fifth polysilicon structure PLE by the second reset signal line RHL is improved. Optionally, the fourth protrusion SA4 can be provided on one side of the second reset signal line RHL. Providing the fourth protrusion SA4 on one side of the second reset signal line RHL can achieve better coverage of the fifth polysilicon structure PLE by the second reset signal line RHL (see FIG. 18 ), thereby helping to reduce deviations in parasitic capacitance of the fourth node N4 and improving display uniformity of the display panel. Of course, a fourth protrusion SA4 can be set on both sides of the second reset signal line RHL along the row direction DH. The fourth protrusion SA4 set on both sides can also reduce the deviation of the parasitic capacitance of the fourth node N4, which helps to improve the display uniformity of the display panel. In the embodiment of the present disclosure, there is no specific restriction on the number of the fourth protrusion SA4 set.

[0147] It can be understood that the fourth protrusion SA4 can be rectangular, trapezoidal or other shapes, and is not limited to the description and combination of the above embodiments.

[0148] Further, referring to Figure 11, the polycrystalline silicon semiconductor layer PSCL may also include a sixth polycrystalline silicon structure PLF; the sixth polycrystalline silicon structure PLF is located in the channel region T8A of the second reset transistor; the overlapping area of ​​the orthographic projection of the second reset signal wiring RHL on the substrate substrate SBT and the orthographic projection of the sixth polycrystalline silicon structure PLF on the substrate substrate SBT is the sixteenth area A8; the overlapping area of ​​the orthographic projection of the first initialization voltage wiring VL1 on the substrate substrate SBT and the orthographic projection of the sixth polycrystalline silicon structure PLF on the substrate substrate SBT is the fifteenth area B8; the sixteenth area A8 covers the fifteenth area B8.

[0149] 4 , the second reset signal trace RHL may further include an eleventh extension portion X11 and a twelfth extension portion X12. The eleventh extension portion X11 is electrically connected to a side of the ninth extension portion X9 away from the tenth extension portion X10, and the twelfth extension portion X12 is electrically connected to a side of the eleventh extension portion X11 away from the ninth extension portion X9. The orthographic projection of the eleventh extension portion X11 on the substrate SBT intersects the orthographic projection of the sixth polysilicon structure PLF on the substrate SBT, and the width of the eleventh extension portion X11 along the column direction DV is greater than the width of the twelfth extension portion X12 along the column direction DV.

[0150] Optionally, the eleventh extension portion X11 can have the same width as the ninth extension portion X9 along the column direction DV. Such a setting can achieve better coverage of the sixth polysilicon structure PLF by locally widening the eleventh extension portion X11, thereby reducing the parasitic capacitance deviation between the first initialization voltage line VL1 and the sixth polysilicon structure PLF.

[0151] Of course, the width of the eleventh extension portion X11 along the column direction DV may also be different from the width of the ninth extension portion X9 along the column direction DV. Specifically, the width of the eleventh extension portion X11 along the column direction DV is greater than the width of the ninth extension portion X9 along the column direction DV. Such a setting can better achieve the coverage of the sixth polysilicon structure PLF by the second reset signal line RHL, and reduce the parasitic capacitance deviation between the first initialization voltage line VL1 and the sixth polysilicon structure PLF. The width of the eleventh extension portion X11 along the column direction DV may be smaller than the width of the ninth extension portion X9 along the column direction DV, and even the width of the eleventh extension portion X11 along the column direction DV may be smaller than the width of the first initialization voltage trace VL1 along the column direction DV. That is, in the area of ​​the eleventh extension portion X11, the second reset signal trace RHL may not cover the sixth polysilicon structure PLF. This is because the eleventh extension portion X11 is located at a non-critical node position of the display panel, and the parasitic capacitance deviation here has little effect on the overall capacitance deviation of the display panel. Therefore, the width of the PHL along the column direction DV at the position of the eleventh extension portion X11 and the width of the first initialization voltage trace VL1 along the column direction DV may not be specifically restricted.

[0152] The present disclosure also provides a display device comprising any of the display panels described in the display panel embodiments above. The display device may be a smartphone screen, a smartwatch screen, or another type of display device. Because the display device comprises any of the display panels described in the display panel embodiments above, it exhibits the same beneficial effects, and the present disclosure will not elaborate further here.

[0153] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that: It includes a base substrate, a first gate layer, a second gate layer, a third gate layer and a first source-drain metal layer stacked in sequence; The second gate layer is provided with a first down-scan signal line extending in the row direction; the third gate layer is provided with a first up-scan signal line extending in the row direction; the first source-drain metal layer has a first metal structure; two ends of the first metal structure are electrically connected to the second electrode of the threshold compensation transistor and the gate of the driving transistor through vias respectively; The gate of the threshold compensation transistor includes a bottom gate of the threshold compensation transistor located on the first lower scan signal line and a top gate of the threshold compensation transistor located on the first upper scan signal line; An overlapping area of ​​the orthographic projection of the first down-scan signal trace on the base substrate and the orthographic projection of the first metal structure on the base substrate is a first area; An overlapping area of ​​the orthographic projection of the first upper scan signal trace on the base substrate and the orthographic projection of the first metal structure on the base substrate is a second area; The second area covers the first area.

2. The display panel according to claim 1, wherein: The display panel further includes a polysilicon semiconductor layer; The polysilicon semiconductor layer includes a first polysilicon structure; the first polysilicon structure is located between the channel region of the data writing transistor and the first electrode of the driving transistor; An overlapping area of ​​the orthographic projection of the first down-scan signal line on the substrate and the orthographic projection of the first polysilicon structure on the substrate is a fourth area; An overlapping area of ​​the orthographic projection of the first upper scan signal line on the substrate and the orthographic projection of the first polysilicon structure on the substrate is a third area; The fourth area covers the third area.

3. The display panel according to claim 2, wherein: The first down scan signal trace includes a first extension portion and a second extension portion; The first extension portion is electrically connected to the second extension portion; and an orthographic projection of the second extension portion intersects an orthographic projection of the first metal structure on the substrate; An orthographic projection of the first extension portion on the base substrate intersects with an orthographic projection of the first polysilicon structure on the base substrate, and a width of the first extension portion along a column direction is greater than a width of the second extension portion along the column direction.

4. The display panel according to claim 2, wherein: The display panel further includes initialization voltage wiring and control signal wiring extending along the row direction; The orthographic projection of at least part of the control signal lines on the substrate overlaps with the orthographic projection of at least part of the initialization voltage lines on the substrate.

5. The display panel according to claim 4, wherein: The initialization voltage routing includes a first initialization voltage routing, a second initialization voltage routing, and a third initialization voltage routing; the first initialization voltage routing, the second initialization voltage routing, and the third initialization voltage routing are respectively used to load a first initialization voltage, a second initialization voltage, and a third initialization voltage; The control signal routing includes a second reset signal routing, a first reset signal routing and a light emitting signal routing; the second reset signal routing is used to load the second reset signal, the first reset signal routing is used to load the first reset signal, and the light emitting signal routing is used to load the enable signal; The orthographic projection of at least one of the second reset signal line, the first reset signal line and the light-emitting signal line on the base substrate overlaps with the orthographic projection of at least one of the first initialization voltage line, the second initialization voltage line and the third initialization voltage line on the base substrate.

6. The display panel according to claim 5, wherein: An orthographic projection of the second reset signal line on the substrate and an orthographic projection of the first initialization voltage line on the substrate overlap each other; An orthographic projection of the first reset signal line on the substrate and an orthographic projection of the second initialization voltage line on the substrate overlap each other; An orthographic projection of the light emitting signal line on the base substrate and an orthographic projection of the third initialization voltage line on the base substrate have an overlapping area.

7. The display panel according to claim 6, wherein: The first gate layer is provided with a light-emitting signal line extending in the row direction; the third gate layer is provided with a third initialization voltage line extending in the row direction; the first source and drain metal layer has a second metal structure; two ends of the second metal structure are electrically connected to the second electrode of the first light-emitting transistor and the second electrode of the second reset transistor through vias respectively; An overlapping area of ​​the orthographic projection of the third initialization voltage trace on the substrate and the orthographic projection of the second metal structure on the substrate is a sixth area; The overlapping area of ​​the orthographic projection of the light emitting signal trace on the substrate and the orthographic projection of the second metal structure on the substrate is the fifth area; The sixth area covers the fifth area.

8. The display panel according to claim 7, wherein: The polysilicon semiconductor layer includes a second polysilicon structure; the second polysilicon structure is located in the channel region of the first light emitting transistor; An overlapping area of ​​the orthographic projection of the light emitting signal trace on the substrate and the orthographic projection of the second polysilicon structure on the substrate is an eighth area; An overlapping area of ​​the orthographic projection of the third initialization voltage trace on the substrate and the orthographic projection of the second polysilicon structure on the substrate is a seventh area; The eighth area covers the seventh area.

9. The display panel according to claim 8, wherein: The light-emitting signal wiring includes a third extension portion and a fourth extension portion; The third extension portion is electrically connected to the fourth extension portion; and an orthographic projection of the fourth extension portion on the base substrate intersects with an orthographic projection of the second metal structure on the base substrate; An orthographic projection of the third extension portion on the base substrate intersects with an orthographic projection of the second polysilicon structure on the base substrate, and a width of the third extension portion along a column direction is greater than a width of the fourth extension portion along the column direction.

10. The display panel according to claim 6, wherein: The polysilicon semiconductor layer includes a third polysilicon structure; the third polysilicon structure is located in the channel region of the first reset transistor; The first gate layer is provided with a first reset signal line extending along the row direction; the third gate layer is provided with a second initialization voltage line extending along the row direction; An overlapping area of ​​the orthographic projection of the first reset signal trace on the substrate and the orthographic projection of the third polysilicon structure on the substrate is a tenth area; An overlapping area of ​​the orthographic projection of the second initialization voltage trace on the substrate and the orthographic projection of the third polysilicon structure on the substrate is a ninth area; The tenth area covers the ninth area.

11. The display panel according to claim 10, wherein: The first reset signal wiring includes a fifth extending portion and a sixth extending portion; The orthographic projection of the fifth extension portion on the substrate intersects with the orthographic projection of the third polysilicon structure on the substrate, and the width of the fifth extension portion along the column direction is greater than the width of the sixth extension portion along the column direction.

12. The display panel according to claim 6, wherein: The polysilicon semiconductor layer includes a fourth polysilicon structure; the fourth polysilicon structure is located in the channel region of the second light emitting transistor; An overlapping area of ​​the orthographic projection of the light emitting signal trace on the substrate and the orthographic projection of the fourth polysilicon structure on the substrate is a twelfth area; An overlapping area of ​​the orthographic projection of the third initialization voltage trace on the substrate and the orthographic projection of the fourth polysilicon structure on the substrate is an eleventh area; The twelfth area covers the eleventh area.

13. The display panel according to claim 12, wherein: The light-emitting signal wiring includes a seventh extension portion and an eighth extension portion; An orthographic projection of the seventh extension portion on the base substrate intersects with an orthographic projection of the fourth polysilicon structure on the base substrate, and a width of the seventh extension portion along a column direction is greater than a width of the eighth extension portion along the column direction.

14. The display panel according to claim 6, wherein: The first gate layer includes a second reset signal line extending in a row direction; the third gate layer includes a first initialization voltage line extending in a row direction; The polysilicon semiconductor layer includes a fifth polysilicon structure; the fifth polysilicon structure is located in the channel region of the electrode reset transistor; An overlapping area of ​​the orthographic projection of the second reset signal trace on the substrate and the orthographic projection of the fifth polysilicon structure on the substrate is a fourteenth area; An overlapping area of ​​the orthographic projection of the first initialization voltage trace on the substrate and the orthographic projection of the fifth polysilicon structure on the substrate is a thirteenth area; The fourteenth area covers the thirteenth area.

15. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 14.

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