Reconfigurable nested time-interleaved delay circuit

Abstract

A nested, time-interleaved (TI) N-path delay circuit is disclosed, in which not only is each sample voltage time-interleaved to increase the signal delay, but also each unit cell in a first level of TI is itself time-expanded by a second level of TI Although the nesting of TI increases hardware and clocking complexity, it dramatically increases the amount of achievable delay. Additionally, the nesting of IL provides coarse, medium, fine, and ultra-fine control of delay. Branching and duplicating hardware downstream of the branch point enables the creation of multiple delays, while efficiently re-using upstream circuitry. This allows for multiple delays (e.g., to combat multipath reflections), without requiring duplication of the entire delay circuit. Techniques are also disclosed for control and differentiation of delays in different branches. Nested interleaving stages can be set to pass-through mode to reduce delays; non-interleaving storage blocks may be inserted in series to increase delays.

Description

[0001] RECONFIGURABLE NESTED TIME-INTERLEAVED DELAY CIRCUIT

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to electronics, and in particular to a nested time- interleaved delay circuit architecture for RF signals, which can be reconfigured by branching to provide multiple delays, by providing serial duplicate delays on one branch to increase delay difference, or by pass-through / bypass to provide short delays.

[0004] BACKGROUND

[0005] In modern electronics, there are a number of applications in which delaying high- frequency signals is advantageous. As one example, in Full Duplex (FD) wireless communications systems, the Receiver (Rx) and Transmitter (Tx) share both time and frequency resources, so that transmission and reception can be carried out simultaneously. A problem in these systems is that at least some of the signal transmitted will inevitably be reflected and / or leaked into the Rx, referred to as a Self-Interference (SI) signal. For FD to work (and provide the advantage of increased spectral efficiency), the SI signal must be cancelled. The SI signal will be complex due to multipath reflections and other environment-based propagation effects. It will have varying amplitude and delay, and often multiple copies superimposed, each with a different delay (for example, from multipath reflection). To cancel the SI signal, a Self-Interference Cancelation (SIC) circuit must obtain varyingly delayed copies of the transmitted signal. Another example of the need for high-frequency delay circuits is analog or hybrid pre-distortion.

[0006] N-path circuits, also known as switched capacitor circuits, have been implemented as delay blocks, such as in FD transceiver systems. They exhibit low delay variation over large bandwidths, high delay resolution, and large tuning ranges. Conceptually, these circuits can be considered as N sample and hold circuits coupled in parallel, each sampling a part of the input waveform and then, after a programmed delay, reconstructing it at the output. One drawback to known N-path delay circuits is that although the total delay achieved is relatively large, it is still too low for many applications, such as most real-world FD cases (e.g, outdoor scenarios). One way to increase the delay is to use Time-Interleaving (TI). In this technique, each Nth sample state is stored in an additional M sample and hold stages. The TI step can utilize lower frequency sample and reconstruction clocks, easing design requirements and thus allowing for larger delays.

[0007] FIG. 1 depicts the unit cell 10 in an N-path circuit. The unit cell 10 comprises a capacitor 12 connected to ground in shunt configuration between an input switch 14 and an output switch function 16. The output switch function 16 may comprise a transistor switch, as shown in FIG. 1, or may comprise a tri-state buffer. In circuit diagrams herein, signal flow is from left to right. The direction of signal flow (left to right in the figures) is referred to herein as “downstream,” and the opposite direction is referred to as “upstream.” Accordingly, the left side of the switch 14 is the input side and the right side of the switch 14, connected to the capacitor 12, is the output side. Similarly, the input side of the output switch function 16 is connected to the capacitor 12, and the output side of the output switch function 16 is to the right. The switch function 16 is downstream of the switch 14. When the switch 14 is closed (with the switch function 16 open or high impedance), the capacitor 12 charges to the voltage applied at that moment to the input side of the switch 14, which is then opened to isolate the capacitor 12. After a programmed delay, the switch function 16 is closed / enabled, and the voltage appears at the output side of switch function 16. Hence, the timing of the switch 14 and switch function 16 controls the delay. To provide a delayed version of a time-varying signal, a number N of unit cells 10 (also referred to as phases) are connected in parallel. As used herein, the reference number 14 refers to a switch that opens to charge a capacitor 12 to hold a sample value, and 16 refers to a switch or switching function that opens to transfer a sample value to a downstream stage or to the output.

[0008] FIG. 2 depicts an N-path delay circuit 20, comprising N unit cells, or phases, 10-1, 10-2, . . ., 10-N. Each input clock Ox operates sequentially, storing successive samples of the input voltage in successive capacitors 12. In the general case, with a clock frequency fcik and number of phases N, the effective sampling frequency becomes fs=Nfcik and the number of samples per waveform is determined by the input signal frequency far.

[0009] FIG. 3 is a timing diagram of one example, depicting an input waveform VRF being sampled eight times per period, and the delayed output VRFCI. The delay introduced in the circuit 20 is determined by the number of phases N, and the time delay id between sample clocks x and delayed (or reconstruction) clocks Oxa, where X denotes the phase index. The total delay achieved by the N-path delay circuit 20 can be expressed as: I Lll J

[0010] In the N-path delay circuit 20, the maximum delay is constrained by the number of phases. The sample stored in, e.g., the first phase 10-1 must be read out within N sample clocks, so that it is available to capture the (N+l) input sample.

[0011] Time-Interleaving (TI) is a technique to achieve longer delay by transferring each sample to a downstream storage, making the sampling phases available to capture new samples, while delaying the time before the signal is reconstructed by reading the stored samples. FIG. 4 illustrates a TI N-path delay circuit 22, which is a variant of the circuit described in U.S. Patent No. 11,683,023. Conceptually, it comprises the delay circuit 20 of FIG. 2, with a TI stage 23 interposed between the capacitors 12 and output switches 16 of each phase. The TI stage 23 comprises N identical TI slices, each connected to a different phase. Each TI slice is itself an N-path delay circuit 20, which operates as described above (although the number of TI phases M may differ from N). However, rather than the TI phases storing successive samples of the input signal, they store successive sample values of the connected sample capacitor 12. Hence, for a TI delay circuit 22 having N sample phases, the first capacitor 12 will store the 1stsample, then samples (N+l), (2N+1), etc. Before being overwritten, each of these samples is transferred to the connected TI slice. The first phase of the TI slice stores the 1stsample, the second phase stores sample (N+l), the third stores (2N+1), etc. Meanwhile, another TI slice successively stores the samples captured by the second phase of the sampling circuit (2nd, (N+2), (2N+2), etc.). The on-time of the TI slice clocks T may be up to N times longer than the sampling clocks O. Note that the TI slice clocks T have a two-digit index - the first denotes the TI slice number (and is the same as the single-digit index of the corresponding sampling clock O), and the second denotes the phase within that TI slice. The samples are de-interleaved by the TI slice clocks Td successively driving each phase output switch function.

[0012] Note that, compared to the N-path delay circuit 20, the TI N-path delay circuit 22 added buffers at the output of each sampling capacitor, and shunt capacitors at the input of each reconstruction switch (Td). These are not logically necessary for operation of the TI N-path delay circuit 22, but they address real-world circuit performance issues such as isolation and capacitive load. Also different to the N-path delay circuit 20, de-interleaving by reading samples from the capacitors within the TI stage 23 is done by enabling tri-state buffers, rather than opening and closing switches. Again, this is for practical implementation reasons. Because either a switch or a tri-state buffer can be used, this circuit element is referred to herein as an output switch function.

[0013] FIG. 5 is a timing diagram showing the clocking signals for TI delay circuit 22 of FIG. 4, where N=8, and M is arbitrary. The sampling clocks T cycle through the N sampling stages starting at TI . At some point before it has cycled through all N stages, the sampled state of the first phase is saved in the first capacitor 12 of the first TI slice, clocked by Ti l, and the TI clock can open its switch to sample the next value. FIG. 5 shows only one of the sets of TI clocks (Tlx), but they all follow the same principle, where the clock TN is interleaved by the slower TNI to TNM clocks. As seen, the T clock pulse width is equal to the 0 clock pulse width T times N. The increased delay of the TI delay circuit 22 is primarily due to the sample time expansion that occurs in the TI stage. One of the limiting factors for the maximum achievable delay for the N-path delay circuit 20 is the parasitic loading of the branches when the number of phases increases. In this TI delay circuit 22, this is mitigated in the TI stage, since the clock frequencies are much lower. This increases the settling time, decreasing the impact of parasitic effects on performance. The total delay achieved in a TI N-path delay circuit 22 with M TI phases is:

[0014] While the TI N-path delay circuit 22 increases the achievable delay (which is scalable by increasing M), it is hardware intensive, and produces only one delay value. In applications such as SIC for FD radio communications, multipath reflections mean that a transmitted signal must be replicated with multiple delays, so that all reflections can be cancelled. Implementing multiple full TI N-path delay circuits 22 consumes integrated circuit area and power, and poses complex clock routing challenges. Also, although the TI N-path delay circuit 22 achieves greater delays than an N-path delay circuit 20, the delay is still limited by the range of the TI stage.

[0015] The Background section of this document is provided to place aspects of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

[0016] SUMMARY

[0017] The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of aspects of the disclosure or to delineate the scope of the disclosure. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[0018] The present disclosure describes and claims aspects relating to a nested TI N-path delay circuit. In the nested TI N-path delay circuit architecture, not only is each sample voltage time- interleaved to increase the signal delay, but also each unit cell in a first level of TI is itself time- expanded by a second level of TI. Although the nesting of TI stages increases hardware and clocking complexity, it dramatically increases the amount of achievable delay. Additionally, the nesting of TI stages provides coarse, medium, fine, and ultra-fine control of delay. Branching and duplicating hardware downstream of the branch point enables the creation of multiple delays, while efficiently re-using upstream circuitry. This allows for multiple delays (e.g., to combat multipath reflections), without requiring duplication of the entire delay circuit. Techniques are also disclosed for control and differentiation of delays in different branches. Nested interleaving stages can be set to pass-through mode to reduce delays; non-interleaving storage blocks may be inserted in series to increase delays.

[0019] One aspect relates to a configurable, nested, time-interleaved delay circuit. The delay circuit includes a sample stage comprising a number N of sample capacitors in parallel, each connected in shunt configuration between a respective sample switch and an output. The input sides of the N sample switches are connected together to form the delay circuit input. The delay circuit further includes a first time-interleaving stage (TI) comprising N Til slices. Each Til slice is connected to a different output of the sample stage. Each Til slice includes: a number M of Til input switches in parallel, wherein the input sides of the M Til input switches are connected together to form the Til slice input; M Til capacitors, each connected in shunt configuration to the output side of a respective Til input switch; M Til output switch functions, wherein the output sides of the M Til output switch functions are connected together to form the Til slice output; and a second, nested time-interleaving stage (TI) interposed between the M Til capacitors and the M corresponding Til output switch functions. The TI2 stage includes M TI2 slices Each TI2 slice is coupled to a different Til capacitor. Each TI2 slice includes: a number K of TI2 input switches in parallel, wherein the input sides of the K TI2 input switches are connected together to form the TI2 slice input; K TI2 output switch functions, wherein the output sides of the K TI2 output switch functions are connected together to form the TI2 slice output; and K TI2 capacitors, each connected in shunt configuration between a TI2 input switch and a corresponding TI2 output switch function. Each Til output switch function is connected to a different TI2 slice output. The Til slice further includes a reconstruction stage comprising N reconstruction switches. Each reconstruction switch is connected to the output of a different Til slice. The output sides of the N reconstruction switches are connected together to form the delay circuit output.

[0020] Another aspect relates to a full duplex communication device. The device includes transmission circuitry configured to transmit a Radio Frequency (RF) signal and receiving circuitry configured to receive an RF signal. The device further includes a Self-Interference Cancelation (SI) circuit configured to cancel, in the received RF signal, multipath reflections of the transmitted RF signal. The SIC includes the delay circuit described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of the disclosure are shown. However, this disclosure should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0022] FIG. l is a schematic diagram of a unit cell for an N-path delay circuit.

[0023] FIG. 2 is a schematic diagram of an N-path delay circuit.

[0024] FIG. 3 is a timing diagram for the N-path delay circuit of FIG. 2.

[0025] FIG. 4 is a schematic diagram of a Time-Interleaved (TI) N-path delay circuit.

[0026] FIG. 5 is a timing diagram for the TI N-path delay circuit of FIG. 4.

[0027] FIG. 6 is a schematic diagram of a nested TI N-path delay circuit.

[0028] FIG. 7 is a timing diagram for the nested TI N-path delay circuit of FIG. 6.

[0029] FIG. 8 is a timing diagram showing coarse, medium, fine, and ultra-fine delays.

[0030] FIG. 9A is block diagram showing six nested TI N-path delay circuits.

[0031] FIG. 9B is block diagram showing one branched, nested TI N-path delay circuit outputting six delays.

[0032] FIG. 10 is a perspective view of a branched, nested TI N-path delay circuit.

[0033] FIG. 11 is a block diagram illustrating bypassing TI stages in a nested TI N-path delay circuit.

[0034] FIG. 12A is a block diagram illustrating a branched, nested TI N-path delay circuit.

[0035] FIG. 12B is a block diagram illustrating a serial TI stage in the branched, nested TI N-path delay circuit of FIG. 12A.

[0036] FIG. 13A is a graph of a 10 GHz sinusoidal signal used as input in a simulation of a branched delay circuit.

[0037] FIG. 13B is a timing diagram of common clock signals in the branched delay circuit.

[0038] FIG. 13C is a graph of the output of one branch, delaying the signal of FIG. 13A by 5600 ps.

[0039] FIG. 13D is a timing diagram of clock signals unique to the branch generating the signal of FIG. 13C.

[0040] FIG. 13E is a graph of the output of a different branch, delaying the signal of FIG. 13A by 6150 ps.

[0041] FIG. 13F is a timing diagram of clock signals unique to the branch generating the signal of FIG. 13E.

[0042] FIG. 14 is a hardware block diagram of a UE. FIG. 15 is a hardware block diagram of a base station.

[0043] DETAILED DESCRIPTION

[0044] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to an exemplary aspect thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0045] FIG. 6 shows, in the upper portion of the figure, a nested TI N-path delay circuit 24 according to one aspect of the present disclosure. Below the nested TI N-path delay circuit 24 is shown a TI N-path delay circuit 22, with a heavy dashed line showing where a TI N-path delayst circuit 22 is split or divided. A set of N-path delay circuits 20 is interposed at this point, to form the nested TI N-path delay circuit 24 shown in the upper figure (for clarity, the TI N-path delay circuit 22 in the lower portion of the figure is not part of the final nested TI N-path delay circuit 24 shown in the upper portion). That is, within each slice of the first TI stage, the sampling and storage operations are upstream of the new, nested TI stage, and the deinterleaving operation is downstream of the nested TI2 stage.

[0046] The nested TI N-path delay circuit 24 comprises a sample stage 26, a first Time- Interleaved stage (Til) 28 (with its interleaving and de-interleaving functions split apart), a second, nested Time-Interleaved stage (TI2) 30, and a reconstruction stage 32. A control circuit 36 generates a sample clock <b, Til interleaving and de-interleaving clocks T, Td, TI2 interleaving and de-interleaving clocks s, sd, and a reconstruction clock <bd.

[0047] The sample stage 26 comprises a number N of sample switches in parallel. The input sides of the N sample switches are connected together to form the input of the nested TI N-path delay circuit 24. The sample stage 26 further comprises N sample outputs, and N sample capacitors, each connected in shunt configuration between a respective sample switch driven by a sample clock x (x=l . . .N) and a sample output. The nested TI N-path delay circuit 24 of FIG. 6 show buffers at the outputs of the sample capacitors, which helps with isolation and driving a heavy capacitive load (fan-out). However, the buffers take up chip area and consume power, and may not be necessary in all implementations.

[0048] The TH stage 28 comprises N Til slices. Each TH slice is connected to a different output of the sample stage 26. Although only the first is shown, each Til slice comprises a number M of TH input switches in parallel, driven by the Til clock 'Fxy (x=l .. N, y=l .. M). M may be equal or different to N. The input sides of the M Til input switches are connected together to form the Til slice input. The Til slice further comprises M Til capacitors. Each Til capacitor is connected in shunt configuration to the output side of a respective Til input switch. Again, FIG. 6 depicts buffers connected to the Til capacitors, which are not limiting. Jumping to the right, the Til slice further comprises M Til output switch functions (depicted here as tri-state buffers, but which could alternatively be transistor switches), driven by the Til clock TXyd. The output sides of the M Til output switch functions are connected together to form the Til slice output.

[0049] Within each Til slice, interposed between the M Til capacitors and the M corresponding Til output switch functions is the TI2 stage 30. The TI2 stage 30 comprises M TI2 slices. Each TI2 slice is coupled to a different Til capacitor (e. ., via a buffer). Each TI2 slice comprises a number K of TI2 input switches in parallel, driven by the TI2 clock Exyz (x=l . . .N, y=l .. M, z=l . ..K). The input sides of the K TI2 input switches are connected together to form the TI2 slice input. The TI2 slice further comprises K TI2 output switch functions (i.e., switches or tri- state buffers) driven by the TI2 clock ExyZd. The output sides of the K TI2 output switch functions are connected together to form the TI2 slice output. The TI2 slice further comprises K TI2 capacitors, each connected in shunt configuration between a TI2 input switch and a corresponding TI2 output switch function.

[0050] Each Til output switch function is connected to a different TI2 slice output.

[0051] The reconstruction stage 32 comprises N reconstruction switches, driven by the reconstruction clock xd (x=l . ..N). Each reconstruction switch is connected to the output of a different Til slice. The output sides of the N reconstruction switch functions are connected together to form the output of the nested TI N-stage delay circuit 24. Reconstruction capacitors may optionally be connected in shut configuration between each Til slice output and the corresponding reconstruction switch.

[0052] By utilizing nested TI stages, the nested TI N-path delay circuit 24 can extend the achievable delay range by M*(K-l) / fcik times.

[0053] FIG. 7 is a timing diagram showing the operation of the nested TI N=path delay circuit 24. In this example, N=5, M=4, and K=3. The sample clock <b has a single index, ranging 1 to N, identifying the sample phase. The Til clocks are indexed with two digits, where the first digit identifies the Til slice (1 to N), and the second digit identifies the phase within the Til slice (1 to M). The TI2 clocks 8 are indexed using three digits, where first identifies the Til slice, the second the TI2 slice, and the third identifies the phase within TI2 (1 to K). For all three, the trailing subscript “d” indicates the corresponding clocks driving the Til and TI2 de-interleaving switching functions and the reconstruction switches. The total delay achievable by the nested TI N-path delay circuit 24 is:

[0054] FIG. 8 shows the degrees of delay control due to the different clock pulse widths. The nested TI N-path delay circuit 24 can achieve a large range of delays using the different TI stages in different ways. The pulse width of the TI2 clock, i3, sets the coarse delay tuning and the maximum achievable delay. By reprogramming the TI2 clocks s, different coarse delays can be obtained. After coarse tuning, a medium tuning is achieved by reprogramming of the Til clocks with the resolution of T2. The sample and reconstruction clocks <b achieve the finest tuning step with TI. A final, ultra-fine delay can be achieved by introducing some small delay in the output reconstruction clock d>d.

[0055] The structure and operation of the nested TI N-path delay circuit 24 is described herein with respect to an implementation having one level of nesting - the TI2 stage 30 is nested within the Til stage 28. Those of skill in the art will appreciate that even greater delay can be achieved by further nesting one or more TI stages. For example, the TI2 stage could be split between its interleaving and de-interleaving hardware, and a third time-interleaving stage TI3 nested within. The TI3 stage would comprise K TI3 slices, each containing L unit cells. This would substantially increase the achievable delay, but would also greatly increase the amount of hardware and hence chip area, power consumption, clock generation and routing complexity, and the like. However, implementation would be straightforward, given the teachings of the present disclosure, and this aspect, and aspects with yet further levels of nested TI, are not further elaborated herein.

[0056] The nested TI N-path delay circuit 24 is proficient in creating large delays. However, each nested TI N-path delay circuit 24 can only create one delay. To create multiple delays, several separate, nested TI N-path delay circuits 24 are arranged in parallel. For example, FIG. 9A shows six nested TI N-path delay circuits 24 in parallel, creating six different delayed versions of the input signal. Because the nested TI N-path delay circuit 24 is very hardware intensive, this duplication of the entire circuit is very inefficient.

[0057] FIG. 9B depicts a branched, nested TI N-path delay circuit 34, which also provides six different delayed versions of the input signal. However, due to the branching, upstream circuitry is reused - that is, it is common to all delay paths. This design improves efficiency by reducing the total number amount of hardware required, while still providing multiple delays. FIG. 9B shows an implementation using single ended circuits and signals; however, the inventive approach is fully applicable to balanced designs. The example of FIG. 9B shows branching both upstream and downstream of the TI2 stage 30. FIG. 10 shows a perspective view of the same circuit, which also shows grouping of delays. From each branch point, the downstream circuit is duplicated. For example, both new branches that connect upstream of the TI2 stage 30 (group 1 and 3 in FIG. 10) replicate the TI2 stage 30, as well as the de-interleaving portion of the Til stage 28, and the reconstruction stage 32. Each of these three branches again branch downstream of the TI2 stage 30, yielding six outputs with six different delays. Again, all circuitry downstream of the branch point is replicated - in this case, the Til stage 28 de-interleaving stages, and the reconstruction stage 32. The sample stage 26 and the interleaving portion of the Til stage 28 are shared by all six outputs. The control circuit is not shown for simplicity. It may generate separate sets of clocks for each branch, to control the delay(s) of that branch.

[0058] The branched, nested TI N-path delay circuit 34 of FIG. 9B is far less hardware intensive than the parallel nested TI N-path delay circuits 24 of FIG. 9A, for the same number of delays. The efficiency arises from the shared use of the upstream stages by all branches. Using the same nomenclature as above, with N phases in the sample and reconstruction stages 26, 32; M phases in the Til stage 28, and K phases in the TI2 stage 30, then the total number of unit cells (see FIG. 1, but note that some unit cells are now split due to the presence of the interleaving stages) can be expressed as:

[0059] #cells_parallel = (0.5N + 0.5NM + NMK + 0.5NM + 0.5N) * 6

[0060] = 6N + 6NM + 6NMK [4]

[0061] #cells_branched = 0.5N + 0.5NM + 3NMK+ (0.5*6) MN+ (0.5*6) N

[0062] = 3.5N + 3.5NM + 3NMK [5]

[0063] Equations 4 and 5 compare the total number of unit cells in a branched structure of FIG. 9B to that of the parallel structure of FIG. 9A. As one example, if N = 8, and if M and K are swept from 2 to 10, then the total number of unit cells can be reduced by approximately 50% (49.17% for M=K=10). The percentage of unit cells reduced is proportional to M and K.

[0064] The branch locations affect both the differences in achievable delays between different branches, and also the total reduction in the number of unit cells. For example, in FIG. 9B, if the branch upstream of the TI2 stage 30 were only two paths, and the branch downstream of the TI2 stages 30 comprised three paths each (for the same total of six different delays), then total number of unit cells would be reduced by approximately 65% (64.19% for M=K=10). In general, the further downstream in the chain the branch points occur, the higher the reduction in the number of unit cells (i.e., more upstream unit cells are shared and not replicated). However, the trade-off is lower achievable spread in the delays. FIG. 8 demonstrates this concept. As an extreme example, if all the branching occurred just upstream of the reconstruction stage 32, then each delay could only be separated by the fine tuning of jn, where j = 0,l,2,...,N-l.

[0065] Those of skill in the art will appreciate that the placement of branch points, and the numeric values of N, M, and K is, for any particular implementation, a design choice based on, e.g., the sampling frequency, the total delay required, number of delays, delay separation, creation of spurs, and resulting chip-area. A general trend is that the more delays a branched, nested TI N-path delay circuit 34 creates, the greater the circuit efficiency. This is particularly beneficial for, e.g., SIC in FD systems at lower frequencies, where propagation losses are weaker, and thus more reflections will interfere with the Rx.

[0066] In many applications, wide separation in delays is desirable or required. According to aspects of the present invention, the delay(s) generated by a branch of a branched, nested TI N- path delay circuit 34 can be reduced, relative to other branches, by a pass-through of an interleaving stage 28, 30. To pass-through an interleaving stage, the relevant clocks simply set to open the switches 14, 16 (i.e., high, for an NMOS implementation), so that sample values pass through their slice and are directly de-interleaved or reconstructed by the next higher stage in the nesting hierarchy. To implement this feature, the upstream buffer must supply enough current to supply the downstream capacitor load. Note that for proper operation of the circuit 24, 34, all slices of a stage 28, 30 must be rendered pass-through together. FIG. 11 shows the pass-through of only the TI2 stage 30, and also a pass-through of both the Til stage 28 (which necessarily includes a pass-through of the nested TI2 state 30).

[0067] The pass-through by opening switches, as described above, is the simplest and most hardware-efficient manner to shorten delays by not interleaving at one or more TI stages. However, an alternative method would be to bypass the selected TI stage(s) by interposing switches, and the routing signals forwarding the relevant sample values around the slices of the selected interleaving stage(s). This approach is shown diagrammatically in FIGs 9B, 11, and 12A-B. Such a bypass path would be straightforward to those of skill in the art, given the teachings of the present disclosure, and is not further elaborated herein.

[0068] In some cases, sufficient distance in delay between two branches may not be achievable by only adjusting the timing (or by using pass-through on one branch). To increase delay separation, according to one aspect of the present disclosure, serial stages may be added to a branched path. The serial stage does not interleave the signal, but simply holds the state.

[0069] FIG. 12A depicts a branched, nested TI N-path delay circuit 34 with a branch downstream of the TI2 stage 30, replicating the de-interleaving portion of the Til stage 28 and the reconstruction stage 30. FIG 12B depicts a similar branched, nested TI N-path delay circuit 34, where greater delay separation is achieved by interposing a serial block 36 between the TI2 stage 30 and the de-interleaving portion of the Til stage 28. Because the entire circuitry upstream of the branch point is shared by the two branches, the area consumption and clock routing per achievable delay is reduced.

[0070] FIG. 13 depicts the results of simulations of the branched, nested TI N-path delay circuit 34 depicted in FIG. 12A, with N=8, M=5, and K=8, operating at a clock frequency of fs=5 GHz and without pass-through of the TI2 stage 30. The coarse tuning is set by reprogramming the TI2 clock e with pulse width T3=l ns, the Til clock with 12=200 ps and the fine tuning is set by the reconstruction clocks <bd with TI=25 ps. The branch point is at the output of the TI2 stage 30. Accordingly, the two created delays share the TI2 stage 30, but are separated relative to each other by different Til clocks d and reconstruction clocks <bd. FIG. 13A shows the RF input at 10GHz is applied after 25ns, allowing the circuit 34 to achieve steady state during the 0- 25ns period. FIG. 13B shows the common clocks, upstream of the branch point. FIG. 13B denotes the starting point (the delay starts here when the three clock pulses overlap) from which the delay is generated in relation to the specific clock pulses is FIGs. 13D and 13F. The TI2 deinterleaving clock d was programmed to cycle 6 times (5i3 to 613, and +400ps in clock offset), which gives a span of 5.4 ns to 6.4 ns for the programmed delay. Within this span, the tuning of the separate Til de-interleaving clocks d and reconstruction clocks <bd determines the exact delay for each branch. As shown in FIGs. 13C and 13D, branch 1 is programmed to 5600 ps, and as shown in FIGs. 13E and 13F, branch 2 is programmed to 6150 ps. Comparison of FIGs. 13C and 13E shows that the delay for the individual branches matches what was programmed in the clock settings. Note that the clocks in FIGs. 13B, 13D, and 13F are not the exact clocks that generate the first sample of the output signals in branch 1 and branch 2. Rather, the clocks in FIGs. 13B, 13D, and 13F show the timing relationships which generate the two different time delays on the two branches.

[0071] As discussed above, accurate programmable delays may be beneficial in many high- frequency circuits. Of particular interest is generating a plurality of delays of a transmitted RF signal in an FD system, for cancellation in a SIC of SI signal components, such as multipath reflections, prior to processing by the Rx. In this or other applications, the outputs of the nested TI N-path delay circuit 24 or branched, nested TI N-path delay circuit 34 may be summed into a single signal, to match the multipath delays in the signal from Rx antennas.

[0072] Another application of interest for long, accurate, multiple delays for RF signals is in an analog or hybrid pre-distortion circuit. The multiple outputs of the branched, nested TI N-path delay circuit 34 may be individually connected either to non-linear functions, or without a nonlinear function (as a direct path). A pre-distorter requires signals with a longer delay, but the signals themselves are spread apart with shorter delay. These branches can be combined after the non-linearities or be kept separate.

[0073] Another application of interest for long, accurate, multiple delays for RF signals is in an analog or hybrid pre-distortion circuit. The multiple outputs of the branched, nested TI N-path delay circuit 34 may be individually connected either to non-linear functions, or without a nonlinear function (as a direct path). A pre-distorter requires signals with a longer delay, but the signals themselves are spread apart with shorter delay. These branches can be combined after the non-linearities or be kept separate.

[0074] Such an SIC and / or pre-distortion circuit may be beneficial in both User Equipment (UE) and base stations of a wireless communication network.

[0075] FIG. 14 illustrates a hardware block diagram of a UE 40 as implemented in accordance with one or more aspects of the present disclosure. A UE 40 is any type of device capable of communicating with a network node and / or access point using radio signals. A UE 40 may therefore refer to a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB loT) device, etc. The UE 40 may also refer to a cellular telephone or “smartphone,” however, the term UE should be understood to encompass any wireless device 40. A UE 40 may also be referred to as a radio device, a radio communication device, a wireless device, a wireless terminal, or simply a terminal - unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices, or devices capable of machine-to-machine communication, sensors equipped with a wireless device, wireless-enabled table computers, mobile terminals, smart phones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), etc. In the discussion herein, the terms machine-to-machine (M2M) device, machine-type communication (MTC) device, wireless sensor, and sensor may also be used. It should be understood that these devices, although referred to as UEs, but may be configured to transmit and / or receive data without direct human interaction.

[0076] In some aspects, the UE 40 includes a user interface (not shown), including features such as a display, touchscreen, keyboard or keypad, microphone, speaker, and the like; in other aspects, such as in many M2M, MTC, orNB loT scenarios, the UE 40 may include only a minimal, or no, user interface. The UE 40 also includes processing circuitry 42; memory 44; and communication circuitry 46 to effect wireless communication across an air interface to one or more radio network nodes, such as a base station, and / or access points. The communication circuitry 46 may operate in FD, and include a SIC circuit 38. The SIC 38 includes a branched, nested TI N-path delay circuit 34, the multiple delays of which the processing circuitry 42 may program to match, and hence cancel, multipath components of a reflected Tx signal prior to Rx processing. The communication circuitry 46 may alternatively or additionally include a predistortion circuit 47, which includes a branched, nested TI N-path delay circuit 34. The communication circuitry 46 is connected to one or more antennas 48. As indicated by the dashed lines, the antenna(s) 48 may protrude externally from the UE 40, or the antenna(s) 48 may be internal.

[0077] FIG. 15 illustrates a hardware block diagram of a base station 50 operative in a wireless communication network. The base station 50 includes processing circuitry 52; memory 54; and communication circuitry 56 to effect wireless communication across an air interface to one or more UEs 40. The communication circuitry 56 may operate in FD, and include a SIC circuit 38. The SIC 38 includes a branched, nested TI N-path delay circuit 34, the multiple delays of which the processing circuitry 52 may program to match, and hence cancel, multipath components of a reflected Tx signal prior to Rx processing. The communication circuitry 56 may alternatively or additionally include a pre-distortion circuit 57, which includes a branched, nested TI N-path delay circuit 34. The communication circuitry 56 is connected to one or more antennas 58. As indicated by the broken connection to the antenna(s) 58, the antenna(s) 58 may be physically located separately from the base station 50, such as mounted on a tower, building, or the like. Although the memory 54 is depicted as being internal to the processing circuitry 52, those of skill in the art understand that the memory 54 may also be external. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 52 to actually be executed by other hardware, perhaps remotely located (e.g, in the so-called “cloud”). The base station 50 is known in LTE as an eNodeB or eNB, and in New Radio (NR) as gNB. In general, in other wireless communication networks, the base station 50 may be known as a Radio Base Station, Base Transceiver Station, Access Point, or the like.

[0078] The circuits or circuitry may comprise circuits dedicated to performing certain functional processing and / or one or more microprocessors in conjunction with memory. For instance, the circuitry may include one or more microprocessor or microcontrollers, as well as other digital hardware, which may include digital signal processors (DSPs), special-purpose digital logic, and the like. The processing circuitry may be configured to execute program code stored in memory, which may include one or several types of memory such as read-only memory (ROM), randomaccess memory, cache memory, flash memory devices, optical storage devices, etc. Program code stored in memory may include program instructions for executing one or more telecommunications and / or data communications protocols as well as instructions for carrying out one or more of the techniques described herein, in several embodiments. In embodiments that employ memory, the memory stores program code that, when executed by the one or more processors, carries out the techniques described herein.

[0079] Aspects of the present disclosure present numerous advantages over the prior art. By nesting the time-interleaving of sample values, much longer delays can be achieved than what is possible in TI N-path delay circuits 22 of the prior art. Additionally, the nesting of interleaving provides coarse, medium, fine, and ultra-fine control of delay. By branching and duplicating downstream circuitry, multiple delays of the same RF signal may be generated, without fully reproducing the entire nested TI N-path delay circuit 24, reducing IC area, power consumption, and clock routing challenges, as compared to parallel implementations of the prior art. Furthermore, innovations of the present disclosure allow for greater variety of delays between branches. Nested IL stages may be set to pass-through mode to greatly reduce a delay. Alternatively, non-interleaving serial stages may be added to increase delays. Selection of the branch point provides a trade-off between achievable delay spread and the degree of hardware duplication required.

[0080] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc. are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. Any feature of any of the aspects disclosed herein may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any other aspects, and vice versa. Other objectives, features and advantages of the enclosed aspects will be apparent from the description.

[0081] The term “unit” may have conventional meaning in the field of electronics, electrical devices and / or electronic devices and may include, for example, electrical and / or electronic circuitry, devices, modules, processors, memories, logic solid state and / or discrete devices, computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and / or displaying functions, and so on, as such as those that are described herein.

[0082] As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to,” or with respect to processing circuitry, “programmed to.”

[0083] Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. Other aspects, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the aspects set forth herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0084] The present disclosure may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the disclosure. The present aspects are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended aspects are intended to be embraced therein.

Claims

CLAIMSWhat is claimed is:

1. A nested time-interleaved N-path delay circuit (24, 34), characterized by: a sample stage (26) comprising: a number N of sample switches (14) in parallel, wherein the input sides of the N sample switches (14) are connected together to form the delay circuit (24, 34) input;N sample outputs; andN sample capacitors (12), each connected in shunt configuration between a respective sample switch (14) and a sample output; a first time-interleaving stage, Til, (28) comprising N Til slices, each Til slice connected to a different output of the sample stage (26), each Til slice comprising: a number M of Til input switches (14) in parallel, wherein the input sides of the M Til input switches (14) are connected together to form the Til slice input;M Til capacitors (12), each connected in shunt configuration to the output side of a respective Til input switch (14);M Til output switch functions (16), wherein the output sides of the M Til output switch functions (16) are connected together to form the Til slice output; and a second, nested time-interleaving stage, TI2, (30) for each Til slice interposed between the M Til capacitors (12) and the M corresponding Til output switch functions (16), the TI2 stage (30) comprising M TI2 slices, each TI2 slice coupled to a different Til capacitor (12), each TI2 slice comprising: a number K of TI2 input switches (14) in parallel, wherein the input sides of the K TI2 input switches (14) are connected together to form the TI2 slice input;K TI2 output switch functions (16), wherein the output sides of the K TI2 output switch functions (16) are connected together to form the TI2 slice output; andK TI2 capacitors (12), each connected in shunt configuration between a TI2 input switch (14) and a corresponding TI2 output switch function (16); wherein each Til output switch function (16) is connected to a different TI2 slice output, and a reconstruction stage (32) comprising N reconstruction switches (16), wherein eachreconstruction switch (16) is connected to the output of a different Til slice and wherein the output sides of the N reconstruction switches (16) are connected together to form the delay circuit (24, 34) output.

2. The delay circuit (24, 34) of claim 1, further characterized by a control circuit (36) configured to generate clock signals to drive the sample switches (14), Til input switches (14), TI2 input switches (14), TI2 output switch functions (16), Til output switch functions (16), and reconstruction switches (16) so as to generate, at the delay circuit (24, 34) output, one or more time-delayed versions of an RF signal applied to the delay circuit (24, 34) input.

3. The delay circuit (24, 34) of claim 1 wherein the TI2 output switch functions (16), Til output switch functions (16), and reconstruction output switch functions (16) are transistor switches.

4. The delay circuit (24, 34) of claim 1 wherein the TI2 output switch functions (16), Til output switch functions (16), and reconstruction output switch functions (16) are tri-state buffers.

5. The delay circuit (24, 34) of any preceding claim, further characterized by N buffers, each interposed between a respective sample capacitor (12) and Til slice input.

6. The delay circuit (24, 34) of any preceding claim, further characterized by M buffers, each interposed between a respective Til capacitor (12) and TI2 slice input.

7. The delay circuit (24, 34) of any preceding claim, further characterized by M Til output capacitors, each connected in shunt configuration between a respective TI2 output and Til output switch function (16).

8. The delay circuit (24, 34) of any preceding claim, further characterized by N reconstruction capacitors, each connected in shunt configuration between a respective Til output and reconstruction switch (16).

9. The delay circuit (34) of any of claims 2-8, further characterized by, at the input of the TI2 stage (30) , one or more sets of N*M parallel connections, each defining a branch, whereby in each branch, the delay circuit (34) circuitry downstream of the branch point is duplicated, and wherein the control circuit (36) is further configured to generate clock signals for each branch soas to provide, at the output of each branch, a time-delayed version of the RF signal, wherein the delay is different than at least one other branch.

10. The delay circuit (34) of any of claims 2-8, further characterized by, at the output of the TI2 stage (30), one or more sets ofN*M parallel connections, each defining a branch, whereby in each branch, the delay circuit (34) circuitry downstream of the branch point is duplicated, and wherein the control circuit (36) is further configured to generate clock signals for each branch so as to provide, at the output of each branch, a time-delayed version of the RF signal, wherein the delay is different than at least one other branch.

11. The delay circuit (34) of claim 9 further characterized by, on a selected branch, a duplicate TI2 stage (30) is connected in series with the TI2 stage (30) of the selected branch.

12. The delay circuit (24, 34) of any of claims 9-11, further comprising a summing circuit connected to two or more branch outputs, configured to combine the differently delayed output signals of the connected branches into a single output signal.

13. The delay circuit (24, 34) of any of claims 2-12, wherein the control circuit (36) is configured to avoid interleaving by one or more Til stage (28) or TI2 stage (30), thereby shortening the delay.

14. The delay circuit (24, 34) of claim 13, wherein the control circuit (36) is configured to avoid interleaving by one or more Til stage (28) or TI2 stage (30) by passing sample values through the stage(s) without interleaving, by controlling the respective clocks to open the relevant input switches and enable the output switch functions, such that samples of the RF signal pass through the stage(s) without time-interleaving.

15. The delay circuit (24, 34) of claim 13, wherein the control circuit (36) is configured to avoid interleaving by one or more Til stage (28) or TI2 stage (30) by routing sample values around the stage(s).

16. A communication device (40, 50), comprising: transmission circuitry (46, 56) configured to transmit a Radio Frequency, RF, signal; receiving circuitry (46, 56) configured to receive an RF signal; and one or both of:a Self-Interference Cancelation, SIC, circuit (18) including the delay circuit (34) of any preceding claim; and an analog or hybrid pre-distortion circuit (39) including the delay circuit (34) of any preceding claim.

17. The communication device (40, 50) of claim 16 wherein the communication device operates in full duplex mode.

18. The communication device (40) of any of claims 16-17, wherein the communication device (40) is a User Equipment, UE, (40) operative in a wireless communication network.

19. The communication device (50) of any of claims 16-17, wherein the communication device (50) is a base station (50) operative in a wireless communication network.

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