Memory coding method, memory decoding method, apparatus, electronic device and storage medium

Abstract

Disclosed in the present disclosure are a memory coding method, a memory decoding method, an apparatus, an electronic device and a storage medium. The coding method comprises: acquiring a data block to be written and a known word string corresponding to said data block; performing error correction coding on said data block and the known word string to obtain error correction information; and splicing the data block and the error correction information to obtain an error-correcting code codeword, and storing same into a memory. The known word string is introduced to undergone error correction coding together with the data block, so as to increase the length of coded data and ensure the protection capability of error-correcting code codewords, and then the data block and the error correction information are spliced to obtain the error-correcting code codeword to be written into the memory. Since the known word string is introduced for error correction coding, when the error-correcting code codeword protects one data block, the strong error correction capability of the error-correcting code codeword having high code length can still be ensured, and the memory access granularity becomes a basic access unit, such that the problems of read amplification and write amplification can be overcome when the data block is updated, thus weakening the contradiction between the code length of the error-correcting code codeword and the memory access granularity.

Description

[0001]This disclosure claims priority to Chinese patent application number 202410190479.3, filed with the China Patent Office on February 20, 2024, entitled "A Method, Apparatus, Electronic Device, and Storage Medium for Memory Encoding and Decoding," the entire contents of which are incorporated herein by reference. Technical Field: This disclosure relates to the field of storage device technology, and more specifically, to a method, apparatus, electronic device, and storage medium for memory encoding and decoding. Background: Persistent memory (PM) provides low-latency access while also enabling persistent data storage. Therefore, its use plays an important role in the storage field. To achieve sufficiently robust error correction capabilities and ensure data accuracy, persistent memory typically uses error correction codes with codewords longer than the basic access unit of persistent memory, such as a cache line. Therefore, currently, multiple basic access units are placed in the same error correction codeword to improve error correction capabilities. For example, K data blocks are used as user data for the error correction code, with each data block being a basic access unit. These K data blocks are subjected to error correction coding (ECC) to generate redundant information for error correction. The K data blocks and the redundant information are then concatenated into a single error correction codeword. However, when one or more of the K data blocks need to be updated, error correction coding must be performed again, requiring not only the corresponding data blocks but also the redundant information to be updated, which can lead to write amplification. Furthermore, when reading any portion of the entire error correction codeword, the entire error correction codeword must be read and decoded, which can also lead to read amplification. SUMMARY OF THE INVENTION The present disclosure addresses the shortcomings of the prior art by providing a memory encoding and decoding method, apparatus, electronic device, and storage medium. This objective is achieved through the following technical solutions. A first aspect of the present disclosure provides a memory encoding method, comprising: obtaining a data block to be written and a known word string corresponding to the data block; performing error correction encoding on the data block and the known word string to obtain error correction information; concatenating the data block and the error correction information to obtain an error correction codeword; and storing the error correction codeword in a memory. The memory encoding method described in the first aspect has at least the following beneficial effects or advantages: By introducing a known word string corresponding to the data block in addition to the data block and performing error correction encoding together with the data block to obtain error correction information, the length of the encoded data is increased, ensuring the protection capability of the error correction codeword. The data block and the error correction information are then concatenated to obtain the error correction codeword, which is then written into the memory.Because known word strings are introduced for error correction encoding, the error correction codeword protects a data block while still ensuring the strong error correction capability of long-length error correction codewords. Memory access granularity becomes a basic access unit, thus overcoming read and write amplification issues when updating data blocks, thereby mitigating the conflict between error correction codeword length and memory access granularity. A second aspect of this disclosure provides a memory decoding method, the method further comprising: reading an error correction codeword to be decoded from a memory; obtaining a known word string corresponding to the error correction codeword; and performing error correction decoding on the error correction codeword based on the known word string to obtain a corrected data block. The memory decoding method described in the second aspect has at least the following beneficial effects or advantages: By introducing a known string corresponding to the error-correcting codeword, the known string and the error-correcting codeword are combined for error-correction decoding. Since the known string is known data and is noise-free and correct, during error-correction decoding, the noise-free portion of the codeword can be used to strengthen the protection of the user data (i.e., data block) in the error-correcting codeword. This reduces the range of erroneous codewords, corrects more erroneous codewords, and thus enhances the error-correcting capability of the error-correcting codeword. Furthermore, since the known string is known to normal users but unknown to abnormal users, even if the abnormal user obtains the error-correcting codeword, they cannot correctly decode it due to the lack of the known string. Therefore, the known string can enhance data security. A third aspect of the present disclosure provides a memory encoding device, comprising: an acquisition module for acquiring a data block to be written and a known word string corresponding to the data block; an encoding module for performing error correction encoding on the data block and the known word string to obtain error correction information; a writing module for concatenating the data block and the error correction information to obtain an error correction codeword, and storing the error correction codeword in the memory. A fourth aspect of the present disclosure provides a memory decoding device, comprising: a codeword reading module for reading an error correction codeword to be decoded from the memory; an acquisition module for acquiring a known word string corresponding to the error correction codeword; and a decoding module for performing error correction decoding on the error correction codeword based on the known word string to obtain an error-corrected data block. A fifth aspect of the present disclosure provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in the first aspect. A sixth aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the program is executed by a processor to implement the method described in the first aspect above.A seventh aspect of the present disclosure provides a computer program that, when executed on a computer, causes the computer to perform the method described in the first aspect. The above description is merely an overview of the technical solution of the present disclosure. To provide a clearer understanding of the technical approach of the present disclosure, implementation may be carried out in accordance with the contents of this specification. To further enhance the understanding of the above and other objectives, features, and advantages of the present disclosure, specific embodiments of the present disclosure are described below. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings described herein are provided to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are provided for illustrative purposes only and are not intended to unduly limit the present disclosure. In the accompanying drawings: FIG1 is a schematic diagram of an application scenario in the prior art; FIG2 is a flow chart of an embodiment of a memory encoding method according to an exemplary embodiment; FIG3A is a schematic diagram of error correction encoding according to an exemplary embodiment; FIG3B is a schematic diagram of known word string and data block permutation modulation according to an exemplary embodiment; FIG3C is a schematic diagram of defective medium replacement according to an exemplary embodiment; FIG4 is a flow chart of an embodiment of a memory decoding method according to an exemplary embodiment; FIG5A is a schematic diagram of error correction decoding according to an exemplary embodiment; FIG5B is a schematic diagram of known word string enabled erasure decoding according to an exemplary embodiment; FIG6 is a flowchart of the overall processing of memory encoding and memory decoding according to an exemplary embodiment; FIG7 is a schematic diagram of the structure of a memory encoding device according to an exemplary embodiment; FIG8 is a schematic diagram of the structure of a memory decoding device according to an exemplary embodiment; FIG9 is a schematic diagram of the hardware structure of an electronic device according to an exemplary embodiment; FIG10 is a schematic diagram of the structure of a storage medium according to an exemplary embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS Exemplary embodiments will be described in detail herein, with examples shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, like numbers in different drawings represent like or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.It should be understood that although the present disclosure may use terms such as "first," "second," and "third" to describe various types of information, such information should not be limited to these terms. These terms are used solely to distinguish information of the same type from one another. For example, without departing from the scope of the present disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the term "if," as used herein, may be interpreted as "when," "when," or "in response to a determination." As previously mentioned, multiple basic access units are currently placed in the same error correction codeword to construct codewords with high code lengths and improve error correction capabilities. As shown in Figure 1, one error correction codeword protects data blocks of two basic access units, represented by user1 and user2, respectively. Error correction encoding is performed on user1 and user2 using an ECC encoder to generate redundant information, parity, for error correction. The protected data, user1 and user2, along with the parity information, are then written to persistent memory as a single error correction codeword. When user2 is updated, the entire error correction code for the corresponding data must be read. The ECC decoder then decodes the error correction code to obtain an error-free error correction code. The user2 portion is then replaced with user2(n). The ECC encoder then performs error correction encoding on user1 and user2(n) to obtain the redundant information parity(n). This information is then written to persistent memory as a single error correction code word, overwritten. Therefore, when part of the data in an error correction code word is updated, in addition to updating the corresponding data itself, the redundant information also needs to be updated. Therefore, the entire error correction code word must be read and decoded, resulting in read amplification. Furthermore, the remaining data in the read error correction code word, after participating in the redundant information update, must be written to persistent memory, resulting in write amplification. When some memory space is freed, if the cleared data is distributed across multiple different error correction codewords, the remaining data must be reassembled for error correction coding, which can also cause write amplification. Furthermore, as shown in Figure 1 , the prior art provides over-provisioning (OP) space in persistent memory for replacing defective media. That is, when the medium storing user 3 is detected to be defective, user 3 is written from the defective medium to the OP space, and the new physical address replaces the defective physical address in the logical address-physical address mapping table.Because reserved space cannot be used for other operations besides replacing defective media, in practical applications, most of the media in the reserved space remains unused throughout its lifecycle, resulting in wasted space. Based on this, the present disclosure proposes a memory encoding and decoding method. During encoding, a known string corresponding to the data block is introduced alongside the data block for error correction encoding to generate error correction information. This increases the length of the encoded data and ensures the protection capability of the error correction codeword. The data block and error correction information are then concatenated to generate the error correction codeword, which is then written into the memory. Because the known string is introduced for error correction encoding, the error correction codeword protects a single data block while still ensuring the strong error correction capability of a long-length error correction codeword. This overcomes the issues of read and write amplification when updating data blocks, thereby mitigating the conflict between the length of the error correction codeword and memory access granularity. The aforementioned known word string is known data and participates in both encoding and decoding, but does not need to be stored. During decoding, the known word string is combined with the error correction codeword for error correction decoding. Since the known word string is noise-free and correct data, during error correction decoding, the noise-free partial codeword can be used to strengthen the protection of the user data (i.e., data block) within the error correction codeword. This reduces the range of erroneous codewords and corrects more erroneous codewords, thereby enhancing the error correction capability of the error correction codeword. Furthermore, since the known word string is known to normal users but unknown to abnormal users, even if an abnormal user obtains the error correction codeword, they cannot correctly decode it due to the lack of the known word string. Therefore, the known word string can enhance data security. The following describes in detail the technical solution of the present disclosure and how it solves the aforementioned technical problems using specific embodiments. The specific embodiments listed above can be combined with each other, and identical or similar concepts or processes may not be described in detail in some embodiments. The following describes the embodiments of the present disclosure in detail with reference to the accompanying drawings. Example 1: Figure 2 is a flow chart illustrating an embodiment of a memory encoding method according to an exemplary embodiment. This method is applied to memory installed in an electronic device. The memory involved in the embodiments of the present disclosure may be persistent memory. To achieve strong error correction capabilities and ensure the accuracy of stored data, it is necessary to use a high-code-length error correction encoding method to encode the data to be written. The electronic device may be a computer, terminal device, or server device. As shown in Figure 2, the method includes the following steps 201-204: Step 201: Obtain a data block to be written and a known word string corresponding to the data block. Step 202: Perform error correction encoding on the data block and the known word string to obtain error correction information.Step 203: Concatenate the data block and the error correction information to obtain an error correction codeword. Step 204: Store the error correction codeword into memory. In the disclosed embodiment, the data block may be a basic access unit of memory, such as a cache line. oIn other words, one error correction codeword protects one basic access unit (BAU) of data block. The known word string is the known data of the corresponding data block and is concatenated with the data block for error correction coding to increase the length of the encoded data. The length of the known word string is the difference between the required code length for error correction coding and the length of the data block. For example, in the scenario shown in Figure 1, the required code length for error correction coding is two BAUs, while the data block length is one BAU. Therefore, the length of the known word string is one BAU. This error correction information is redundant information and should be used to correct errors in the data block and the known word string during decoding. Since the known word string is known correct data and does not require error correction, only the data block needs to be corrected. This reduces the range of erroneous codewords and allows for correction of more erroneous codewords, thereby enhancing the error correction capability of the error correction codeword. For example, as shown in Figure 3A, both data blocks user1 and user2 need to be written to persistent memory. For data block user1 corresponding to known string 1, an ECC encoder is used to perform error correction encoding on known string 1 and user1, obtaining error correction information parity 1. User1 and parity 1 are then written together as a single error correction codeword into persistent memory. For data block user2 corresponding to known string 2, an ECC encoder is used to perform error correction encoding on known string 2 and user2, obtaining error correction information parity 2. User2 and parity 2 are then written together as a single error correction codeword into persistent memory. Comparing Figure 1 with Figure 3A shows that both write two data blocks, occupying the same amount of memory space. However, Figure 1 writes the data as a single error correction codeword, while Figure 3A writes the data as two error correction codewords. This ensures the same high code length and strong error correction capability as in Figure 1. The memory access granularity is also the basic access unit, so even when data is updated, read amplification and write amplification issues are avoided. Therefore, when a data block is updated, error correction encoding is performed on the new data block and the corresponding known string to obtain new error correction information. This information is then written to the same location in persistent memory, completing the update. The entire update process is zero read / write amplification. Accordingly, when some memory space is freed, the physical addresses occupied by the cleared data blocks can be directly used to write new error correction codewords, eliminating the need to reassemble the data for error correction encoding.At this point, the encoding process shown in FIG. 2 is completed. A known word string corresponding to the data block is introduced outside the data block for error correction encoding. Error correction information is obtained along with the data block to increase the length of the encoded data and ensure the protection capability of the error correction codeword. The data block and the error correction information are then concatenated to obtain the error correction codeword and written into memory. Because the known word string is introduced for error correction encoding, the error correction codeword protects a data block while still ensuring the strong error correction capability of the long-length error correction codeword. The memory access granularity becomes the basic access unit. This overcomes read and write amplification issues when updating the data block, thereby mitigating the conflict between the length of the error correction codeword and memory access granularity. In some embodiments of the present disclosure, the process of obtaining the known word string corresponding to the data block can be accomplished by obtaining at least one attribute information of the data block and then concatenating the obtained at least one attribute information to obtain the known word string. In this embodiment, the at least one attribute information obtained is a component of the known string, which can be one or more of the logical address of the data block in memory, the physical address, the identifier of the preset modulation mode, the private key information, or the custom information. The logical address is provided by the application when writing data, while the physical address can be obtained by looking up an address mapping table. The preset modulation mode is a modulation mode for the encoded data designed for the error correction codeword, and its identifier is pre-set. The private key information and the custom information are strings pre-set by the user. For example, all user data can use the same private key information and custom information. Thus, all components of the known string are known data and can be obtained by obtaining and concatenating the various attributes when needed, without the need to record the corresponding data blocks separately. In some embodiments of the present disclosure, the process of performing error correction encoding on the data block and the known string to obtain error correction information can be performed by generating the data to be encoded based on the data block and the known string, and then performing error correction encoding on the data to be encoded to obtain the error correction information. In this embodiment, the data to be encoded is generated from a data block and a known word string. The data contains components of both the data block and the known word string. The length of the data to be encoded determines the length of the error correction information. Therefore, by using the known word string and the data block to generate the data to be encoded, the requirement for long codeword lengths can be met, thereby ensuring strong error correction capabilities. In a specific implementation, the data to be encoded can be input into an ECC encoder, which then performs a function conversion on the data to obtain error correction information output.The error correction encoding process of an ECC encoder can be implemented using relevant technologies. Taking the error correction codeword as an LDPC (Low Density Parity Check Code) code as an example, the ECC encoder uses a preset generator matrix to perform an XOR operation with the data to be encoded, and outputs error correction information based on the operation result. The generator matrix is ​​a pre-designed matrix, and the matrix size is set according to actual error correction requirements. Assume that the data to be encoded s = (c1, c2, c3), 3 bits, and the LDPC code C (s) = (c1, c2, c3, c4, c5, c6), where c4, c5, and c6 are 3 bits of error correction information, and the function conversion relationship is C (s) = sG, where G is the generator matrix. It can be concluded that the size of the generator matrix G is (3*6). The element values ​​in the generator matrix are determined by the design formula for each error correction bit in the error correction information. The process of setting the generator matrix used for error correction encoding can be implemented using relevant technologies and is not specifically limited in this disclosure. In one specific embodiment, the process of generating the data to be encoded based on the data block and the known string involves concatenating the data block and the known string to obtain concatenated data. The data belonging to the data block and the known string in the concatenated data are then repositioned according to a preset modulation scheme to obtain the data to be encoded. In this embodiment, the preset modulation scheme may pre-set a position mapping table to insert the individual data items contained in the known string into different positions within the data block, rather than simply concatenating the data block and the known string to form the data to be encoded. Therefore, using the preset modulation scheme to generate the data to be encoded can enhance encryption. As shown in FIG3B , the known string includes private key information A, user-defined information B, and identification information C for the preset modulation scheme. After scrambling the data positions of the known string and the data block user according to the position mapping table corresponding to the preset modulation scheme, the data to be encoded is obtained. FIG3B shows that each bit of the private key information A, user-defined information B, and identification information C in the known string is inserted into a different position within the data block. In other embodiments of the present disclosure, before generating the data to be encoded based on the data block and the known word string, a cyclic redundancy check (CRC) signature of the data block may be calculated and saved for use in verifying whether the codeword is the written codeword after error correction decoding.In other embodiments of the present disclosure, after the error correction codeword is stored in memory, if the medium corresponding to the physical address of the data block is detected to be defective, the error correction codeword corresponding to the physical address is read from the memory, and the currently available physical address in the memory is obtained. The error correction codeword is then written to the medium corresponding to the obtained physical address, and the obtained physical address is used to update the physical address of the data block in the address mapping table. In this embodiment, the currently available physical address may be the physical address currently indicated by the write pointer in the memory, i.e., the address currently allocated for use. By replacing the defective medium according to the position of the write pointer, reserved space can be released, thereby expanding the available memory capacity. The address mapping table is stored in the memory controller for managing memory usage and records the mapping relationship between logical addresses and physical addresses in the memory space. For example, as shown in FIG3C , when the medium storing data block user1 is detected to be defective, the error correction codeword corresponding to user1 is read and written to the medium corresponding to the physical address indicated by the write pointer in the memory. The address mapping table is then updated using this physical address, thereby completing the replacement of the defective medium. Example 2: FIG4 is a flow chart illustrating an embodiment of a memory decoding method according to an exemplary embodiment. The decoding process provided by this decoding method corresponds to the encoding process shown in FIG2 and FIG3A through FIG3C . As shown in FIG4 , the method includes the following steps 401 to 403: Step 401: Read the error correction codeword to be decoded from the memory. Step 402: Obtain a known word string corresponding to the error correction codeword. Step 403: Perform error correction decoding on the error correction codeword based on the known word string to obtain an error-corrected data block. In the disclosed embodiments, error correction codewords can be read based on a logical address provided by the application. Due to interference in the memory storage channel, the error correction codewords read from the memory may contain noise, necessitating error correction decoding to obtain the same data block as when it was written. As described in the aforementioned embodiments regarding known word strings, the known word strings used during decoding are the known word strings corresponding to the data block used during encoding. These are known data, and the length of the known word strings is the difference between the encoding length required by the error correction encoding and the length of the data block. As can be seen from the aforementioned encoding process, the error correction information in the error correction codewords is generated based on the known word strings and the data block. Therefore, the known word strings are also required during error correction decoding.As shown in FIG5A , a noisy error correction codeword is read from persistent memory. The codeword includes a data block portion, user i, and error correction information, parity i. A corresponding known string i is then obtained. This known string i consists of several segments of custom data, such as the logical address and physical address of the data block to be read in memory, private key information, modulation scheme identification information, and custom information. An ECC decoder performs error correction decoding on the error correction codeword consisting of user i and parity i based on the known string i, outputting the noise-free error correction codewords, user i and parity i. Based on the above-described second embodiment, by introducing a known word string corresponding to the error correction codeword, the known word string and the error correction codeword are jointly subjected to error correction decoding. Since the known word string is known data and is noise-free and correct data, during error correction decoding, the noise-free partial codeword can be used to strengthen the protection of the user data (i.e., data block) in the error correction codeword. This reduces the range of erroneous codewords and corrects more additional erroneous codewords, thereby enhancing the error correction capability of the error correction codeword. Furthermore, since the known word string is known to normal users but unknown to abnormal users, even if the abnormal user obtains the error correction codeword, they cannot correctly decode it due to the lack of the known word string. Therefore, the known word string can enhance data security. In some embodiments of the present disclosure, the process of obtaining the known word string corresponding to the error correction codeword can be performed by obtaining at least one attribute information of the error correction codeword and then concatenating the obtained at least one attribute information to obtain the known word string. In this embodiment, the at least one attribute information includes one or more of the logical address, physical address, identification information of a preset modulation scheme, private key information, or user-defined information of the data block to be read in the memory. The logical address is provided by the application when reading data, while the physical address can be obtained by looking up an address mapping table. For explanations of the identification information, private key information, and user-defined information of the preset modulation scheme, please refer to the relevant descriptions in the aforementioned encoding process embodiments and will not be repeated here. In some embodiments of the present disclosure, error correction decoding of the error correction codeword based on the known word string to obtain an error-corrected data block involves splicing data belonging to the data block portion of the error correction codeword with the known word string to obtain spliced ​​data. Positioning of the data belonging to the data block portion and the data belonging to the known word string in the spliced ​​data is then adjusted according to the preset modulation scheme. The position-adjusted spliced ​​data is then spliced ​​with the error correction information belonging to the error correction portion of the error correction codeword to obtain the data to be decoded. The error-corrected data block is then obtained based on the decoded data.In this embodiment, since the error correction codeword is written into memory after being concatenated with error correction information and a data block, data belonging to the data block can be obtained in the read error correction codeword. This data may contain noise and require error correction. Since the error correction information in the error correction codeword is generated based on the data block and a known word string using a preset modulation scheme, the concatenated data of the data block and the known word string in the read error correction codeword also needs to be permuted using the preset modulation scheme before error correction decoding. In some embodiments of the present disclosure, the process of obtaining an error-corrected data block from the data to be decoded involves performing error correction decoding on the data to be decoded to obtain decoded data. Data other than the error correction information is then obtained from the decoded data as error-corrected concatenated data. The error-corrected data block is then obtained from the error-corrected concatenated data using a demodulation scheme corresponding to the preset modulation scheme. In a specific implementation, the data to be decoded can be input into an ECC decoder, which then performs error correction decoding on the data to be decoded using a parity check matrix to output decoded data. The error correction decoding process of the ECC decoder can be implemented using relevant technologies. Still taking LDPC codes as an example, in the ECC decoder, a check matrix is ​​used to calculate a check vector with the data to be decoded. If the check vector is a zero vector, the data to be decoded is determined to conform to the check matrix, no error correction is required, and the data to be decoded can be directly used as the decoded data. Otherwise, suspected error data in the data to be decoded is located based on the positions of non-zero elements in the check vector. Data in the suspected error data that does not belong to a known string or error correction information is set to zero to obtain modified data to be decoded. The check matrix and the check vector for the modified data to be decoded are then calculated, and a determination is made as to whether the check vector is a zero vector. If not, the process returns to the process of locating suspected error data in the data to be decoded based on the positions of non-zero elements in the check vector until the check vector is a zero vector. The final modified data to be decoded is used as the decoded data after error correction. It is worth noting that if the maximum number of error correction iterations is reached and the calculated check vector still does not meet the zero vector condition, the ECC decoder will output a notification indicating error correction failure. The above-mentioned check matrix is ​​used to perform error detection and correction on the data to be decoded, and has a one-to-one correspondence with the generator matrix used in the encoding process. The check matrix H and the generator matrix G satisfy GH. T =0O Therefore, the check matrix can also be regarded as a pre-designed matrix. Assuming that the data to be decoded is C (s), the calculation formula for calculating the check vector A with the check matrix is: A=HC T(s), which is the multiplication of the check matrix and the transpose of the data to be decoded. The suspected error data mentioned above refers to code bits that may be erroneous in the data to be decoded. The known word string is the deterministic correct data, and the error correction information is also considered known data. Therefore, among these code bits, the code bits belonging to the known word string or error correction information are retained, and the remaining code bits are set to 0. This utilization of the known word string can expand error correction capabilities, narrow the range of erroneous code words, correct more additional erroneous code bits, accelerate decoding convergence, and increase the error correction success rate. For example, the data to be decoded C (s) = (c1, c2, c3, c4, c5, c6) has 6 bits, of which c4, c5, and c6 are error correction information, each having 3 bits. The size of the check matrix H is (3*6). Then, the check vector calculated by combining the check matrix and the data to be decoded has 3 bits, indicating that there are 3 corresponding check equations. c2 / c3 / c5=a2 c1 / c2 / c3 / c6=a3 The above three check equations show that in the check vector A, the value of element al is determined by code bits c1, c2, and c4 in the data to be decoded; the value of element a2 is determined by code bits c2, c3, and c5 in the data to be decoded; and the value of element a3 is determined by code bits c1, c2, c3, and c6 in the data to be decoded. Therefore, if element al is not 0, the suspected erroneous data in the data to be decoded are c1, c2, and c4. Based on the above example, it can be seen that for a check matrix, each row corresponds to an element in the check vector, and each column corresponds to a code bit in the data to be decoded. If the calculated check vector contains a non-zero element, the row corresponding to the non-zero element in the check matrix is ​​located, and the code bit in the data to be decoded corresponding to the 1 element in that row is considered the suspected erroneous data. As shown in FIG5B , elements ai and aj in the check vector obtained by calculating the data to be decoded and the check matrix are not 0. The code bits corresponding to the element ai in the row of the check matrix where the value is 1 are U and V. Code bit U belongs to the known word string and remains unchanged. Code bit V is set to 0. The code bits corresponding to the element aj in the row of the check matrix where the value is 1 are X, Y, and Z. Code bit X belongs to the known word string and code bit Y belongs to error correction information, both of which remain unchanged. Code bit Z is set to 0. In other embodiments of the present disclosure, after error correction decoding is performed on the error correction codeword based on the known word string to obtain an error-corrected data block, a cyclic redundancy check signature of the error-corrected data block can be calculated. This cyclic redundancy check signature is compared with the cyclic redundancy check signature stored during the encoding process. If the comparison is consistent, decoding is determined to be successful. If the comparison is inconsistent, decoding is determined to be unsuccessful. In this embodiment, the error-corrected data block only meets the check conditions of the check matrix, but does not necessarily correspond to the data block when it was written. A cyclic redundancy check signature is calculated and compared with the stored cyclic redundancy check signature to determine whether the error-corrected data block is the data block when it was written.Based on the memory encoding and decoding processes shown in Figures 2, 3A-3C, 4, and 5A-5B, Figure 6 is a flowchart illustrating the overall processing of memory encoding and decoding according to an exemplary embodiment. On the write path, the data block to be written is encoded by a CRC encoder to generate a cyclic redundancy check signature, which is saved. The known word string of the data block and the data block are then input into a modulator for modulation to generate the data to be encoded. Finally, the data to be encoded is passed through an ECC encoder to generate an error correction codeword, which is then written to the persistent memory. On the read path, a noisy error correction codeword is read from persistent memory. The error correction codeword and the corresponding known word string are input into a modulator for modulation to generate data to be decoded. The data to be decoded is then error-corrected by an ECC decoder to generate decoded data. The decoded data is then input into a demodulator for demodulation to generate an error-corrected data block. Finally, the error-corrected data block is subjected to a cyclic redundancy check by a CRC decoder, and a notification of decoding success or failure is output. It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, storage, and display, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties. The collection, use, and processing of the relevant data must comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation portals are provided for the user to select authorization or rejection. Corresponding to the aforementioned embodiments of the memory encoding method, this disclosure also provides embodiments of a memory encoding device. FIG7 is a schematic structural diagram of a memory encoding device according to an exemplary embodiment. The device is used to execute the memory encoding method provided in any of the above embodiments. As shown in FIG7 , the memory encoding device includes: an acquisition module 710, used to acquire a data block to be written and a known word string corresponding to the data block; an encoding module 720, used to perform error correction encoding on the data block and the known word string to obtain the error correction information; and a writing module 730, used to concatenate the data block and the error correction information to obtain an error correction codeword, and store the error correction codeword into a memory.In an optional implementation, the acquisition module 710 is specifically configured to, during the process of acquiring the known word string corresponding to the data block, acquire at least one piece of attribute information of the data block; the at least one piece of attribute information includes one or more of the data block's logical address in memory, physical address, identification information of a preset modulation scheme, private key information, or custom information; concatenate the at least one piece of attribute information to obtain a known word string; wherein the length of the known word string is the difference between the code length required for error correction coding and the length of the data block. In an optional implementation, the encoding module 720 is specifically configured to generate data to be encoded based on the data block and the known word string; perform error correction coding on the data to be encoded to obtain the error correction information. In an optional implementation, the encoding module 720 is specifically configured to, during the process of generating data to be encoded based on the data block and the known word string, concatenate the data block and the known word string to obtain concatenated data; and adjust the positions of data belonging to the data block and data belonging to the known word string in the concatenated data according to a preset modulation scheme to obtain the data to be encoded. In an optional implementation, the apparatus further includes (not shown in FIG. 7 ): a verification module configured to calculate a cyclic redundancy check signature for the data block before the encoding module 720 generates the data to be encoded based on the data block and the known string; and to store the cyclic redundancy check signature for the data block. In an optional implementation, the apparatus further includes (not shown in FIG. 7 ): a medium replacement module configured to, after the write module 730 stores the error correction codeword in the memory, if it detects that the medium corresponding to the physical address of the data block is defective, read the error correction codeword corresponding to the physical address from the memory; obtain a currently available physical address in the memory; write the error correction codeword to the medium corresponding to the obtained physical address, and use the obtained physical address to update the physical address of the data block in the address mapping table. Corresponding to the aforementioned embodiments of the memory decoding method, the present disclosure also provides embodiments of a memory decoding apparatus. FIG8 is a schematic structural diagram of a memory decoding device according to an exemplary embodiment. The device is configured to execute the memory decoding method provided in any of the aforementioned embodiments. As shown in FIG8 , the memory decoding device includes: a codeword reading module 810 configured to read an error correction codeword to be decoded from a memory; an acquisition module 820 configured to acquire a known word string corresponding to the error correction codeword; and a decoding module 830 configured to perform error correction decoding on the error correction codeword based on the known word string to obtain a corrected data block.In an optional implementation, the acquisition module 820 is specifically configured to acquire at least one piece of attribute information of the error correction codeword; the at least one piece of attribute information includes one or more of a logical address of the data block to be read in memory, a physical address, identification information of a preset modulation mode, private key information, or user-defined information; concatenate the at least one piece of attribute information to obtain a known string; wherein the length of the known string is the difference between the code length required by the error correction code and the length of the data block to be read. In an optional implementation, the decoding module 830 is specifically configured to concatenate data belonging to the data block portion of the error correction codeword with the known string to obtain concatenated data; adjust the position of the data belonging to the data block portion and the data belonging to the known string in the concatenated data according to the preset modulation mode; concatenate the position-adjusted concatenated data with the error correction information belonging to the error correction portion of the error correction codeword to obtain data to be decoded; and obtain an error-corrected data block based on the data to be decoded. In an optional implementation, the decoding module 830 is specifically configured to, during the process of obtaining a post-error-corrected data block based on the data to be decoded, perform error-correction decoding on the data to be decoded to obtain decoded data; obtain data other than the error correction information from the decoded data as post-error-corrected spliced ​​data; and obtain a post-error-corrected data block from the post-error-corrected spliced ​​data according to a demodulation mode corresponding to the preset modulation mode. In an optional implementation, the apparatus further includes (not shown in FIG8 ): a verification module configured to calculate a cyclic redundancy check (CRC) signature of the post-error-corrected data block after the decoding module 830 performs error-correction decoding on the error-correcting codeword based on the known word string; determine that decoding is successful if the CRC signature is consistent with a CRC signature stored during the encoding process; and determine that decoding is unsuccessful if the CRC signature is inconsistent with the CRC signature stored during the encoding process. The implementation of the functions and effects of each unit in the apparatus is described in detail in the implementation of the corresponding steps in the method described above and will not be further elaborated here. Since the apparatus embodiments generally correspond to the method embodiments, reference will be made to the description of the method embodiments for relevant details. The apparatus embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of these modules may be selected to achieve the objectives of the disclosed solutions based on actual needs.Those skilled in the art can understand and implement the present invention without inventive effort. The present disclosure also provides an electronic device corresponding to the memory encoding and decoding method provided in the aforementioned embodiments, for executing the aforementioned memory encoding and decoding method. Figure 9 is a hardware structure diagram of an electronic device according to an exemplary embodiment. The electronic device includes a communication interface 601, a processor 602, a memory 603, and a bus 604. The communication interface 601, the processor 602, and the memory 603 communicate with each other via the bus 604. The processor 602 executes the aforementioned memory encoding and decoding method by reading and executing machine-executable instructions in the memory 603 corresponding to the control logic of the memory encoding and decoding method. The details of this method are described in the aforementioned embodiments and will not be repeated here. The memory 603 mentioned in this disclosure can be any electronic, magnetic, optical, or other physical storage device, and can contain stored information, such as executable instructions, data, and so on. Specifically, the memory 603 may be RAM (Random Access Memory), flash memory, a storage drive (such as a hard disk drive), any type of storage disk (such as an optical disk, DVD, etc.), or similar storage media, or a combination thereof. The communication connection between the system network element and at least one other network element is achieved via at least one communication interface 601 (which may be wired or wireless), and may utilize the Internet, a wide area network, a local area network, a metropolitan area network, etc. The bus 604 may be an ISA bus, a PCI bus, or an EISA bus. Such buses may be classified as address buses, data buses, and control buses. The memory 603 is used to store programs, and the processor 602 executes the programs after receiving execution instructions. The processor 602 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method may be completed by hardware integrated logic circuits in the processor 602 or by software instructions. The processor 602 may be a general-purpose processor, including a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It may implement or execute the various methods, steps, and logic diagrams disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or any conventional processor.The steps of the methods disclosed in conjunction with the embodiments of the present disclosure can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules within the decoding processor. The electronic device provided in the embodiments of the present disclosure and the memory encoding and decoding methods provided in the embodiments of the present disclosure are based on the same inventive concept and have the same beneficial effects as the methods employed, executed, or implemented therein. The embodiments of the present disclosure also provide a computer-readable storage medium corresponding to the memory encoding and decoding methods provided in the aforementioned embodiments. Referring to FIG. 10 , the computer-readable storage medium shown is an optical disc 30 storing a computer program (i.e., a program product). When executed by a processor, the computer program executes the memory encoding and decoding methods provided in any of the aforementioned embodiments. It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or other optical or magnetic storage media, and are not further detailed here. The computer-readable storage media provided in the above-described embodiments of the present disclosure and the memory encoding and decoding methods provided in the embodiments of the present disclosure are based on the same inventive concept and have the same beneficial effects as the methods employed, executed, or implemented by the application programs stored therein. The embodiments of the present disclosure also provide a computer program that, when executed on a computer, causes the computer to execute the memory encoding and decoding methods provided in any of the aforementioned embodiments. Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered exemplary only; the true scope and spirit of the present disclosure are indicated by the following claims. It should also be noted that the terms "comprise," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, product, or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, product, or apparatus.In the absence of further limitations, elements defined by the phrase "comprising a..." do not preclude the presence of other identical elements in the process, method, product, or device comprising the elements. The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

Claims 1. A memory encoding method, the method comprising: Obtaining a data block to be written and a known string corresponding to the data block; performing error correction coding on the data block and the known word string to obtain error correction information; The data block and the error correction information are concatenated to obtain an error correction code word; and the error correction code word is stored in a memory.

2. The method according to claim 1, wherein obtaining the known string corresponding to the data block comprises: Acquiring at least one attribute information of the data block; the at least one attribute information including one or more of a logical address, a physical address, identification information of a preset modulation mode, private key information, or custom information of the data block in a memory; and concatenating the at least one attribute information to obtain a known string; The length of the known word string is the difference between the coding length required by the error correction coding and the length of the data block.

3. The method according to claim 1 or 2, wherein the performing error correction coding on the data block and the known word string to obtain error correction information comprises: generating data to be encoded based on the data block and the known string; Perform error correction coding on the data to be encoded to obtain the error correction information.

4. The method according to claim 3, wherein generating the data to be encoded based on the data block and the known string comprises: splicing the data block and the known string to obtain spliced ​​data; According to a preset modulation mode, positions of the data belonging to the data block and the data belonging to the known word string in the spliced ​​data are adjusted to obtain data to be encoded.

5. The method according to claim 3 or 4, before generating the data to be encoded based on the data block and the known string, the method further comprises: Calculating a cyclic redundancy check signature for the data block; A cyclic redundancy check signature of the data block is saved.

6. The method according to any one of claims 1 to 5, further comprising: after storing the error correction codeword into a memory; When detecting that the medium corresponding to the physical address of the data block is defective, reading the error correction codeword corresponding to the physical address from the memory; Acquire a currently available physical address in the memory; write the error correction codeword into a medium corresponding to the acquired physical address, and update the physical address of the data block in the address mapping table using the acquired physical address.

7. A memory decoding method, the method further comprising: Read the error correction codeword to be decoded from the memory; Obtaining a known word string corresponding to the error correction code word; Error correction decoding is performed on the error correction codeword based on the known word string to obtain an error-corrected data block.

8. The method according to claim 7, wherein obtaining the known word string corresponding to the error correction codeword comprises: Obtaining at least one attribute information of the error correction codeword; wherein the at least one attribute information includes one or more of a logical address of a data block to be read in a memory, a physical address, identification information of a preset modulation mode, private key information, or user-defined information; and concatenating the at least one attribute information to obtain a known string; The length of the known word string is the difference between the coding length required by the error correction coding and the length of the data block to be read.

9. The method according to claim 7 or 8, wherein the performing error correction decoding on the error correction codeword based on the known word string to obtain an error-corrected data block comprises: The method includes splicing data belonging to a data block portion in the error correction code codeword and the known word string to obtain spliced ​​data; adjusting the positions of the data belonging to the data block portion and the data belonging to the known word string in the spliced ​​data according to a preset modulation mode; splicing the position-adjusted spliced ​​data with error correction information belonging to the error correction portion in the error correction code codeword to obtain data to be decoded; and obtaining an error-corrected data block based on the data to be decoded.

10. The method according to claim 9, wherein obtaining the error-corrected data block based on the data to be decoded comprises: performing error correction decoding on the data to be decoded to obtain decoded data; obtaining data other than the error correction information from the decoded data as error-corrected spliced ​​data; and obtaining the error-corrected data block from the error-corrected spliced ​​data according to a demodulation mode corresponding to the preset modulation mode.

11. The method according to any one of claims 7 to 10, further comprising: after performing error correction decoding on the error correction codeword based on the known word string; Calculate the cyclic redundancy check signature of the error-corrected data block; If the cyclic redundancy check signature is consistent with the cyclic redundancy check signature saved during the encoding process, determining that the decoding is successful; If the cyclic redundancy check signature is inconsistent with the cyclic redundancy check signature stored during the encoding process, it is determined that the decoding has failed.

12. A memory encoding device, the device comprising: an acquisition module, configured to acquire a data block to be written and a known string corresponding to the data block; an encoding module, configured to perform error correction encoding on the data block and the known word string to obtain the error correction information; A writing module is configured to concatenate the data block and the error correction information to obtain an error correction code word, and store the error correction code word into a memory.

13. A memory decoding device, the device comprising: A codeword reading module, used to read the error correction codeword to be decoded from the memory; An acquisition module, configured to acquire a known word string corresponding to the error correction code word; A decoding module is configured to perform error correction decoding on the error correction codeword based on the known word string to obtain an error-corrected data block.

14. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method according to any one of claims 1 to 11.

15. A computer-readable storage medium having a computer program stored thereon, wherein the program is executed by a processor to implement the method according to any one of claims 1 to 11.

16. A computer program, which, when executed in a computer, causes the computer to execute the method according to any one of claims 1 to 11.

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