Method for manufacturing porous silicon, method for manufacturing capacitor, and capacitor

Abstract

This method for manufacturing porous silicon involves preparing a p-type silicon wafer having a first main surface and a second main surface on the opposite side from the first main surface, directly forming a metal layer in a second region out of a first region to be made porous and a second region not to be made porous on the first main surface of the p-type silicon wafer, and forming porous silicon by anodizing the p-type silicon wafer in an electrolytic solution containing hydrofluoric acid while running current between an electrode disposed on the second main surface of the p-type silicon wafer and a cathode that faces the metal layer and the first main surface of the p-type silicon wafer.

Description

Method for manufacturing porous silicon, method for manufacturing capacitor, and capacitor

[0001] The present disclosure relates to a method for manufacturing porous silicon, a method for manufacturing a capacitor, and a capacitor, and more particularly to a method for manufacturing porous silicon, a method for manufacturing a capacitor including porous silicon, and a capacitor including porous silicon.

[0002] Patent Document 1 discloses a method for manufacturing a capacitor including a p-type silicon substrate having a first main surface and a second main surface, a conductive layer, and a dielectric layer, wherein the first main surface of the p-type silicon substrate includes a capacitance-producing region and a non-capacitance-producing region.

[0003] In the capacitor manufacturing method disclosed in Patent Document 1, a laminated structure of an oxide film and a masking layer is formed on a non-capacitance generating region of a p-type silicon substrate. A backside electrode is then formed over the entire second main surface of the p-type silicon substrate. A porous portion (porous silicon) is then formed in the thickness direction of the p-type silicon substrate in the capacitance generating region not covered by the masking layer by anodizing using a mixture of hydrofluoric acid and ethanol. A dielectric layer is then formed. A conductor layer is then formed.

[0004] International Publication No. 2020 / 184517

[0005] In the manufacturing method of the porous portion (porous silicon) disclosed in Patent Document 1, the corners of the porous portion are formed by embedding from the portion that overlaps the capacitance generating region of the p-type silicon substrate in the thickness direction into the portion that overlaps the non-capacitance generating region of the p-type silicon substrate in the thickness direction.

[0006] In a method for producing porous silicon, it is sometimes desirable to prevent porous silicon from being formed in a second region that is different from the first region to be made porous.

[0007] A method for producing porous silicon according to one aspect of the present disclosure includes preparing a p-type silicon wafer having a first main surface and a second main surface opposite to the first main surface, forming a metal layer directly on a first region of the first main surface of the p-type silicon wafer that is to be made porous and a second region of the first main surface of the p-type silicon wafer that is not to be made porous, and anodizing the p-type silicon wafer in an electrolyte containing hydrofluoric acid while passing a current between an electrode placed on the second main surface of the p-type silicon wafer and a cathode facing the first main surface of the p-type silicon wafer and the metal layer, thereby forming porous silicon.

[0008] A method for manufacturing a capacitor according to one aspect of the present disclosure includes preparing a p-type silicon wafer having a first main surface and a second main surface opposite to the first main surface, forming a metal layer directly in a second region of the first main surface of the p-type silicon wafer, the second region being one that is to be made porous and the first region being one that is not to be made porous, anodizing the p-type silicon wafer while passing current between an electrode placed on the second main surface of the p-type silicon wafer and a cathode facing the first main surface of the p-type silicon wafer and the metal layer in an electrolyte containing hydrofluoric acid, thereby forming porous silicon, forming a dielectric layer on a surface of the porous silicon in the p-type silicon wafer, and forming a conductor layer on the dielectric layer.

[0009] A capacitor according to one aspect of the present disclosure includes a p-type silicon substrate, a dielectric layer, a conductor layer, and a silicide layer. The p-type silicon substrate has a first main surface and a second main surface opposite the first main surface. The p-type silicon substrate includes porous silicon. The dielectric layer is disposed on a surface of the porous silicon in the p-type silicon substrate. The conductor layer is stacked on the dielectric layer. The silicide layer is in contact with a second region, distinct from a first region in which porous silicon is formed on the first main surface of the p-type silicon substrate, and surrounding the entire first region, and is electrically connected to the p-type silicon substrate.

[0010] A capacitor according to one aspect of the present disclosure includes a p-type silicon substrate, a dielectric layer, a conductor layer, an insulating layer, and a metal layer. The p-type silicon substrate has a first main surface and a second main surface opposite the first main surface. The p-type silicon substrate includes porous silicon. The dielectric layer is disposed on a surface of the porous silicon in the p-type silicon substrate. The conductor layer is stacked on the dielectric layer. The insulating layer is disposed on the first main surface of the p-type silicon substrate. The insulating layer is disposed on the first main surface of the p-type silicon substrate. The insulating layer has a first opening and a second opening surrounding the first opening. The first opening in the insulating layer exposes a first region of the p-type silicon substrate where porous silicon is formed. The second opening in the insulating layer exposes a portion of a second region on the first main surface of the p-type silicon substrate that is different from the first region and surrounds the entire periphery of the first region. The metal layer is disposed across the portion of the insulating layer exposed by the second opening in the second region of the first main surface of the p-type silicon substrate and the main surface of the insulating layer, and the metal layer is in contact with the first main surface of the p-type silicon substrate and electrically connected to the p-type silicon substrate.

[0011] According to the method for manufacturing porous silicon, the method for manufacturing a capacitor, and the capacitor according to the above aspects of the present disclosure, it is possible to prevent porous silicon from being formed in a second region that is different from the first region to be made porous.

[0012] FIG. 1 is a schematic cross-sectional view of a capacitor according to a first embodiment. FIG. 2 is a plan view of the capacitor. FIG. 3A is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 3B is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 4A is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 4B is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 5A is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 5B is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 6 is an explanatory diagram of a method for manufacturing the capacitor according to the first embodiment. FIG. 7 is a partially cutaway perspective view of a capacitor according to a second embodiment. FIG. 8 is a plan view of the capacitor according to the first embodiment. FIG. 9A is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 9B is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 10 is a plan view of a wafer illustrating the manufacturing method according to the first embodiment. FIG. 11A is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 11B is a cross-sectional view illustrating steps in a method for manufacturing the capacitor according to the first embodiment. FIG. 12 is a partially cutaway perspective view illustrating the manufacturing method according to the first embodiment. 13A, 13B, and 14 are cross-sectional views illustrating steps in a method for manufacturing the capacitor according to the embodiment of the present invention.

[0013] Hereinafter, embodiments 1, 2, etc. will be described with reference to the drawings. The drawings referred to in the following embodiments 1, 2, etc. are schematic diagrams, and the sizes and thicknesses of the components in the drawings do not necessarily reflect the actual dimensions, and the size ratios and thickness ratios between the components do not necessarily reflect the actual dimensional ratios.

[0014] (Embodiment 1) (1) Capacitor Before describing the method for manufacturing porous silicon and the method for manufacturing a capacitor 1 according to embodiment 1, the configuration of the capacitor 1 will be described below with reference to Figures 1 and 2. Note that Figure 1 is a cross-sectional view taken along line XX in Figure 2.

[0015] The capacitor 1 according to the first embodiment includes a p-type silicon substrate 2, a dielectric layer 5, a conductor layer 6, and a silicide layer 31. The p-type silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The p-type silicon substrate 2 includes porous silicon 23. The dielectric layer 5 is disposed on a surface 231 of the porous silicon 23 in the p-type silicon substrate 2. The conductor layer 6 is stacked on the dielectric layer 5. The silicide layer 31 is in contact with a second region A2 that surrounds the entire periphery of the first region A1, unlike the first region A1 in which the porous silicon 23 is formed on the first main surface 21 of the p-type silicon substrate 2, and is electrically connected to the p-type silicon substrate 2.

[0016] The first external connection electrode 7 is in contact with the silicide layer 31 and is electrically connected to the p-type silicon substrate 2 via the silicide layer 31. The second external connection electrode 8 is disposed in a second portion 62 of the conductor layer 6 that overlaps the second region A2 in the thickness direction D1 of the p-type silicon substrate 2 and is electrically connected to the conductor layer 6.

[0017] (2) Components of the Capacitor Each component of the capacitor 1 according to the first embodiment will be described below with reference to FIGS.

[0018] (2.1) p-Type Silicon Substrate As shown in FIG. 1 , the p-type silicon substrate 2 has a first main surface 21 arranged in the thickness direction D1 and a second main surface 22 opposite to the first main surface 21. The first main surface 21 and the second main surface 22 are perpendicular to the thickness direction D1. When viewed from above in the thickness direction D1 of the p-type silicon substrate 2, the outer edge of the p-type silicon substrate 2 is rectangular. The thickness of the p-type silicon substrate 2 is, for example, not less than 300 μm and not more than 1 mm.

[0019] The p-type silicon substrate 2 contains, for example, boron as an impurity, but may contain indium as an impurity instead of boron.

[0020] From the viewpoints of suppressing the generation of a surface coating having a plurality of micropores smaller than the plurality of pores 24 on the p-type silicon substrate 2 during the manufacture of the porous silicon 23 in the capacitor 1 and reducing ESR (Equivalent Series Resistance), the resistivity of the p-type silicon substrate 2 is 0.001 Ωcm or more and 100 Ωcm or less, and from the viewpoint of improving the shape of the porous silicon 23, it is more preferable that the resistivity be 1 Ωcm or more and 10 Ωcm or less.

[0021] The p-type silicon substrate 2 includes porous silicon 23. The porous silicon 23 is a porous portion and is formed by anodization as part of the p-type silicon substrate 2. When viewed from a plane in the thickness direction D1 of the p-type silicon substrate 2, a first region A1 (see FIG. 2) is a rectangular region. When viewed from a plane in the thickness direction D1 of the p-type silicon substrate 2, the first region A1 is surrounded by a second region A2 (see FIG. 2). When viewed from a plane in the thickness direction D1 of the p-type silicon substrate 2, the first region A1 is not limited to a rectangular region, and may be, for example, a circular region or a polygonal region other than a rectangular shape.

[0022] The porous silicon 23 has a plurality of pores 24 arranged along the thickness direction D1 of the p-type silicon substrate 2. In the porous silicon 23, the distance L1 between adjacent pores 24 among the plurality of pores 24 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2.

[0023] The plurality of pores 24 are formed in the first main surface 21 of the p-type silicon substrate 2. The depth of each of the plurality of pores 24 in the thickness direction D1 from the first main surface 21 of the p-type silicon substrate 2 is longer than the opening width of the pore 24 in the first main surface 21 of the p-type silicon substrate 2. The plurality of pores 24 are formed from the first main surface 21 of the p-type silicon substrate 2 along the thickness direction D1 of the p-type silicon substrate 2, and do not reach the second main surface 22 of the p-type silicon substrate 2. In other words, the plurality of pores 24 do not penetrate the p-type silicon substrate 2 in the thickness direction D1 of the p-type silicon substrate 2. That is, the plurality of pores 24 are separated from the second main surface 22 of the p-type silicon substrate 2. The opening width of each of the plurality of pores 24 in the first main surface 21 of the p-type silicon substrate 2 is, for example, not less than 0.1 μm and not more than 10 μm. The depth of the plurality of pores 24 is smaller than the thickness of the p-type silicon substrate 2. The depth of each of the pores 24 in the thickness direction D1 of the p-type silicon substrate 2 is, for example, 20 μm to 300 μm, and more preferably 30 μm to 100 μm. The upper limit of the depth of the pores 24 may be determined appropriately depending on, for example, the opening width of the pores 24 and the methods for forming the dielectric layer 5 and the conductor layer 6. The opening width and depth of the pores 24 in the porous silicon 23 of the p-type silicon substrate 2 are values ​​determined, for example, from a cross-sectional SEM (Scanning Electron Microscope) image of the capacitor 1.

[0024] The surface 231 of the porous silicon 23 includes inner surfaces 241 of the pores 24 formed in the first main surface 21 of the p-type silicon substrate 2 and the surface in the first region A1 of the first main surface 21 of the p-type silicon substrate 2. In the embodiment, the inner surfaces 241 of the pores 24 have inner side surfaces and an inner bottom surface.

[0025] In the capacitor 1, the deeper the pores 24 in the porous silicon 23, the larger the surface area of ​​the surface 231 of the porous silicon 23, and the larger the capacitance of the capacitor 1. Furthermore, in the capacitor 1, the larger the number of pores 24 in the porous silicon 23, the larger the surface area of ​​the surface 231 of the porous silicon 23, and the larger the capacitance of the capacitor 1.

[0026] As described above, in the capacitor 1, the distance L1 between two adjacent pores 24 among the plurality of pores 24 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2. In the capacitor 1, the surface area of ​​the surface 231 of the porous silicon 23 can be increased compared to when the distance L1 between two adjacent pores 24 among the plurality of pores 24 is uniform in the thickness direction D1 of the p-type silicon substrate 2. Note that the distance L1 between two adjacent pores 24 among the plurality of pores 24 becomes uniform in the thickness direction D1 of the p-type silicon substrate 2 when the plurality of pores 24 are formed by, for example, dry etching. Furthermore, in the capacitor 1, the opening width of each of the plurality of pores 24 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2.

[0027] In a cross-sectional view from a second direction D2 (see FIG. 2 ) perpendicular to the thickness direction D1 (hereinafter also referred to as the first direction D1) of the p-type silicon substrate 2, as shown in FIG. 1 , the inner surface of the inner surface 241 of one of two adjacent pores 24 and the inner surface of the inner surface 241 of the other pore 24 are not straight lines but are lines with irregularities. The height difference between the peaks and valleys of the irregularities is smaller than the opening width of the pores 24. The height difference between the peaks and valleys of the irregularities is a value obtained, for example, from a cross-sectional SEM image of the capacitor 1. The height difference between the peaks and valleys of the irregularities can be changed, for example, by the impurity concentration of the p-type silicon wafer 20 (see FIG. 3A ) that is the basis of the p-type silicon substrate 2, the conditions of the anodization process, etc.

[0028] (2.2) Dielectric Layer The dielectric layer 5 is disposed so as to expose the first region A1 across the surface 231 of the porous silicon 23 in the p-type silicon substrate 2 and the surface in the second region A2 of the first main surface 21 of the p-type silicon substrate 2. More specifically, the dielectric layer 5 has a shape that follows the surface 231 of the porous silicon 23 in the p-type silicon substrate 2 and the surface in the second region A2 of the first main surface 21 of the p-type silicon substrate 2. That is, the dielectric layer 5 has a shape that follows the inner surfaces 241 including the inner sides of the pores 24 of the porous silicon 23 and the first main surface 21 of the p-type silicon substrate 2. The dielectric layer 5 straddles the surface 231 of the porous silicon 23 and the main surface 311 of the silicide layer 31.

[0029] The thickness of the dielectric layer 5 is, for example, 10 nm to 500 nm, and the upper limit of the thickness of the dielectric layer 5 is limited by the opening width of the pores 24 of the porous silicon 23 in one direction along the first main surface 21 of the p-type silicon substrate 2, the thickness of the conductor layer 6 in the pores 24 of the porous silicon 23 in the above-mentioned one direction, and the like.

[0030] The dielectric layer 5 has a multilayer structure in which a plurality of dielectric films are stacked, but is not limited to this and may be a single dielectric layer. When the dielectric layer 5 has a multilayer structure, it includes, for example, a first dielectric film (e.g., a first silicon oxide film), a second dielectric film (e.g., a silicon nitride film) on the first dielectric film, and a third dielectric film (e.g., a second silicon oxide film) on the second dielectric film. The material of the first silicon oxide film and the second silicon oxide film may be, for example, silicon dioxide (SiO ２ The composition of each of the first silicon oxide film and the second silicon oxide film is strictly SiO ２ It is not essential that the first silicon oxide film and the second silicon oxide film have different compositions. When the dielectric layer 5 is formed of a single dielectric film, the material of the dielectric film is, for example, silicon oxide. The material of the dielectric film is not limited to silicon oxide, and may be, for example, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, tungsten oxide, niobium oxide, tantalum oxide, or aluminum oxide.

[0031] (2.3) Conductor Layer The conductor layer 6 is laminated on the dielectric layer 5. The conductor layer 6 is formed on the dielectric layer 5. When viewed from above in the thickness direction D1 of the p-type silicon substrate 2, the conductor layer 6 overlaps the first region A1 and the second region A2 of the p-type silicon substrate 2. When viewed from above in the thickness direction D1 of the p-type silicon substrate 2, the conductor layer 6 also overlaps the porous silicon 23.

[0032] The conductive layer 6 is, for example, a conductive polysilicon layer. The impurity concentration of the conductive polysilicon layer is, for example, 1×10 １８ cm －３ 1x10 or more ２１ cm －３ is less than or equal to 5×10 １８ cm－３ 1x10 or more ２０ cm －３ It is more preferable that the impurity of the conductive polysilicon layer is, for example, one selected from the group consisting of boron, indium, phosphorus, arsenic, and antimony. The conductor layer 6 is not limited to a conductive polysilicon layer, and may be, for example, a metal electrode layer. The material of the metal electrode layer is, for example, at least one selected from the group consisting of ruthenium, titanium, tantalum, tungsten, and aluminum. More specifically, the material of the metal electrode layer is, for example, ruthenium, titanium, tantalum, tungsten, aluminum, or an alloy mainly containing any of these metals.

[0033] The conductor layer 6 has a first portion 61 overlapping the first region A1 and a second portion 62 overlapping the second region A2 in the thickness direction D1 of the p-type silicon substrate 2. The first portion 61 of the conductor layer 6 overlaps the porous silicon 23 in a plan view from the thickness direction D1 of the p-type silicon substrate 2. The first portion 61 of the conductor layer 6 includes a plurality of columnar portions 611 located in a plurality of pores 24 of the porous silicon 23 of the p-type silicon substrate 2, and a portion 612 where the plurality of columnar portions 611 are connected.

[0034] (2.4) Silicide Layer The silicide layer 31 is disposed in the second region A2 of the first main surface 21 of the p-type silicon substrate 2. The material of the silicide layer 31 is, for example, TiSi. The material of the silicide layer 31 is not limited to TiSi, and may be, for example, CoSi, NiSi, or WSi.

[0035] The silicide layer 31 is electrically connected to the p-type silicon substrate 2. "The silicide layer 31 is electrically connected to the p-type silicon substrate 2" means that the silicide layer 31 and the p-type silicon substrate 2 are in ohmic contact.

[0036] (2.5) First External Connection Electrode As shown in FIG. 1 , the first external connection electrode 7 is disposed on a portion of the main surface 311 of the silicide layer 31. The first external connection electrode 7 is in contact with the silicide layer 31 and is electrically connected to the p-type silicon substrate 2 via the silicide layer 31. More specifically, the first external connection electrode 7 is connected to the silicide layer 31 through an opening 57 formed in a portion 52 of the dielectric layer 5 that is disposed in the second region A2 of the first main surface 21 of the p-type silicon substrate 2. In the capacitor 1, the first external connection electrode 7 is electrically connected to the p-type silicon substrate 2 via the silicide layer 31. The first external connection electrode 7 and the silicide layer 31 form a metal layer.

[0037] In plan view from the thickness direction D1 of the p-type silicon substrate 2, the outer edge of the first external connection electrode 7 is, for example, rectangular (see FIG. 2 ), but is not limited to a rectangular shape and may be, for example, circular. In plan view from the thickness direction D1 of the p-type silicon substrate 2, the first external connection electrode 7 overlaps a part of the second region A2 of the first main surface 21 of the p-type silicon substrate 2, but does not overlap the first region A1. Therefore, in plan view from the thickness direction D1 of the p-type silicon substrate 2, the first external connection electrode 7 does not overlap the porous silicon 23 of the p-type silicon substrate 2.

[0038] The material of the first external connection electrode 7 includes, for example, aluminum, but is not limited to aluminum and may include, for example, gold, platinum, ruthenium, or the like.

[0039] The thickness of the first external connection electrode 7 is, for example, not less than 1 μm and not more than 3 μm.

[0040] (2.6) Second External Connection Electrode The second external connection electrode 8 is connected to the conductive layer 6. In the capacitor 1, the second external connection electrode 8 is electrically connected to the conductive layer 6. "The second external connection electrode 8 is electrically connected to the conductive layer 6" means that the second external connection electrode 8 and the conductive layer 6 are in ohmic contact. In a plan view from the thickness direction D1 of the p-type silicon substrate 2, the second external connection electrode 8 overlaps a part of the second region A2 of the first main surface 21 of the p-type silicon substrate 2, but does not overlap the first region A1. Therefore, in a plan view from the thickness direction D1 of the p-type silicon substrate 2, the second external connection electrode 8 does not overlap the porous silicon 23 of the p-type silicon substrate 2.

[0041] The material of the second external connection electrode 8 includes, for example, aluminum, but is not limited to aluminum and may include, for example, gold, platinum, ruthenium, etc. The material of the second external connection electrode 8 is the same as the material of the first external connection electrode 7, but may be a material different from the material of the first external connection electrode 7.

[0042] The thickness of the second external connection electrode 8 is, for example, 1 μm or more and 3 μm or less. The thickness of the second external connection electrode 8 is the same as the thickness of the first external connection electrode 7, but may be different from the thickness of the first external connection electrode 7.

[0043] (3) Capacitor Manufacturing Method The method for manufacturing the capacitor 1 includes, for example, steps 1, 2, 3, 4, 5, 6, and 7. The method for manufacturing the capacitor 1 will be described below with reference to Figures 3A, 3B, 4A, 4B, 5, 6A, and 6B.

[0044] In the first step, a p-type silicon wafer 20 (see FIG. 3A ) that will become the p-type silicon substrate 2 is prepared. The p-type silicon wafer 20 has a first main surface 201 and a second main surface 202 that are arranged in the thickness direction D11 and are opposite to the first main surface 201. The first main surface 201 and the second main surface 202 are perpendicular to the thickness direction D11. The first main surface 201 of the p-type silicon wafer 20 corresponds to the first main surface 21 of the p-type silicon substrate 2, and the second main surface 202 of the p-type silicon wafer 20 corresponds to the second main surface 22 of the p-type silicon substrate 2. The first main surface 201 of the p-type silicon wafer 20 is, for example, a (100) plane, but is not limited to the (100) plane and may be, for example, a (110) plane or a (111) plane. Furthermore, the first main surface 201 of the p-type silicon wafer 20 may be, for example, a crystal plane having an off angle from the (100) plane of more than 0° and not more than 5°. Here, the "off angle" refers to the tilt angle of the first main surface 201 with respect to the (100) plane. Therefore, if the off angle is 0°, the first main surface 201 is the (100) plane. The resistivity of the p-type silicon wafer 20 is, for example, 0.001 Ωcm or more and 100 Ωcm or less, and is more preferably 1 Ωcm or more and 10 Ωcm or less from the viewpoint of improving the shape of the porous silicon 23.

[0045] In the second step, a metal layer 3 is formed directly in the second region A2 of the first region A1 to be made porous and the second region A2 not to be made porous on the first main surface 201 of the p-type silicon wafer 20, thereby exposing the first region A1 from the metal layer 3. In this embodiment, the metal layer 3 is formed directly in the second region A2. In this embodiment, the second step is a metal layer formation step in which the metal layer 3 is formed. In the second step, the metal layer 3 is formed so that the metal layer 3 surrounds the entire periphery of the first region A1 in a plan view from the thickness direction D11 of the p-type silicon wafer 20. In the second step, for example, first, an adhesion layer 31T (in this embodiment, a layer containing a metal such as a Ti layer that will become the silicide layer 31) is formed on the first main surface 201 of the p-type silicon wafer 20, and then a noble metal layer 32 (in this embodiment, for example, an Au layer or a Pt layer) is formed on the adhesion layer 31T. Thereafter, the laminate of the adhesion layer 31T and the noble metal layer 32 is patterned using photolithography and etching techniques, followed by annealing to form a metal layer 3 composed of a metal-containing silicide layer 31 and the noble metal layer 32 (see FIG. 3B ). In the second step, annealing is performed to form the silicide layer 31 by diffusion between the adhesion layer 31T and the p-type silicon wafer 20. The adhesion layer 31T is not limited to a Ti layer, but may also be a silicide layer. The material of the silicide layer is, for example, TiSi, but is not limited to TiSi and may be other silicide metals such as CoSi, NiSi, or WSi. From the viewpoint of reducing the contact resistance between the metal layer 3 and the p-type silicon substrate 2, it is preferable that the metal layer 3 include a silicide layer as the adhesion layer 31T.

[0046] In this embodiment, the third step is an anodization step in which anodization is performed. In the third step, as shown in FIG. 4A , the p-type silicon wafer 20 is anodized while passing current between an electrode 400 disposed on the second main surface 202 of the p-type silicon wafer 20 and a cathode 600 facing the first main surface 201 of the p-type silicon wafer 20 and the metal layer 3 in an electrolytic solution 500 containing hydrofluoric acid, thereby forming porous silicon 23. More specifically, in the third step, the p-type silicon wafer 20 is anodized using the p-type silicon wafer 20 as the anode, thereby forming a p-type silicon wafer 20 (see FIG. 3A ) containing porous silicon 23. In the anodization step, a cathode 600 is disposed opposite the first main surface 201 of the p-type silicon wafer 20 and the metal layer 3 in the electrolytic solution 500, and a current of a predetermined current density is passed between the anode and the cathode using the p-type silicon wafer 20 as the anode for a predetermined time. As a result, the anodization process forms porous silicon 23 by making a portion of the p-type silicon wafer 20 porous. The electrolyte 500 is, for example, a mixture of hydrofluoric acid, alcohol, and water. The alcohol is, for example, ethanol, but is not limited to ethanol. Other examples include isopropanol (IPA), methanol, and propanol. Instead of alcohol, organic solvents such as dimethylformamide (DMF), dimethyl sulfoxide (DMSO), and diethyl ether may be used in the electrolyte 500. In the third step, the shape and depth of the pores 24 can be controlled by changing at least one of the hydrogen fluoride concentration in the electrolyte 500, the predetermined current density, and the predetermined time. The hydrogen fluoride concentration in the electrolyte 500 is, for example, 1 wt% to 80 wt%, and more preferably 1 wt% to 25 wt%. Furthermore, in the method for manufacturing the capacitor 1, the shape of the pores 24 can also be changed by changing the resistivity of the p-type silicon wafer 20. The cathode 600 is resistant to the electrolyte 500. The cathode 600 is, for example, a platinum electrode. The method for manufacturing the porous silicon 23 according to this embodiment includes first to third steps. A more detailed description of the anodization process will be given later.

[0047] In the fourth step, the electrode 400 on the second main surface 202 of the p-type silicon wafer 20 is etched away, and the noble metal layer 32 on the silicide layer 31 is etched away, thereby obtaining the structure shown in FIG. 4B.

[0048] 5A, the dielectric layer 5 is formed. In this embodiment, the fifth step is a dielectric layer formation step of forming the dielectric layer 5. In the fifth step, the first silicon oxide film of the dielectric layer 5 is formed by, for example, a CVD method, the silicon nitride film of the dielectric layer 5 is formed by, for example, a CVD method, and the second silicon oxide film of the dielectric layer 5 is formed by, for example, a CVD method. The first silicon oxide film may be formed by a thermal oxidation method.

[0049] 5B , in the sixth step, a conductor layer 6 is formed on the dielectric layer 5. In this embodiment, the sixth step is a conductor layer formation step in which the conductor layer 6 is formed. More specifically, in the sixth step, a conductor material layer that will become the conductor layer 6 is first formed on the dielectric layer 5. In the sixth step, the conductor material layer is formed by, for example, a CVD method, and then the conductor material layer is patterned using, for example, photolithography and etching techniques to form the conductor layer 6 made of a part of the conductor material layer.

[0050] In the seventh step, the first external connection electrode 7 (see FIG. 1 ) and the second external connection electrode 8 (see FIG. 1 ) are formed. In this embodiment, the seventh step is an electrode formation step in which the first external connection electrode 7 and the second external connection electrode 8 are formed. More specifically, in the seventh step, an opening 57 (see FIG. 1 ) is first formed in the dielectric layer 5 to expose a portion of the silicide layer 31 on the second region A2 of the first main surface 21 of the p-type silicon wafer 20. In the seventh step, the opening 57 is formed using, for example, photolithography and etching techniques. Thereafter, the first external connection electrode 7 and the second external connection electrode 8 are formed using, for example, a thin-film formation method, photolithography and etching techniques, or the like. The thin-film formation method is, for example, a vapor deposition method, a sputtering method, or a CVD method.

[0051] In the method for manufacturing the capacitor 1, a p-type silicon wafer 20 is prepared in the first step, and then steps 2 to 7 are performed to obtain a wafer including a plurality of capacitors 1. In the method for manufacturing the capacitor 1, after step 7, the wafer is cut with, for example, a dicing saw or a laser dicing device, thereby obtaining a plurality of capacitors 1.

[0052] (4) Anodizing Treatment In the anodizing treatment, as described above, a mixed solution of hydrofluoric acid, alcohol (for example, ethanol), and water is used as the electrolyte 500 (see FIG. 4A).

[0053] 6, in the first region A1 of the first main surface 201 of the p-type silicon wafer 20 that is not covered with the metal layer 3 and is exposed from the metal layer 3, the p-type silicon wafer 20 is made porous to form porous silicon 23. When making the p-type silicon wafer 20 porous, holes are formed in the first region A1. ＋ Then, it is considered that the reaction of formula (1) occurs in the first region A1 of the first main surface 201 of the p-type silicon wafer 20. The arrows in FIG. ＋ The flow of Si+6F is shown in the figure. － +2H ＋ +2h ＋ →SiF ６ ２－ +H ２ In this embodiment, the anodization process is performed using the metal layer 3 formed directly on the second region A2 of the first main surface 201 of the p-type silicon wafer 20 as a mask layer. As a result, in this embodiment, during the anodization process, holes h moving through the p-type silicon wafer 20 in a projection region of the metal layer 3 on the p-type silicon wafer 20, which is a region where the metal layer 3 overlaps the p-type silicon wafer 20 as viewed in the thickness direction D11, are ＋However, the metal ions are more likely to flow into the metal layer 3 and less likely to flow into the projected area of ​​the first region A1 in the thickness direction D11 of the p-type silicon wafer 20, i.e., the first region A1 on the first main surface 201 of the p-type silicon wafer 20. The "projected area of ​​the metal layer 3 on the p-type silicon wafer 20" refers to the projected area of ​​the metal layer 3 on the p-type silicon wafer 20 in the thickness direction D11 of the p-type silicon wafer 20. Furthermore, the "projected area of ​​the first region A1 on the p-type silicon wafer 20" refers to the projected area of ​​the first region A1 on the p-type silicon wafer 20 in the thickness direction D11 of the p-type silicon wafer 20. Therefore, the "projected area of ​​the first region A1 on the p-type silicon wafer 20" does not overlap with the metal layer 3 in the thickness direction D11 of the p-type silicon wafer 20.

[0054] In this embodiment, during the anodization treatment, holes h that flowed from the p-type silicon wafer 20 into the metal layer 3 and reached the main surface 30 of the metal layer 3 are present on the main surface 30 of the metal layer 3. ＋ It is believed that the reaction of formula (2) occurs between the 2H and the water in the electrolyte solution 500. ２ O+4h ＋ →O ２ ↑+4H ＋ Formula (2) Therefore, in this embodiment, the hole h of the projected area of ​​the metal layer 3 on the p-type silicon wafer 20 ＋ is likely to flow into the metal layer 3, and the hole h ＋ is easily supplied to the main surface 30 of the metal layer 3, the holes h ＋ is easily consumed near the interface between the main surface 30 of the metal layer 3 and the electrolyte 500. As a result, in this embodiment, the hole h ＋ The rate at which the hole h ＋Therefore, in this embodiment, the mask layer used in the anodization process is made of the metal layer 3 formed directly on the first main surface 201 of the p-type silicon wafer 20, and it is possible to prevent pores from being formed under the mask layer along a direction inclined with respect to the thickness direction D11 of the p-type silicon wafer 20.

[0055] As described above, in this embodiment, pores extending in a direction inclined with respect to the thickness direction D11 of the p-type silicon wafer 20 are prevented from being formed near the second region A2 between the second region A2 of the first main surface 201 and the second main surface 202 of the p-type silicon wafer 20.

[0056] (5) Advantages The method for producing porous silicon 23 according to the first embodiment includes the steps of: preparing a p-type silicon wafer 20 having a first main surface 201 and a second main surface 202 opposite to the first main surface 201; forming a metal layer 3 in the second region A2 of the first region A1 to be made porous on the first main surface 201 of the p-type silicon wafer 20 and a second region A2 not to be made porous; and anodizing the p-type silicon wafer 20 in an electrolytic solution 500 containing hydrofluoric acid while passing current between an electrode 400 placed on the second main surface 202 of the p-type silicon wafer 20 and a cathode 600 facing the first main surface 201 and the metal layer 3 of the p-type silicon wafer 20, thereby forming porous silicon 23.

[0057] According to the above configuration, it is possible to prevent the formation of porous silicon 23 in the second region A2, which is different from the first region A1 to be made porous on the first main surface 201 of the p-type silicon wafer 20.

[0058] The method for manufacturing the capacitor 1 according to the first embodiment includes the steps of: preparing a p-type silicon wafer 20 having a first main surface 201 and a second main surface 202 opposite to the first main surface 201; forming a metal layer 3 directly in the second region A2 of a first region A1 to be made porous on the first main surface 201 of the p-type silicon wafer 20 and a second region A2 not to be made porous; anodizing the p-type silicon wafer 20 while passing current between an electrode 400 placed on the second main surface 202 of the p-type silicon wafer 20 and a cathode 600 facing the first main surface 201 and the metal layer 3 of the p-type silicon wafer 20 in an electrolyte 500 containing hydrofluoric acid, thereby forming porous silicon 23; forming a dielectric layer 5 on a surface 231 of the porous silicon 23 in the p-type silicon wafer 20; and forming a conductor layer 6 on the dielectric layer 5.

[0059] The above configuration makes it possible to prevent the formation of porous silicon 23 in the second region A2, which is different from the first region A1 to be made porous, on the first main surface 201 of the p-type silicon wafer 20. The above configuration makes it possible to prevent side etching from occurring when anodizing the p-type silicon wafer 20, thereby improving the manufacturing yield of the capacitor 1. The above configuration also makes it possible to prevent the formation of pores inclined with respect to the thickness direction D11 in the projection region of the metal layer 3 in the thickness direction D11 of the p-type silicon wafer 20. This makes it possible to improve the film-forming properties of the dielectric layer 5 and the conductor layer 6 in the multiple pores 24 of the porous silicon 23.

[0060] The capacitor 1 according to the first embodiment includes a p-type silicon substrate 2, a dielectric layer 5, a conductor layer 6, and a silicide layer 31. The p-type silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. The p-type silicon substrate 2 includes porous silicon 23. The dielectric layer 5 is disposed on a surface 231 of the porous silicon 23 in the p-type silicon substrate 2. The conductor layer 6 is stacked on the dielectric layer 5. The silicide layer 31 is in contact with a second region A2 that is different from a first region A1 in which the porous silicon 23 is formed on the first main surface 21 of the p-type silicon substrate 2 and that surrounds the first region A1 over the entire periphery. The silicide layer 31 is electrically connected to the p-type silicon substrate 2.

[0061] According to the above configuration, it is possible to prevent the porous silicon 23 from being formed in the second region A2 different from the first region A1. Furthermore, according to the above configuration, the silicide layer 31 in contact with the first main surface 21 of the p-type silicon substrate 2 is electrically connected to the p-type silicon substrate 2, so that it is possible to reduce the ESR.

[0062] Second Embodiment Before describing a method for manufacturing porous silicon 23 and a method for manufacturing a capacitor 1A according to a second embodiment, the configuration of the capacitor 1A will be described with reference to Fig. 7 and Fig. 8. Fig. 7 is a partially cutaway perspective view of the capacitor 1A in Fig. 8, and the cross section in Fig. 7 is the cross section taken along line X-X in Fig. 8.

[0063] Regarding the capacitor 1A according to the second embodiment, the same components as those of the capacitor 1 according to the first embodiment (see FIGS. 1 and 2) are denoted by the same reference numerals and the description thereof will be omitted.

[0064] (1) Capacitor A capacitor 1A according to the second embodiment includes a p-type silicon substrate 2, a dielectric layer 5, a conductor layer 6, a first external connection electrode 7, a second external connection electrode 8, an insulating layer 4, and a metal layer 3. The p-type silicon substrate 2 includes porous silicon 23. The dielectric layer 5 is disposed on a surface 231 of the porous silicon 23 in the p-type silicon substrate 2. The conductor layer 6 is laminated on the dielectric layer 5. The insulating layer 4 has a first opening 41 exposing the porous silicon 23 in the p-type silicon substrate 2 and a second opening 42 surrounding the first opening 41. The metal layer 3 is disposed across a portion of the first main surface 21 of the p-type silicon substrate 2 exposed by the second opening 42 of the insulating layer 4 and a main surface 40 of the insulating layer 4. The metal layer 3 is in contact with the first main surface 21 of the p-type silicon substrate 2 and is electrically connected to the p-type silicon substrate 2.

[0065] The capacitor 1 according to the second embodiment further includes a first external connection electrode 7 and a second external connection electrode 8. The first external connection electrode 7 is connected to the p-type silicon substrate 2. The second external connection electrode 8 is connected to the conductive layer 6.

[0066] (2) Components of the Capacitor Hereinafter, each component of the capacitor 1A according to the second embodiment will be described with reference to FIGS.

[0067] 7, the p-type silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. When viewed in a thickness direction D1 of the p-type silicon substrate 2, the outer edge of the p-type silicon substrate 2 has a rectangular shape.

[0068] The p-type silicon substrate 2 includes porous silicon 23. The porous silicon 23 is a porous portion formed by anodization as part of the p-type silicon substrate 2. When viewed from a plane in the thickness direction D1 of the p-type silicon substrate 2, a first region A1 (see FIG. 8) is a rectangular region. When viewed from a plane in the thickness direction D1 of the p-type silicon substrate 2, the first region A1 is surrounded by a second region A2 (see FIG. 8).

[0069] The porous silicon 23 has a plurality of pores 24 arranged along the thickness direction D1 of the p-type silicon substrate 2. In the porous silicon 23, the distance L1 between adjacent pores 24 among the plurality of pores 24 is non-uniform in the thickness direction D1 of the p-type silicon substrate 2.

[0070] The plurality of pores 24 are formed in the first main surface 21 of the p-type silicon substrate 2. Each of the plurality of pores 24 is a hole whose depth in the thickness direction D1 of the p-type silicon substrate 2 from the first main surface 21 of the p-type silicon substrate 2 is longer than the opening width of the pore 24 in the first main surface 21 of the p-type silicon substrate 2. The plurality of pores 24 are formed from the first main surface 21 of the p-type silicon substrate 2 along the thickness direction D1 of the p-type silicon substrate 2, and do not reach the second main surface 22 of the p-type silicon substrate 2.

[0071] (2.2) Dielectric Layer The dielectric layer 5 is disposed so as to cover the surface 231 of the porous silicon 23 in the p-type silicon substrate 2, the insulating layer 4, and the metal layer 3. More specifically, the dielectric layer 5 has a shape that conforms to the surface 231 including the inner surfaces of the pores 24 of the porous silicon 23 in the p-type silicon substrate 2, the insulating layer 4, and the metal layer 3. The dielectric layer 5 covers the portions of the insulating layer 4 that are not covered by the metal layer 3. The dielectric layer 5 also covers most of the metal layer 3. The dielectric layer 5 has an opening 57 that exposes a portion of the main surface 30 of the metal layer 3.

[0072] (2.3) Conductor Layer The conductor layer 6 is laminated on the dielectric layer 5. The conductor layer 6 is formed on the dielectric layer 5. When viewed from above in the thickness direction D1 of the p-type silicon substrate 2, the conductor layer 6 overlaps the first region A1 and the second region A2 of the p-type silicon substrate 2. When viewed from above in the thickness direction D1 of the p-type silicon substrate 2, the conductor layer 6 also overlaps the porous silicon 23.

[0073] The conductor layer 6 has a first portion 61 overlapping the first region A1 in the thickness direction D1 of the p-type silicon substrate 2, a second portion 62 overlapping the second region A2, and a third portion 63 overlapping the metal layer 3. The first portion 61 of the conductor layer 6 overlaps the porous silicon 23 in a plan view from the thickness direction D1 of the p-type silicon substrate 2. The first portion 61 of the conductor layer 6 includes a plurality of columnar portions 611 located in a plurality of pores 24 of the porous silicon 23 of the p-type silicon substrate 2 and a portion 612 where the plurality of columnar portions 611 are connected. A portion of the insulating layer 4 is interposed between the second portion 62 of the conductor layer 6 and the first main surface 21 of the p-type silicon substrate 2. A portion of the dielectric layer 5 is interposed between the third portion 63 of the conductor layer 6 and the main surface 30 of the metal layer 3.

[0074] (2.4) Insulating Layer The insulating layer 4 is disposed in the second region A2 of the first main surface 21 of the p-type silicon substrate 2. The insulating layer 4 has electrical insulating properties. The material of the insulating layer 4 is, for example, SiO ２ or Si ３ N ４ The insulating layer 4 is, for example, a silicon oxide film or a silicon nitride film, but may also be a laminated film of a silicon oxide film and a silicon nitride film. The insulating layer 4 is disposed on the first main surface 21 of the p-type silicon substrate 2. The insulating layer 4 has a first opening 41 that exposes the porous silicon 23 in the p-type silicon substrate 2 and a second opening 42 that surrounds the first opening 41. The opening shape of the first opening 41 is rectangular, but is not limited to rectangular and may be, for example, circular. In a plan view from the thickness direction D1 of the p-type silicon substrate 2, the second opening 42 surrounds the entire periphery of the first opening 41.

[0075] In the insulating layer 4, the shortest distance L10 between the first opening 41 and the second opening 42 in a direction perpendicular to the thickness direction D1 of the p-type silicon substrate 2 is 1 μm or more and 50 μm or less, and more preferably 5 μm or more and 10 μm or less.

[0076] (2.5) Metal Layer The metal layer 3 is disposed across the portion of the first main surface 21 of the p-type silicon substrate 2 exposed by the second opening 42 of the insulating layer 4 and the main surface 40 of the insulating layer 4 .

[0077] In a plan view from the thickness direction D1 of the p-type silicon substrate 2, the metal layer 3 has a shape that conforms to the first opening 41 of the insulating layer 4. In this embodiment, the shape of the first opening 41 of the insulating layer 4 is rectangular, and the metal layer 3 has a rectangular frame shape.

[0078] The metal layer 3 is electrically connected to the p-type silicon substrate 2. "The metal layer 3 is electrically connected to the p-type silicon substrate 2" means that the metal layer 3 and the p-type silicon substrate 2 are in ohmic contact. The material of the metal layer 3 includes a noble metal (e.g., Au or Pt), as in the first embodiment. The metal layer 3 may have a laminated structure, for example, of an adhesion layer (e.g., a Ti layer) in contact with the first main surface 21 of the p-type silicon substrate 2 and a noble metal layer (e.g., an Au film or a Pt film) laminated on the adhesion layer. The adhesion layer is not limited to a Ti layer, but may also be a silicide layer. The material of the silicide layer is, for example, TiSi, but is not limited to TiSi. It may also be other silicide metals such as CoSi, NiSi, or WSi. From the viewpoint of reducing the contact resistance between the metal layer 3 and the p-type silicon substrate 2, the metal layer 3 preferably includes a silicide layer as an adhesion layer.

[0079] (2.6) First External Connection Electrode In this embodiment, the metal layer 3 also serves as the first external connection electrode 7. Therefore, the first external connection electrode 7 is electrically connected to the p-type silicon substrate 2 through the second opening 42 of the insulating layer 4 that is disposed in the second region A2 of the first main surface 21 of the p-type silicon substrate 2.

[0080] The first external connection electrode 7 overlaps a part of the second region A2 of the first main surface 21 of the p-type silicon substrate 2, but does not overlap the first region A1, in plan view from the thickness direction D1 of the p-type silicon substrate 2. Therefore, the first external connection electrode 7 does not overlap the porous silicon 23 of the p-type silicon substrate 2, in plan view from the thickness direction D1 of the p-type silicon substrate 2.

[0081] (2.7) Second External Connection Electrode In this embodiment, a second portion 62 of the conductive layer 6 that overlaps the second region A2 of the first main surface 21 of the p-type silicon substrate 2 in the thickness direction D1 of the p-type silicon substrate 2 also serves as the second external connection electrode 8. Therefore, the second external connection electrode 8 does not overlap the porous silicon 23 of the p-type silicon substrate 2 in a plan view from the thickness direction D1 of the p-type silicon substrate 2.

[0082] The second external connection electrode 8 may be disposed on the second portion 62 of the conductive layer 6 and electrically connected to the conductive layer 6 .

[0083] (3) Method of Manufacturing Capacitor With regard to the method of manufacturing the capacitor 1A according to the second embodiment, the same steps as those in the method of manufacturing the capacitor 1 according to the first embodiment will not be described as appropriate.

[0084] The method for manufacturing the capacitor 1A includes, for example, steps 1, 2, 3, 4, 5, 6, 7, and 8. The method for manufacturing the capacitor 1 will be described below with reference to Figures 9A, 9B, 10, 11A, 11B, 12, 13A, 13B, and 14. In Figure 10, the dashed double-dashed lines indicate dicing lanes.

[0085] In the first step, a p-type silicon wafer 20 (see FIG. 9A ) that will become the base of the p-type silicon substrate 2 is prepared. The p-type silicon wafer 20 has a first main surface 201 and a second main surface 202 opposite to the first main surface 201. The first main surface 201 of the p-type silicon wafer 20 corresponds to the first main surface 21 of the p-type silicon substrate 2, and the second main surface 202 of the p-type silicon wafer 20 corresponds to the second main surface 22 of the p-type silicon substrate 2. The resistivity of the p-type silicon wafer 20 is, for example, 0.001 Ωcm or more and 100 Ωcm or less, and from the viewpoint of improving the shape of the porous silicon 23, it is more preferably 1 Ωcm or more and 10 Ωcm or less.

[0086] In the manufacturing method of the capacitor 1A, the insulating layer 4 (see FIGS. 9B and 10) is formed in the second step, and the metal layer 3 (see FIGS. 9B and 10) is formed in the third step. In this embodiment, the second step is an insulating layer forming step for forming the insulating layer 4, and the third step is a metal layer forming step for forming the metal layer 3.

[0087] In the second step, an insulating layer 4 is formed on the first main surface 201 of the p-type silicon wafer 20. The insulating layer 4 has a first opening 41 exposing a first region A1 of the first main surface 201 of the p-type silicon wafer 20 and a second opening 42 surrounding the first opening 41. The first region A1 is a region of the first main surface 201 of the p-type silicon wafer 20 that is to be made porous. The second region A2 is a region of the first main surface 201 of the p-type silicon wafer 20 that is not to be made porous. The insulating layer 4 does not cover the first region A1. The insulating layer 4 exposes a portion of the second region A2 of the first main surface 201 of the p-type silicon wafer 20 through the second opening 42. The second opening 42 in the insulating layer 4 surrounds the entire periphery of the first opening 41. Furthermore, the inner peripheral edge of the frame-shaped metal layer 3 in a plan view from the thickness direction D1 of the p-type silicon wafer 20 is located away from the opening edge of the first opening 41 in the insulating layer 4.

[0088] In the second step, when forming the insulating layer 4, for example, a silicon oxide layer is formed over the entire first main surface 201 of the p-type silicon wafer 20 by, for example, thermal oxidation, and a silicon nitride layer is formed on the silicon oxide layer by, for example, CVD (Chemical Vapor Deposition). The laminated film of the silicon oxide layer and the silicon nitride layer is then patterned to form the insulating layer 4 having the first opening 41 and the second opening 42. In other words, the insulating layer 4 is composed of part of the laminated film of the silicon oxide layer and the silicon nitride layer. In the second step, instead of forming a laminated film of the silicon oxide layer and the silicon nitride layer, only a silicon oxide layer or only a silicon nitride layer may be formed.

[0089] In the insulating layer 4, the shortest distance L10 between the first opening 41 and the second opening 42 in a direction perpendicular to the thickness direction D11 of the p-type silicon wafer 20 is 1 μm or more and 50 μm or less, and is more preferably 5 μm or more and 10 μm or less from the viewpoints of preventing a portion of the porous silicon 23 formed by the anodization process described below from being formed under the insulating layer 4 and improving the shape of the porous silicon 23 near the boundary between the first region A1 and the second region A2.

[0090] In the third step, a metal layer 3 is formed in the second region A2 of the first region A1 to be made porous and the second region A2 not to be made porous on the first main surface 201 of the p-type silicon wafer 20. In the third step, the metal layer 3 is formed so that the metal layer 3 surrounds the entire periphery of the first region A1 in a plan view from the thickness direction D11 of the p-type silicon wafer 20. The metal layer 3 extends across the portion of the first main surface 201 of the p-type silicon wafer 20 exposed by the second opening 42 of the insulating layer 4 and the main surface 40 of the insulating layer 4. More specifically, in the third step, for example, a metal material layer that will become the metal layer 3 is formed so as to cover the exposed portion of the first main surface 201 of the p-type silicon wafer 20 and the insulating layer 4, and then the metal material layer is patterned to form the metal layer 3 consisting of a portion of the metal material layer. When the metal layer 3 has a single-layer structure, the metal material layer is, for example, an Au layer, but is not limited to an Au layer and may be, for example, a Pt layer. When the metal layer 3 has a laminated structure, the metal material layer includes, for example, an adhesion layer 31T (e.g., a Ti layer) and a noble metal layer 32 (e.g., an Au layer or a Pt layer in this embodiment) on the adhesion layer 31T. In the third step, the metal material layer is patterned using, for example, photolithography and etching techniques to form the metal layer 3. Note that in the third step, after patterning the laminated metal material layer, an annealing process may be performed to form a silicide layer by diffusion between the adhesion layer 31T and the p-type silicon wafer 20. Note that the adhesion layer 31T is not limited to a Ti layer and may be another metal layer, such as a Ni layer or a Cr layer.

[0091] In this embodiment, the fourth step is an anodization step in which anodization is performed. In the fourth step, as shown in FIG. 11A , the p-type silicon wafer 20 is anodized while passing current between an electrode 400 disposed on the second main surface 202 of the p-type silicon wafer 20 and a cathode 600 facing the first main surface 201, metal layer 3, and insulating layer 4 of the p-type silicon wafer 20 in an electrolytic solution 500 containing hydrofluoric acid, thereby forming porous silicon 23. More specifically, in the fourth step, the p-type silicon wafer 20 is anodized using the p-type silicon wafer 20 as the anode, thereby forming a p-type silicon wafer 20 (see FIG. 11A ) containing porous silicon 23. In the anodization step, a cathode 600 is disposed in the electrolytic solution 500 facing the first main surface 201, metal layer 3, and insulating layer 4 of the p-type silicon wafer 20, and a current of a predetermined current density is passed between the anode and the cathode for a predetermined time. As a result, the anodization process forms porous silicon 23 by making a portion of the p-type silicon wafer 20 porous. The electrolyte 500 is, for example, a mixture of hydrofluoric acid, alcohol, and water. The alcohol is, for example, ethanol, but is not limited to ethanol. Other examples include isopropanol (IPA), methanol, and propanol. Instead of alcohol, organic solvents such as dimethylformamide (DMF), dimethyl sulfoxide (DMSO), and diethyl ether may be used in the electrolyte 500. In the fourth step, the shape and depth of the pores 24 can be controlled by changing at least one of the hydrogen fluoride concentration in the electrolyte 500, the predetermined current density, and the predetermined time. The hydrogen fluoride concentration in the electrolyte 500 is, for example, 1 wt% to 80 wt%, and more preferably 1 wt% to 25 wt%. Furthermore, in the manufacturing method of the capacitor 1A, the shape of the pores 24 can also be changed by changing the resistivity of the p-type silicon wafer 20. The method for manufacturing the porous silicon 23 according to this embodiment includes steps 1 to 4. A more detailed description of the anodization process will be given later.

[0092] In the fifth step, the electrode 400 on the second main surface 202 of the p-type silicon wafer 20 is etched away to obtain the structure shown in FIGS. 11B and 12.

[0093] 13A , the dielectric layer 5 is formed. In this embodiment, the 65th step is a dielectric layer formation step of forming the dielectric layer 5. In the 6th step, the first silicon oxide film of the dielectric layer 5 is formed by, for example, a CVD method, the silicon nitride film of the dielectric layer 5 is formed by, for example, a CVD method, and the second silicon oxide film of the dielectric layer 5 is formed by, for example, a CVD method. The first silicon oxide film may be formed by a thermal oxidation method.

[0094] In the manufacturing method of the capacitor 1A, in the seventh step, a conductor layer 6 is formed on the dielectric layer 5 (see FIG. 13B), and then in the eighth step, the dielectric layer 5 is patterned so as to expose a portion of the metal layer 3.

[0095] In this embodiment, the seventh step is a conductor layer forming step of forming the conductor layer 6. More specifically, in the seventh step, first, a conductor material layer that will become the conductor layer 6 is formed on the dielectric layer 5. In the seventh step, the conductor material layer is formed by, for example, a CVD method, and then the conductor material layer is patterned using, for example, photolithography and etching techniques to form the conductor layer 6 made of a part of the conductor material layer.

[0096] In the eighth step, a part of the metal layer 3 is exposed as the first external connection electrode 7 by using, for example, photolithography and etching techniques.

[0097] In the method for manufacturing the capacitor 1A, a p-type silicon wafer 20 is prepared in the first step, and a wafer including a plurality of capacitors 1A is obtained by performing the second to eighth steps. In the method for manufacturing the capacitor 1A, after the eighth step, the wafer is cut with, for example, a dicing saw or a laser dicing device, thereby obtaining a plurality of capacitors 1A.

[0098] (4) Anodizing Treatment In the anodizing treatment, as described above, a mixed solution of hydrofluoric acid, alcohol (for example, ethanol), and water is used as the electrolytic solution 500 (see FIG. 11A).

[0099] 14, in the first region A1 of the first main surface 201 of the p-type silicon wafer 20 that is not covered by either the metal layer 3 or the insulating layer 4, the p-type silicon wafer 20 is made porous to form porous silicon 23. When making the p-type silicon wafer 20 porous, holes are formed in the first region A1. ＋ Then, it is considered that the reaction of formula (3) occurs in the first region A1 of the first main surface 201 of the p-type silicon wafer 20. The arrows in FIG. 14 indicate holes h ＋ The flow of Si+6F is shown in the figure. － +2H ＋ +2h ＋ →SiF ６ ２－ +H ２ In this embodiment, the anodization process is performed using the metal layer 3 and the insulating layer 4 formed directly on the second region A2 of the first main surface 201 of the p-type silicon wafer 20 as a mask layer. As a result, in this embodiment, during the anodization process, holes h moving through the p-type silicon wafer 20 in the projection region of the metal layer 3 and the insulating layer 4 on the p-type silicon wafer 20 are ＋ However, the metal layer 3 is more likely to flow into the metal layer 3 and less likely to flow into the projected area of ​​the first region A1 in the thickness direction D11 of the p-type silicon wafer 20. The "projected area of ​​the metal layer 3 and the insulating layer 4 in the p-type silicon wafer 20" refers to the projected area of ​​the metal layer 3 and the insulating layer 4 in the thickness direction D11 of the p-type silicon wafer 20. Furthermore, the "projected area of ​​the first region A1 in the p-type silicon wafer 20" refers to the projected area of ​​the first region A1 in the thickness direction D11 of the p-type silicon wafer 20. Therefore, the "projected area of ​​the first region A1 in the p-type silicon wafer 20" does not overlap with either the metal layer 3 or the insulating layer 4 in the thickness direction D11 of the p-type silicon wafer 20.

[0100] In this embodiment, during the anodization treatment, holes h that flowed from the p-type silicon wafer 20 into the metal layer 3 and reached the main surface 30 of the metal layer 3 are present on the main surface 30 of the metal layer 3. ＋ It is believed that the reaction of formula (4) occurs between the 2H and the water in the electrolyte solution 500. ２ O+4h ＋ →O ２ ↑+4H ＋ Formula (4) Therefore, in this embodiment, the hole h of the projected area of ​​the metal layer 3 and the insulating layer 4 on the p-type silicon wafer 20 ＋ The hole h in the projection area of ​​the metal layer 3 and the insulating layer 4 in the p-type silicon wafer 20 is easily inflowed into the metal layer 3. ＋ is easily supplied to the main surface 30 of the metal layer 3, the holes h ＋ is easily consumed near the interface between the main surface 30 of the metal layer 3 and the electrolyte 500. As a result, in this embodiment, the hole h ＋ The rate at which the hole h ＋ Therefore, in this embodiment, the mask layer used in the anodization process is made up of the metal layer 3 and the insulating layer 4 formed directly on the first main surface 201 of the p-type silicon wafer 20, and it is possible to prevent pores from being formed under the mask layer along a direction inclined with respect to the thickness direction D11 of the p-type silicon wafer 20.

[0101] As described above, in this embodiment, pores extending in a direction inclined with respect to the thickness direction D11 of the p-type silicon wafer 20 are prevented from being formed near the second region A2 between the second region A2 of the first main surface 201 and the second main surface 202 of the p-type silicon wafer 20.

[0102] (5) Advantages The method for producing porous silicon 23 according to the second embodiment includes the following steps: preparing a p-type silicon wafer 20 having a first main surface 201 and a second main surface 202 opposite to the first main surface 201; forming a metal layer 3 directly in the second region A2 of the first main surface 201 of the p-type silicon wafer 20, which is a first region A1 to be made porous and a second region A2 not to be made porous; anodizing the p-type silicon wafer 20 in an electrolytic solution 500 containing hydrofluoric acid while passing current between an electrode 400 placed on the second main surface 202 of the p-type silicon wafer 20 and a cathode 600 facing the first main surface 201 of the p-type silicon wafer 20 and the metal layer 3, thereby forming porous silicon 23.

[0103] According to the above configuration, it is possible to prevent the porous silicon 23 from being formed in the second region A2, which is different from the first region A1 to be made porous.

[0104] The method for manufacturing the capacitor 1A according to the second embodiment involves forming a metal layer 3 directly in the second region A2 of a first region A1 to be made porous on the first main surface 201 of a p-type silicon wafer 20 and a second region A2 not to be made porous, anodizing the p-type silicon wafer 20 while passing current between an electrode 400 placed on the second main surface 202 of the p-type silicon wafer 20 and a cathode 600 facing the first main surface 201 of the p-type silicon wafer 20 and the metal layer 3 in an electrolytic solution 500 containing hydrofluoric acid, thereby forming porous silicon 23, forming a dielectric layer 5 on a surface 231 of the porous silicon 23 in the p-type silicon wafer 20, and forming a conductor layer 6 on the dielectric layer 5.

[0105] In the method for manufacturing the capacitor 1 according to the second embodiment, the metal layer 3 surrounds the entire periphery of the first region A1 in plan view in the thickness direction D11 of the p-type silicon wafer 20.

[0106] According to the above configuration, it is possible to improve the shape of the portion of the porous silicon 23 formed in the first region A1 near the boundary between the first region A1 and the second region A2.

[0107] Furthermore, in the method for manufacturing the capacitor 1A according to the second embodiment, before forming the metal layer 3, an insulating layer 4 having a first opening 41 exposing the first region A1 in the p-type silicon wafer 20 and a second opening 42 surrounding the first opening 41 is formed on the first main surface 201 of the p-type silicon wafer 20. The metal layer 3 straddles the portion of the first main surface 201 of the p-type silicon wafer 20 exposed by the second opening 42 of the insulating layer 4 and the main surface 40 of the insulating layer 4.

[0108] According to the above configuration, it is possible to improve the accuracy of the shape of the portion of the porous silicon 23 formed in the first region A1 near the boundary between the first region A1 and the second region A2.

[0109] Furthermore, in the manufacturing method of the capacitor 1A according to the second embodiment, the second opening 42 in the insulating layer 4 surrounds the first opening 41 all around, and when viewed in a plan view from the thickness direction D1 of the p-type silicon wafer 20, the inner peripheral edge of the metal layer 3 is positioned at a distance from the opening edge of the first opening 41 in the insulating layer 4.

[0110] According to the above configuration, it is possible to improve the shape of the portion of the porous silicon 23 formed in the first region A1 near the boundary between the first region A1 and the second region A2.

[0111] In addition, in the manufacturing method of the capacitor 1A according to the second embodiment, in the insulating layer 4, the shortest distance L10 between the first opening 41 and the second opening 42 in a direction perpendicular to the thickness direction D11 of the p-type silicon wafer 20 is 1 μm or more and 50 μm or less.

[0112] In addition, in the manufacturing method of the capacitor 1A according to the second embodiment, in the insulating layer 4, the shortest distance L10 between the first opening 41 and the second opening 42 in a direction perpendicular to the thickness direction D11 of the p-type silicon wafer 20 is 5 μm or more and 10 μm or less.

[0113] According to the above configuration, when the porous silicon 23 is formed by anodization, it is possible to suppress the formation of pores inclined with respect to the thickness direction D11 of the p-type silicon wafer 20 by side etching in the projection region of the second region (A2) of the first main surface 201 of the p-type silicon wafer 20, while improving the shape of the portion of the porous silicon 23 formed in the first region A1 near the boundary between the first region A1 and the second region A2.

[0114] The capacitor 1A according to the second embodiment includes a p-type silicon substrate 2, a dielectric layer 5, a conductor layer 6, an insulating layer 4, and a metal layer 3. The p-type silicon substrate 2 includes porous silicon 23. The dielectric layer 5 is disposed on a surface 231 of the porous silicon 23 in the p-type silicon substrate 2. The conductor layer 6 is stacked on the dielectric layer 5. The insulating layer 4 is disposed on a first main surface 21 of the p-type silicon substrate 2. The insulating layer 4 has a first opening 41 and a second opening 42 surrounding the first opening 41. The first opening 41 in the insulating layer 4 exposes a first region A1 in the p-type silicon substrate 2 where the porous silicon 23 is formed. The second opening 42 in the insulating layer 4 exposes a portion of a second region A2, which is different from the first region A1 and surrounds the entire periphery of the first region A1, on the first main surface 21 of the p-type silicon substrate 2. The metal layer 3 is disposed across the portion exposed by the second opening 42 of the insulating layer 4 in the second region A2 of the first main surface 21 of the p-type silicon substrate 2 and the main surface 40 of the insulating layer 4. The metal layer 3 is in contact with the first main surface 21 of the p-type silicon substrate 2 and is electrically connected to the p-type silicon substrate 2.

[0115] According to the above configuration, it is possible to prevent the porous silicon 23 from being formed in the second region A2, which is different from the first region A1 to be made porous, thereby improving the shape of the porous silicon 23. Furthermore, according to the above configuration, it is possible to reduce the ESR.

[0116] (Modifications) The first and second embodiments are merely examples of various embodiments of the present disclosure. The first and second embodiments can be modified in various ways depending on the design and the like as long as the object of the present disclosure can be achieved.

[0117] For example, a plurality of circuit elements (e.g., MOSFETs) other than the capacitors 1 and 1A may be formed on the p-type silicon substrate 2. In other words, the capacitors 1 and 1A according to the present disclosure can be applied to semiconductor devices including the capacitors 1 and 1A, for example, IC (Integrated Circuit) chips including the capacitors 1 and 1A.

[0118] Furthermore, in the capacitor 1, when viewed in a plan view from the thickness direction D1 of the p-type silicon substrate 2, the silicide layer 31 surrounds the entire first region A1, but it is not essential that the silicide layer 31 surrounds the entire first region A1.

[0119] Furthermore, in capacitor 1A, when viewed in a plane from the thickness direction D1 of p-type silicon substrate 2, metal layer 3 surrounds first opening 41 all around, but it is not essential that metal layer 3 surrounds first opening 41 all around.

[0120] (Aspects) Based on the above-described first and second embodiments, the present specification discloses the following aspects.

[0121] A method for producing porous silicon (23) according to a first aspect includes preparing a p-type silicon wafer (20) having a first main surface (201) and a second main surface (202) opposite to the first main surface (201), directly forming a metal layer (3) on the second main surface (201) of the p-type silicon wafer (20) out of a first region (A1) to be made porous and a second region (A2) not to be made porous, and anodizing the p-type silicon wafer (20) in an electrolyte (500) containing hydrofluoric acid while passing current between an electrode (400) placed on the second main surface (202) of the p-type silicon wafer (20) and a cathode (600) facing the first main surface (201) and the metal layer (3) of the p-type silicon wafer (20), thereby forming porous silicon (23).

[0122] According to this aspect, it is possible to prevent the formation of porous silicon (23) in the second region (A2) different from the first region (A1) to be made porous.

[0123] In the method for producing porous silicon (23) according to the second aspect, in the first aspect, the metal layer (3) surrounds the entire first region (A1) in a plan view in the thickness direction (D1) of the p-type silicon wafer (20).

[0124] According to this aspect, it is possible to improve the shape of the portion of the porous silicon (23) formed in the first region (A1) near the boundary between the first region (A1) and the second region (A2).

[0125] In the method for producing porous silicon (23) according to the third aspect, in the second aspect, an insulating layer (4) having a first opening (41) exposing a first region (A1) in the p-type silicon wafer (20) and a second opening (42) surrounding the first opening (41) is formed on a first main surface (201) of the p-type silicon wafer (20) before forming a metal layer (3). The metal layer (3) spans a portion of the first main surface (201) of the p-type silicon wafer (20) exposed by the second opening (42) of the insulating layer (4) and the main surface (40) of the insulating layer (4).

[0126] According to this aspect, it is possible to improve the shape of the portion of the porous silicon (23) formed in the first region (A1) near the boundary between the first region (A1) and the second region (A2).

[0127] In the method for producing porous silicon (23) according to the fourth aspect, in the third aspect, the second opening (42) of the insulating layer (4) surrounds the first opening (41) all around, and the inner peripheral edge of the metal layer (3) is located at a distance from the opening edge of the first opening (41) in the insulating layer (4) when viewed in a plan view in the thickness direction (D1) of the p-type silicon wafer (20).

[0128] According to this aspect, it is possible to improve the shape of the portion of the porous silicon (23) formed in the first region (A1) near the boundary between the first region (A1) and the second region (A2).

[0129] A fifth aspect of the present invention relates to a method for producing porous silicon (23) based on the fourth aspect. In the insulating layer (4), the shortest distance (L10) between the first opening (41) and the second opening (42) in a direction perpendicular to the thickness direction (D11) of the p-type silicon wafer (20) is 1 μm or more and 50 μm or less.

[0130] According to this aspect, when forming the porous silicon (23) by anodization, it is possible to suppress the formation of pores inclined with respect to the thickness direction (D11) of the p-type silicon wafer (20) by side etching in the projected region of the second region (A2) of the first main surface (201) of the p-type silicon wafer (20), while improving the shape of the portion of the porous silicon (23) formed in the first region (A1) near the boundary between the first region (A1) and the second region (A2).

[0131] A sixth aspect of the present invention relates to a method for producing porous silicon (23) based on the fourth aspect. In the insulating layer (4), the shortest distance (L10) between the first opening (41) and the second opening (42) in a direction perpendicular to the thickness direction (D11) of the p-type silicon wafer (20) is 5 μm or more and 10 μm or less.

[0132] According to this aspect, when forming the porous silicon (23) by anodization, it is possible to suppress the formation of pores inclined with respect to the thickness direction (D11) of the p-type silicon wafer (20) by side etching in the projected region of the second region (A2) of the first main surface (201) of the p-type silicon wafer (20), while improving the shape of the portion of the porous silicon (23) formed in the first region (A1) near the boundary between the first region (A1) and the second region (A2).

[0133] A method for manufacturing a capacitor (1; 1A) according to a seventh aspect includes the steps of: preparing a p-type silicon wafer (20) having a first main surface (201) and a second main surface (202) opposite to the first main surface (201); forming a metal layer (3) directly on the second region (A2) of a first region (A1) to be made porous and a second region (A2) not to be made porous on the first main surface (201) of the p-type silicon wafer (20); and disposing a metal layer (3) on the second main surface (202) of the p-type silicon wafer (20). The p-type silicon wafer (20) is anodized while passing current between the first main surface (201) of the p-type silicon wafer (20) and a cathode (600) facing the metal layer (3) in an electrolyte (500) containing hydrofluoric acid, thereby forming porous silicon (23), forming a dielectric layer (5) on the surface (231) of the porous silicon (23) in the p-type silicon wafer (20), and forming a conductor layer (6) on the dielectric layer (5).

[0134] According to this aspect, it is possible to prevent the formation of porous silicon (23) in the second region (A2) different from the first region (A1) to be made porous.

[0135] In the method for manufacturing a capacitor (1; 1A) according to the eighth aspect, in the seventh aspect, the metal layer (3) surrounds the entire first region (A1) in a planar view from the thickness direction (D11) of the p-type silicon wafer (20).

[0136] According to this aspect, when forming the porous silicon (23) by anodization, it is possible to suppress the formation of pores inclined with respect to the thickness direction (D11) of the p-type silicon wafer (20) by side etching in the projected region of the second region (A2) of the first main surface (201) of the p-type silicon wafer (20), while improving the shape of the portion of the porous silicon (23) formed in the first region (A1) near the boundary between the first region (A1) and the second region (A2).

[0137] A method for manufacturing a capacitor (1A) according to a ninth aspect is based on the seventh aspect. In the method for manufacturing a capacitor (1A) according to the ninth aspect, before forming a metal layer (3), an insulating layer (4) having a first opening (41) exposing a first region (A1) in the p-type silicon wafer (20) and a second opening (42) surrounding the first opening (41) is formed on a first main surface (201) of the p-type silicon wafer (20). The metal layer (3) spans a portion of the first main surface (201) of the p-type silicon wafer (20) exposed by the second opening (42) of the insulating layer (4) and the main surface (40) of the insulating layer (4).

[0138] According to this aspect, it is possible to prevent a portion of the porous silicon (23) from being formed on the first main surface (201) of the p-type silicon wafer (20) in a projection region of the second region (A2) of the first main surface (201) of the p-type silicon wafer (20).

[0139] A tenth aspect of the present invention relates to a method for manufacturing a capacitor (1A) based on the ninth aspect. In the insulating layer (4), the shortest distance (L10) between the first opening (41) and the second opening (42) in a direction perpendicular to the thickness direction (D11) of the p-type silicon wafer (20) is 1 μm or more and 50 μm or less.

[0140] According to this aspect, when forming the porous silicon (23) by anodization, it is possible to suppress the formation of pores inclined with respect to the thickness direction (D11) of the p-type silicon wafer (20) by side etching in the projected region of the second region (A2) of the first main surface (201) of the p-type silicon wafer (20), while improving the shape of the portion of the porous silicon (23) formed in the first region (A1) near the boundary between the first region (A1) and the second region (A2).

[0141] A method for manufacturing a capacitor (1A) according to an eleventh aspect is based on the ninth aspect. In the insulating layer (4), the shortest distance (L10) between the first opening (41) and the second opening (42) in a direction perpendicular to the thickness direction (D11) of the p-type silicon wafer (20) is 5 μm or more and 10 μm or less.

[0142] According to this aspect, when forming the porous silicon (23) by anodization, it is possible to suppress the formation of pores inclined with respect to the thickness direction (D11) of the p-type silicon wafer (20) by side etching in the projected region of the second region (A2) of the first main surface (201) of the p-type silicon wafer (20), while improving the shape of the portion of the porous silicon (23) formed in the first region (A1) near the boundary between the first region (A1) and the second region (A2).

[0143] In a method for manufacturing a capacitor (1) according to a twelfth aspect, in the eighth aspect, the metal layer (3) includes a silicide layer (adhesion layer 31T) disposed on the first main surface (201) of the p-type silicon wafer (20) and a noble metal layer (32) laminated on the silicide layer (adhesion layer 31T). In the method for manufacturing a capacitor (1) according to the twelfth aspect, the noble metal layer (32) is removed after forming the porous silicon (23) and before forming the dielectric layer (5). The dielectric layer (5) spans the surface (231) of the porous silicon (23) and the main surface (311) of the silicide layer (31). A portion of the conductor layer (6) overlapping the first main surface (201) of the p-type silicon wafer (20) in a plan view from the thickness direction (D11) of the p-type silicon wafer (20) also serves as a first external connection electrode (7). In the method for manufacturing a capacitor (1) according to the twelfth aspect, after forming a conductive layer (6), a second external connection electrode (8) that is different from the first external connection electrode (7) and contacts the silicide layer (31) is formed.

[0144] According to this aspect, it is possible to reduce the ESR of the capacitor (1).

[0145] In the method for manufacturing a capacitor (1; 1A) according to a thirteenth aspect, in any one of the seventh to twelfth aspects, the resistivity of the p-type silicon wafer (20) is 1 Ωcm or more and 10 Ωcm or less.

[0146] According to this embodiment, it is possible to suppress the formation of a microporous layer when anodizing treatment is performed, and it is possible to improve the shape of the porous silicon (23).

[0147] A capacitor (1) according to a fourteenth aspect includes a p-type silicon substrate (2), a dielectric layer (5), a conductor layer (6), and a silicide layer (31). The p-type silicon substrate (2) has a first main surface (21) and a second main surface (22) opposite the first main surface (21). The p-type silicon substrate (2) includes porous silicon (23). The dielectric layer (5) is disposed on a surface (231) of the porous silicon (23) in the p-type silicon substrate (2). The conductor layer (6) is laminated on the dielectric layer (5). The silicide layer (31) is in contact with a second region (A2) that completely surrounds the first region (A1) on the first main surface (21) of the p-type silicon substrate (2), different from the first region (A1) in which the porous silicon (23) is formed, and is electrically connected to the p-type silicon substrate (2).

[0148] According to this aspect, it is possible to prevent the formation of porous silicon (23) in the second region (A2) different from the first region (A1) to be made porous.

[0149] A capacitor (1A) according to a fifteenth aspect includes a p-type silicon substrate (2), a dielectric layer (5), a conductor layer (6), an insulating layer (4), and a metal layer (3). The p-type silicon substrate (2) has a first main surface (21) and a second main surface (22) opposite the first main surface (21). The p-type silicon substrate (2) includes porous silicon (23). The dielectric layer (5) is disposed on a surface (231) of the porous silicon (23) in the p-type silicon substrate (2). The conductor layer (6) is laminated on the dielectric layer (5). The insulating layer (4) is disposed on the first main surface (21) of the p-type silicon substrate (2). The insulating layer (4) has a first opening (41) and a second opening (42) surrounding the first opening (41). The first opening (41) in the insulating layer (4) exposes a first region (A1) in the p-type silicon substrate (2) where the porous silicon (23) is formed. The second opening (42) in the insulating layer (4) exposes a portion of a second region (A2) in the first main surface (21) of the p-type silicon substrate (2), the second region (A2) being different from the first region (A1) and surrounding the entire periphery of the first region (A1). The metal layer (3) is disposed across the portion exposed by the second opening (42) in the insulating layer (4) in the second region (A2) of the first main surface (21) of the p-type silicon substrate (2) and the main surface (40) of the insulating layer (4). The metal layer (3) is in contact with the first main surface (21) of the p-type silicon substrate (2) and is electrically connected to the p-type silicon substrate (2).

[0150] According to this aspect, it is possible to prevent the formation of porous silicon (23) in the second region (A2) different from the first region (A1) to be made porous.

[0151] In the capacitor (1A) according to the sixteenth aspect, in the fifteenth aspect, the metal layer (3) surrounds the first opening (41) all around when viewed in a plan view in the thickness direction (D1) of the p-type silicon substrate (2).

[0152] According to this embodiment, it is possible to further improve the shape of the porous silicon (23) and further reduce the ESR.

[0153] In the capacitor (1A) according to the seventeenth aspect, in the fifteenth or sixteenth aspect, the metal layer (3) includes a silicide layer (31) disposed on the first main surface (21) of the p-type silicon substrate (2), and a noble metal layer (32) stacked on the silicide layer (31).

[0154] According to this embodiment, it is possible to further reduce the ESR.

[0155] A capacitor (1A) according to an eighteenth aspect is based on any one of the fifteenth to seventeenth aspects. In the insulating layer (4), the shortest distance (L10) between the first opening (41) and the second opening (42) in a direction perpendicular to the thickness direction (D1) of the p-type silicon substrate (2) is 1 μm or more and 50 μm or less.

[0156] According to this aspect, when forming porous silicon (23) by anodization, the reaction in the first region (A1) and the reaction in the second region (A2) can be controlled by the pattern design of the insulating layer (4), making it possible to improve the shape of the porous silicon (23) near the boundary between the first region (A1) and the second region (A2).

[0157] A capacitor (1A) according to a 19th aspect is based on any one of the 15th to 17th aspects. In the insulating layer (4), the shortest distance (L10) between the first opening (41) and the second opening (42) in a direction perpendicular to the thickness direction (D1) of the p-type silicon substrate (2) is 5 μm or more and 10 μm or less.

[0158] According to this embodiment, it is possible to further improve the shape of the porous silicon (23) near the boundary between the first region (A1) and the second region (A2).

[0159] In a capacitor (1; 1A) according to a twentieth aspect, in any one of the fifteenth to nineteenth aspects, the resistivity of the p-type silicon substrate (2) is 1 Ωcm or more and 10 Ωcm or less.

[0160] According to this aspect, it is possible to suppress the formation of microporosity when forming the porous silicon (23) by anodization, and it is possible to improve the shape of the porous silicon (23).

[0161] 1, 1A Capacitor 2 p-type silicon substrate 21 First main surface 22 Second main surface 23 Porous silicon 231 Surface 24 Pore 3 Metal layer 31 Silicide layer 311 Main surface 32 Noble metal layer 4 Insulating layer 40 Main surface 41 First opening 42 Second opening 5 Dielectric layer 6 Conductor layer 7 First external connection electrode 8 Second external connection electrode 20 p-type silicon wafer 400 Electrode 500 Electrolyte 600 Cathode A1 First region A2 Second region D1 Thickness direction D11 Thickness direction L1 Distance L10 Shortest distance

Claims

1. A method for producing porous silicon, comprising: preparing a p-type silicon wafer having a first main surface and a second main surface opposite to the first main surface; forming a metal layer directly on a first region of the first main surface of the p-type silicon wafer, the second region being one that is not to be made porous; and anodizing the p-type silicon wafer in an electrolyte containing hydrofluoric acid while passing a current between an electrode placed on the second main surface of the p-type silicon wafer and a cathode facing the first main surface of the p-type silicon wafer and the metal layer, thereby forming the porous silicon.

2. The method for producing porous silicon according to claim 1, wherein the metal layer surrounds the entire periphery of the first region when viewed from above in the thickness direction of the p-type silicon wafer.

3. The method for producing porous silicon according to claim 2, wherein, before forming the metal layer, an insulating layer having a first opening exposing the first region in the p-type silicon wafer and a second opening surrounding the first opening is formed on the first main surface of the p-type silicon wafer, and the metal layer straddles the portion of the insulating layer exposed by the second opening on the first main surface of the p-type silicon wafer and the main surface of the insulating layer.

4. The method for producing porous silicon according to claim 3, wherein the second opening in the insulating layer surrounds the entire periphery of the first opening, and the inner peripheral edge of the metal layer is located at a distance from the edge of the first opening in the insulating layer when viewed in a plan view in the thickness direction of the p-type silicon wafer.

5. The method for producing porous silicon according to claim 4, wherein in the insulating layer, the shortest distance between the first opening and the second opening in a direction perpendicular to the thickness direction of the p-type silicon wafer is 1 μm or more and 50 μm or less.

6. The method for producing porous silicon according to claim 4, wherein in the insulating layer, the shortest distance between the first opening and the second opening in a direction perpendicular to the thickness direction of the p-type silicon wafer is 5 μm or more and 10 μm or less.

7. A method for manufacturing a capacitor, comprising: preparing a p-type silicon wafer having a first main surface and a second main surface opposite to the first main surface; forming a metal layer directly on the second region of the first main surface of the p-type silicon wafer, of which a first region is to be made porous and a second region is not to be made porous; anodizing the p-type silicon wafer while passing a current between an electrode placed on the second main surface of the p-type silicon wafer and a cathode facing the first main surface of the p-type silicon wafer and the metal layer in an electrolyte containing hydrofluoric acid, thereby forming porous silicon; forming a dielectric layer on the surface of the porous silicon of the p-type silicon wafer; and forming a conductor layer on the dielectric layer.

8. The method for manufacturing a capacitor according to claim 7, wherein the metal layer surrounds the entire periphery of the first region when viewed from above in the thickness direction of the p-type silicon wafer.

9. The method for manufacturing a capacitor according to claim 7, wherein, before forming the metal layer, an insulating layer is formed on the first main surface of the p-type silicon wafer, the insulating layer having a first opening exposing the first region in the p-type silicon wafer and a second opening surrounding the first opening, and the metal layer straddles the portion of the insulating layer exposed by the second opening on the first main surface of the p-type silicon wafer and the main surface of the insulating layer.

10. The method for manufacturing a capacitor according to claim 9, wherein in the insulating layer, the shortest distance between the first opening and the second opening in a direction perpendicular to the thickness direction of the p-type silicon wafer is 1 μm or more and 50 μm or less.

11. The method for manufacturing a capacitor according to claim 9, wherein in the insulating layer, the shortest distance between the first opening and the second opening in a direction perpendicular to the thickness direction of the p-type silicon wafer is 5 μm or more and 10 μm or less.

12. The method for manufacturing a capacitor according to claim 8, wherein the metal layer includes a silicide layer disposed on the first main surface of the p-type silicon wafer, and a precious metal layer stacked on the silicide layer, the precious metal layer is removed after the porous silicon is formed and before the dielectric layer is formed, the dielectric layer straddles the surface of the porous silicon and the main surface of the silicide layer, a portion of the conductor layer overlapping the first main surface of the p-type silicon wafer in a plan view in the thickness direction of the p-type silicon wafer also serves as a first external connection electrode, and after the conductor layer is formed, a second external connection electrode different from the first external connection electrode and in contact with the silicide layer is formed.

13. The method for manufacturing a capacitor according to any one of claims 7 to 12, wherein the p-type silicon wafer has a resistivity of 1 Ωcm or more and 10 Ωcm or less.

14. A capacitor comprising: a p-type silicon substrate having a first main surface and a second main surface opposite to the first main surface and including porous silicon; a dielectric layer disposed on a surface of the porous silicon in the p-type silicon substrate; a conductor layer laminated on the dielectric layer; and a silicide layer in contact with a second region distinct from a first region in which porous silicon is formed on the first main surface of the p-type silicon substrate and surrounding the first region all around, and electrically connected to the p-type silicon substrate.

15. A capacitor comprising: a p-type silicon substrate having a first main surface and a second main surface opposite to the first main surface and including porous silicon; a dielectric layer disposed on a surface of the porous silicon in the p-type silicon substrate; a conductor layer laminated on the dielectric layer; an insulating layer disposed on the first main surface of the p-type silicon substrate, the insulating layer having a first opening exposing a first region in the first main surface of the p-type silicon substrate where the porous silicon is formed, and a second opening surrounding the first opening so as to expose a part of a second region different from the first region and surrounding the entire periphery of the first region; and a metal layer disposed across the main surface of the insulating layer and a portion exposed by the second opening in the second region on the first main surface of the p-type silicon substrate, the metal layer being in contact with the first main surface of the p-type silicon substrate and electrically connected to the p-type silicon substrate.

16. The capacitor according to claim 15, wherein the metal layer surrounds the entire periphery of the first opening in a plan view in the thickness direction of the p-type silicon substrate.

17. The capacitor according to claim 15 or 16, wherein the metal layer includes: a silicide layer disposed on the first main surface of the p-type silicon substrate; and a noble metal layer stacked on the silicide layer.

18. The capacitor according to any one of claims 15 to 17, wherein in the insulating layer, the shortest distance between the first opening and the second opening in a direction perpendicular to the thickness direction of the p-type silicon substrate is 1 μm or more and 50 μm or less.

19. The capacitor according to any one of claims 15 to 17, wherein in the insulating layer, the shortest distance between the first opening and the second opening in a direction perpendicular to the thickness direction of the p-type silicon substrate is not less than 5 μm and not more than 10 μm.

20. The capacitor according to any one of claims 15 to 17, wherein the resistivity of the p-type silicon substrate is 1 Ωcm or more and 10 Ωcm or less.

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