Display device and method for manufacturing same

Abstract

This display device comprises: light-emitting elements disposed on a pixel circuit layer; light extraction structures spaced apart from each other on the pixel circuit layer so as to overlap the light-emitting elements; a first bank layer disposed between the light extraction structures; and a reflective layer disposed between the light extraction structures and the first bank layer so as to surround at least side surfaces of respective light extraction structures. Each of the light-emitting elements is covered by a corresponding light extraction structure among the light extraction structures. Side surfaces of respective light extraction structures comprise substantially reverse-tapered sloping surfaces.

Description

Display device and manufacturing method thereof

[0001] The present disclosure relates to a display device and a method for manufacturing the same.

[0002] A display device includes pixels, each of which can emit light. The display device can display an image by combining the light emitted from the pixels.

[0003] Much research is being conducted to improve the light output efficiency of pixels included in display devices.

[0004] It should be understood that this Background section is, in part, intended to provide useful background for understanding the technology. However, the material described in this Background section may also include ideas, concepts, or perceptions that were not part of what was known or recognized by those skilled in the art prior to the effective filing date of this disclosure.

[0005] One object of the present disclosure is to provide a display device with improved light emission efficiency.

[0006] Another object of the present disclosure is to provide a method for manufacturing the display device.

[0007] A display device according to embodiments of the present disclosure includes a plurality of light-emitting elements arranged on a pixel circuit layer, a plurality of light-extracting structures overlapping the plurality of light-emitting elements and spaced apart from each other on the pixel circuit layer, a first bank layer arranged between the plurality of light-extracting structures, and a reflective layer arranged between the plurality of light-extracting structures and the first bank layer, the reflective layer surrounding at least a side surface of each of the plurality of light-extracting structures, wherein each of the plurality of light-emitting elements is covered by a corresponding light-extracting structure among the plurality of light-extracting structures, and a side surface of each of the plurality of light-extracting structures may include a substantially reverse-tapered slope.

[0008] In one embodiment, each of the plurality of light extraction structures may comprise a negative photoresist material.

[0009] In one embodiment, the reflective layer may not be disposed between the lower surface of each of the plurality of light extraction structures and the pixel circuit layer.

[0010] In one embodiment, each of the plurality of light extraction structures can surround at least a portion of a side surface adjacent to a top surface of a corresponding light emitting element among the plurality of light emitting elements.

[0011] In one embodiment, each of the plurality of light extraction structures may include a scattering particle.

[0012] In one embodiment, in cross-section, the upper edge of each of the plurality of light extraction structures may have a substantially rounded shape.

[0013] In one embodiment, the side surface between the lower surface and the upper edge of each of the plurality of light extraction structures may be a substantially reverse tapered slope.

[0014] In one embodiment, the reflective layer may extend from the side surface of each of the plurality of light extraction structures to further cover the upper edge of each of the plurality of light extraction structures and a portion of the upper surface adjacent to the upper edge.

[0015] In one embodiment, the reflective layer may cover the lowermost surface of the first bank layer.

[0016] In one embodiment, on the upper surface of each of the plurality of light extraction structures, a side surface of the reflective layer and a side surface of the first bank layer may be aligned with each other.

[0017] In one embodiment, the reflective layer may cover a portion of the upper edge adjacent to the side surface of each of the plurality of light extracting structures, and may not cover an upper surface of each of the plurality of light extracting structures.

[0018] In one embodiment, the lowermost surface of the first bank layer may not be covered by the reflective layer.

[0019] In one embodiment, the display device may further include a plurality of light conversion patterns spaced apart from each other on the plurality of light extraction structures so as to overlap the plurality of light extraction structures.

[0020] In one embodiment, the display device may further include a second bank layer arranged to overlap the first bank layer so as to surround each of the plurality of light conversion patterns, and a light reflective layer arranged between the plurality of light conversion patterns and the second bank layer.

[0021] A method for manufacturing a display device according to embodiments of the present disclosure includes the steps of forming a plurality of light-emitting elements on a pixel circuit layer, forming a plurality of light-extracting structures overlapping the plurality of light-emitting elements and spaced apart from each other on the pixel circuit layer, forming a reflective layer entirely on the pixel circuit layer, the reflective layer covering the plurality of light-extracting structures, forming a first bank layer entirely on the reflective layer, the first bank layer covering the reflective layer, etching the first bank layer disposed in an area overlapping at least a portion of an upper surface of each of the plurality of light-extracting structures, and etching the reflective layer using the first bank layer as a mask, wherein each of the plurality of light-emitting elements is surrounded by a corresponding light-extracting structure among the plurality of light-extracting structures, and a side surface of each of the plurality of light-extracting structures may include a substantially reverse-tapered inclined surface.

[0022] In one embodiment, the step of forming the plurality of light extraction structures may include the steps of forming an overcoating layer entirely over the pixel circuit layer, the overcoating layer covering the plurality of light emitting elements, and exposing and developing the overcoating layer to form the plurality of light extraction structures.

[0023] In one embodiment, the overcoating layer may comprise a negative photoresist material.

[0024] A method for manufacturing a display device according to embodiments of the present disclosure includes the steps of forming a plurality of light-emitting elements on a pixel circuit layer, forming a plurality of light-extracting structures overlapping the plurality of light-emitting elements and spaced apart from each other on the pixel circuit layer, forming a reflective layer entirely over the pixel circuit layer, the reflective layer covering the plurality of light-extracting structures, etching the reflective layer disposed in an area overlapping at least a portion of an upper surface of each of the plurality of light-extracting structures, forming a first bank layer entirely over the pixel circuit layer, the first bank layer covering the plurality of light-extracting structures and the reflective layer, and etching the first bank layer disposed in an area overlapping at least a portion of the upper surface of each of the plurality of light-extracting structures, wherein each of the plurality of light-emitting elements is surrounded by a corresponding light-extracting structure among the plurality of light-extracting structures, and a side surface of each of the plurality of light-extracting structures may include a substantially reverse-tapered slope.

[0025] In one embodiment, the step of etching the reflective layer may include the step of anisotropically dry etching the reflective layer.

[0026] In one embodiment, in the step of etching the reflective layer, a portion of the reflective layer disposed between the plurality of light extraction structures may be etched.

[0027] A display device according to embodiments of the present disclosure may include a plurality of light-emitting elements, a plurality of light-extracting structures spaced apart from each other and overlapping a plurality of light-emitting elements, and a reflective layer surrounding at least a side surface of each of the plurality of light-extracting structures. Each of the plurality of light-emitting elements is covered by a corresponding light-extracting structure among the plurality of light-extracting structures, and a side surface of each of the plurality of light-extracting structures may include a substantially reverse-tapered slope. Accordingly, the light emission efficiency of light emitted from the plurality of light-emitting elements may be improved by the plurality of light-extracting structures and the reflective layer.

[0028] A method for manufacturing a display device according to embodiments of the present disclosure can provide an efficient method for manufacturing the above-described display device.

[0029] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present disclosure.

[0030] FIG. 2 is a block diagram for explaining one of the sub-pixels included in the display device of FIG. 1.

[0031] FIG. 3 is a schematic plan view for explaining a display panel constituting the display device of FIG. 1.

[0032] FIG. 4 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0033] FIG. 5 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0034] FIG. 6 is a schematic plan view illustrating one embodiment of one of the pixels included in the display panel of FIG. 3.

[0035] FIGS. 7 and 8 are schematic cross-sectional views illustrating a pixel according to one embodiment of FIG. 6.

[0036] FIGS. 9 and 10 are schematic cross-sectional views illustrating a variant embodiment of a pixel according to one embodiment of FIG. 6.

[0037] FIGS. 11 and 12 are schematic cross-sectional views illustrating a variation example of a pixel according to one embodiment of FIG. 6.

[0038] FIG. 13 is a schematic plan view illustrating a second embodiment of one of the pixels included in the display panel of FIG. 3.

[0039] Figure 14 is a schematic cross-sectional view taken along line X2-X2' of Figure 13.

[0040] Figure 15 is a schematic cross-sectional view taken along line Y2-Y2' of Figure 13.

[0041] FIG. 16 is a schematic plan view for explaining a third embodiment of one of the pixels included in the display panel of FIG. 3.

[0042] Figure 17 is a schematic cross-sectional view taken along line X3-X3' of Figure 16.

[0043] FIGS. 18 to 24 are drawings for explaining a method of manufacturing a display device according to one embodiment of the present disclosure.

[0044] FIGS. 25 to 28 are drawings for explaining a method of manufacturing a display device according to one embodiment.

[0045] Figure 29 is a block diagram illustrating a display system according to one embodiment.

[0046] Figures 30 to 33 are schematic perspective views illustrating application examples of the display system of Figure 29.

[0047] Hereinafter, embodiments according to the present disclosure will be described in detail with reference to the attached drawings. It should be noted that the following description will describe parts suitable for understanding the operation according to the present disclosure, and the description of other parts will be omitted so as not to obscure the gist of the present disclosure. The present disclosure is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical ideas of the present disclosure in such a detailed manner that those skilled in the art to which the present disclosure pertains can easily practice them.

[0048] Throughout this specification, when a part is said to be "connected" to another part, this includes not only "directly connected" but also "indirectly connected" with other elements intervening. The terminology used herein is for the purpose of describing specific embodiments and is not intended to limit the present disclosure.

[0049] The words “include,” “have,” and variations thereof refer to the presence of stated features, integers, steps, operations, elements, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and / or groups thereof.

[0050] “At least one of X, Y, and Z”, and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, “and / or” includes any combination of one or more of the configurations.

[0051] Here, singular expressions are intended to include plural expressions as well, unless the context clearly indicates otherwise.

[0052] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for purposes of meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B." The terms "and" and "or" can be used in a conjunction or disjunction sense and can be understood to be equivalent to "and / or."

[0053] In the specification and claims, the term "at least one" is intended to include, for purposes of meaning and interpretation, the meaning of "at least one selected from the group." For example, "at least one of A and B" can be understood to mean "A, B, or A and B."

[0054] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0055] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features are now positioned "above" the other elements or features. Thus, in one embodiment, the term "below" can encompass both above and below. The device can be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0056] The term "overlap" means that the first object can be on top of, below, or to the side of the second object, or vice versa. Furthermore, the term "overlap" may include terms such as layer, stack, surface, facing, extending upward, covering, or partially covering, or other appropriate terms recognized and understood by those skilled in the art.

[0057] The term "confrontation" implies that the first element may directly or indirectly oppose the second. If a third element intervenes between the first and second elements, the first and second elements may still be perceived as facing each other, but indirectly opposing each other.

[0058] When an element is described as 'non-overlapping' or 'non-overlapping' with another element, this may include the elements being spaced apart from each other, offset from each other, separated from each other, or other appropriate terms that would be recognizable and understandable to a person of ordinary skill in the art.

[0059] Various embodiments are described with reference to drawings illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the embodiments are not limited thereto.

[0060] As used herein, the terms "about" or "approximately" include the stated value and mean within an acceptable range of deviation from the stated value as determined by a person skilled in the art, taking into account the measurement in question and the errors associated with measuring the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0061] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the disclosed material relates. Terms defined in commonly used dictionaries, for example, should be interpreted as having a meaning consistent with their meaning in the relevant technical context, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0062] Embodiments may be illustrated and described in the attached drawings in terms of functional blocks, units, and / or modules.

[0063] A person skilled in the art will understand that such blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques.

[0064] When blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software.

[0065] It is also contemplated that each block, unit, and / or module may be implemented as dedicated hardware or a combination of dedicated hardware performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions.

[0066] Each block, unit, and / or module of the embodiments may be physically separated into two or more interacting and individual blocks, units, and / or modules without departing from the scope of the present invention.

[0067] Additionally, the blocks, units, and / or modules of the embodiments may be physically combined into more complex blocks, units, and / or modules without departing from the scope of the present disclosure.

[0068] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present disclosure.

[0069] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0070] The display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) may be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0071] Sub-pixels (SP) can generate light of two or more colors. For example, each sub-pixel (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0072] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. The pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included in the pixel (PXL).

[0073] The gate driver (120) is connected to the sub-pixels (SP) arranged (or placed) in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GSC) can include a start signal indicating the start of each frame, a horizontal synchronization signal, or the like, within the spirit and scope of the present disclosure.

[0074] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and these drivers may be arranged on one side of the display panel (DP) and the other side opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0075] The data driver (130) is connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, and the like within the spirit and scope of the present disclosure.

[0076] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn) using the received voltages. When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0077] In embodiments, the gate driver (120) and the data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0078] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) is configured to generate voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate voltages by receiving an input voltage from outside the display device (DD) and regulating the received voltage.

[0079] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In one embodiment, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0080] The voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). In FIG. 1, the pixel control lines (PXCL) are illustrated as being connected between the voltage generator (140) and the display panel (DP), but embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0081] The controller (150) controls all operations of the display device (DD). The controller (150) receives input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0082] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by arranging the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0083] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0084] Fig. 2 is a block diagram for explaining one of the sub-pixels included in the display device of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is illustrated as an example.

[0085] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0086] A light emitting element (LD) is connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) is connected to one of the power supply lines (PL) of FIG. 1 and receives a first power supply voltage. The second power supply voltage node (VSSN) is connected to another of the power supply lines (PL) of FIG. 1 and receives a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0087] A light emitting element (LD) is connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power voltage node (VSSN). The light emitting element (LD) is configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0088] The sub-pixel circuit (SPC) may be connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) controls the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0089] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0090] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, and the like within the spirit and scope of the present disclosure.

[0091] FIG. 3 is a schematic plan view for explaining a display panel constituting the display device of FIG. 1.

[0092] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) displays an image through the display area (DA). The non-display area (NDA) is arranged around the display area (DA).

[0093] A display panel (DP) may include sub-pixels (SP) arranged in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0094] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1, SP2, SP3), but the embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) can include first to third sub-pixels (SP1, SP2, SP3).

[0095] Each of the first to third sub-pixels (SP1, SP2, SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. In the following, for clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) is configured to generate blue color light.

[0096] Each of the first to third sub-pixels (SP1, SP2, SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1, SP2, SP3) may generate red light, green light, and blue light, respectively.

[0097] As a display panel (DP), a self-luminous display panel can be used, such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements.

[0098] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0099] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0100] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have a closed-loop shape including straight and / or curved edges. For example, the display area (DA) may have shapes within the scope and spirit of the present disclosure, such as a polygon, a circle, a semicircle, or an ellipse.

[0101] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In these cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0102] FIG. 4 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0103] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially stacked on the substrate (SUB) in a third direction (DR3) intersecting the first and second directions (DR1, DR2).

[0104] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0105] In the embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0106] A pixel circuit layer (PCL) is disposed on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, or other elements within the spirit and scope of the present disclosure.

[0107] The circuit elements of the pixel circuit layer (PCL) may include sub-pixel circuits (SPCs of FIG. 2) of each of the sub-pixels (SP) of FIG. 3. In other words, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0108] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines for driving the display element layer (DPL).

[0109] A display element layer (DPL) is arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0110] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0111] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or color). In some embodiments, the color filter layer may be omitted.

[0112] A window may be provided on the light-functional layer (LFL) to protect the exposed surface (or upper surface) of the display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded or connected to the light-functional layer (LFL) through an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0113] FIG. 5 is a schematic cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0114] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) may be configured to be substantially the same as (or similar to) the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4. Therefore, description of overlapping content may be omitted.

[0115] The input sensing layer (ISL) can detect a user's input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting an external object, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0116] FIG. 6 is a schematic plan view illustrating one embodiment of one of the pixels included in the display panel of FIG. 3.

[0117] Referring to FIG. 6, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in a first direction (DR1). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0118] First to third anode electrodes (AE1, AE2, AE3) may be respectively disposed in the first to third sub-pixels (SP1, SP2, SP3). The first anode electrode (AE1) may be provided as an anode electrode (AE in FIG. 2) connected to the sub-pixel circuit (SPC in FIG. 2) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) connected to the sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0119] The cathode electrode (CE) can be spaced apart from the first to third anode electrodes (AE1, AE2, AE3). The cathode electrode (CE) can be arranged at the same height as the first to third anode electrodes (AE1, AE2, AE3). The cathode electrode (CE) can be spaced apart from the first to third anode electrodes (AE1, AE2, AE3) in the second direction (DR2).

[0120] In the embodiments, the cathode electrode (CE) may extend in the first direction (DR1) and may be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). Although not shown, the cathode electrode (CE) may extend in the second direction (DR2) as well as the first direction (DR1) and may be used as a common electrode for all of the sub-pixels (SP) of FIG. 3. In this way, the cathode electrode (CE) may have various shapes.

[0121] First to third light-emitting elements (LD1, LD2, LD3) may be disposed on first to third anode electrodes (AE1, AE2, AE3) and a cathode electrode (CE). The first light-emitting element (LD1) may be electrically connected to the first anode electrode (AE1) and the cathode electrode (CE). The first light-emitting element (LD1) may be provided as a light-emitting element (LD of FIG. 2) connected to a sub-pixel circuit (SPC) of a first sub-pixel (SP1). The second light-emitting element (LD2) may be electrically connected to the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2) may be provided as a light-emitting element (LD) connected to a sub-pixel circuit (SPC) of a second sub-pixel (SP2). The third light-emitting element (LD3) may be electrically connected to the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3) may be provided as a light-emitting element (LD) connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0122] The first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) may be inorganic light-emitting diodes containing inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0123] Figures 7 and 8 are schematic cross-sectional views for explaining a pixel according to one embodiment of Figure 6. Figure 7 is a schematic cross-sectional view taken along line X1-X1' of Figure 6, and Figure 8 is a schematic cross-sectional view taken along line Y1-Y1' of Figure 6.

[0124] Referring to FIGS. 6 and 7, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0125] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (IDL), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0126] As described with reference to FIG. 2, each of the first to third sub-pixels (SP1, SP2, SP3) may include a sub-pixel circuit (SPC of FIG. 2) of transistors and one or more capacitors. The semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). The conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1.

[0127] A buffer layer (BFL) may be disposed on one side or on the side of a substrate (SUB). The buffer layer (BFL) may serve to prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0128] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may include polyimide.

[0129] A transistor (T_SP1) may be placed on the buffer layer (BFL). The transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). For example, the transistor (T_SP1) may be a transistor connected to the first anode electrode (AE1) among the transistors of the sub-pixel circuit (SPC).

[0130] The transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0131] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. As the impurities, for example, a p-type impurity may be used, but embodiments are not limited thereto.

[0132] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0133] Interlayer insulating layers (ILDs) sequentially stacked on a semiconductor pattern (SCP) may be arranged. The interlayer insulating layers (ILDs) may be inorganic insulating layers including inorganic materials. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide. However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0134] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor pattern (SCP). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL) to cover the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for forming the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0135] A gate electrode (GE) is disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag).

[0136] The first and second terminals (ET1, ET2) are disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) can contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) can include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0137] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), the embodiments are not limited thereto. In the embodiments, the first terminal (ET1) may be a first contact region adjacent to one side or a side of a channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the light emitting element (LD) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0138] In embodiments, the transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, the embodiments are not limited thereto. For example, the transistor (T_SP1) may also be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit of the first sub-pixel (SP1) may include transistors of different types. For example, the transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and the other transistors of the first sub-pixel (SP1) may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the transistor (T_SP1) is formed.

[0139] In the embodiments, the transistor (T_SP1) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the transistor (T_SP1) may be a transistor having a bottom gate structure. The structure of the transistor (T_SP1) may be changed in various ways.

[0140] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0141] A first passivation layer (PSV1) may be disposed over the interlayer insulating layers (ILD) and the first and second terminals (ET1, ET2). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed beneath the first passivation layer (PSV1) and may provide a flat upper surface.

[0142] A connection electrode (CP) may be disposed on the first passivation layer (PSV1). The connection electrode (CP) may penetrate the first passivation layer (PSV1) and be connected to the first terminal (ET1) of the transistor (T_SP1). The connection electrode (CP) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0143] At least some of the various wires of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0144] A second passivation layer (PSV2) is disposed on the connecting electrode (CP) and the first passivation layer (PSV1). The second passivation layer (PSV2) protects components disposed beneath the second passivation layer (PSV2) and can provide a flat upper surface.

[0145] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0146] A display element layer (DPL) may be disposed on a second passivation layer (PSV2). The display element layer (DPL) may include a first anode electrode (AE1), a cathode electrode (CE), an adhesive layer (ADL), first and second bridge electrodes (BRE1, BRE2), a first light-emitting element (LD1), a third passivation layer (PSV3), a first light-extracting structure (OC1), a capping layer (CPL), a reflective layer (RFL), and a first bank layer (BNK).

[0147] An electrode layer including a first anode electrode (AE1) and a cathode electrode (CE) may be disposed on the pixel circuit layer (PCL).

[0148] The first anode electrode (AE1) can be electrically connected to the connection electrode (CP) through a contact hole penetrating the second passivation layer (PSV2). In this way, the first anode electrode (AE1) can be electrically connected to the transistor (T_SP1).

[0149] The cathode electrode (CE) can be spaced apart from the first anode electrode (AE1) in the second direction (DR2). The cathode electrode (CE) can be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) can be transmitted to the cathode electrode (CE).

[0150] An adhesive layer (ADL) may be disposed on a first anode electrode (AE1), a cathode electrode (CE), and a second passivation layer (PSV2) between the first anode electrode (AE1) and the cathode electrode (CE). The adhesive layer (ADL) may include an insulating material having adhesive properties. The adhesive layer (ADL) may serve to fix a first light-emitting element (LD1) attached to the adhesive layer (ADL).

[0151] The first light-emitting element (LD1) may include a light-emitting stack including a first semiconductor layer (11), a second semiconductor layer (12) disposed on the first semiconductor layer (11), and an active layer (13) disposed between the first semiconductor layer (11) and the second semiconductor layer (12). In embodiments, the light-emitting stack may further include an auxiliary layer (14) disposed on the second semiconductor layer (12).

[0152] The first semiconductor layer (11) provides holes to the active layer (13). The first semiconductor layer (11) may include at least one p-type semiconductor layer. For example, the first semiconductor layer (11) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a p-type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material constituting the first semiconductor layer (11) is not limited thereto, and various other materials may constitute the first semiconductor layer (11). In one embodiment, the first semiconductor layer (11) may include a gallium nitride (GaN) semiconductor material doped with a p-type dopant.

[0153] The second semiconductor layer (12) provides electrons to the active layer (13). The second semiconductor layer (12) may include at least one n-type semiconductor material. For example, the second semiconductor layer (12) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with an n-type dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the second semiconductor layer (12) is not limited thereto, and various other materials may constitute the second semiconductor layer (12). In one embodiment, the second semiconductor layer (12) may include a gallium nitride (GaN) semiconductor material doped with an n-type dopant. According to an embodiment, the second semiconductor layer (12) may form an n-type semiconductor layer together with the auxiliary layer (14).

[0154] The active layer (13) may be arranged between the first semiconductor layer (11) and the second semiconductor layer (12), and may be a region where electrons and holes recombine. As electrons and holes recombine in the active layer (13), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The active layer (13) may be formed in a single or multiple quantum well structure. When the active layer (13) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer may be repeatedly stacked on each other to form the active layer (13). However, embodiments of the active layer (13) are not limited thereto.

[0155] The auxiliary layer (14) may include a gallium nitride (GaN) semiconductor material that is substantially not doped with impurities or is doped with impurities at a relatively low concentration, and may form an n-type semiconductor layer together with the second semiconductor layer (12).

[0156] The first light-emitting element (LD1) may include a first bonding electrode (BDE1) and a second bonding electrode (BDE2). The first bonding electrode (BDE1) may be connected to a lower surface of the first semiconductor layer (11). The first bonding electrode (BDE1) may not be in physical contact with the second semiconductor layer (12) and the active layer (13). The second bonding electrode (BDE2) may be connected to a second semiconductor layer (12) that does not overlap with the first semiconductor layer (11) and the active layer (13). For example, the second bonding electrode (BDE2) may be connected to the second semiconductor layer (12) exposed when the first semiconductor layer (11) and the active layer (13) are removed by etching. The second bonding electrode (BDE2) may not be in physical contact with the first semiconductor layer (11), the active layer (13), and the first bonding electrode (BDE1). The first light-emitting element (LD1) may be a flip chip type light-emitting element. In embodiments, the first bonding electrode (BDE1) and the second bonding electrode (BDE2) may include a eutectic metal.

[0157] In one embodiment, the first bonding electrode (BDE1) and the second bonding electrode (BDE2) may include a material suitable for reflecting incident light. For example, the first bonding electrode (BDE1) and the second bonding electrode (BDE2) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto. Since the first bonding electrode (BDE1) and the second bonding electrode (BDE2) include a material suitable for reflecting light, the light emission efficiency of light generated from the active layer (13) can be further improved.

[0158] The first light-emitting element (LD1) may include an insulating film (15) covering at least a portion of the outer peripheral surface of the light-emitting stack. For example, the insulating film (15) may cover the entire outer peripheral surface except for the upper surface of the light-emitting stack. The insulating film (15) may serve to prevent an electrical short circuit that may occur when the active layer (13) comes into contact with a conductive material other than the first semiconductor layer (11) and the second semiconductor layer (12). The insulating film (15) may serve to prevent an electrical short circuit that may occur when the second bonding electrode (BDE2) comes into contact with the first semiconductor layer (11) and the active layer (13). The insulating film (15) may include a transparent insulating material. As illustrated in FIG. 7, a portion of the first bonding electrode (BDE1) and a portion of the second bonding electrode (BDE2) may be exposed without being covered by the insulating film (15).

[0159] The first bonding electrode (BDE1) may extend along an insulating film (15) covering a side surface of the light-emitting stack. An extended portion of the first bonding electrode (BDE1) and an exposed portion of the first anode electrode (AE1) on which an adhesive layer (ADL) is not disposed may be electrically connected to each other via a first bridge electrode (BRE1). The second bonding electrode (BDE1) may extend along an insulating film (15) covering a side surface of the light-emitting stack. An extended portion of the second bonding electrode (BDE2) and an exposed portion of the cathode electrode (CE) on which an adhesive layer (ADL) is not disposed may be electrically connected to each other via a second bridge electrode (BRE2). The first bridge electrode (BRE1) and the second bridge electrode (BRE2) may include the same material as any one of the first anode electrode (AE1), the cathode electrode (CE), the first bonding electrode (BDE1), and the second bonding electrode (BDE2), but the embodiments are not limited thereto.

[0160] A third passivation layer (PSV3) is disposed on the pixel circuit layer (PCL) to entirely cover components such as the first bridge electrode (BRE1), the second bridge electrode (BRE2), and the first light-emitting element (LD1). The third passivation layer (PSV3) can protect components disposed below the third passivation layer (PSV3). The third passivation layer (PSV3) may include the same material as any one of the first passivation layer (PSV1), the second passivation layer (PSV2), and the interlayer insulating layers (ILD), but embodiments are not limited thereto. In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface of the first light-emitting element (LD1). The third passivation layer (PSV3) may be omitted.

[0161] The first light extraction structure (OC1) is arranged to overlap the first light emitting element (LD1). The first light extraction structure (OC1) can cover the first light emitting element (LD1). In embodiments, the first light extraction structure (OC1) can surround at least a portion of a side surface adjacent to the upper surface of the first light emitting element (LD1). The first light extraction structure (OC1) can include a material having relatively high light transmittance so as to transmit light generated from the first light emitting element (LD1).

[0162] The capping layer (CPL) can entirely cover the first light extraction structure (OC1) and the third passivation layer (PSV3). The capping layer (CPL) can protect components under the capping layer (CPL), such as the first light-emitting element (LD1), from external moisture and humidity, and other things within the spirit and scope of the present disclosure. The capping layer (CPL) can include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto. The capping layer (CPL) may be omitted.

[0163] The first bank layer (BNK) may be disposed between the first light extraction structure (OC1) and the second and third light extraction structures (OC2, OC3 in FIG. 8) described below. Accordingly, the first bank layer (BNK) may surround the first light extraction structure (OC1) and the second and third light extraction structures (OC2, OC3) described below. The first bank layer (BNK) may be configured to include a light-blocking material, thereby preventing light mixing between adjacent sub-pixels. In embodiments, the first bank layer (BNK) may include an organic material. For example, the first bank layer (BNK) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0164] A reflective layer (RFL) is disposed between the first bank layer (BNK) and the first light extraction structure (OC1). The reflective layer (RFL) may surround at least a side surface of the first light extraction structure (OC1). The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0165] The first light extraction structure (OC1) and the reflective layer (RFL) may serve to improve the light emission efficiency of the light generated from the first light emitting element (LD1). More specifically, the side surface of the first light extraction structure (OC1) may include a reversely tapered slope. For example, as illustrated in FIG. 7, the first light extraction structure (OC1) may have a shape that is substantially the same as (or similar to) a trapezoidal shape in which the length of the upper side in the cross section is longer than the length of the lower side. Here, the reflective layer (RFL) surrounding the side surface of the first light extraction structure (OC1) may also have a reversely tapered shape corresponding to the shape of the side surface of the first light extraction structure (OC1). Accordingly, the light generated from the first light emitting element (LD1) may be reflected so as to propagate in the front direction (e.g., the third direction (DR3) and a direction crossing therewith), thereby improving the light emission efficiency.

[0166] In one embodiment, the first light extraction structure (OC1) may include a negative photoresist material. Accordingly, the first light extraction structure (OC1) may be formed to have a side surface including a reverse tapered slope. This will be described in detail later with reference to FIGS. 18 and 19 .

[0167] In one embodiment, the first light extraction structure (OC1) may include a scattering particle (SCT). The scattering particle (SCT) may scatter light generated from the first light-emitting element (LD1). Accordingly, light emission efficiency may be further improved.

[0168] In one embodiment, the upper edge of the first light extraction structure (OC1) may have a rounded shape. In this case, the side surface between the lower surface and the upper edge of the first light extraction structure (OC1) may be a reverse tapered slope.

[0169] In one embodiment, the reflective layer (RFL) may extend from a side surface of the first light extracting structure (OC1) to further cover an upper edge of the first light extracting structure (OC1) and a portion of an upper surface adjacent to the upper edge. In this case, the side surface of the reflective layer (RFL) and the side surface of the first bank layer (BNK) may be aligned with each other on the upper surface of the first light extracting structure (OC1). In this way, since the upper edge of the first light extracting structure (OC1) and a portion of an upper surface adjacent to the upper edge are covered by the reflective layer (RFL) and the first bank layer (BNK), light mixing between adjacent sub-pixels can be more effectively prevented.

[0170] In the above-described embodiment, another part of the upper surface of the first light extraction structure (OC1) may not be covered by the reflective layer (RFL) and the first bank layer (BNK). Accordingly, light generated from the first light-emitting element (LD1) may be normally emitted through another part of the upper surface of the first light extraction structure (OC1) that is not covered by the reflective layer (RFL) and the first bank layer (BNK).

[0171] In one embodiment, the reflective layer (RFL) may cover the lowermost surface of the first bank layer (BNK). This may be a structure achieved by the manufacturing method of the present disclosure, which forms the reflective layer (RFL) by an etching process using the first bank layer (BNK) as a mask. This will be described in detail later with reference to FIGS. 21 to 24.

[0172] In one embodiment, the reflective layer (RFL) may not be disposed between the lower surface of the first light extraction structure (OC1) and the pixel circuit layer (PCL). For example, the reflective layer (RFL) may not be disposed between the first light extraction structure (OC1) and a component disposed directly below the first light extraction structure (OC1) (e.g., the third passivation layer (PSV3), or, if the third passivation layer (PSV3) is omitted, the first light emitting element (LD1), the first bridge electrode (BRE1), and the second bridge electrode (BRE2)). This may be a structure exhibited by the manufacturing method of the present disclosure in which the reflective layer (RFL) is formed after the first light extraction structure (OC1) is formed. This will be described in detail later with reference to FIGS. 19 to 21.

[0173] Above, the pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1) have been described. Each of the second and third sub-pixels (SP2, SP3) of FIG. 6 may also be configured similarly to the first sub-pixel (SP1), to the extent not otherwise described herein.

[0174] A light-functional layer (LFL) is provided on the first bank layer (BNK) and the capping layer (CPL). The light-functional layer (LFL) may include a filling layer (LRL) and a color filter layer (CFL).

[0175] A fill layer (LRL) is disposed on the first bank layer (BNK) and the capping layer (CPL). The fill layer (LRL) may include a material with relatively high light transmittance. The fill layer (LRL) may provide a flat upper surface. The fill layer (LRL) may be omitted.

[0176] A color filter layer (CFL) is disposed on the filling layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) overlaps the first light extraction structure (OC1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0177] Referring to FIGS. 6 and 8, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0178] The pixel circuit layer (PCL) is described in the same manner as described with reference to Fig. 7. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1, SP2, SP3) are provided, respectively.

[0179] The display element layer (DPL) is described in the same manner as described with reference to FIG. 7. In the display element layer (DPL), first to third light-emitting elements (LD1, LD2, LD3) corresponding to first to third sub-pixels (SP1, SP2, SP3) are provided, respectively. The first light-emitting element (LD1) is connected between a cathode electrode (CE of FIG. 7) and a transistor (T_SP1 of FIG. 7) included in a sub-pixel circuit of the first sub-pixel (SP1). The second light-emitting element (LD2) is connected between the cathode electrode (CE) and a transistor included in a sub-pixel circuit of the second sub-pixel (SP2). The third light-emitting element (LD3) is connected between the cathode electrode (CE) and a transistor included in a sub-pixel circuit of the third sub-pixel (SP3).

[0180] In the embodiments, when the first sub-pixel (SP1) is a red sub-pixel, the first light-emitting element (LD1) may be configured to emit red color light. When the second sub-pixel (SP2) is a green sub-pixel, the second light-emitting element (LD2) may be configured to emit green color light. When the third sub-pixel (SP3) is a blue sub-pixel, the third light-emitting element (LD3) may be configured to emit blue color light. In this way, each of the first to third light-emitting elements (LD1, LD2, LD3) may be configured to emit light of a color corresponding to the type of the corresponding sub-pixel.

[0181] First to third light extraction structures (OC1, OC2, OC3) are provided, respectively corresponding to first to third light emitting elements (LD1, LD2, LD3). The first to third light extraction structures (OC1, OC2, OC3) may be spaced apart from each other. The first light extraction structure (OC1) may cover the first light emitting element (LD1). The second light extraction structure (OC2) may cover the second light emitting element (LD2). The third light extraction structure (OC3) may cover the third light emitting element (LD3). Each side surface of the first to third light extraction structures (OC1, OC2, OC3) may include a reverse tapered slope.

[0182] A first bank layer (BNK) is provided between the first to third light extraction structures (OC1, OC2, OC3). Accordingly, the first bank layer (BNK) can surround the first to third light extraction structures (OC1, OC2, OC3).

[0183] A reflective layer (RFL) is disposed between the first to third light extraction structures (OC1, OC2, OC3) and the first bank layer (BNK). The reflective layer (RFL) may surround at least a side surface of each of the first to third light extraction structures (OC1, OC2, OC3).

[0184] In one embodiment, the reflective layer (RFL) can cover the lowermost surface of the first bank layer (BNK). That is, the reflective layer (RFL) can extend from the side surfaces of the first to third light extraction structures (OC1, OC2, OC3) and be disposed between the lowermost surface of the first bank layer (BNK) and the capping layer (CPL) (or between the lowermost surface of the first bank layer (BNK) and the third passivation layer (PSV3) when the capping layer (CPL) is omitted).

[0185] A light-functional layer (LFL) is provided on the display element layer (DPL). The light-functional layer (LFL) is described in the same manner as described with reference to FIG. 7.

[0186] A filling layer (LRL) is disposed on the first bank layer (BNK) and the capping layer (CPL). In some embodiments, the filling layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3).

[0187] A color filter layer (CFL) is disposed on the filling layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0188] Each of the first to third color filters (CF1, CF2, CF3) can selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) can include a red color filter. When the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) can include a green color filter. When the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) can include a blue color filter.

[0189] Light blocking patterns (LBP) are arranged between the first to third color filters (CF1, CF2, CF3). It can be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0190] The light blocking patterns (LBP) can be overlapped with the first bank layer (BNK). The first to third color filters (CF1, CF2, CF3) can be overlapped with the first to third light extraction structures (OC1, OC2, OC3). For example, the first color filter (CF1) can be overlapped with the first light extraction structure (OC1), the second color filter (CF2) can be overlapped with the second light extraction structure (OC2), and the third color filter (CF3) can be overlapped with the third light extraction structure (OC3).

[0191] In embodiments, the light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light-blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light-blocking pattern between the first and second color filters (CF1, CF2) among the light-blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light-blocking pattern between the second and third color filters (CF2, CF3) among the light-blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) can extend into the non-emitting area (NEMA) to form light blocking patterns (LBP).

[0192] FIGS. 9 and 10 are schematic cross-sectional views illustrating a modified embodiment of a pixel according to one embodiment of FIG. 6. FIG. 9 is a schematic cross-sectional view taken along line X1-X1' of FIG. 6, and FIG. 10 is a schematic cross-sectional view taken along line Y1-Y1' of FIG. 6.

[0193] As described above with reference to FIGS. 7 and 8, a reflective layer (RFL of FIGS. 7 and 8) may be provided. Here, the pixels illustrated in FIGS. 9 and 10 may be substantially identical to the pixels described with reference to FIGS. 7 and 8, except for the shape of the reflective layer (RFL'). Therefore, description of overlapping content may be omitted.

[0194] Referring to FIGS. 6, 9, and 10, the reflective layer (RFL') may cover a portion of an upper edge adjacent to a side surface of each of the first to third light extracting structures (OC1, OC2, OC3). In this case, another portion of the upper edge of each of the first to third light extracting structures (OC1, OC2, OC3) and the upper surface of each of the first to third light extracting structures (OC1, OC2, OC3) may not be covered by the reflective layer (RFL').

[0195] In this case, the lowermost surface of the first bank layer (BNK) may not be covered by the reflective layer (RFL'). This may be a structure exhibited by the manufacturing method of the present disclosure, which forms the reflective layer (RFL') prior to the formation of the first bank layer (BNK). This will be described in detail later with reference to FIGS. 25 to 28.

[0196] Figures 11 and 12 are schematic cross-sectional views for explaining a modified embodiment of a pixel according to one embodiment of Figure 6. Figure 11 is a schematic cross-sectional view taken along line X1-X1' of Figure 6, and Figure 12 is a schematic cross-sectional view taken along line Y1-Y1' of Figure 6.

[0197] Referring to FIG. 6 and FIG. 11, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0198] The pixel circuit layer (PCL) is described in the same manner as described with reference to Fig. 7. Therefore, description of overlapping content may be omitted.

[0199] The display element layer (DPL) is described in the same manner as described with reference to Fig. 7. Therefore, description of overlapping content may be omitted.

[0200] A light functional layer (LFL) is provided on a first bank layer (BNK) and a capping layer (CPL). The light functional layer (LFL) may include a second bank layer (BNK'), a light reflecting layer (RFL"), a first light conversion pattern (CCP1), a filling layer (LRL), and a color filter layer (CFL).

[0201] The second bank layer (BNK') is disposed on the first bank layer (BNK) so as to overlap the first bank layer (BNK). The second bank layer (BNK') may have an opening (OP) that overlaps the first light extraction structure (OC1). The second bank layer (BNK') is configured to include a light-blocking material, thereby preventing light mixing between adjacent sub-pixels. In embodiments, the second bank layer (BNK') may include an organic material. For example, the second bank layer (BNK') may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0202] A light reflective layer (RFL") is disposed on side surfaces of the second bank layer (BNK') adjacent to the opening (OP). The light reflective layer (RFL") is configured to reflect incident light, and thus, light emission efficiency can be improved. The light reflective layer (RFL") can include a material suitable for reflecting light. The light reflective layer (RFL") can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0203] A first light conversion pattern (CCP1) is disposed on the first light extraction structure (OC1) so as to overlap the first light extraction structure (OC1). The first light conversion pattern (CCP1) is disposed within the opening (OP). The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of the incident light to convert the incident light into light of a different color. The color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots.

[0204] When the first sub-pixel (SP1) is a red sub-pixel, the first light-emitting element (LD1) can emit light of a color different from the red color. For example, the first light-emitting element (LD1) can emit blue light. In this case, the first light conversion pattern (CCP1) can include first color conversion particles (QD1) configured to convert blue light into red light.

[0205] A filling layer (LRL) is disposed on the second bank layer (BNK') and the first light conversion pattern (CCP1). The filling layer (LRL) may include a material having relatively high light transmittance. The filling layer (LRL) may provide a flat upper surface. In embodiments, the filling layer (LRL) may have a lower refractive index than the first light conversion pattern (CCP1). The filling layer (LRL) is configured to refract or totally reflect light depending on an incident angle. For example, the filling layer (LRL) may provide light passing through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved. The filling layer (LRL) may be omitted.

[0206] A color filter layer (CFL) is disposed on the filling layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) overlaps the first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0207] Referring to FIG. 6 and FIG. 12, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0208] The pixel circuit layer (PCL) is described in the same manner as described with reference to Fig. 7. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1, SP2, SP3) are provided, respectively.

[0209] The display element layer (DPL) is described in the same manner as described with reference to FIG. 7, except for the color of light emitted from each of the first to third light-emitting elements (LD1, LD2, LD3). The first to third light-emitting elements (LD1, LD2, LD3) illustrated in FIG. 12 can emit light of the same color. For example, the first to third light-emitting elements (LD1, LD2, LD3) can generate blue-colored light.

[0210] A light-functional layer (LFL) is provided on the display element layer (DPL). The light-functional layer (LFL) is described in the same manner as described with reference to FIG. 11.

[0211] A second bank layer (BNK') is disposed on the first bank layer (BNK) so as to overlap with the first bank layer (BNK). The second bank layer (BNK') may have openings (OP) overlapping the first to third light extraction structures (OC1, OC2, OC3). The first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) are disposed within the openings (OP) so as to overlap with the first to third light extraction structures (OC1, OC2, OC3). The first light conversion pattern (CCP1) is disposed on the first light extraction structure (OC1). The second light conversion pattern (CCP2) is disposed on the second light extraction structure (OC2). The light scattering pattern (LSP) is disposed on the third light extraction structure (OC3). The first and second optical conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) can be arranged spaced apart from each other.

[0212] A light reflecting layer (RFL") is disposed on the side surfaces of the second bank layer (BNK') adjacent to the openings (OP). Here, the light reflecting layer (RFL") can be viewed as being disposed between the first and second light conversion patterns (CCP1, CCP2) and the second bank layer (BNK') surrounding them, and between the light scattering pattern (LSP) and the second bank layer (BNK') surrounding them.

[0213] In embodiments, the first sub-pixel (SP1) may be a red sub-pixel, the second sub-pixel (SP2) may be a green sub-pixel, and the third sub-pixel (SP3) may be a blue sub-pixel. The first to third light-emitting elements (LD1, LD2, LD3) may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light emission efficiency. Accordingly, the first to third sub-pixels (SP1, SP2, SP3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0214] A filling layer (LRL) may be disposed on the second bank layer (BNK'), the first and second light conversion patterns (CCP1, CCP2), and the light scattering pattern (LSP). In some embodiments, the filling layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3).

[0215] A color filter layer (CFL) may be disposed on the filling layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0216] Each of the first to third color filters (CF1, CF2, CF3) can selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) can include a red color filter. When the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) can include a green color filter. When the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) can include a blue color filter.

[0217] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1, SP2, SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0218] The light blocking patterns (LBP) can be overlapped with the second bank layer (BNK'). The first to third color filters (CF1, CF2, CF3) can be overlapped with the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). For example, the first color filter (CF1) can be overlapped with the first light conversion pattern (CCP1), the second color filter (CF2) can be overlapped with the second light conversion pattern (CCP2), and the third color filter (CF3) can be overlapped with the light scattering pattern (LSP).

[0219] In embodiments, the light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light-blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). As another example, the light-blocking pattern between the first and second color filters (CF1, CF2) among the light-blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light-blocking pattern between the second and third color filters (CF2, CF3) among the light-blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1, CF2, CF3) can extend into the non-emitting area (NEMA) to form light blocking patterns (LBP).

[0220] In FIGS. 11 and 12, the pixels are depicted as including the reflective layer (RFL) described with reference to FIGS. 7 and 8, but the pixels of FIGS. 11 and 12 may also include the reflective layer (RFL') described with reference to FIGS. 9 and 10.

[0221] FIG. 13 is a schematic plan view illustrating a second embodiment of one of the pixels included in the display panel of FIG. 3.

[0222] Referring to FIG. 13, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) are described in the same manner as described with reference to FIG. 6. Therefore, description of overlapping content may be omitted.

[0223] The first to third anode electrodes (AE1, AE2, AE3) and the cathode electrode (CE) are described in the same manner as described with reference to FIG. 6. The first to third anode electrodes (AE1, AE2, AE3) may be arranged in the first to third sub-pixels (SP1, SP2, SP3), respectively. The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1, AE2, AE3). Hereinafter, descriptions of overlapping content may be omitted.

[0224] First to third light-emitting elements (LD1', LD2', LD3') may be disposed on first to third anode electrodes (AE1, AE2, AE3) and a cathode electrode (CE). The first light-emitting element (LD1') may be electrically connected to the first anode electrode (AE1) and the cathode electrode (CE). The first light-emitting element (LD1') may be provided as a light-emitting element (LD of FIG. 2) connected to a sub-pixel circuit (SPC of FIG. 2) of the first sub-pixel (SP1). The second light-emitting element (LD2') may be electrically connected to the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2') may be provided as a light-emitting element (LD of FIG. 2) connected to a sub-pixel circuit (SPC of FIG. 2) of the second sub-pixel (SP2). The third light-emitting element (LD3') may be electrically connected to the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3') may be provided as a light-emitting element (LD of FIG. 2) connected to the sub-pixel circuit (SPC of FIG. 2) of the third sub-pixel (SP3).

[0225] The first light-emitting element (LD1'), the second light-emitting element (LD2'), and the third light-emitting element (LD3') may be inorganic light-emitting diodes including an inorganic light-emitting material. However, the embodiments are not limited thereto, and for example, the first light-emitting element (LD1'), the second light-emitting element (LD2'), and the third light-emitting element (LD3') may be organic light-emitting diodes including an organic light-emitting material.

[0226] Fig. 14 is a schematic cross-sectional view taken along line X2-X2' of Fig. 13. Fig. 15 is a schematic cross-sectional view taken along line Y2-Y2' of Fig. 13.

[0227] Referring to FIGS. 13 and 14, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0228] The pixel circuit layer (PCL) is described in the same manner as described with reference to Fig. 7. Therefore, description of overlapping content may be omitted.

[0229] A display element layer (DPL) may be disposed on a second passivation layer (PSV2). The display element layer (DPL) may include a first anode electrode (AE1), a cathode electrode (CE), a first reflective electrode (RFE1), a second reflective electrode (RFE2), an adhesive layer (ADL), first and second bridge electrodes (BRE1, BRE2), a first light-emitting element (LD1'), a third passivation layer (PSV3), a first light-extracting structure (OC1), a capping layer (CPL), a reflective layer (RFL), and a first bank layer (BNK).

[0230] An electrode layer including a first anode electrode (AE1) and a cathode electrode (CE) may be disposed on a pixel circuit layer (PCL). The first anode electrode (AE1) and the cathode electrode (CE) are described in the same manner as described with reference to FIG. 7. Therefore, description of overlapping content may be omitted.

[0231] The first reflective electrode (RFE1) may cover the first anode electrode (AE1). The second reflective electrode (RFE2) may cover the cathode electrode (CE). The first and second reflective electrodes (RFE1, RFE2) may include a material suitable for reflecting light. For example, the first and second reflective electrodes (RFE1, RFE2) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. Accordingly, light emitted from the light-emitting element (LD1') may be reflected by the first and second reflective electrodes (RFE1, RFE2), so that light emission efficiency may be improved.

[0232] In embodiments, the first and second reflective electrodes (RFE1, RFE2) may be omitted. In this case, the first anode electrode (AE1) and the cathode electrode (CE) may include a material suitable for reflecting light. That is, the first anode electrode (AE1) and the cathode electrode (CE) may perform the functions of the first and second reflective electrodes (RFE1, RFE2) described above.

[0233] An adhesive layer (ADL) may be disposed on a first reflective electrode (RFE1), a second reflective electrode (RFE2), and a second passivation layer (PSV2) between the first reflective electrode (RFE1) and the second reflective electrode (RFE2). The adhesive layer (ADL) may include an insulating material having adhesive properties. The adhesive layer (ADL) may serve to fix a first light-emitting element (LD1') attached to the adhesive layer (ADL).

[0234] The first light-emitting element (LD1') may include a light-emitting stack including a first semiconductor layer (11'), a second semiconductor layer (12') disposed under the first semiconductor layer (11'), and an active layer (13') disposed between the first semiconductor layer (11') and the second semiconductor layer (12'). In embodiments, the light-emitting stack may further include an auxiliary layer (14') disposed under the second semiconductor layer (12').

[0235] The first semiconductor layer (11') can be described in the same manner as the first semiconductor layer (11) described with reference to FIG. 7. The first semiconductor layer (11') provides holes to the active layer (13'). The first semiconductor layer (11') may include at least one p-type semiconductor material. Hereinafter, descriptions of overlapping content may be omitted.

[0236] The second semiconductor layer (12') can be described in the same manner as the second semiconductor layer (12) described with reference to FIG. 7. The second semiconductor layer (12') provides electrons to the active layer (13'). The second semiconductor layer (12') may include at least one n-type semiconductor material. Hereinafter, descriptions of overlapping content may be omitted.

[0237] The active layer (13') can be described in the same manner as the active layer (13') described with reference to Fig. 7. The active layer (13') is disposed between the first semiconductor layer (11') and the second semiconductor layer (12'), and may be a region where electrons and holes recombine. As electrons and holes recombine in the active layer (13'), they transition to a lower energy level, and light having a corresponding wavelength may be generated. Hereinafter, descriptions of overlapping content may be omitted.

[0238] The auxiliary layer (14') may include a gallium nitride (GaN) semiconductor material that is substantially not doped with impurities or is doped with impurities at a relatively low concentration, and may form an n-type semiconductor layer together with the second semiconductor layer (12').

[0239] The first light-emitting element (LD1') includes a first bonding electrode (BDE1') and a second bonding electrode (BDE2'). The first bonding electrode (BDE1') may be connected to an upper surface of the first semiconductor layer (11'). The first bonding electrode (BDE1') may not be in physical contact with the second semiconductor layer (12') and the active layer (13'). The second bonding electrode (BDE2') may be connected to a second semiconductor layer (12') that does not overlap with the first semiconductor layer (11') and the active layer (13'). For example, the second bonding electrode (BDE2') may be connected to the second semiconductor layer (12') exposed when the first semiconductor layer (11') and the active layer (13') are removed by etching. The second bonding electrode (BDE2') may not be in physical contact with the first semiconductor layer (11'), the active layer (13'), and the first bonding electrode (BDE1'). This first light-emitting element (LD1') may be a lateral chip type light-emitting element.

[0240] The first and second bonding electrodes (BDE1', BDE2') may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In embodiments, the first and second bonding electrodes (BDE1', BDE2') may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the first and second bonding electrodes (BDE1', BDE2') is not limited thereto.

[0241] The first light-emitting element (LD1') may include an insulating film (15') that covers at least a portion of the outer circumferential surface of the light-emitting stack. For example, the insulating film (15') may cover the entire outer circumferential surface of the light-emitting stack. The insulating film (15') may serve to prevent an electrical short circuit that may occur when the active layer (13') comes into contact with a conductive material other than the first semiconductor layer (11') and the second semiconductor layer (12'). The insulating film (15') may serve to prevent an electrical short circuit that may occur when the second bonding electrode (BDE2') comes into contact with the first semiconductor layer (11') and the active layer (13'). The insulating film (15') may include a transparent insulating material. As illustrated in FIG. 14, a portion of the first bonding electrode (BDE1') and a portion of the second bonding electrode (BDE2') may be exposed without being covered by the insulating film (15').

[0242] The first bonding electrode (BDE1') may extend along an insulating film (15') covering a side surface of the light-emitting stack. The extended portion of the first bonding electrode (BDE1') and the exposed portion of the first reflective electrode (RFE1) on which the adhesive layer (ADL) is not disposed (the exposed portion of the first anode electrode (AE1) when the first reflective electrode (RFE1) is omitted) may be electrically connected to each other via the first bridge electrode (BRE1). The second bonding electrode (BDE2') may extend along an insulating film (15') covering a side surface of the light-emitting stack. The extended portion of the second bonding electrode (BDE2') and the exposed portion of the second reflective electrode (RFE2) on which the adhesive layer (ADL) is not disposed (the exposed portion of the cathode electrode (CE) when the second reflective electrode (RFE2) is omitted) may be electrically connected to each other via the second bridge electrode (BRE2). The first bridge electrode (BRE1) and the second bridge electrode (BRE2) may include the same material as any one of the first anode electrode (AE1), the cathode electrode (CE), the first bonding electrode (BDE1'), and the second bonding electrode (BDE2'), but the embodiments are not limited thereto.

[0243] A third passivation layer (PSV3) is disposed on the pixel circuit layer (PCL) to entirely cover components such as the first bridge electrode (BRE1), the second bridge electrode (BRE2), and the first light-emitting element (LD1'). The third passivation layer (PSV3) can protect components disposed below the third passivation layer (PSV3). The third passivation layer (PSV3) may include the same material as any one of the first passivation layer (PSV1), the second passivation layer (PSV2), and the interlayer insulating layers (ILD), but embodiments are not limited thereto. In embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface of the first light-emitting element (LD1'). The third passivation layer (PSV3) may be omitted.

[0244] The first light extraction structure (OC1) is described in the same manner as described with reference to FIG. 7. The first light extraction structure (OC1) is arranged to overlap the first light-emitting element (LD1'). In embodiments, the first light extraction structure (OC1) may surround at least a portion of a side surface adjacent to the upper surface of the first light-emitting element (LD1'). Hereinafter, descriptions of overlapping content may be omitted.

[0245] The capping layer (CPL) is described in the same manner as described with reference to FIG. 7. The capping layer (CPL) can entirely cover the first light extraction structure (OC1) and the third passivation layer (PSV3). Hereinafter, descriptions of overlapping content may be omitted.

[0246] The first bank layer (BNK) and the reflective layer (RFL) are described in the same manner as described with reference to FIG. 7. The first bank layer (BNK1) may be disposed between the first light extraction structure (OC1) and the second and third light extraction structures (OC2, OC3 of FIG. 15) described below. The reflective layer (RFL) is disposed between the first bank layer (BNK) and the first light extraction structure (OC1). Hereinafter, descriptions of overlapping content may be omitted.

[0247] The first light extraction structure (OC1) and the reflective layer (RFL) can serve to improve the light emission efficiency of light generated from the first light-emitting element (LD1'). In this way, even when the first light-emitting element (LD1') is of a lateral chip type, the structures of the first light extraction structure (OC1) and the reflective layer (RFL) for improving the light emission efficiency of the first light-emitting element (LD1) of the flip chip type described with reference to FIG. 7 can be applied substantially identically (or similarly).

[0248] Above, the pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1) have been described. Each of the second and third sub-pixels (SP2, SP3) of FIG. 13 may also be configured similarly to the first sub-pixel (SP1), to the extent not otherwise described herein.

[0249] A light-functional layer (LFL) is provided on the first bank layer (BNK) and the capping layer (CPL). The light-functional layer (LFL) is described in the same manner as described with reference to FIG. 7. The light-functional layer (LFL) may include a filling layer (LRL) and a color filter layer (CFL). Hereinafter, descriptions of overlapping content may be omitted.

[0250] Referring to FIGS. 13 and 15, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0251] The pixel circuit layer (PCL) is described in the same manner as described with reference to Fig. 14. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1, SP2, SP3) are provided, respectively.

[0252] The display element layer (DPL) is described in the same manner as described with reference to FIG. 14. In the display element layer (DPL), first to third light-emitting elements (LD1', LD2', LD3') corresponding to first to third sub-pixels (SP1, SP2, SP3) are provided, respectively. The first light-emitting element (LD1') is connected between a cathode electrode (CE of FIG. 14) and a transistor (T_SP1 of FIG. 14) included in a sub-pixel circuit of the first sub-pixel (SP1). The second light-emitting element (LD2') is connected between the cathode electrode (CE) and a transistor included in a sub-pixel circuit of the second sub-pixel (SP2). The third light-emitting element (LD3') is connected between the cathode electrode (CE) and a transistor included in a sub-pixel circuit of the third sub-pixel (SP3).

[0253] In the embodiments, when the first sub-pixel (SP1) is a red sub-pixel, the first light-emitting element (LD1') may be configured to emit red color light. When the second sub-pixel (SP2) is a green sub-pixel, the second light-emitting element (LD2') may be configured to emit green color light. When the third sub-pixel (SP3) is a blue sub-pixel, the third light-emitting element (LD3') may be configured to emit blue color light. In this way, each of the first to third light-emitting elements (LD1', LD2', LD3') may be configured to emit light of a color corresponding to the type of the corresponding sub-pixel.

[0254] First to third light extraction structures (OC1, OC2, OC3) are provided, respectively corresponding to first to third light emitting elements (LD1', LD2', LD3'). The first to third light extraction structures (OC1, OC2, OC3) may be spaced apart from each other. The first light extraction structure (OC1) may cover the first light emitting element (LD1'). The second light extraction structure (OC2) may cover the second light emitting element (LD2'). The third light extraction structure (OC3) may cover the third light emitting element (LD3'). Each side surface of the first to third light extraction structures (OC1, OC2, OC3) may include a reverse tapered slope.

[0255] The first bank layer (BNK) and the reflective layer (RFL) are described in the same manner as described with reference to FIG. 8. The first bank layer (BNK) is provided between the first to third light extraction structures (OC1, OC2, OC3). Accordingly, the first bank layer (BNK) can surround the first to third light extraction structures (OC1, OC2, OC3). The reflective layer (RFL) is arranged between the first to third light extraction structures (OC1, OC2, OC3) and the first bank layer (BNK). The reflective layer (RFL) can surround at least a side surface of each of the first to third light extraction structures (OC1, OC2, OC3).

[0256] A light-emitting diode (LFL) layer is provided on the display element layer (DPL). The light-emitting diode (LFL) layer is described in the same manner as described with reference to Fig. 8. Therefore, description of overlapping content may be omitted.

[0257] Referring again to FIGS. 13 to 15, instead of the reflective layer (RFL) illustrated in FIGS. 14 and 15, the reflective layer (RFL') described with reference to FIGS. 9 and 10 may be applied.

[0258] According to embodiments, the first to third light-emitting elements (LD1', LD2', LD3') may emit light of the same color. In this case, instead of the light functional layer (LFL) illustrated in FIGS. 14 and 15, the light functional layer (LFL) described with reference to FIGS. 11 and 12 may be applied.

[0259] FIG. 16 is a schematic plan view for explaining a third embodiment of one of the pixels included in the display panel of FIG. 3.

[0260] Referring to FIG. 16, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in a first direction (DR1). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0261] First to third anode electrodes (AE1, AE2, AE3) may be respectively disposed in the first to third sub-pixels (SP1, SP2, SP3). The first anode electrode (AE1) may be provided as an anode electrode (AE of FIG. 2) included in a sub-pixel circuit (SPC of FIG. 2) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) included in a sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0262] One or more first light-emitting elements (LD1"), one or more second light-emitting elements (LD2"), and one or more third light-emitting elements (LD3") may be arranged on the first to third anode electrodes (AE1, AE2, AE3). The first light-emitting elements (LD1") are connected to the first anode electrode (AE1). The second light-emitting elements (LD2") are connected to the second anode electrode (AE2). The third light-emitting elements (LD3") are connected to the third anode electrode (AE3). When light-emitting elements are provided in each sub-pixel, each anode electrode may have a shape extending in a specific direction, such as the second direction (DR2), and the light-emitting elements connected thereto may be arranged in the same direction.

[0263] The first light-emitting elements (LD1") may be provided as light-emitting elements (LD of FIG. 2) included in the first sub-pixel (SP1). The second light-emitting elements (LD2") may be provided as light-emitting elements (LD) included in the second sub-pixel (SP2). The third light-emitting elements (LD3") may be provided as light-emitting elements (LD) included in the third sub-pixel (SP3). When light-emitting elements are provided in one sub-pixel, the light-emitting elements may be connected in parallel between the anode electrode and the cathode electrode and provided as light-emitting elements (LD) of FIG. 2.

[0264] The first light-emitting elements (LD1"), the second light-emitting elements (LD2"), and the third light-emitting elements (LD3") may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0265] Figure 17 is a schematic cross-sectional view taken along line X3-X3' of Figure 16.

[0266] Referring to FIGS. 16 and 17, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0267] The pixel circuit layer (PCL) is described in the same manner as described with reference to Fig. 7. Therefore, description of overlapping content may be omitted.

[0268] On the pixel circuit layer (PCL), first to third anode electrodes (AE1, AE2, AE3) are respectively arranged in the first to third sub-pixels (SP1, SP2, SP3).

[0269] The first anode electrode (AE1) may be electrically connected to a transistor included in a first sub-pixel circuit through a contact hole penetrating at least a portion of the pixel circuit layer (PCL). The second anode electrode (AE2) may be electrically connected to a transistor included in a second sub-pixel circuit through a contact hole penetrating at least a portion of the pixel circuit layer (PCL). The third anode electrode (AE3) may be electrically connected to a transistor included in a third sub-pixel circuit through a contact hole penetrating at least a portion of the pixel circuit layer (PCL).

[0270] First to third light-emitting elements (LD1", LD2", LD3") are respectively disposed on the first to third anode electrodes (AE1, AE2, AE3). The first to third light-emitting elements (LD1", LD2", LD3") can be bonded to, coupled to, or connected to the first to third anode electrodes (AE1, AE2, AE3), respectively.

[0271] The first light-emitting element (LD1") may include a bonding electrode (BDE"), a first semiconductor layer (11"), a second semiconductor layer (12"), an active layer (13"), and an auxiliary layer (14"). The first light-emitting element (LD1") may be implemented as a vertical light-emitting laminate in which the bonding electrode (BDE"), the first semiconductor layer (11"), the active layer (13"), the second semiconductor layer (12"), and the auxiliary layer (14") are sequentially laminated along a third direction (DR3).

[0272] The first semiconductor layer (11") is described in the same manner as the first semiconductor layer (11) described with reference to FIG. 7. The second semiconductor layer (12") is described in the same manner as the second semiconductor layer (12) described with reference to FIG. 7. The active layer (13") is described in the same manner as the active layer (13) described with reference to FIG. 7. The auxiliary layer (14") is described in the same manner as the auxiliary layer (14) described with reference to FIG. 7. Therefore, description of overlapping content may be omitted.

[0273] The bonding electrode (BDE) may be electrically connected to the first semiconductor layer (11"). The bonding electrode (BDE) may include a eutectic metal.

[0274] The first light-emitting element (LD1") may further include an insulating film (15") covering at least a portion of an outer surface of the vertical light-emitting stack. The insulating film (15") may prevent an electrical short circuit that may occur when the active layer (13") comes into contact with a conductive material other than the first and second semiconductor layers (11", 12"). The insulating film (15") may include a transparent insulating material. As illustrated in FIG. 17, the insulating film (15") is configured to expose at least a portion of the bonding electrode (BDE"). The insulating film (15") is configured to expose an upper surface of the auxiliary layer (14") that is to be in contact with the cathode electrode (CE).

[0275] The lower surface of the bonding electrode (BDE) may be connected to the first anode electrode (AE1). The upper surface of the auxiliary layer (14") may be connected to the cathode electrode (CE). Accordingly, the first light-emitting element (LD1") may be electrically connected between the first anode electrode (AE1) and the cathode electrode (CE).

[0276] According to embodiments, a reflective electrode may be further disposed between the bonding electrode (BDE) and the first semiconductor layer (11"). In this case, light emitted from the first light-emitting element (LD1") can be efficiently output toward the light functional layer (LFL). The reflective electrode may be formed of a conductive material having a predetermined reflectivity. The conductive material may include an opaque metal. The opaque metal may include, for example, a metal such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), or an alloy thereof. However, the material of the reflective electrode is not limited thereto.

[0277] Each of the second and third light-emitting elements (LD2", LD3") is configured similarly to the first light-emitting element (LD1"). Hereinafter, description of overlapping content may be omitted.

[0278] A third passivation layer (PSV3) is disposed entirely on the pixel circuit layer (PCL). The third passivation layer (PSV3) may serve to fix the first to third light-emitting elements (LD1", LD2", LD3") bonded to the first to third anode electrodes (AE1, AE2, AE3) so as not to move. The third passivation layer (PSV3) may serve to protect components disposed below the third passivation layer (PSV3) from foreign substances such as dust and moisture. For example, the third passivation layer (PSV3) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the third passivation layer (PSV3) may include epoxy, but embodiments are not limited thereto.

[0279] In the embodiments, the third passivation layer (PSV3) may not be disposed on the upper surface of each of the first to third light-emitting elements (LD1", LD2", LD3"). Each of the first to third light-emitting elements (LD1", LD2", LD3") may protrude from the third passivation layer (PSV3) in the third direction (DR3).

[0280] A cathode electrode (CE) is disposed on the first to third light-emitting elements (LD1", LD2", LD3"). The cathode electrode (CE) can be disposed entirely on the first to third light-emitting elements (LD1", LD2", LD3") and the third passivation layer (PSV3). The cathode electrode (CE) can contact the auxiliary layer (14") of each of the first to third light-emitting elements (LD1", LD2", LD3"). The cathode electrode (CE) can be electrically connected to the second power voltage node (VSSN) of FIG. 2. Accordingly, the second power voltage applied to the second power voltage node (VSSN) can be transmitted to the first to third light-emitting elements (LD1", LD2", LD3") through the cathode electrode (CE).

[0281] The cathode electrode (CE) may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In embodiments, the cathode electrode (CE) may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the cathode electrode (CE) is not limited thereto.

[0282] According to embodiments, an encapsulation layer may be further disposed on the cathode electrode (CE). The encapsulation layer may be disposed to entirely cover the cathode electrode (CE). The encapsulation layer may protect components under the encapsulation layer, such as the cathode electrode (CE) and the first to third light-emitting elements (LD1", LD2", LD3"), from external moisture and humidity, etc., within the spirit and scope of the present disclosure. The encapsulation layer may include at least one of a metal oxide such as silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. However, the material of the encapsulation layer is not limited thereto.

[0283] First to third light extraction structures (OC1, OC2, OC3) are respectively disposed on the first to third light emitting elements (LD1", LD2", LD3"). The first light extraction structure (OC1) may be disposed to overlap the first light emitting element (LD1"). The first light extraction structure (OC1) may surround at least a portion of a side surface adjacent to an upper surface of the first light emitting element (LD1"). The second light extraction structure (OC2) may be disposed to overlap the second light emitting element (LD2"). The second light extraction structure (OC2) may surround at least a portion of a side surface adjacent to an upper surface of the second light emitting element (LD2"). The third light extraction structure (OC3) may be disposed to overlap the third light emitting element (LD3"). The third light extraction structure (OC3) can surround at least a portion of a side surface adjacent to the upper surface of the third light emitting element (LD3"). The first to third light extraction structures (OC1, OC2, OC3) can be spaced apart from each other.

[0284] The capping layer (CPL) is described in the same manner as described with reference to FIGS. 7 and 8. The capping layer (CPL) can entirely cover the first to third light extraction structures (OC1, OC2, OC3) and the cathode electrode (CE).

[0285] The first bank layer (BNK) and the reflective layer (RFL) are described in the same manner as described with reference to FIGS. 7 and 8. The first bank layer (BNK) is disposed between the first to third light extraction structures (OC1, OC2, OC3). The reflective layer (RFL) is disposed between the first bank layer (BNK) and the first to third light extraction structures (OC1, OC2, OC3). The reflective layer (RFL) may surround at least a side surface of each of the first to third light extraction structures (OC1, OC2, OC3).

[0286] The first to third light extraction structures (OC1, OC2, OC3) and the reflective layer (RFL) can serve to improve the light emission efficiency of light generated from the first to third light-emitting elements (LD1", LD2", LD3"). In this way, even when the first to third light-emitting elements (LD1", LD2", LD3") are vertical light-emitting elements, the structure of the first light extraction structure (OC1) and the reflective layer (RFL) for improving the light emission efficiency of the first light-emitting element (LD1) of the flip chip type described with reference to FIGS. 7 and 8 can be applied substantially identically (or similarly).

[0287] A light-functional layer (LFL) is provided on the first bank layer (BNK) and the capping layer (CPL). The light-functional layer (LFL) is described in the same manner as described with reference to FIG. 7. The light-functional layer (LFL) may include a filling layer (LRL) and a color filter layer (CFL).

[0288] In the embodiments, when the first sub-pixel (SP1) is a red sub-pixel, the first light-emitting element (LD1") may be configured to emit red color light. When the second sub-pixel (SP2) is a green sub-pixel, the second light-emitting element (LD2") may be configured to emit green color light. When the third sub-pixel (SP3) is a blue sub-pixel, the third light-emitting element (LD3") may be configured to emit blue color light. In this way, each of the first to third light-emitting elements (LD1", LD2", LD3") may be configured to emit light of a color corresponding to the type of the corresponding sub-pixel. In this case, instead of the reflective layer (RFL) illustrated in FIG. 17, the reflective layer (RFL') described with reference to FIGS. 9 and 10 may be applied.

[0289] According to embodiments, the first to third light-emitting elements (LD1", LD2", LD3") may emit light of the same color. In this case, instead of the light functional layer (LFL) illustrated in FIG. 17, the light functional layer (LFL) described with reference to FIGS. 11 and 12 may be applied.

[0290] FIGS. 18 to 24 are drawings for explaining a method of manufacturing a display device according to one embodiment of the present disclosure.

[0291] Hereinafter, with reference to FIGS. 18 to 24, a method for manufacturing a display element layer (DPL) described with reference to FIGS. 6 to 8 will be described. In describing FIGS. 18 to 24, descriptions of content that overlaps with the content described with reference to FIGS. 6 to 8 may be omitted.

[0292] Referring to FIG. 18, a substrate (SUB), a pixel circuit layer (PCL), an adhesive layer (ADL), first to third light-emitting elements (LD1, LD2, LD3), and a third passivation layer (PSV3) can be formed.

[0293] Thereafter, an overcoating layer (OC) can be formed entirely on the third passivation layer (PSV3). The overcoating layer (OC) can have a sufficient thickness in the third direction (DR3) so as to entirely cover the first to third light-emitting elements (LD1, LD2, LD3).

[0294] Referring to FIG. 19, the overcoating layer (OC) of FIG. 18 can be exposed and developed to form first to third light extraction structures (OC1, OC2, OC3).

[0295] In one embodiment, the overcoat layer (OC) may include a negative photoresist material. Here, the negative photoresist material is a material that is hardened by exposure, and when developed after exposure, the exposed portion of the negative photoresist material remains, and the unexposed portion can be removed. For example, the first to third light extraction structures (OC1, OC2, OC3) may be exposed portions of the overcoat layer (OC).

[0296] In this way, when the first to third light extraction structures (OC1, OC2, OC3) are formed by exposure and development of the overcoating layer (OC) including a negative photoresist material, the side surfaces of the first to third light extraction structures (OC1, OC2, OC3) may include reverse tapered slopes. In contrast, when the first to third light extraction structures (OC1, OC2, OC3) are formed by exposure and development of the overcoating layer (OC) including a positive photoresist material, the side surfaces of the first to third light extraction structures (OC1, OC2, OC3) may include regular tapered slopes.

[0297] In the embodiments, the overcoating layer (OC) may include scattering particles (SCT). Accordingly, the first to third light extraction structures (OC1, OC2, OC3) formed by exposure and development of the overcoating layer (OC) may also include scattering particles (SCT).

[0298] Referring to FIG. 20, a capping layer (CPL) can be formed that entirely covers the first to third light extraction structures (OC1, OC2, OC3) and the third passivation layer (PSV3). There is no limitation on the method for forming the capping layer (CPL), and various methods can be used.

[0299] Referring to Fig. 21, a reflective layer (RFL) can be formed that covers the entire capping layer (CPL). There is no limitation on the method for forming the reflective layer (RFL), and various methods can be used.

[0300] Referring to FIG. 22, a first bank layer (BNK) can be formed that entirely covers the reflective layer (RFL). In this case, the upper surface of the first bank layer (BNK) can be substantially flat. Between the first to third light extraction structures (OC1, OC2, and OC3), the lowermost surface of the first bank layer (BNK) can be entirely covered by the reflective layer (RFL).

[0301] Referring to FIG. 23, the first bank layer (BNK) disposed in an area overlapping at least a portion of the upper surface of each of the first to third light extraction structures (OC1, OC2, OC3) can be etched and removed. Accordingly, the reflective layer (RFL) disposed in an area overlapping at least a portion of the upper surface of each of the first to third light extraction structures (OC1, OC2, OC3) can be exposed.

[0302] Referring to Fig. 24, the reflective layer (RFL) can be etched using the first bank layer (BNK) as a mask. Accordingly, the exposed portion of the reflective layer (RFL) described with reference to Fig. 23 can be removed. The side surfaces of the first bank layer (BNK) and the side surfaces of the reflective layer (RFL) can be aligned with each other.

[0303] FIGS. 25 to 28 are drawings for explaining a method of manufacturing a display device according to one embodiment.

[0304] Hereinafter, with reference to FIGS. 25 to 28, a method for manufacturing a display element layer (DPL) described with reference to FIGS. 6, 9, and 10 will be described. In describing FIGS. 25 to 28, descriptions of content that overlaps with the content described with reference to FIGS. 6, 9, and 10 may be omitted.

[0305] Referring to Fig. 25, the steps described with reference to Figs. 18 to 21 may be performed. Accordingly, descriptions of overlapping content may be omitted.

[0306] Referring to FIG. 26, a reflective layer (RFL) disposed in an area overlapping at least a portion of the upper surface of each of the first to third light extraction structures (OC1, OC2, OC3) can be etched.

[0307] In one embodiment, the etching of the reflective layer (RFL) may be anisotropic dry etching of the reflective layer (RFL). In this case, a portion of the reflective layer (RFL) surrounding the side surface including the reverse tapered inclined surface of the first to third light extracting structures (OC1, OC2, OC3) may remain without being removed by the anisotropic dry etching. Another portion of the reflective layer (RFL) disposed on the capping layer (CPL) between the first to third light extracting structures (OC1, OC2, OC3) so as to be adjacent to the portion of the reflective layer (RFL) may remain without being removed by the anisotropic dry etching. Accordingly, the reflective layer (RFL') described with reference to FIGS. 9 and 10 may be formed. In this case, between the first to third light extraction structures (OC1, OC2, OC3), a portion of the capping layer (CPL) may be exposed without being covered by the reflective layer (RFL').

[0308] Referring to FIG. 27, a first bank layer (BNK) may be formed that entirely covers the capping layer (CPL) and the reflective layer (RFL'). In this case, the upper surface of the first bank layer (BNK) may be substantially flat. The lowermost surface of the first bank layer (BNK) may be in contact with the capping layer (CPL) that is exposed and not covered by the reflective layer (RFL') between the first to third light extraction structures (OC1, OC2, and OC3).

[0309] Referring to FIG. 28, the first bank layer (BNK) disposed in an area overlapping at least a portion of the upper surface of each of the first to third light extraction structures (OC1, OC2, OC3) can be etched and removed. Accordingly, the capping layer (CPL) disposed in an area overlapping at least a portion of the upper surface of each of the first to third light extraction structures (OC1, OC2, OC3) can be exposed.

[0310] Figure 29 is a block diagram illustrating a display system according to one embodiment.

[0311] Referring to FIG. 29, the display system (1000) may include a processor (1100) and a display device (1200).

[0312] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), and the like, all within the spirit and scope of the present disclosure. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0313] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0314] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. The display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0315] Figures 30 to 33 are schematic perspective views illustrating application examples of the display system of Figure 29.

[0316] Referring to FIG. 30, the display system (1000) of FIG. 29 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0317] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0318] Referring to FIG. 31, the display system (1000) of FIG. 29 can be applied to an automotive display system (3000). Here, the automotive display system (3000) can include a computing system provided inside and / or outside a vehicle to provide image data.

[0319] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0320] Referring to FIG. 32, the display system (1000) of FIG. 29 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0321] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0322] The frame (4100) may include a battery, a touch pad, a microphone, a camera, etc. The frame (4100) may include a projector that outputs light, a processor that controls light signals, etc.

[0323] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or other materials within the spirit and scope of the present disclosure.

[0324] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0325] Referring to FIG. 33, the display system (1000) of FIG. 29 can be applied to a head-mounted display device (5000).

[0326] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0327] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in a form within the spirit and scope of the present disclosure, such as a glasses frame form or a helmet form.

[0328] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0329] Although the present disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the claims below.

Claims

1. A plurality of light-emitting elements arranged on a pixel circuit layer; A plurality of light extraction structures overlapping the plurality of light emitting elements and spaced apart from each other on the pixel circuit layer; a first bank layer disposed between the plurality of light extraction structures; and A reflective layer disposed between the plurality of light extraction structures and the first bank layer, the reflective layer surrounding at least a side surface of each of the plurality of light extraction structures, Each of the plurality of light-emitting elements is covered by a corresponding light-extracting structure among the plurality of light-extracting structures, A display device, wherein each side surface of the plurality of light extraction structures includes a substantially reverse tapered slope.

2. In paragraph 1, A display device, wherein each of the plurality of light extraction structures comprises a negative photoresist material.

3. In paragraph 1, A display device, wherein the reflective layer is not disposed between the lower surface of each of the plurality of light extraction structures and the pixel circuit layer.

4. In paragraph 1, A display device, wherein each of the plurality of light extraction structures surrounds at least a portion of a side surface adjacent to the upper surface of a corresponding light emitting element among the plurality of light emitting elements.

5. In paragraph 1, A display device, wherein each of the plurality of light extraction structures includes a scattering particle.

6. In paragraph 1, A display device, wherein, in cross-section, the upper edge of each of the plurality of light extraction structures has a substantially rounded shape.

7. In paragraph 1, A display device, wherein, in cross-section, the side surface between the lower surface and the upper edge of each of the plurality of light extraction structures is a substantially reverse tapered slope.

8. In paragraph 7, A display device, wherein the reflective layer extends from the side surface of each of the plurality of light extraction structures to further cover the upper edge of each of the plurality of light extraction structures and a portion of the upper surface adjacent to the upper edge.

9. In paragraph 8, A display device in which the reflective layer covers the lowermost surface of the first bank layer.

10. In paragraph 8, A display device, wherein on the upper surface of each of the plurality of light extraction structures, the side surface of the reflective layer and the side surface of the first bank layer are aligned with each other.

11. In paragraph 7, A display device, wherein the reflective layer covers a portion of the upper edge adjacent to the side surface of each of the plurality of light extraction structures, and does not cover the upper surface of each of the plurality of light extraction structures.

12. In paragraph 11, A display device, wherein the lowermost surface of the first bank layer is not covered by the reflective layer.

13. In paragraph 1, A display device further comprising a plurality of light conversion patterns spaced apart from each other on the plurality of light extraction structures so as to overlap the plurality of light extraction structures.

14. In paragraph 13, A second bank layer surrounding each of the plurality of light conversion patterns and overlapping the first bank layer; and A display device further comprising an optical reflection layer disposed between the plurality of optical conversion patterns and the second bank layer.

15. A step of forming a plurality of light-emitting elements on a pixel circuit layer; A step of forming a plurality of light extraction structures spaced apart from each other on the pixel circuit layer so as to overlap the plurality of light emitting elements; A step of forming a reflective layer entirely on the pixel circuit layer, the reflective layer covering the plurality of light extraction structures; A step of forming a first bank layer entirely on the above reflective layer, wherein the first bank layer covers the reflective layer; A step of etching the first bank layer disposed in an area overlapping at least a portion of the upper surface of each of the plurality of light extraction structures; and A step of etching the reflective layer using the first bank layer as a mask is included. Each of the plurality of light-emitting elements is surrounded by a corresponding light-extracting structure among the plurality of light-extracting structures, A method for manufacturing a display device, wherein each side surface of the plurality of light extraction structures includes a substantially reverse tapered slope.

16. In paragraph 15, The step of forming the plurality of light extraction structures is: A step of forming an overcoating layer entirely on the pixel circuit layer, the overcoating layer covering the plurality of light-emitting elements; and A method for manufacturing a display device, comprising a step of forming the plurality of light extraction structures by exposing and developing the overcoating layer.

17. In paragraph 16, A method for manufacturing a display device, wherein the overcoating layer comprises a negative photoresist material.

18. A step of forming a plurality of light-emitting elements on a pixel circuit layer; A step of forming a plurality of light extraction structures that overlap the plurality of light emitting elements and are spaced apart from each other on the pixel circuit layer; A step of forming a reflective layer entirely on the pixel circuit layer, the reflective layer covering the plurality of light extraction structures; A step of etching the reflective layer disposed in an area overlapping at least a portion of the upper surface of each of the plurality of light extraction structures; A step of forming a first bank layer entirely on the pixel circuit layer, the first bank layer covering the plurality of light extraction structures and the reflective layer; and A step of etching the first bank layer disposed in an area overlapping at least a portion of the upper surface of each of the plurality of light extraction structures, Each of the plurality of light-emitting elements is surrounded by a corresponding light-extracting structure among the plurality of light-extracting structures, A method for manufacturing a display device, wherein each side surface of the plurality of light extraction structures includes a substantially reverse tapered slope.

19. In paragraph 18, A method for manufacturing a display device, wherein the step of etching the reflective layer includes a step of anisotropically dry etching the reflective layer.

20. In paragraph 19, A method for manufacturing a display device, wherein, in the step of etching the reflective layer, a part of the reflective layer disposed between the plurality of light extraction structures is etched.

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