Pixel circuit, driving method, and display apparatus

Abstract

Provided are a pixel circuit, a driving method, and a display apparatus. The pixel circuit comprises a light-emitting element (E1), a driving circuit (10), a first energy storage circuit (11), a second energy storage circuit (12), a third energy storage circuit (21), and a first reset control circuit (13). The first reset control circuit (13) writes a reference voltage (REF) into a first node (N1) under the control of a first reset control signal (R1); a first end of the first energy storage circuit (11) is electrically connected to the first node (N1), a second end of the first energy storage circuit (11) is electrically connected to a third node (N3), and the first energy storage circuit (11) is configured to store electric energy; the second energy storage circuit (12) is electrically connected to the third node (N3), and the second energy storage circuit (12) is configured to store electric energy; and the third energy storage circuit (21) is electrically connected to the first node (N1), and the third energy storage circuit (21) is configured to store electric energy. The pixel circuit performs threshold voltage compensation by means of the first reset control circuit (13), and enables threshold voltage compensation to be separated from data writing time, thereby improving the threshold voltage compensation effect.

Description

Pixel circuit, driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, and a display device. Background Art

[0002] As the resolution and frequency of display devices increase, the solution of using data voltage to compensate for threshold voltage has encountered a driving bottleneck, and the demand for separate compensation circuits has greatly increased. Increasing the threshold voltage compensation time can improve the uniformity of the picture display. Since the LTPS (low-temperature polycrystalline silicon) process has high requirements for equipment precision, how to reduce costs has always been a difficult problem in the manufacturing process. Oxide thin-film transistors have their own low cost, high uniformity, and low leakage. Pixel circuits for oxides are urgently needed to be developed.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit, comprising a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a third energy storage circuit, and a first reset control circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the light-emitting element via a third node; the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of the first node;

[0006] The first reset control circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the first node respectively, and is configured to write the reference voltage provided by the reference voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal;

[0007] A first end of the first energy storage circuit is electrically connected to the first node, a second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy;

[0008] The second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy;

[0009] The third energy storage circuit is electrically connected to the first node, and the third energy storage circuit is used to store electrical energy.

[0010] Optionally, the first end of the second energy storage circuit is electrically connected to the third node, and the second end of the second energy storage circuit is electrically connected to the first control voltage end;

[0011] The first control voltage terminal is a DC voltage terminal; or,

[0012] In a refresh frame, the first control voltage terminal is used to provide a first control voltage and a second control voltage in a time-sharing manner; the first control voltage is different from the second control voltage.

[0013] Optionally, the first end of the third energy storage circuit is electrically connected to the first node, and the second end of the third energy storage circuit is electrically connected to the second control voltage terminal;

[0014] The second control voltage terminal is a DC voltage terminal; or,

[0015] In a refresh frame, the second control voltage terminal is used to provide a third control voltage and a fourth control voltage in a time-sharing manner; the third control voltage is different from the fourth control voltage.

[0016] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit;

[0017] The data writing circuit is electrically connected to the scanning end, the data line and the first node respectively. The data writing circuit is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end.

[0018] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit and a second light emitting control circuit;

[0019] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of a first light-emitting control signal provided by the first light-emitting control terminal;

[0020] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node and the first pole of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0021] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset control circuit;

[0022] The second reset control circuit is electrically connected to the second reset control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0023] Optionally, the driving circuit includes a driving transistor, the first reset control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor;

[0024] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0025] The gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0026] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node.

[0027] Optionally, the second energy storage circuit includes a second capacitor;

[0028] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the first control voltage end.

[0029] Optionally, the third energy storage circuit includes a third capacitor;

[0030] A first terminal of the third capacitor is electrically connected to the first node, and a second terminal of the third capacitor is electrically connected to the second control voltage terminal.

[0031] Optionally, the data writing circuit includes a second transistor;

[0032] The gate of the second transistor is electrically connected to the scanning end, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the first node;

[0033] The first light emitting control circuit includes a third transistor, and the second light emitting control circuit includes a fourth transistor;

[0034] The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the second node;

[0035] The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

[0036] Optionally, the second reset control circuit includes a fifth transistor;

[0037] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light emitting element.

[0038] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit. The driving method includes:

[0039] The driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node;

[0040] The first reset control circuit writes a reference voltage into the first node under the control of a first reset control signal.

[0041] Optionally, the pixel circuit further includes a first light emitting control circuit and a second light emitting control circuit; the display cycle includes a refresh frame; the refresh frame includes a refresh time period, and the refresh time period is sequentially provided with a compensation phase, a data writing phase, and a light emitting phase;

[0042] The driving method includes:

[0043] During the compensation phase, the first reset control circuit writes a reference voltage into the first node under the control of a first reset control signal; and the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal.

[0044] In the data writing phase, the data writing circuit writes the data voltage provided by the data line into the first node under the control of the scan signal;

[0045] In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0046] Optionally, the pixel circuit further includes a third energy storage circuit; a first end of the third energy storage circuit is electrically connected to the first node, a second end of the third energy storage circuit is electrically connected to the DC voltage terminal, and the third energy storage circuit is used to store electrical energy; the refresh time period also includes a bias phase;

[0047] The driving method further includes:

[0048] In the compensation phase, the data writing phase and the light emitting phase, the first control voltage terminal is used to provide a first control voltage;

[0049] During the bias phase, the first control voltage terminal provides a second control voltage;

[0050] The first control voltage is different from the second control voltage.

[0051] Optionally, the display cycle further includes at least one hold frame arranged after the refresh frame; the hold frame includes a hold bias phase and a hold light emitting phase arranged in sequence; and the driving method further includes:

[0052] In the bias holding phase, the first control voltage terminal provides a second control voltage;

[0053] During a time period of the holding frame except the holding bias phase, the first control voltage terminal provides a first control voltage;

[0054] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0055] Optionally, the refresh frame further includes at least one holding period arranged after the refresh period; the holding period includes a holding bias phase and a holding light-emitting phase arranged in sequence; and the driving method further includes:

[0056] In the bias holding phase, the first control voltage terminal provides a second control voltage;

[0057] During a time period included in the holding time period except the holding bias phase, the first control voltage terminal provides a first control voltage;

[0058] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0059] Optionally, the first control voltage terminal is a DC voltage terminal; the pixel circuit further includes a third energy storage circuit; a first terminal of the third energy storage circuit is electrically connected to the first node, a second terminal of the third energy storage circuit is electrically connected to the second control voltage terminal, and the third energy storage circuit is used to store electrical energy;

[0060] The refresh period also includes a bias phase;

[0061] The driving method further includes:

[0062] In the compensation phase, the data writing phase and the light emitting phase, the second control voltage terminal is used to provide a third control voltage;

[0063] In the bias phase, the second control voltage terminal provides a fourth control voltage;

[0064] The third control voltage is different from the fourth control voltage.

[0065] Optionally, the display cycle further includes at least one hold frame arranged after the refresh frame; the hold frame includes a hold bias phase and a hold light emitting phase arranged in sequence; and the driving method further includes:

[0066] In the bias holding phase, the second control voltage terminal provides a fourth control voltage;

[0067] During a time period of the holding frame except the holding bias phase, the second control voltage terminal provides a third control voltage;

[0068] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0069] Optionally, the refresh frame further includes at least one holding period arranged after the refresh period; the holding period includes a holding bias phase and a holding light-emitting phase arranged in sequence; and the driving method further includes:

[0070] In the bias holding phase, the second control voltage terminal provides a fourth control voltage;

[0071] During a time period included in the holding time period except the holding bias phase, the second control voltage terminal provides a third control voltage;

[0072] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0073] Optionally, the refresh period further includes an initialization phase provided before the compensation phase; the pixel circuit further includes a second reset control circuit;

[0074] The driving method further includes:

[0075] In the initialization phase, the second reset control circuit writes an initial voltage into the first electrode of the light-emitting element under the control of the second reset control signal; and the second light-emitting control circuit controls the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal;

[0076] The bias stage is set before the initialization stage; or, the bias stage is set between the initialization stage and the compensation stage; or, the bias stage is set between the compensation stage and the data writing stage; or, the bias stage is set between the data writing stage and the light emitting stage.

[0077] In a third aspect, an embodiment of the present disclosure provides a display device, including the above-mentioned display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0086] FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0087] FIG10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] FIG11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0089] FIG12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0090] FIG13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0091] FIG14 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG13 ;

[0092] FIG15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0093] FIG16 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG15 ;

[0094] FIG17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0095] FIG18 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG17 ;

[0096] FIG19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0097] FIG. 20 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 19 . DETAILED DESCRIPTION

[0098] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0099] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element E1, a driving circuit 10, a first energy storage circuit 11, a second energy storage circuit 12, a third energy storage circuit 21 and a first reset control circuit 13;

[0100] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the light-emitting element E1 via the third node N3. The driving circuit 10 is configured to generate a driving current for driving the light-emitting element E1 under the control of the potential of the first node N1.

[0101] The first reset control circuit 13 is electrically connected to the first reset control terminal R1, the reference voltage terminal REF and the first node N1 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1;

[0102] A first end of the first energy storage circuit 11 is electrically connected to the first node N1, a second end of the first energy storage circuit 11 is electrically connected to the third node N3, and the first energy storage circuit 11 is used to store electrical energy;

[0103] The second energy storage circuit 12 is electrically connected to the third node N3, and the second energy storage circuit 12 is used to store electrical energy;

[0104] The third energy storage circuit 21 is electrically connected to the first node N1 , and the third energy storage circuit 21 is used to store electrical energy.

[0105] The pixel circuit described in the embodiment of the present disclosure can perform threshold voltage compensation through the first reset control circuit 13, and can separate the threshold voltage compensation from the data writing time, thereby improving the threshold voltage compensation effect and supporting compensation of depletion-type devices.

[0106] Optionally, the light emitting element may be an organic light emitting diode, but is not limited thereto.

[0107] In at least one embodiment of the present disclosure, the first terminal of the second energy storage circuit is electrically connected to the third node, and the second terminal of the second energy storage circuit is electrically connected to the first control voltage terminal;

[0108] The first control voltage terminal is a DC voltage terminal; or,

[0109] In a refresh frame, the first control voltage terminal is used to provide a first control voltage and a second control voltage in a time-sharing manner; the first control voltage is different from the second control voltage.

[0110] In a specific implementation, the first end of the second energy storage circuit can be electrically connected to the third node, and the second end of the second energy storage circuit can be electrically connected to the first control voltage end; wherein, the first control voltage end can be a DC voltage end, or, in a refresh frame, the first control voltage end can provide different control voltages in a time-sharing manner.

[0111] In at least one embodiment of the present disclosure, a first terminal of the third energy storage circuit is electrically connected to the first node, and a second terminal of the third energy storage circuit is electrically connected to the second control voltage terminal;

[0112] The second control voltage terminal is a DC voltage terminal; or,

[0113] In a refresh frame, the second control voltage terminal is used to provide a third control voltage and a fourth control voltage in a time-sharing manner; the third control voltage is different from the fourth control voltage.

[0114] In a specific implementation, the first end of the third energy storage circuit can be electrically connected to the first node, and the second end of the third energy storage circuit can be electrically connected to the second control voltage end; wherein, the second control voltage end can be a DC voltage end, or, in a refresh frame, the second control voltage end can provide different control voltages in a time-sharing manner.

[0115] In a specific implementation, the pixel circuit may include a third energy storage circuit, which is electrically connected to the first node and is used to store electrical energy. At this time, the first control voltage terminal can provide different control voltages in different time periods. In the bias stage, the corresponding control voltage can be provided through the first control voltage terminal to change the gate-source voltage of the driving transistor in the driving circuit to improve the hysteresis phenomenon of the driving transistor.

[0116] In at least one embodiment of the present disclosure, the pixel circuit may include a third energy storage circuit; a first end of the third energy storage circuit is electrically connected to the first node, and a second end of the third energy storage circuit is electrically connected to a second control voltage end; the third energy storage circuit is used to store electrical energy; the second control voltage end can provide different control voltages during the stress application phase and in time periods other than the stress application phase, so as to change the gate-source voltage of the driving transistor included in the driving circuit in combination with the third energy storage circuit during the stress application phase, so as to stress bias the driving transistor, restore the threshold voltage offset of the driving transistor caused by hysteresis, and support stress reset between low-frequency frames or PWM (pulse width modulation) pulses.

[0117] Optionally, the stress application phase may be set before the initialization phase; or the stress application phase may be set between the initialization phase and the compensation phase; or the stress application phase may be set between the compensation phase and the data writing phase; or the stress application phase may be set between the data writing phase and the light emitting phase. As shown in FIG2 , based on at least one embodiment of the pixel circuit shown in FIG1 ; the first end of the second energy storage circuit 12 is electrically connected to the third node N3, and the second end of the second energy storage circuit 12 is electrically connected to the first control voltage terminal VB1;

[0118] A first end of the third energy storage circuit 21 is electrically connected to the first node N1 , a second end of the third energy storage circuit 21 is electrically connected to the power supply voltage terminal VDD, and the third energy storage circuit 21 is used to store electrical energy.

[0119] In at least one embodiment of the pixel circuit shown in FIG. 2 , the second control voltage terminal is a power voltage terminal VDD.

[0120] In at least one embodiment of the pixel circuit shown in Figure 2, the second end of the third energy storage circuit 21 can be replaced by being electrically connected to the reference voltage end or the initial voltage end, that is, the second control voltage end can be the reference voltage end or the initial voltage end, but is not limited to this.

[0121] In a specific implementation, when the first control voltage terminal is a DC voltage terminal, the pixel circuit may further include a third energy storage circuit, and the third energy storage circuit may be electrically connected to the first node and the second control voltage terminal, respectively. The second control voltage terminal may provide different control voltages in different time periods. In the bias stage, a corresponding control voltage may be provided through the second control voltage terminal to change the gate-source voltage of the driving transistor in the driving circuit to improve the hysteresis phenomenon of the driving transistor.

[0122] As shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG1 ,

[0123] A first terminal of the second energy storage circuit 12 is electrically connected to the third node N3, and a second terminal of the second energy storage circuit 12 is electrically connected to the first control voltage terminal VB1;

[0124] The first control voltage terminal VB1 is used to provide a DC voltage signal;

[0125] A first end of the third energy storage circuit 21 is electrically connected to the first node N1 , a second end of the third energy storage circuit 21 is electrically connected to the second control voltage terminal VB2 , and the third energy storage circuit 21 is used to store electrical energy.

[0126] In a specific implementation, when at least one embodiment of the pixel circuit shown in Figure 3 is in operation, in the bias stage, the second control voltage terminal VB2 can provide a fourth control voltage, and in other time periods other than the bias stage, the second control voltage terminal VB2 can provide a third control voltage. In the bias stage, the gate-source voltage of the driving transistor in the driving circuit can be changed by changing the voltage value of the voltage signal provided by the second control voltage terminal VB2 to improve the hysteresis phenomenon of the driving transistor.

[0127] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit;

[0128] The data writing circuit is electrically connected to the scanning end, the data line and the first node respectively. The data writing circuit is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end.

[0129] In a specific implementation, the pixel circuit may further include a data writing circuit, and the data writing circuit writes the data voltage into the first node under the control of the scanning signal.

[0130] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 41 ;

[0131] The data writing circuit 41 is electrically connected to the scan terminal GT, the data line DT and the first node N1 respectively. The data writing circuit 41 is used to write the data voltage Vdata provided by the data line DT into the first node N1 under the control of the scan signal provided by the scan terminal GT.

[0132] When at least one embodiment of the pixel circuit shown in FIG4 of the present disclosure is in operation, in the compensation stage, the first reset control circuit writes the reference voltage to the first node under the control of the first reset control signal; in the data writing stage, the data writing circuit writes the data voltage provided by the data line to the first node under the control of the scan signal; the embodiment of the present disclosure can separate the threshold voltage compensation from the data writing time, improve the threshold voltage compensation effect, and can support compensation of depletion-type devices.

[0133] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG2 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 41 ;

[0134] The data writing circuit 41 is electrically connected to the scan terminal GT, the data line DT and the first node N1 respectively. The data writing circuit 41 is used to write the data voltage Vdata provided by the data line DT into the first node N1 under the control of the scan signal provided by the scan terminal GT.

[0135] When at least one embodiment of the pixel circuit shown in Figure 5 of the present disclosure is in operation, in the compensation stage, the first reset control circuit writes the reference voltage to the first node under the control of the first reset control signal; in the data writing stage, the data writing circuit writes the data voltage provided by the data line to the first node under the control of the scan signal; the embodiment of the present disclosure can separate the threshold voltage compensation from the data writing time, improve the threshold voltage compensation effect, and can support compensation of depletion-type devices.

[0136] As shown in FIG6 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 41 ;

[0137] The data writing circuit 41 is electrically connected to the scan terminal GT, the data line DT and the first node N1 respectively. The data writing circuit 41 is used to write the data voltage Vdata provided by the data line DT into the first node N1 under the control of the scan signal provided by the scan terminal GT.

[0138] When at least one embodiment of the pixel circuit shown in Figure 6 of the present disclosure is in operation, in the compensation stage, the first reset control circuit writes the reference voltage to the first node under the control of the first reset control signal; in the data writing stage, the data writing circuit writes the data voltage provided by the data line to the first node under the control of the scan signal; the embodiment of the present disclosure can separate the threshold voltage compensation from the data writing time, improve the threshold voltage compensation effect, and can support compensation of depletion-type devices.

[0139] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit and a second light emitting control circuit;

[0140] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of a first light-emitting control signal provided by the first light-emitting control terminal;

[0141] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node and the first pole of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal.

[0142] In a specific implementation, the pixel circuit may further include a first light emitting control circuit and a second light emitting control circuit; the first light emitting control circuit and the second light emitting control circuit are used for light emitting control.

[0143] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG4 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit 71 and a second light emitting control circuit 72 ;

[0144] The first light emitting control circuit 71 is electrically connected to the first light emitting control terminal EM1, the power supply voltage terminal VDD, and the second node N2, respectively, and is configured to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of a first light emitting control signal provided by the first light emitting control terminal EM1;

[0145] The second light-emitting control circuit 72 is electrically connected to the second light-emitting control terminal EM2, the third node N3 and the first electrode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0146] In at least one embodiment of the pixel circuit shown in Figure 7 of the present disclosure, in the compensation stage, the first light-emitting control circuit 71 controls the connection between the power supply voltage terminal VDD and the second node N2 under the control of the first light-emitting control signal; in the light-emitting stage, the first light-emitting control circuit 71 controls the connection between the power supply voltage terminal VDD and the second node N2 under the control of the first light-emitting control signal; and the second light-emitting control circuit 72 controls the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal.

[0147] As shown in FIG8 , based on at least one embodiment of the pixel circuit shown in FIG5 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit 71 and a second light emitting control circuit 72 ;

[0148] The first light emitting control circuit 71 is electrically connected to the first light emitting control terminal EM1, the power supply voltage terminal VDD, and the second node N2, respectively, and is configured to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of a first light emitting control signal provided by the first light emitting control terminal EM1;

[0149] The second light-emitting control circuit 72 is electrically connected to the second light-emitting control terminal EM2, the third node N3 and the first electrode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0150] In at least one embodiment of the pixel circuit shown in Figure 8 of the present disclosure, in the compensation stage, the first light-emitting control circuit 71 controls the connection between the power supply voltage terminal VDD and the second node N2 under the control of the first light-emitting control signal; in the light-emitting stage, the first light-emitting control circuit 71 controls the connection between the power supply voltage terminal VDD and the second node N2 under the control of the first light-emitting control signal; and the second light-emitting control circuit 72 controls the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal.

[0151] As shown in FIG9 , based on at least one embodiment of the pixel circuit shown in FIG6 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit 71 and a second light emitting control circuit 72 ;

[0152] The first light emitting control circuit 71 is electrically connected to the first light emitting control terminal EM1, the power supply voltage terminal VDD, and the second node N2, respectively, and is configured to control the connection or disconnection between the power supply voltage terminal VDD and the second node N2 under the control of a first light emitting control signal provided by the first light emitting control terminal EM1;

[0153] The second light-emitting control circuit 72 is electrically connected to the second light-emitting control terminal EM2, the third node N3 and the first electrode of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first electrode of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0154] In at least one embodiment of the pixel circuit shown in Figure 9 of the present disclosure, in the compensation stage, the first light-emitting control circuit 71 controls the connection between the power supply voltage terminal VDD and the second node N2 under the control of the first light-emitting control signal; in the light-emitting stage, the first light-emitting control circuit 71 controls the connection between the power supply voltage terminal VDD and the second node N2 under the control of the first light-emitting control signal; and the second light-emitting control circuit 72 controls the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal.

[0155] The pixel circuit according to at least one embodiment of the present disclosure further includes a second reset control circuit;

[0156] The second reset control circuit is electrically connected to the second reset control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0157] In a specific implementation, the pixel circuit may further include a second reset control circuit, which, under the control of a second reset control signal, writes the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element.

[0158] As shown in FIG10 , based on at least one embodiment of the pixel circuit shown in FIG7 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset control circuit 101 ;

[0159] The second reset control circuit 101 is electrically connected to the second reset control terminal R2, the initial voltage terminal I1 and the first electrode of the light-emitting element E1, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0160] When at least one embodiment of the pixel circuit shown in Figure 10 of the present disclosure is in operation, in the initialization stage, the second reset control circuit 101, under the control of the second reset control signal provided by the second reset control terminal R2, writes the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1, thereby clearing the residual charge in the first electrode of the light-emitting element E1; and the second light-emitting control circuit 72, under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2, controls the connection between the third node N3 and the first electrode of the light-emitting element E1, thereby writing the initial voltage Vinit into the third node, thereby initializing the potential of the third node.

[0161] As shown in FIG11 , based on at least one embodiment of the pixel circuit shown in FIG8 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset control circuit 101 ;

[0162] The second reset control circuit 101 is electrically connected to the second reset control terminal R2, the initial voltage terminal I1 and the first electrode of the light-emitting element E1, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0163] When at least one embodiment of the pixel circuit shown in Figure 11 of the present disclosure is in operation, in the initialization stage, the second reset control circuit 101, under the control of the second reset control signal provided by the second reset control terminal R2, writes the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1, thereby clearing the residual charge in the first electrode of the light-emitting element E1; and the second light-emitting control circuit 72, under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2, controls the connection between the third node N3 and the first electrode of the light-emitting element E1, thereby writing the initial voltage Vinit into the third node, thereby initializing the potential of the third node.

[0164] As shown in FIG12 , based on at least one embodiment of the pixel circuit shown in FIG9 , the pixel circuit according to at least one embodiment of the present disclosure further includes a second reset control circuit 101 ;

[0165] The second reset control circuit 101 is electrically connected to the second reset control terminal R2, the initial voltage terminal I1 and the first electrode of the light-emitting element E1, respectively, and is used to write the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0166] When at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure is in operation, in the initialization stage, the second reset control circuit 101, under the control of the second reset control signal provided by the second reset control terminal R2, writes the initial voltage Vinit provided by the initial voltage terminal I1 into the first electrode of the light-emitting element E1, thereby clearing the residual charge in the first electrode of the light-emitting element E1; and the second light-emitting control circuit 72, under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2, controls the connection between the third node N3 and the first electrode of the light-emitting element E1, thereby writing the initial voltage Vinit into the third node, thereby initializing the potential of the third node.

[0167] Optionally, the driving circuit includes a driving transistor, the first reset control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0168] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0169] The gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0170] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node;

[0171] A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the first control voltage end.

[0172] Optionally, the third energy storage circuit includes a third capacitor;

[0173] A first end of the third capacitor is electrically connected to the first node, and a second end of the third capacitor is electrically connected to a DC voltage terminal.

[0174] Optionally, the third energy storage circuit includes a third capacitor;

[0175] A first terminal of the third capacitor is electrically connected to the first node, and a second terminal of the third capacitor is electrically connected to the second control voltage terminal.

[0176] Optionally, the data writing circuit includes a second transistor;

[0177] A gate of the second transistor is electrically connected to the scan end, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the first node.

[0178] Optionally, the first light emitting control circuit includes a third transistor, and the second light emitting control circuit includes a fourth transistor;

[0179] The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the second node;

[0180] The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

[0181] Optionally, the second reset control circuit includes a fifth transistor;

[0182] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light emitting element.

[0183] At least one embodiment of the pixel circuit shown in FIG13 of the present disclosure may include an organic light emitting diode O1, a driving transistor TD, a first transistor T1, a first capacitor C1, a second capacitor C2, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5;

[0184] The gate of the driving transistor TD is electrically connected to the first node N1, the drain of the driving transistor TD is electrically connected to the second node N2, and the source of the driving transistor TD is electrically connected to the third node N3;

[0185] The gate of the first transistor T1 is electrically connected to the first reset control terminal R1, the drain of the first transistor T1 is electrically connected to the reference voltage terminal REF, and the source of the first transistor T1 is electrically connected to the first node N1; the reference voltage terminal REF is used to provide a reference voltage Vref;

[0186] A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3;

[0187] A first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the first control voltage terminal VB1;

[0188] The gate of the second transistor T2 is electrically connected to the scanning terminal GT, the drain of the second transistor T2 is electrically connected to the data line DT, and the source of the second transistor T2 is electrically connected to the first node N1;

[0189] The gate of the third transistor T3 is electrically connected to the first light emitting control terminal EM1, the drain of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the source of the third transistor T3 is electrically connected to the second node N2;

[0190] The gate of the fourth transistor T4 is electrically connected to the second emission control terminal EM2, the drain of the fourth transistor T4 is electrically connected to the third node N3, the source of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0191] The gate of the fifth transistor T5 is electrically connected to the second reset control terminal R2, the drain of the fifth transistor T5 is electrically connected to the initial voltage terminal I1, and the source of the fifth transistor T5 is electrically connected to the anode of the organic light emitting diode O1; the initial voltage terminal I1 is used to provide an initial voltage Vinit.

[0192] In at least one embodiment of the pixel circuit shown in FIG13 , all transistors are n-type transistors, and TD is a depletion-type transistor.

[0193] In at least one embodiment of the pixel circuit shown in FIG13 , the first control voltage terminal VB1 is used to provide a first control voltage, and the first control voltage terminal VB1 is used to provide a DC voltage signal.

[0194] In at least one embodiment of the pixel circuit shown in Figure 13, the light-emitting element is an organic light-emitting diode O1, the driving circuit includes a driving transistor TD, the first reset control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a second capacitor C2, and the data writing circuit includes a second transistor T2; the first light-emitting control circuit includes a third transistor T3, the second light-emitting control circuit includes a fourth transistor T4; and the second reset control circuit includes a fifth transistor T5.

[0195] As shown in FIG14 , when at least one embodiment of the pixel circuit shown in FIG13 is in operation, a display cycle may include a refresh frame, wherein the refresh frame includes a refresh period TS, and the refresh period TS includes an initialization phase S1, a compensation phase S2, a data writing phase S3, and a light emitting phase S5, which are sequentially arranged.

[0196] In the initialization phase S1, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R2 provides a high voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, T5 is turned on, T1 is turned on, REF provides a reference voltage Vref to the first node N1, I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1; T4 is turned on, I1 provides an initial voltage Vinit to the third node N3, so that TD can be turned on when the compensation phase S2 begins;

[0197] In the compensation phase S2, EM1 provides a high voltage signal, EM2 provides a low voltage signal, R2 provides a low voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, T3 is turned on, T1 is turned on, and REF provides a reference voltage Vref to the first node N1;

[0198] At the beginning of compensation phase S2, TD can be turned on to charge C1 and C2, changing the potential of N3 until the potential of N3 becomes Vref-Vth, and TD is turned off, where Vth is the threshold voltage of TD.

[0199] In the data writing phase S3, EM1 provides a low voltage signal, EM2 provides a low voltage signal, R2 and R1 both provide low voltage signals, GT provides a high voltage signal, T2 is turned on, and DT provides a data voltage Vdata to the first node N1; the potential of N3 becomes Vref-Vth+C1z×(Vdata-Vref) / (C1z+C2z); where C1z is the capacitance value of C1, and C2z is the capacitance value of C2;

[0200] In the light-emitting stage S5, EM1 and EM2 provide high voltage signals, T3 and T4 are turned on, TD drives O1 to emit light, and Id is equal to 0.5K×(C2z×(Vdata-Vref)) 2 / (C1z+C2z) 2 ; Wherein, K is the current coefficient of TD, and Id is the driving current generated by TD.

[0201] When working, at least one embodiment of the pixel circuit shown in Figure 13 of the present disclosure resets the gate of the driving transistor TD and the source of the driving transistor TD, detects the threshold voltage at the source of the driving transistor TD, and separates the data voltage writing time and the compensation time, thereby improving the threshold voltage compensation effect and supporting compensation of depletion-type devices.

[0202] During specific implementation, the threshold voltage drift of the depletion-mode transistor may be relatively serious. At least one embodiment of the present disclosure can support compensation of the threshold voltage of the depletion-mode drive transistor.

[0203] When at least one embodiment of the pixel circuit shown in FIG13 of the present disclosure is in operation, the display cycle may further include at least two hold frames arranged after the refresh frame, and the hold frames may include a hold initialization phase and a hold light emission phase;

[0204] In the initialization stage, T1, T2, T3, and T4 are turned off, T5 is turned on, and I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1;

[0205] During the light-maintaining stage, T3 and T4 are turned on, and TD drives O1 to emit light.

[0206] In a specific implementation, the refresh frame may further include a holding period arranged after the refresh period, and the holding period may include a holding initialization phase and a holding light-emitting phase arranged successively.

[0207] As shown in FIG14 , the refresh frame includes a holding period marked TK and is provided after the refresh period TS.

[0208] The phase marked SK1 is for initialization, and the phase marked SK3 is for light emission.

[0209] TK includes SK1 and SK3 which are set successively.

[0210] As shown in Figure 14,

[0211] In the initialization phase SK1, R2 provides a high voltage signal, T5 is turned on, and I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1;

[0212] In the light-maintaining stage SK3, EM1 and EM2 provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light.

[0213] As shown in FIG15 , based on at least one embodiment of the pixel circuit shown in FIG11 , the light emitting element is an organic light emitting diode O1;

[0214] The driving circuit includes a driving transistor TD, the first reset control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0215] The gate of the driving transistor TD is electrically connected to the first node N1, the drain of the driving transistor TD is electrically connected to the second node N2, and the source of the driving transistor TD is electrically connected to the third node N3;

[0216] The gate of the first transistor T1 is electrically connected to the first reset control terminal R1, the drain of the first transistor T1 is electrically connected to the reference voltage terminal REF, and the source of the first transistor T1 is electrically connected to the first node N1; the reference voltage terminal REF is used to provide a reference voltage Vref;

[0217] A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3;

[0218] A first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the first control voltage terminal VB1;

[0219] The third energy storage circuit includes a third capacitor C3;

[0220] A first end of the third capacitor C3 is electrically connected to the first node N1, and a second end of the third capacitor C3 is electrically connected to the power supply voltage terminal VDD;

[0221] The data writing circuit includes a second transistor T2;

[0222] The gate of the second transistor T2 is electrically connected to the scanning terminal GT, the drain of the second transistor T2 is electrically connected to the data line DT, and the source of the second transistor T2 is electrically connected to the first node N1;

[0223] The first light emitting control circuit includes a third transistor T3, and the second light emitting control circuit includes a fourth transistor T4;

[0224] The gate of the third transistor T3 is electrically connected to the first light emitting control terminal EM1, the drain of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the source of the third transistor T3 is electrically connected to the second node N2;

[0225] The gate of the fourth transistor T4 is electrically connected to the second emission control terminal EM2, the drain of the fourth transistor T4 is electrically connected to the third node N3, the source of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0226] The second reset control circuit includes a fifth transistor T5;

[0227] The gate of the fifth transistor T5 is electrically connected to the second reset control terminal R2, the drain of the fifth transistor T5 is electrically connected to the initial voltage terminal I1, and the source of the fifth transistor T5 is electrically connected to the anode of the organic light emitting diode O1; the initial voltage terminal I1 is used to provide an initial voltage Vinit.

[0228] In at least one embodiment of the pixel circuit shown in FIG. 15 , all transistors are n-type transistors, and TD is a depletion-type transistor.

[0229] In at least one embodiment of the pixel circuit shown in Figure 15 of the present disclosure, in the initialization stage, the compensation stage, the data writing stage and the light-emitting stage, the first control voltage terminal VB1 provides a first control voltage, and in the bias stage, the first control voltage terminal VB1 provides a second control voltage, and the first control voltage is different from the second control voltage.

[0230] During specific implementation, according to actual conditions, the first control voltage may be greater than the second control voltage, or the first control voltage may be less than the second control voltage.

[0231] As shown in FIG16 , when at least one embodiment of the pixel circuit shown in FIG15 of the present disclosure is in operation, a display cycle may include a refresh frame, wherein the refresh frame includes a refresh period TS, and the refresh period TS may include an initialization phase S1, a compensation phase S2, a data writing phase S3, a bias phase S4, and a light emitting phase S5, which are sequentially arranged.

[0232] In the initialization phase S1, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R2 provides a high voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, T5 is turned on, T1 is turned on, REF provides a reference voltage Vref to the first node N1, I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1; T4 is turned on, I1 provides an initial voltage Vinit to the third node N3, so that TD can be turned on when the compensation phase S2 begins; VB1 provides a first control voltage Vb1;

[0233] In the compensation phase S2, EM1 provides a high voltage signal, EM2 provides a low voltage signal, R2 provides a low voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, T3 is turned on, T1 is turned on, REF provides a reference voltage Vref to the first node N1; VB1 provides a first control voltage Vb1;

[0234] At the beginning of compensation phase S2, TD can be turned on to charge C1 and C2, changing the potential of N3 until the potential of N3 becomes Vref-Vth, and TD is turned off, where Vth is the threshold voltage of TD.

[0235] In the data writing phase S3, EM1 provides a low voltage signal, EM2 provides a low voltage signal, R2 and R1 both provide low voltage signals, GT provides a high voltage signal, T2 is turned on, and DT provides a data voltage Vdata to the first node N1; the potential of N3 becomes Vref-Vth+C1z×(Vdata-Vref) / (C1z+C2z); where C1z is the capacitance value of C1, and C2z is the capacitance value of C2; VB1 provides the first control voltage Vb1;

[0236] In bias phase S4, no transistor is turned on, the potential of N3 is Vref-Vref+C1z×(Vdata-Vref) / (C1z+C2z)+C1z×ΔV / (C1z+C2z), and the potential of N1 is Vdata+C1z×C2z×ΔV / ((C1z+C3z)×(C1z+C2z)); where ΔV is equal to Vb2-Vb1;

[0237] In the light-emitting stage S5, EM1 and EM2 provide high voltage signals, T3 and T4 are turned on, TD drives O1 to emit light, and Id is equal to 0.5K×(C2z×(Vdata-Vref)) 2 / (C1z+C2z) 2 ; Wherein, K is the current coefficient of TD, Id is the driving current generated by TD; VB1 provides a first control voltage Vb1.

[0238] As shown in FIG. 16 , Vb2 is greater than Vb1 , but the present invention is not limited thereto; in a specific implementation, Vb2 may also be less than Vb1 .

[0239] As shown in FIG. 16 , the biasing stage S4 is provided between the data writing stage S3 and the light emitting stage S5 .

[0240] In at least one embodiment of the present disclosure, the bias stage S4 can be changed to be set before the initialization stage S1; or, the bias stage S4 can be changed to be set between the initialization stage S1 and the compensation stage S2; or, the bias stage S4 can be changed to be set between the compensation stage S2 and the data writing stage S3.

[0241] In at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure, when in operation, a display cycle may include at least one hold frame arranged after the refresh frame; the hold frame may include a hold initialization phase, a hold bias phase, and a hold light emission phase;

[0242] In the initialization stage, T1, T2, T3, and T4 are turned off, T5 is turned on, and I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1;

[0243] During a time period of the holding frame except the holding bias phase, VB1 provides a first control voltage Vb1;

[0244] In the bias holding phase, VB1 provides a second control voltage Vb2, which puts TD in a stress bias state to restore the threshold voltage of TD and improve the hysteresis of TD.

[0245] During the light-maintaining stage, T3 and T4 are turned on, and TD drives O1 to emit light.

[0246] In a specific implementation, the refresh frame may further include at least one holding period arranged after the refresh period; the holding period may include a holding initialization phase, a holding bias phase, and a holding light-emitting phase.

[0247] As shown in FIG16 , the refresh frame includes a holding period marked TK and is provided after the refresh period TS.

[0248] The phase labeled SK1 is the initialization phase, the phase labeled SK2 is the bias phase, and the phase labeled SK3 is the light-emitting phase.

[0249] TK includes SK1, SK2 and SK3 which are set up in sequence.

[0250] In at least one embodiment shown in FIG. 16 , SK1 is disposed in front of SK2 . In a specific implementation, the positions of SK1 and SK2 may also be interchanged.

[0251] As shown in FIG16 , in the initialization phase SK1 , R2 provides a high voltage signal, T5 is turned on, and I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1 ;

[0252] During the holding period TK except the holding bias phase SK2, VB1 provides the first control voltage Vb1;

[0253] In the bias holding phase SK2, VB1 provides a second control voltage Vb2, so that TD is in a stress bias state, which is used to restore the threshold voltage of TD and improve the hysteresis of TD;

[0254] In the light-maintaining stage SK3, EM1 and EM2 provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light.

[0255] As shown in FIG17 , based on at least one embodiment of the pixel circuit shown in FIG12 ,

[0256] The driving circuit includes a driving transistor TD, the first reset control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0257] The gate of the driving transistor TD is electrically connected to the first node N1, the drain of the driving transistor TD is electrically connected to the second node N2, and the source of the driving transistor TD is electrically connected to the third node N3;

[0258] The gate of the first transistor T1 is electrically connected to the first reset control terminal R1, the drain of the first transistor T1 is electrically connected to the reference voltage terminal REF, and the source of the first transistor T1 is electrically connected to the first node N1; the reference voltage terminal REF is used to provide a reference voltage Vref;

[0259] A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the third node N3;

[0260] A first end of the second capacitor C2 is electrically connected to the third node N3, and a second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD;

[0261] The third energy storage circuit includes a third capacitor C3;

[0262] A first end of C3 is electrically connected to the first node N1, and a second end of C3 is electrically connected to the second control voltage terminal VB2;

[0263] The data writing circuit includes a second transistor T2;

[0264] The gate of the second transistor T2 is electrically connected to the scanning terminal GT, the drain of the second transistor T2 is electrically connected to the data line DT, and the source of the second transistor T2 is electrically connected to the first node N1;

[0265] The first light emitting control circuit includes a third transistor T3, and the second light emitting control circuit includes a fourth transistor T4;

[0266] The gate of the third transistor T3 is electrically connected to the first light emitting control terminal EM1, the drain of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the source of the third transistor T3 is electrically connected to the second node N2;

[0267] The gate of the fourth transistor T4 is electrically connected to the second emission control terminal EM2, the drain of the fourth transistor T4 is electrically connected to the third node N3, the source of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0268] The second reset control circuit includes a fifth transistor T5;

[0269] The gate of the fifth transistor T5 is electrically connected to the second reset control terminal R2, the drain of the fifth transistor T5 is electrically connected to the initial voltage terminal I1, and the source of the fifth transistor T5 is electrically connected to the anode of the organic light emitting diode O1; the initial voltage terminal I1 is used to provide an initial voltage Vinit.

[0270] In at least one embodiment of the pixel circuit shown in FIG17 , all transistors are n-type transistors, and TD is a depletion-type transistor.

[0271] As shown in FIG18 , when at least one embodiment of the pixel circuit shown in FIG17 is in operation, a display cycle may include a refresh frame, wherein the refresh frame includes a refresh period TS, and the refresh period TS may include an initialization phase S1, a compensation phase S2, a data writing phase S3, a bias phase S4, and a light emitting phase S5, which are sequentially arranged.

[0272] In the initialization phase S1, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R2 provides a high voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, VB2 provides a third control voltage Vb3, T5 is turned on, I1 provides an initial voltage Vinit1 to the anode of O1, T4 is turned on to provide Vinit1 to the third node N3; T1 is turned on, and REF provides a reference voltage Vref to the first node N1; so that TD can be turned on when the compensation phase S2 begins;

[0273] In the compensation phase S2, EM1 provides a high voltage signal, EM2 provides a low voltage signal, R2 provides a low voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, T3 is turned on, N2 is connected to VDD, T1 is turned on, REF writes Vref to the first node N1; VB2 provides a third control voltage Vb3;

[0274] At the beginning of compensation phase S2, TD is turned on to charge the capacitor to change the potential of N3 until the potential of N3 becomes Vref-Vth, and TD is turned off; Vth is the threshold voltage of TD;

[0275] In the data writing phase S3, EM1 and EM2 provide low voltage signals, R2 provides a low voltage signal, R1 provides a low voltage signal, GT provides a high voltage signal, T2 is turned on, and DT provides a data voltage Vdata to the first node N1; the potential of N2 is Vref+Vth+C1z×(Vdata-Vref) / (C1z+C2z); where C1z is the capacitance value of C1, and C2z is the capacitance value of C2; VB2 provides a third control voltage Vb3;

[0276] In bias phase S4, EM1, EM2, R2, R1, and GT provide low voltage signals, VB2 provides a fourth control voltage Vb4, and the potential of N1 is Vdata + C3z × ΔV / (C1z + C3z). The potential of N3 is Vref - Vth + C1z × (Vdata - Vref) / (C1z + C2z) + C1z × C3z × ΔV / (C1z + C3z), where C3z is the capacitance of C3, and ΔV is Vb4 - Vb3.

[0277] In the bias phase S4, the gate-source voltage of TD is controlled to put TD in a stress bias state, thereby restoring the threshold voltage of TD and improving the hysteresis phenomenon of TD.

[0278] In the light-emitting phase S5, EM1 and EM2 provide high voltage signals, T3 and T4 are both turned on, and TD drives O1 to emit light; VB2 provides the third control voltage Vb3; Id is equal to 0.5K×(C2z×(Vdata-Vref)). 2 / (C1z+C2z) 2 ; Wherein, K is the current coefficient of TD, and Id is the driving current generated by TD.

[0279] As shown in FIG. 18 , Vb4 is smaller than Vb3 , but the present invention is not limited thereto; in a specific implementation, Vb4 may be larger than Vb3 .

[0280] When at least one embodiment of the pixel circuit shown in FIG17 is in operation, the display period may include at least one hold frame arranged after the refresh frame, and the hold frame may include a hold initialization phase, a hold bias phase, and a hold light emission phase;

[0281] During the initialization phase, T5 is turned on and I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1.

[0282] During other time periods of the holding frame except the holding bias phase, VB2 provides a third control voltage Vb3;

[0283] In the bias holding phase, VB2 provides a fourth control voltage Vb4 to change the gate-source voltage of TD and improve the hysteresis phenomenon of TD;

[0284] During the light-maintaining stage, T3 and T4 are turned on, and TD drives O1 to emit light.

[0285] In a specific implementation, the refresh frame may include at least one holding period arranged after the refresh period, and the holding period may include a holding initialization phase, a holding bias phase, and a holding light-emitting phase arranged in sequence.

[0286] As shown in FIG18 , the refresh frame includes a holding period marked TK and is provided after the refresh period TS.

[0287] The phase labeled SK1 is the initialization phase, the phase labeled SK2 is the bias phase, and the phase labeled SK3 is the light-emitting phase.

[0288] TK includes SK1, SK2 and SK3 which are set up in sequence.

[0289] In at least one embodiment shown in FIG. 18 , SK1 is disposed in front of SK2 . In a specific implementation, the positions of SK1 and SK2 may also be interchanged.

[0290] As shown in Figure 18,

[0291] In the initialization phase SK1, R2 provides a high voltage signal, T5 is turned on, and I1 provides an initial voltage Vinit to the anode of O1 to clear the residual charge on the anode of O1;

[0292] During other time periods included in the holding time period TK except the holding bias phase SK2, VB2 provides a third control voltage Vb3;

[0293] In the bias holding phase SK2, VB2 provides a fourth control voltage Vb4 to change the gate-source voltage of TD and improve the hysteresis phenomenon of TD;

[0294] In the light-maintaining stage SK3, EM1 and EM2 provide high voltage signals, T3 and T4 are turned on, and TD drives O1 to emit light.

[0295] The difference between at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure is that:

[0296] C3 is not included.

[0297] As shown in FIG20 , during operation, at least one embodiment of the pixel circuit shown in FIG19 of the present disclosure may include a refresh frame in a display cycle. The refresh frame may include a refresh period TS. The refresh period TS includes an initialization phase S1, a compensation phase S2, a data writing phase S3, and a light emitting phase S5, which are sequentially arranged.

[0298] In the initialization phase S1, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R2 provides a high voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, T5 is turned on, I1 provides an initial voltage Vinit1 to the anode of O1, T4 is turned on to provide Vinit1 to the third node N3; T1 is turned on, REF provides a reference voltage Vref to the first node N1; so that TD can be turned on when the compensation phase S2 begins;

[0299] In the compensation phase S2, EM1 provides a high voltage signal, EM2 provides a low voltage signal, R2 provides a low voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, T3 is turned on, N2 is connected to VDD, T1 is turned on, and REF writes Vref to the first node N1;

[0300] At the beginning of compensation phase S2, TD is turned on to charge the capacitor to change the potential of N3 until the potential of N3 becomes Vref-Vth, and TD is turned off; Vth is the threshold voltage of TD;

[0301] In the data writing phase S3, EM1 and EM2 provide low voltage signals, R2 provides a low voltage signal, R1 provides a low voltage signal, GT provides a high voltage signal, T2 is turned on, and DT provides a data voltage Vdata to the first node N1; the potential of N2 is Vref+Vth+C1z×(Vdata-Vref) / (C1z+C2z); where C1z is the capacitance value of C1, and C2z is the capacitance value of C2;

[0302] In the light-emitting stage S5, EM1 and EM2 provide high voltage signals, T3 and T4 are both turned on, and TD drives O1 to emit light.

[0303] In at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure, when in operation, the display period may include at least one hold frame arranged after the refresh frame, and the hold frame may include a hold initialization phase and a hold light emission phase arranged in sequence;

[0304] In the initialization stage, EM1 provides a low voltage signal, EM2 provides a low voltage signal, R2 provides a high voltage signal, R1 provides a low voltage signal, GT provides a low voltage signal, T5 is turned on, and I1 provides an initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1;

[0305] In the light-maintaining stage, EM1 and EM2 provide high voltage signals, T3 and T4 are both turned on, and TD drives O1 to emit light.

[0306] In a specific implementation, the refresh frame may include at least one holding time period arranged after the refresh time period, and the holding time period may include a holding initialization phase and a holding light-emitting phase arranged successively.

[0307] As shown in FIG20 , the refresh frame includes a holding period marked TK and is provided after the refresh period TS.

[0308] The phase marked SK1 is for initialization, and the phase marked SK3 is for light emission.

[0309] TK includes SK1 and SK3 which are set successively.

[0310] As shown in Figure 20,

[0311] In the initialization phase SK1, R2 provides a high voltage signal, T5 is turned on, and I1 provides an initial voltage Vinit1 to the anode of O1 to clear the residual charge on the anode of O1;

[0312] In the light-maintaining stage SK3, EM1 and EM2 provide high voltage signals, T3 and T4 are both turned on, and TD drives O1 to emit light.

[0313] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:

[0314] The driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node;

[0315] The first reset control circuit writes a reference voltage into the first node under the control of a first reset control signal.

[0316] In at least one embodiment of the present disclosure, the pixel circuit further includes a first light-emitting control circuit and a second light-emitting control circuit; the display cycle includes a refresh frame; the refresh frame includes a refresh time period, and the refresh time period is sequentially provided with a compensation phase, a data writing phase, and a light-emitting phase;

[0317] The driving method includes:

[0318] During the compensation phase, the first reset control circuit writes a reference voltage into the first node under the control of a first reset control signal; and the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal.

[0319] In the data writing phase, the data writing circuit writes the data voltage provided by the data line into the first node under the control of the scan signal;

[0320] In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0321] In at least one embodiment of the present disclosure, the pixel circuit further includes a third energy storage circuit; a first end of the third energy storage circuit is electrically connected to the first node, a second end of the third energy storage circuit is electrically connected to a DC voltage terminal, and the third energy storage circuit is used to store electrical energy; the refresh period further includes a bias phase provided between the data writing phase and the light emitting phase;

[0322] The driving method further includes:

[0323] In the compensation phase, the data writing phase and the light emitting phase, the first control voltage terminal is used to provide a first control voltage;

[0324] During the bias phase, the first control voltage terminal provides a second control voltage;

[0325] The first control voltage is different from the second control voltage.

[0326] In at least one embodiment of the present disclosure, the display period further includes at least one hold frame provided after the refresh frame; the hold frame includes a hold bias phase and a hold light emitting phase provided in sequence; and the driving method further includes:

[0327] In the bias holding phase, the first control voltage terminal provides a second control voltage;

[0328] During a time period of the holding frame except the holding bias phase, the first control voltage terminal provides a first control voltage;

[0329] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0330] In at least one embodiment of the present disclosure, the refresh frame further includes at least one hold period arranged after the refresh period; the hold period includes a hold bias phase and a hold light phase arranged in sequence; and the driving method further includes:

[0331] In the bias holding phase, the first control voltage terminal provides a second control voltage;

[0332] During a time period included in the holding time period except the holding bias phase, the first control voltage terminal provides a first control voltage;

[0333] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0334] In at least one embodiment of the present disclosure, the first control voltage terminal may be a DC voltage terminal; the pixel circuit further includes a third energy storage circuit; a first terminal of the third energy storage circuit is electrically connected to the first node, a second terminal of the third energy storage circuit is electrically connected to the second control voltage terminal, and the third energy storage circuit is used to store electrical energy;

[0335] The refresh period also includes a bias phase arranged between the data writing phase and the light emitting phase;

[0336] The driving method further includes:

[0337] In the compensation phase, the data writing phase and the light emitting phase, the second control voltage terminal is used to provide a third control voltage;

[0338] In the bias phase, the second control voltage terminal provides a fourth control voltage;

[0339] The third control voltage is different from the fourth control voltage.

[0340] In at least one embodiment of the present disclosure, the display period further includes at least one hold frame provided after the refresh frame; the hold frame includes a hold bias phase and a hold light emitting phase provided in sequence; and the driving method further includes:

[0341] In the bias holding phase, the second control voltage terminal provides a fourth control voltage;

[0342] During a time period of the holding frame except the holding bias phase, the second control voltage terminal provides a third control voltage;

[0343] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0344] In at least one embodiment of the present disclosure, the refresh frame further includes at least one hold period arranged after the refresh period; the hold period includes a hold bias phase and a hold light phase arranged in sequence; and the driving method further includes:

[0345] In the bias holding phase, the second control voltage terminal provides a fourth control voltage;

[0346] During a time period included in the holding time period except the holding bias phase, the second control voltage terminal provides a third control voltage;

[0347] In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0348] In at least one embodiment of the present disclosure, the refresh period further includes an initialization phase provided before the compensation phase; the pixel circuit further includes a second reset control circuit;

[0349] The driving method further includes:

[0350] During the initialization phase, the second reset control circuit writes the initial voltage to the first electrode of the light-emitting element under the control of the second reset control signal; and the second light-emitting control circuit controls the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal. The display device described in the embodiment of the present disclosure includes the above-mentioned display device.

[0351] In at least one embodiment of the present disclosure, the bias stage is set before the initialization stage; or, the bias stage is set between the initialization stage and the compensation stage; or, the bias stage is set between the compensation stage and the data writing stage; or, the bias stage is set between the data writing stage and the light emitting stage.

[0352] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0353] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit comprising a light-emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, a third energy storage circuit, and a first reset control circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the light-emitting element via a third node; the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of the first node; The first reset control circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the first node respectively, and is configured to write the reference voltage provided by the reference voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal; A first end of the first energy storage circuit is electrically connected to the first node, a second end of the first energy storage circuit is electrically connected to the third node, and the first energy storage circuit is used to store electrical energy; The second energy storage circuit is electrically connected to the third node, and the second energy storage circuit is used to store electrical energy; The third energy storage circuit is electrically connected to the first node, and the third energy storage circuit is used to store electrical energy.

2. The pixel circuit according to claim 1, wherein: The first end of the second energy storage circuit is electrically connected to the third node, and the second end of the second energy storage circuit is electrically connected to the first control voltage end; The first control voltage terminal is a DC voltage terminal; or, In a refresh frame, the first control voltage terminal is used to provide a first control voltage and a second control voltage in a time-sharing manner; the first control voltage is different from the second control voltage.

3. The pixel circuit according to claim 1, wherein: The first end of the third energy storage circuit is electrically connected to the first node, and the second end of the third energy storage circuit is electrically connected to the second control voltage end; The second control voltage terminal is a DC voltage terminal; or, In a refresh frame, the second control voltage terminal is used to provide a third control voltage and a fourth control voltage in a time-sharing manner; the third control voltage is different from the fourth control voltage.

4. The pixel circuit according to any one of claims 1 to 3, wherein: Also included is a data writing circuit; The data writing circuit is electrically connected to the scan end, the data line and the first node respectively. The data writing circuit is used to write the data voltage provided by the data line into the first node under the control of the scan signal provided by the scan end.

5. The pixel circuit according to claim 4, wherein: Also includes a first light emitting control circuit and a second light emitting control circuit; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of a first light-emitting control signal provided by the first light-emitting control terminal; The second light emitting control circuit is electrically connected to the second light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is used to control the third node under the control of the second light emitting control signal provided by the second light emitting control terminal. The node is connected to or disconnected from the first electrode of the light-emitting element.

6. The pixel circuit according to claim 5, wherein: Also comprising a second reset control circuit; The second reset control circuit is electrically connected to the second reset control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the initial voltage provided by the initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

7. The pixel circuit according to claim 2, wherein: The driving circuit includes a driving transistor, the first reset control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The gate of the first transistor is electrically connected to the first reset control terminal, the first electrode of the first transistor is electrically connected to the reference voltage terminal, and the second electrode of the first transistor is electrically connected to the first node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the third node; The second energy storage circuit includes a second capacitor; A first end of the second capacitor is electrically connected to the third node, and a second end of the second capacitor is electrically connected to the first control voltage end.

8. The pixel circuit according to claim 3, wherein: The third energy storage circuit includes a third capacitor; A first terminal of the third capacitor is electrically connected to the first node, and a second terminal of the third capacitor is electrically connected to the second control voltage terminal.

9. The pixel circuit according to claim 5, wherein: The data writing circuit includes a second transistor; The gate of the second transistor is electrically connected to the scanning end, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the first node; The first light emitting control circuit includes a third transistor, and the second light emitting control circuit includes a fourth transistor; The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the second node; The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

10. The pixel circuit according to claim 6, wherein: The second reset control circuit includes a fifth transistor; The gate of the fifth transistor is electrically connected to the second reset control terminal, the first electrode of the fifth transistor is electrically connected to the initial voltage terminal, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light emitting element.

11. A driving method, applied to the pixel circuit according to any one of claims 1 to 10, the driving method comprising: The driving circuit generates a driving current for driving the light emitting element under the control of the potential of the first node; The first reset control circuit writes a reference voltage into the first node under the control of a first reset control signal.

12. The driving method according to claim 11, wherein: The pixel circuit further includes a first light emitting control circuit and a second light emitting control circuit; the display cycle includes a refresh frame; The refresh frame includes a refresh period, and the refresh period is sequentially provided with a compensation phase, a data writing phase and a light emitting phase; The driving method includes: During the compensation phase, the first reset control circuit writes a reference voltage into the first node under the control of a first reset control signal; and the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal. In the data writing phase, the data writing circuit writes the data voltage provided by the data line into the first node under the control of the scan signal; In the light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

13. The driving method according to claim 12, wherein: The pixel circuit further includes a third energy storage circuit; a first end of the third energy storage circuit is electrically connected to the first node, a second end of the third energy storage circuit is electrically connected to the DC voltage terminal, and the third energy storage circuit is used to store electrical energy; the refresh time period also includes a bias phase; The driving method further includes: In the compensation phase, the data writing phase and the light emitting phase, the first control voltage terminal is used to provide a first control voltage; During the bias phase, the first control voltage terminal provides a second control voltage; The first control voltage is different from the second control voltage.

14. The driving method according to claim 13, wherein: The display cycle further includes at least one hold frame arranged after the refresh frame; the hold frame includes a hold bias phase and a hold light phase arranged in sequence; the driving method further includes: In the bias holding phase, the first control voltage terminal provides a second control voltage; During a time period of the holding frame except the holding bias phase, the first control voltage terminal provides a first control voltage; In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

15. The driving method according to claim 13, wherein: The refresh frame further includes at least one holding period arranged after the refresh period; the holding period includes a holding bias phase and a holding light-emitting phase arranged in sequence; the driving method further includes: In the bias holding phase, the first control voltage terminal provides a second control voltage; During a time period included in the holding time period except the holding bias phase, the first control voltage terminal provides a first control voltage; In the light-maintaining stage, the first light-emitting control circuit controls the power supply circuit under the control of the first light-emitting control signal. The voltage end is connected to the second node, and the second light-emitting control circuit controls the third node to be connected to the first electrode of the light-emitting element under the control of the second light-emitting control signal.

16. The driving method according to claim 12, wherein: The first control voltage terminal is a DC voltage terminal; the pixel circuit further includes a third energy storage circuit; a first terminal of the third energy storage circuit is electrically connected to the first node, a second terminal of the third energy storage circuit is electrically connected to the second control voltage terminal, and the third energy storage circuit is used to store electrical energy; The refresh period also includes a bias phase; The driving method further includes: In the compensation phase, the data writing phase and the light emitting phase, the second control voltage terminal is used to provide a third control voltage; In the bias phase, the second control voltage terminal provides a fourth control voltage; The third control voltage is different from the fourth control voltage.

17. The driving method according to claim 16, wherein: The display cycle further includes at least one hold frame arranged after the refresh frame; the hold frame includes a hold bias phase and a hold light phase arranged in sequence; the driving method further includes: In the bias holding phase, the second control voltage terminal provides a fourth control voltage; During a time period of the holding frame except the holding bias phase, the second control voltage terminal provides a third control voltage; In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

18. The driving method according to claim 16, wherein: The refresh frame further includes at least one holding period arranged after the refresh period; the holding period includes a holding bias phase and a holding light-emitting phase arranged in sequence; the driving method further includes: In the bias holding phase, the second control voltage terminal provides a fourth control voltage; During a time period included in the holding time period except the holding bias phase, the second control voltage terminal provides a third control voltage; In the maintaining light-emitting stage, the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal, and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

19. The driving method according to any one of claims 13 to 18, wherein: The refresh period also includes an initialization phase provided before the compensation phase; the pixel circuit also includes a second reset control circuit; The driving method further includes: In the initialization phase, the second reset control circuit writes an initial voltage into the first electrode of the light-emitting element under the control of the second reset control signal; and the second light-emitting control circuit controls the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal; The bias stage is set before the initialization stage; or, the bias stage is set between the initialization stage and the compensation stage; or, the bias stage is set between the compensation stage and the data writing stage; or, the bias stage is set between the data writing stage and the light emitting stage.

20. A display device comprising the pixel circuit according to any one of claims 1 to 10.

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