Array substrate, driving method therefor, display panel and display device

Abstract

An array substrate, a driving method therefor, a display panel and a display device. The array substrate comprises a display area (AA) and a non-display area (BB) on at least one side of the display area (AA); a plurality of gate lines (G1-G8), which extend in a row direction (X) and are arranged in a column direction (Y) in the display area (AA); a plurality of pixels (PX), which are arranged in an array in the display area (AA), wherein pixels (PX) in the same row are electrically connected to two gate lines, two gate lines are comprised between two adjacent rows of pixels (PX), at least one column of pixels (PX) is taken as a group, gate lines corresponding to odd-numbered groups of pixels (PX1) in the same row are different from gate lines corresponding to even-numbered groups of pixels (PX2) in the same row, and gate lines corresponding to odd-numbered groups of pixels (PX1) in each row are located on the same side of the row, and gate lines corresponding to even-numbered groups of pixels (PX2) in the row are located on the other side of the row; and a gate driving circuit, which is located in the non-display area (BB), the gate driving circuit comprising a plurality of shift registers (GOA1-GOA9) arranged in cascade, wherein a first-stage shift register (GOA1) is electrically connected to the first gate line (G1), a (2q+1)th-stage shift register is electrically connected to the 2qth gate line, and a 2qth-stage shift register is electrically connected to the (2q+1)th gate line, and q is a positive integer.

Description

Array substrate, driving method thereof, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method thereof, a display panel, and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, driving method thereof, display panel, and display device provided by the embodiments of the present disclosure are specifically described as follows:

[0005] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0006] a base substrate, the base substrate comprising a display area and a non-display area located on at least one side of the display area;

[0007] A plurality of gate lines extending in a row direction and arranged in a column direction in the display area;

[0008] A plurality of pixels are arranged in an array in the display area, wherein the pixels in a row correspond to two gate lines, and two adjacent rows of pixels include two gate lines; the pixels in at least one column form a group, and the gate lines corresponding to the odd-group pixels in a row are different from the gate lines corresponding to the even-group pixels; the gate lines corresponding to the odd-group pixels in each row are located on the same side of the row, and the gate lines corresponding to the even-group pixels are located on the other side of the row;

[0009] A gate drive circuit is located in the non-display area, and the gate drive circuit includes multiple shift registers arranged in cascade, wherein the first-level shift register is electrically connected to the first gate line, the (2q+1)-th level shift register is electrically connected to the 2q-th gate line, and the 2q-th level shift register is electrically connected to the (2q+1)-th gate line, where q is a positive integer.

[0010] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the qth level shift register is cascaded with the (q+p)th level shift register, and the 1st level shift register, the (2q+1)th level shift register, and the 2qth level shift register are arranged in sequence along the column direction, and p is an integer greater than or equal to 2.

[0011] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of data lines extending along the column direction and arranged along the row direction in the display area;

[0012] The pixel includes multiple sub-pixels, and the sub-pixels in the same column are electrically connected to the same data line. An adjacent odd-group pixel and an adjacent even-group pixel constitute a cycle. Within the cycle, the data line corresponding to the sub-pixel in the nth column is connected to the data line corresponding to the sub-pixel in the (n+m)th column, wherein n is greater than or equal to 1 and less than or equal to the number of columns of the sub-pixels in a group of pixels, and m is the number of columns of the sub-pixels in a group of pixels.

[0013] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, two columns of pixels form a group, or four columns of pixels form a group.

[0014] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a plurality of clock signal lines located in the non-display area, and the clock signal lines include 6, the i-th clock signal line is coupled to the clock signal end of the [6(j-1)+i]-th level shift register, i is an integer greater than or equal to 1 and less than or equal to 6, and j is a positive integer.

[0015] On the other hand, an embodiment of the present disclosure provides a driving method of the array substrate described above, comprising:

[0016] Within one frame time, the 1st-level shift register is used to load the scanning voltage for the 1st gate line, the (2q+1)th-level shift register is used to load the scanning voltage for the 2qth gate line, and the 2qth-level shift register is used to load the scanning voltage for the (2q+1)th gate line, and the data voltages with the same polarity are loaded for the sub-pixels contained in the pixel in a single-column or double-column manner.

[0017] On the other hand, an embodiment of the present disclosure provides an array substrate, comprising:

[0018] a base substrate, the base substrate comprising a display area;

[0019] A plurality of gate lines extending in a row direction and arranged in a column direction in the display area, the gate lines being electrically connected to the clock signal lines;

[0020] A plurality of pixels are arranged in an array in the display area, wherein the pixels in a row correspond to two gate lines, and two gate lines are included between two adjacent rows of pixels; at least one column of pixels forms a group, and the gate lines corresponding to the odd-group pixels in a row are different from the gate lines corresponding to the even-group pixels; one of the two gate lines corresponding to the odd-group pixels and the two gate lines corresponding to the even-group pixels in each two adjacent rows is located between the two adjacent rows, and the other is located on both sides of the two adjacent rows.

[0021] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a plurality of data lines extending along the column direction and arranged along the row direction in the display area;

[0022] The pixel includes multiple sub-pixels, and the sub-pixels in the same column are electrically connected to the same data line. An adjacent odd-group pixel and an adjacent even-group pixel constitute a cycle. Within the cycle, the data line corresponding to the sub-pixel in the nth column is connected to the data line corresponding to the sub-pixel in the (n+m)th column, wherein n is greater than or equal to 1 and less than or equal to the number of columns of the sub-pixels in a group of pixels, and m is the number of columns of the sub-pixels in a group of pixels.

[0023] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, two columns of pixels form a group, or four columns of pixels form a group.

[0024] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the base substrate also includes a non-display area located on at least one side of the display area, and the array substrate also includes a gate driving circuit located in the non-display area, and the gate driving circuit includes a plurality of shift registers arranged in cascade, and the plurality of shift registers are arranged along the column direction in the order of the first-stage shift register to the last-stage shift register, wherein the s-th stage shift register is electrically connected to the s-th gate line, and s is a positive integer.

[0025] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a plurality of clock signal lines located in the non-display area, the i-th clock signal line is coupled to the clock signal end of the [k*(j-1)+i]-th level shift register, k is the total number of the clock signal lines, i is an integer greater than or equal to 1 and less than or equal to k, and j is a positive integer.

[0026] On the other hand, an embodiment of the present disclosure provides a driving method of the array substrate, comprising:

[0027] In one frame time, scanning voltages are applied to the gate lines row by row, and data voltages with the same polarity are applied to the sub-pixels contained in the pixels in a manner of single or double rows.

[0028] On the other hand, an embodiment of the present disclosure provides a display panel, including: the above-mentioned array substrate provided by an embodiment of the present disclosure.

[0029] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of a pixel structure in the related art;

[0031] FIG2 is a schematic diagram of the pixel architecture shown in FIG1 under a red screen;

[0032] FIG3 is a schematic diagram of a corresponding data voltage waveform when the red image shown in FIG2 is displayed;

[0033] FIG4 is a schematic diagram of another pixel structure in the related art;

[0034] FIG5 is a schematic diagram of the pixel structure shown in FIG4 under a red screen;

[0035] FIG6 is a schematic diagram of a corresponding data voltage waveform when the red image shown in FIG5 is displayed;

[0036] FIG7 is an equivalent circuit diagram of the pixel architecture shown in FIG4 ;

[0037] FIG8 is a schematic diagram of charging of the pixel electrodes controlled by the odd-numbered gate lines or the even-numbered gate lines in FIG4 ;

[0038] FIG9 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0039] FIG10 is a schematic diagram of a pixel structure of an array substrate provided by an embodiment of the present disclosure within a cycle;

[0040] FIG11 is a schematic structural diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0041] FIG12 is another structural diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0042] FIG13 is another structural diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0043] FIG14 is another structural diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0044] FIG15 is a schematic diagram of charging of the pixel electrodes controlled by the odd-numbered gate lines or the even-numbered gate lines in FIG10 ;

[0045] FIG16 is a schematic diagram of another pixel structure of an array substrate provided by an embodiment of the present disclosure within a cycle;

[0046] FIG17 is a schematic diagram of the pixel architecture shown in FIG10 using H2line flip drive;

[0047] FIG18 is a schematic diagram of the pixel architecture shown in FIG16 using H2line flip drive;

[0048] FIG19 is a schematic diagram of the pixel architecture shown in FIG16 using H2line flip drive in a one dot image;

[0049] FIG20 is a schematic diagram of another pixel structure of an array substrate provided by an embodiment of the present disclosure within a cycle;

[0050] FIG21 is another structural diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0051] FIG22 is another structural diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0052] FIG23 is a schematic diagram of another pixel structure of an array substrate provided by an embodiment of the present disclosure within a cycle;

[0053] FIG24 is a schematic diagram of the pixel architecture shown in FIG20 using H2line flip drive;

[0054] FIG25 is a schematic diagram of the pixel architecture shown in FIG23 using H2line flip drive;

[0055] FIG26 is a schematic diagram of the pixel architecture shown in FIG23 using H2line flip drive in a one dot image;

[0056] FIG27 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0057] FIG28 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0058] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes of the drawings due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended only to illustrate the present disclosure. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components have been omitted.

[0059] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0060] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0061] To reduce costs, related products employ a dual-gate (Dual Gate-Z) architecture, as shown in Figure 1. This effectively reduces the number of bonding leads corresponding to data lines, thereby reducing the number of chip-on-film (COF) driver ICs. However, the existing architecture makes the product prone to insufficient charging when displaying solid-color images. With the demand for high refresh rates in high-end products, this charging problem has become increasingly prominent. Figure 2 illustrates a solid-color image using the Dual Gate-Z architecture shown in Figure 1. The figure uses a solid-color image of red as an example, where Y indicates that the red subpixel R is not at grayscale L0, and N indicates that the green subpixel G and the blue subpixel B are at grayscale L0. Figure 3 illustrates the corresponding data voltage waveforms when displaying the red image shown in Figure 2, where Da1-Da6 represent the data voltages of data lines D1-D6, respectively, and Vcom represents the common voltage. Figure 3 shows that the subpixels R are not pre-charged (pre-charging refers to pre-charging the pixel voltage for a certain period of time before charging). Similar issues exist for other solid colors or mixed colors.

[0062] To address the charging rate issue of the dual-gate product shown in Figure 1, a Dual Gate architecture was invented, as shown in Figure 4. The data line D1 corresponding to the first column of sub-pixels is connected to the data line D7 corresponding to the seventh column of sub-pixels, so that the first column of sub-pixels and the seventh column of pixels are controlled by the same data voltage; the data line D3 corresponding to the second column of sub-pixels is connected to the data line D8 corresponding to the eighth column of sub-pixels, so that the second column of sub-pixels and the eighth column of sub-pixels are controlled by the same data voltage, and so on. A pure color image (e.g., a red image) and its data voltage waveforms of this architecture are shown in Figures 5 and 6. As can be seen from Figures 5 and 6, each red sub-pixel R is pre-charged, and similarly, other pure colors or mixed colors are pre-charged, solving the problem of insufficient charging rate in high-refresh products.

[0063] By analyzing the architecture shown in Figure 4, it can be seen that the first six columns of sub-pixels are controlled by even-numbered gate lines G_E, such as G2, G4, and G6, and the last six columns of sub-pixels are controlled by odd-numbered gate lines G_O, such as G1, G2, and G5, in a periodic arrangement; and the scanning voltage gN (e.g., g1-g8) output by the Nth stage shift register GOAN is correspondingly provided to the Nth gate line (e.g., gate lines 1-8 G1-G8). The equivalent circuit diagram of the pixel architecture shown in Figure 4 is shown in Figure 7, where the first six columns of sub-pixels are referred to as p_column 1 and the last six columns of pixels are referred to as p_column 2. As can be seen from the equivalent circuit diagram 7, the sub-pixel charging voltage (specifically, the charging voltage of the pixel electrode contained in the sub-pixel) is not only affected by charging-related factors, namely the storage capacitor Cst, the liquid crystal capacitor Clc, and the charge and discharge performance of the transistor TFT, but is also affected by coupling capacitance, especially the coupling capacitance between the pixel electrode and the gate line, namely Cgs and Cgs' shown in the figure. Among them, Cgs is the coupling capacitance between the gate line of this row and the pixel electrode of this row, and Cgs' is the coupling capacitance between the gate line of the adjacent row and the pixel electrode of this row. It can be understood that the pixel electrode of the same row is affected by the two gate lines above and below in spatial position, and the magnitude of the influence is called ΔVp and ΔVp' respectively.

[0064] Because the gate line has a jump voltage, Cgs and Cgs' will cause the pixel voltage to change. However, this change varies significantly depending on whether it occurs during the charging period or outside of the charging period. The pixel voltage will recover during the charging period, but not outside of the charging period. A schematic diagram of pixel electrode charging is shown in Figure 8. Figure 8 uses a gate drive circuit (GOA) architecture with six clock signal lines (i.e., 6CLK) and a gate line open time of 3 hours as an example, where H is the charging time for a row of pixels.

[0065] The pixel voltage of P_column 1, controlled by the even-numbered gate line G_E, changes as follows. During the initial charging phase, it rapidly rises to the pre-charge voltage. Then, influenced by the coupling capacitance Cgs' of the previous odd-numbered gate line GO, the moment the odd-numbered gate line G_O turns off, it pulls the pixel voltage down. However, since pixel charging is not complete at this point, the pixel voltage returns to the pre-charge voltage. Influenced by the coupling capacitance Cgs of the current gate line, when the current gate line turns off, the pixel voltage drops by a value of ΔVp. Since the current gate line is already closed at this point, it cannot recover. In summary, due to the influence of Cgs and Cgs', the final voltage drop of P_column 1 is ΔVp.

[0066] Similarly, the pixel voltage of P_column 2, controlled by the odd-numbered gate line G_O, changes as follows. In the initial charging phase, it rapidly rises to the pre-charge voltage. Then, influenced by the coupling capacitance Cgs' of the next even-numbered gate line G_E, the even-numbered gate line G_E pulls up the pixel voltage the moment it opens. However, since pixel charging is not complete at this point, the pixel voltage returns to the pre-charge voltage. Influenced by the coupling capacitance Cgs of the current gate line, the pixel voltage drops by a value of ΔVp when the current gate line is closed. Since the current gate line is already closed at this point, it cannot recover. Influenced by the coupling capacitance Cgs' of the even-numbered gate line G_E, the pixel voltage drops by a value of ΔVp' the moment the even-numbered gate line G_E is closed. Since the even-numbered gate line G_E is already closed at this point, it cannot recover. As can be seen from the above, influenced by Cgs and Cgs', the final voltage drop of P_column 2 is (ΔVp+ΔVp').

[0067] Based on the above analysis, it can be seen that in the architecture shown in FIG4 , there is a significant difference in the final pixel voltage between the sub-pixels in P_column 1 and P_column 2 , with the difference being ΔVp′. The resulting macroscopic defect is periodic vertical streaks.

[0068] In order to at least improve the above-mentioned technical problems existing in the related art, an embodiment of the present disclosure provides an array substrate. FIG9 is a structural schematic diagram of the array substrate provided by the embodiment of the present disclosure. FIG10 is a structural schematic diagram of the array substrate provided by the embodiment of the present disclosure within a cycle. FIG11 to FIG14 are structural schematic diagrams of the gate drive circuit in the array substrate provided by the embodiment of the present disclosure, wherein FIG11 and FIG13 indicate that the gate drive circuit is provided only at one end of the gate line, and FIG12 and FIG14 indicate that the gate drive circuit is provided at both ends of the gate line. As can be seen from FIG9 to FIG14, the array substrate provided by the embodiment of the present disclosure includes:

[0069] A base substrate 101, comprising a display area AA and a non-display area BB located on at least one side of the display area AA;

[0070] A plurality of gate lines (eg, G1 to G8) extending along a row direction X and arranged along a column direction Y in the display area AA;

[0071] A plurality of pixels PX are arranged in an array in the display area AA. Pixels PX in the same row correspond to two gate lines (e.g., G1 and G2, G3 and G4, G5 and G6, G7 and G8). Optionally, the pixel PX includes a plurality of sub-pixels (e.g., a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G, etc.). The pixel electrodes of the sub-pixels correspond to the gate lines through transistors. In the present disclosure, the gate line corresponding to the pixel PX refers to the gate line electrically connected to the transistor electrically connected to the pixel PX. Optionally, two adjacent rows of pixels PX include two gate lines (e.g., G2 and G3). G3, G4 and G5, G6 and G7); at least one column of pixels PX is a group, and the gate lines (for example, G2, G4, G6, G8) corresponding to the odd-group pixels PX1 of the same row are different from the gate lines (for example, G1, G3, G5, G7) corresponding to the even-group pixels PX2; the gate lines (for example, G2, G4, G6, G8) corresponding to the odd-group pixels PX1 of each row are located on the same side (for example, the lower side) of each row, and the gate lines (for example, G1, G3, G5, G7) corresponding to the even-group pixels PX2 are located on the other side (for example, the upper side) of each row;

[0072] The gate drive circuit is located in the non-display area BB, and the gate drive circuit includes a plurality of shift registers (for example, GOA1 to GOA9) arranged in cascade, wherein the first-stage shift register GOA1 is electrically connected to the first gate line G1, the (2q+1)-stage shift register is electrically connected to the 2q-th gate line, and the 2q-stage shift register is electrically connected to the (2q+1)-th gate line, where q is a positive integer; for example, the third-stage shift register GOA3 is electrically connected to the second gate line G2, and the second-stage shift register is electrically connected to the (2q+1)-th gate line. Register GOA2 is electrically connected to the 3rd gate line G3; the 5th-level shift register GOA5 is electrically connected to the 4th gate line G4, and the 4th-level shift register GOA4 is electrically connected to the 5th gate line G5; the 7th-level shift register GOA7 is electrically connected to the 6th gate line G6, and the 6th-level shift register GOA6 is electrically connected to the 7th gate line G7; the 9th-level shift register GOA9 is electrically connected to the 8th gate line G8, and the 8th-level shift register GOA8 is electrically connected to the 9th gate line G9.

[0073] It should be noted that in the present disclosure, the Nth (N is a positive integer) level shift register GOAN refers to the Nth shift register opened within a frame time, that is, N represents the opening order of the shift registers during the operation of the gate drive circuit. For example, the opening order of the shift register GOAN is earlier than the opening order of the shift register GOA(N+1). In terms of physical arrangement, as shown in Figures 13 and 14, the present disclosure can set the shift register GOAN in front of the shift register GOA(N+1); or, as shown in Figures 11 and 12, the shift register GOAN can be set behind the shift register GOA(N+1). Optionally, the present disclosure uses gN (for example, g1 to g9) to represent the scanning voltage provided to the gate line by the output signal terminal Gout of the Nth level shift register GOAN (for example, the 1st to 9th level shift registers).

[0074] Taking the first pixel P1 belonging to the odd pixel group PX1 and the second pixel P2 belonging to the even pixel group PX2 in the second row shown in FIG. 10 as an example, the pixel charging schematic diagram is shown in FIG. 15 .

[0075] The second pixel P2 is controlled by the second scanning signal g2 on the third gate line G3 and is affected by the coupling capacitance associated with the third and fourth gate lines G3 and G4. Its pixel voltage changes as follows: ① In the initial charging phase, it rapidly rises to the pre-charge voltage; ② Influenced by the coupling capacitance Cgs of the third gate line G3, when the third gate line G3 is turned off, the pixel voltage is pulled down by a value of ΔVp. Since the third gate line G3 is already off at this time, it cannot recover; ③ Influenced by the coupling capacitance Cgs' of the fourth gate line G4, the pixel voltage is pulled up by a value of ΔVp' at the moment of pull-up. Since the fourth gate line G4 is already off at this time, it cannot recover. ② and ③ occur at the same time point, but are distinguished in the figure; ④ Influenced by the coupling capacitance Cgs' of the fourth gate line G4, the pixel voltage is pulled down by a value of ΔVp' at the moment of pull-down. Since the fourth gate line G4 is already off at this time, it cannot recover. In summary, affected by Cgs and Cgs', the final voltage drop value of the second pixel P2 is (ΔVp+ΔVp'-ΔVp'), that is, Vp. The main reason for the difference from the architecture shown in Figure 4 is that the charging time of the second scanning signal g2 on the third gate line G3 and the fifth scanning signal g5 on the fourth gate line G4 do not overlap.

[0076] Similarly, the first pixel P1 is controlled by the fifth scan signal g5 on the fourth gate line G4 and is affected by the coupled voltages between the fourth gate line G4 and the third gate line G3. Its pixel voltage changes as follows: ① In the initial charging phase, it rapidly rises to the precharge voltage. Then, affected by the pull-down effect of the second scan signal g2 on the third gate line G3, the voltage drops by ΔVp'. However, since charging is not complete, it quickly recovers and is not shown in the diagram. ② Influenced by the coupling capacitor Cgs of the fourth gate line G4, when the fourth gate line G4 in this row is turned off, the pixel voltage drops by a value of ΔVp. Since the fourth gate line G4 is already off at this point, it cannot recover. Therefore, affected by Cgs and Cgs', the final voltage drop of the first pixel P1 is ΔVp.

[0077] As can be seen from the above, the voltage change caused by Cgs and Cgs' in the first pixel P1 and the second pixel P2 is ΔVp, which effectively solves the vertical streak problem caused by the different voltage changes between different pixels PX. In addition, the present invention only needs to intermodulate the driving order of the 2qth gate line and the (2q+1)th gate line, without changing the pixel layout within the display area AA, making it easy to implement.

[0078] In some embodiments, in the display substrate provided in the embodiments of the present disclosure, as shown in FIG11 and FIG12 , a first-stage shift register, a (2q+1)th-stage shift register, and a 2qth-stage shift register may be arranged in sequence along the column direction Y. For example, a first-stage shift register GOA1, a third-stage shift register GOA3, a second-stage shift register GOA2, a fifth-stage shift register GOA5, a fourth-stage shift register GOA4, a seventh-stage shift register GOA7, a sixth-stage shift register GOA6, and a sixth-stage shift register GOA7 may be arranged in sequence along the column direction Y. The 9th-level shift register GOA9, etc.; in this way, the 1st-level shift register GOA1 and the 1st-row pixel PX are located in the same row, the (2q+1)th-level shift register and the 2qth-row pixel PX are located in the same row, and the 2qth-level shift register and the (2q+1)th-row pixel PX are located in the same row, without winding wires, the 1st-level shift register GOA1 can be electrically connected to the 1st gate line G1, the (2q+1)th-level shift register can be electrically connected to the 2qth-row gate line, and the 2qth-level shift register can be electrically connected to the (2q+1)th-row gate line. Moreover, given that the structures of the shift registers are the same, the present disclosure does not affect the basic design inside the gate drive circuit. It is only necessary to adjust the connection line position between the shift register and the multiple clock signal lines, and therefore, it does not substantially affect the overall layout design of the gate drive circuit. Optionally, as shown in Figures 11 to 14, the multiple clock signal lines located in the non-display area BB in the present disclosure include the 1st to 6th clock signal lines CLK1 to CLK6. Optionally, the i-th clock signal line is coupled to the clock signal terminal CLK of the [6(j-1)+i]th level shift register, where i is an integer greater than or equal to 1 and less than or equal to 6, and j is a positive integer.

[0079] In some embodiments, as shown in Figures 13 and 14, the present disclosure can also set the 1st level shift register, the 2qth level shift register, and the (2q+1)th level shift register to be arranged in sequence along the column direction Y. For example, the 1st level shift register GOA1, the 2nd level shift register GOA2, the 3rd level shift register GOA3, the 4th level shift register GOA4, the 5th level shift register GOA5, the 6th level shift register GOA6, the 7th level shift register GOA7, the 8th level shift register GOA8, etc. are arranged in sequence in the column direction Y; in this way, the Nth level shift register GOA1 and the Nth row of pixels PX are located in the same row. At this time, the external wiring of the output signal terminal Gout of the 2qth level shift register needs to be crossed with the external wiring of the output signal terminal Gout of the (2q+1)th level shift register, so as to facilitate the electrical connection between the (2q+1)th level shift register and the 2qth gate line, and the electrical connection between the 2qth level shift register and the (2q+1)th gate line. Furthermore, since the structures of the shift registers are identical, the present disclosure does not affect the basic design of the gate drive circuit. It only requires adjusting the connection relationship between the shift registers and the plurality of gate lines, thus substantially not affecting the overall layout design of the gate drive circuit.

[0080] In some embodiments, in the gate drive circuit shown in Figures 11 to 14, the q-th stage shift register and the (q+p)-th stage shift register can be set to be cascaded, where p is an integer greater than or equal to 2; specifically, the cascade output terminal Gout_C of the q-th stage shift register is electrically connected to the input signal terminal IN of the (q+p)-th stage shift register, and p=3 is used as an example in the figure; optionally, the cascade output terminal Gout_C of the (q+p')-th stage shift register of the present disclosure is electrically connected to the reset signal terminal Rpu of the q-th stage shift register, and p=3 is used as an example in the figure; The example of p'=4 is used for illustration; in some embodiments, the clock signal terminal CLK, the first power supply terminal VDD1, the second power supply terminal VDD2, the first reference signal terminal LVGL, the second reference signal terminal VGL, and the reset signal terminal TR of each shift register (for example, GOA1~GOA9) in the present disclosure can be electrically connected to the corresponding signal lines CLK1~6, VD1, VDD2, LVGL, VGL, and STV0 respectively; the input signal terminal IN of the 1st to 3rd stage shift registers GOA1~3 can be electrically connected to the frame start signal terminal STV1.

[0081] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in Figures 10 and 16, it may also include a plurality of data lines (for example, D1 to D12) extending along the column direction Y and arranged along the row direction X in the display area AA; the pixel PX includes a plurality of sub-pixels (for example, red sub-pixels R, green sub-pixels G, blue sub-pixels B, etc.), and the sub-pixels in the same column (for example, red sub-pixels R, green sub-pixels G, blue sub-pixels B, etc.) are electrically connected to the same data line (for example, D1 to D12), and an adjacent odd-group pixel PX1 and an even-group pixel PX2 constitute a cycle. Within the cycle, the data line corresponding to the sub-pixel in the nth column is connected to the data line corresponding to the sub-pixel in the (n+m)th column, where n is greater than or equal to 1 and less than or equal to the number of columns of sub-pixels in a group of pixels PX, and m is the number of columns of sub-pixels in a group of pixels PX.

[0082] For example, in Figure 10, two columns of pixels PX form a group, and one cycle has four columns of pixels PX and 12 columns of sub-pixels (for example, red sub-pixels R, green sub-pixels G, blue sub-pixels B, etc.), 1≤n≤6, m=6, that is, the data line D1 corresponding to the first column of sub-pixels is connected to the data line D7 corresponding to the seventh column of sub-pixels, the data line D2 corresponding to the second column of sub-pixels is connected to the data line D8 corresponding to the eighth column of sub-pixels, the data line D3 corresponding to the third column of sub-pixels is connected to the data line D9 corresponding to the ninth column of sub-pixels, the data line D4 corresponding to the fourth column of sub-pixels is connected to the data line D10 corresponding to the tenth column of sub-pixels, the data line D5 corresponding to the fifth column of sub-pixels is connected to the data line D11 corresponding to the eleventh column of sub-pixels, and the data line D6 corresponding to the sixth column of sub-pixels is connected to the data line D12 corresponding to the twelfth column of sub-pixels.

[0083] For example, in FIG16 , 4 columns of pixels PX form a group, and one cycle has 8 columns of pixels PX and 24 columns of sub-pixels (for example, red sub-pixels R, green sub-pixels G, blue sub-pixels B, etc.), 1≤n≤12, m=12, that is, the data line D1 corresponding to the 1st column of sub-pixels is connected to the data line D13 corresponding to the 13th column of sub-pixels, the data line D2 corresponding to the 2nd column of sub-pixels is connected to the data line D14 corresponding to the 14th column of sub-pixels, the data line D3 corresponding to the 3rd column of sub-pixels is connected to the data line D15 corresponding to the 15th column of sub-pixels, the data line D4 corresponding to the 4th column of sub-pixels is connected to the data line D16 corresponding to the 16th column of sub-pixels, and the data line D5 corresponding to the 5th column of sub-pixels is connected to the data line D17 corresponding to the 17th column of sub-pixels. The data lines D6 corresponding to the sub-pixels in the 6th column are connected to the data lines D18 corresponding to the sub-pixels in the 18th column, the data lines D7 corresponding to the sub-pixels in the 7th column are connected to the data lines D19 corresponding to the sub-pixels in the 19th column, the data lines D8 corresponding to the sub-pixels in the 8th column are connected to the data lines D20 corresponding to the sub-pixels in the 20th column, the data lines D9 corresponding to the sub-pixels in the 9th column are connected to the data lines D21 corresponding to the sub-pixels in the 21st column, the data lines D10 corresponding to the sub-pixels in the 10th column are connected to the data lines D22 corresponding to the sub-pixels in the 22nd column, the data lines D11 corresponding to the sub-pixels in the 11th column are connected to the data lines D23 corresponding to the sub-pixels in the 23rd column, and the data lines D12 corresponding to the sub-pixels in the 12th column are connected to the data lines D24 corresponding to the sub-pixels in the 24th column.

[0084] In FIG10 , a cycle of 12 columns of sub-pixels is formed, and within a cycle, the Mth (1≤M≤6)th data line is connected to the (M+6)th data line. The data lines can only be driven using the one-line flipping method, i.e., the polarity of the data voltage on the data lines is (+, -, +, -, +, -, ...). The H2line flipping method, i.e., the polarity of the data voltage on the data lines is (+, -, -, +, +, -, -, +, ...), cannot be used. As shown in FIG17 , when the architecture shown in FIG10 employs H2line flipping, the polarity in the row direction X within the display area AA is non-uniform (the polarity in a minimum cycle, per column, is +, -, -, +, +, -, +, -, +, +, -, +, +, -, +, +, -, +, +, -, +), i.e., every other two columns have the same polarity, and every other column has the same polarity. When Figure 16 uses 24 columns of sub-pixels as a cycle, it is compatible with both one-line flip and H2-line flip designs. When using H2-line flip, the polarity in the row direction X within the display area AA is evenly arranged (+, -, -, +, +, -, -, +, +, -, -, +, +, -, -, +, +, -, -, +, +, -, +), with every other column having the same polarity, as shown in Figure 18.

[0085] The combination of these two drivers can effectively avoid image quality issues associated with certain display types, such as the one-dot display (one-dot), where every other RGB pixel is lit. This design utilizes an H2line flipped driver to effectively prevent lateral crosstalk (H-crosstalk) caused by fluctuations in the common voltage VCOM due to differences in data voltage polarity. As shown in Figure 19, sub-pixels filled with a dot pattern illuminate, while sub-pixels not filled with the dot pattern remain dark. In a one-dot display (which is used by many end customers and whose image quality is highly valued, such as the Excel crosstalk display commonly used in the industry), the pixel architecture shown in Figure 16 ensures that all lit pixels in a row receive an equal number of positive (+) data voltages (e.g., Da1, Da4, Da5, Da8, Da9, Da12) and negative (-) data voltages (e.g., Da2, Da3, Da6, Da7, Da10, Da11). This offsets the coupling of data voltage fluctuations on the common voltage VCOM, eliminating crosstalk risk.

[0086] Accordingly, the present disclosure further provides a driving method for the array substrate including the pixel architecture shown in FIG10 and FIG16, comprising:

[0087] Within one frame, the first-level shift register is used to load the scanning voltage for the first gate line, the (2q+1)-level shift register is used to load the scanning voltage for the 2q-th gate line, and the 2q-level shift register is used to load the scanning voltage for the (2q+1)-th gate line, and the sub-pixels contained in the pixel are loaded with data voltages of the same polarity in a single-column or double-column manner; wherein loading the sub-pixels contained in the pixel with the same polarity with the data voltage in a single-column manner is to load the data voltage in a one-line flip manner; loading the sub-pixels contained in the pixel with the same polarity with the data voltage in a double-column manner is to load the data voltage in an H2line flip manner. Optionally, the array substrate shown in FIG10 adopts a one-line flip drive, and the array substrate shown in FIG16 can adopt either a one-line flip drive or an H2line flip drive. In the case of adopting the H2line flip drive, the display quality of the one-dot image can be effectively improved.

[0088] In some embodiments, embodiments of the present disclosure provide an array substrate, including the pixel architecture shown in FIG20 , and FIG21 and FIG22 are schematic diagrams of a gate drive circuit structure corresponding to the pixel architecture shown in FIG20 . In FIG20 to FIG22 , the s-th stage shift register of the gate drive circuit is electrically connected to the s-th gate line, where s is a positive integer; the i-th clock signal line is coupled to the clock signal terminal of the [k*(j-1)+i]-th stage shift register, where k (e.g., i=6) is the total number of clock signal lines, i is an integer greater than or equal to 1 and less than or equal to k, and j is a positive integer. In Figure 20, at least one column of pixels PX forms a group, and the gate lines (for example, G2, G3, G6, G7) corresponding to the odd-array pixels PX1 in the same row are different from the gate lines (for example, G1, G4, G5, G8) corresponding to the even-array pixels PX2; one of the two gate lines (for example, G2 and G3, G4 and G5, G6 and G7) corresponding to the odd-array pixels PX1 of each two adjacent rows and the two gate lines (for example, G1 and G4, G5 and G8) corresponding to the even-array pixels PX2 (for example, G2 and G3, G4 and G5, G6 and G7) is located between the two adjacent rows, and the other (for example, G1 and G4, G5 and G8) is located on both sides of the two adjacent rows, so that the pixels PX in each row of the odd-array pixels PX1 are alternately driven by the even-odd row gate lines, and the pixels PX in each row of the even-array pixels PX2 are alternately driven by the odd-even row gate lines.

[0089] Based on the above analysis of Figure 4 , the final pixel voltage difference between pixels PX controlled by odd-numbered gate lines and pixels PX controlled by even-numbered gate lines is ΔVp'. In Figure 20 , the pixels PX controlled by odd-numbered and even-numbered gate lines are alternately arranged in both the row direction X and the column direction Y, so that the pixel voltage difference ΔVp' is arranged in a crosswise manner, neutralizing the pixel brightness difference and eliminating the vertical stripe problem; and the pixel aperture ratio is not changed.

[0090] In some embodiments, as shown in FIG20 , two columns of pixels PX form a group, or, as shown in FIG23 , four columns of pixels PX form a group. In both FIG20 and FIG23 , a cycle is formed by an adjacent odd-group pixel PX1 and an even-group pixel PX2. Within the cycle, the data line corresponding to the sub-pixel in the nth column is connected to the data line corresponding to the sub-pixel in the (n+m)th column, where n is greater than or equal to 1 and less than or equal to the number of sub-pixel columns in a group of pixels, and m is the number of sub-pixel columns in a group of pixels. Because the electrical connection relationship between the data lines in FIG20 is the same as the electrical connection relationship between the data lines in FIG10 , and the electrical connection relationship between the data lines in FIG23 is the same as the electrical connection relationship between the data lines in FIG16 , the electrical connection relationship between the data lines in FIG20 and FIG23 will not be further described herein.

[0091] In some embodiments, as shown in Figure 24, the pixel architecture shown in Figure 20 is not suitable for H2line inversion driving. However, as shown in Figures 25 and 26, the pixel architecture shown in Figure 23 is suitable for H2line inversion driving and can solve the crosstalk problem caused by common voltage fluctuations in one-dot display. The specific principles can be found in the description of Figures 17 to 19 and will not be elaborated here.

[0092] Accordingly, for the array substrates shown in FIG. 20 and FIG. 23 , the driving method includes:

[0093] Within one frame time, scanning voltages are loaded on the gate lines row by row, and data voltages with the same polarity are loaded on the sub-pixels contained in the pixels in a single-column (i.e., one line flip) or double-column (i.e., H2line flip) manner; optionally, the array substrate shown in FIG20 adopts one line flip drive, and the array substrate shown in FIG23 can adopt either one line flip drive or H2line flip drive, and in the case of adopting H2line flip drive, the display quality of the one dot picture can be effectively improved.

[0094] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, as shown in FIG27 , comprising the array substrate 001 described above and an opposing substrate 002 disposed opposite the array substrate 001. Optionally, as shown in FIG27 , the display panel provided by the embodiment of the present disclosure may further include a liquid crystal layer 003 disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 facing away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 facing away from the array substrate 001. The polarization directions of the first polarizer 004 and the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0095] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in FIG28 , comprising the above-mentioned display panel PNL provided in an embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. The backlight module BLU can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightening film stacked on the light-emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0096] In some embodiments, the lamp beads can also be micro light-emitting devices (such as Mini LED, Micro LED), etc. Submillimeter or even micron-scale micro light-emitting devices are self-luminous devices like organic light-emitting devices (OLED). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. And because the light emission of inorganic light-emitting devices is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting devices based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when the micro light-emitting device is used as a backlight source, it can achieve a more precise dynamic backlight effect. While effectively improving the brightness and contrast of the screen, it can also solve the glare phenomenon caused by traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0097] In some embodiments, the above-mentioned display device provided by the embodiments of the present disclosure may be: a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the above-mentioned display device includes but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer executable codes, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0098] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0099] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein: include: a base substrate, the base substrate comprising a display area and a non-display area located on at least one side of the display area; A plurality of gate lines extending in a row direction and arranged in a column direction in the display area; A plurality of pixels are arranged in an array in the display area, wherein the pixels in a row correspond to two gate lines, and two adjacent rows of pixels include two gate lines; at least one column of pixels forms a group, and the gate lines corresponding to the odd-group pixels in a row are different from the gate lines corresponding to the even-group pixels; the gate lines corresponding to the odd-group pixels in each row are located on the same side of the row, and the gate lines corresponding to the even-group pixels are located on the other side of the row; A gate drive circuit is located in the non-display area, and the gate drive circuit includes multiple shift registers arranged in cascade, wherein the first-level shift register is electrically connected to the first gate line, the (2q+1)-th level shift register is electrically connected to the 2q-th gate line, and the 2q-th level shift register is electrically connected to the (2q+1)-th gate line, where q is a positive integer.

2. The array substrate according to claim 1, wherein: The qth stage shift register is cascaded with the (q+p)th stage shift register, and the 1st stage shift register, the (2q+1)th stage shift register, and the 2qth stage shift register are arranged in sequence along the column direction, and p is an integer greater than or equal to 2.

3. The array substrate according to claim 1 or 2, wherein: Also included are a plurality of data lines extending in the column direction and arranged in the row direction in the display area; The pixel includes multiple sub-pixels, and the sub-pixels in the same column are electrically connected to the same data line. An adjacent odd-group pixel and an adjacent even-group pixel constitute a cycle. Within the cycle, the data line corresponding to the sub-pixel in the nth column is connected to the data line corresponding to the sub-pixel in the (n+m)th column, wherein n is greater than or equal to 1 and less than or equal to the number of columns of the sub-pixels in a group of pixels, and m is the number of columns of the sub-pixels in a group of pixels.

4. The array substrate according to any one of claims 1 to 3, wherein: Two columns of pixels form a group, or four columns of pixels form a group.

5. The array substrate according to any one of claims 1 to 4, wherein: It also includes multiple clock signal lines located in the non-display area, and the clock signal lines include 6. The i-th clock signal line is coupled to the clock signal end of the [6(j-1)+i]-th level shift register, i is an integer greater than or equal to 1 and less than or equal to 6, and j is a positive integer.

6. A driving method for an array substrate according to any one of claims 1 to 5, wherein: include: Within one frame time, the 1st-level shift register is used to load the scanning voltage for the 1st gate line, the (2q+1)th-level shift register is used to load the scanning voltage for the 2qth gate line, and the 2qth-level shift register is used to load the scanning voltage for the (2q+1)th gate line, and the data voltages with the same polarity are loaded for the sub-pixels contained in the pixel in a single-column or double-column manner.

7. An array substrate, wherein: include: a base substrate, the base substrate comprising a display area; A plurality of gate lines extending in a row direction and arranged in a column direction in the display area; A plurality of pixels are arranged in an array in the display area, wherein the pixels in a row correspond to two gate lines, and two gate lines are included between two adjacent rows of pixels; at least one column of pixels forms a group, and the gate lines corresponding to the odd-group pixels in a row are different from the gate lines corresponding to the even-group pixels; one of the two gate lines corresponding to the odd-group pixels and the two gate lines corresponding to the even-group pixels in each two adjacent rows is located between the two adjacent rows, and the other is located on both sides of the two adjacent rows.

8. The array substrate according to claim 7, wherein: Also included are a plurality of data lines extending in the column direction and arranged in the row direction in the display area; The pixel includes multiple sub-pixels, and the sub-pixels in the same column are electrically connected to the same data line. An adjacent odd-group pixel and an adjacent even-group pixel constitute a cycle. Within the cycle, the data line corresponding to the sub-pixel in the nth column is connected to the data line corresponding to the sub-pixel in the (n+m)th column, wherein n is greater than or equal to 1 and less than or equal to the number of columns of the sub-pixels in a group of pixels, and m is the number of columns of the sub-pixels in a group of pixels.

9. The array substrate according to claim 8, wherein: Two columns of pixels form a group, or four columns of pixels form a group.

10. The array substrate according to any one of claims 7 to 9, wherein: The base substrate also includes a non-display area located on at least one side of the display area, and the array substrate also includes a gate drive circuit located in the non-display area. The gate drive circuit includes a plurality of shift registers arranged in cascade, and the plurality of shift registers are arranged along a column direction in the order of a first-stage shift register to a last-stage shift register, wherein the s-th stage shift register is electrically connected to the s-th gate line, and s is a positive integer.

11. The array substrate according to claim 10, wherein: It also includes multiple clock signal lines located in the non-display area, the i-th clock signal line is coupled to the clock signal end of the [k*(j-1)+i]-th level shift register, k is the total number of the clock signal lines, i is an integer greater than or equal to 1 and less than or equal to k, and j is a positive integer.

12. A driving method for an array substrate according to any one of claims 7 to 11, wherein: include: In one frame time, scanning voltages are applied to the gate lines row by row, and data voltages with the same polarity are applied to the sub-pixels contained in the pixels in a manner of single or double rows.

13. A display panel, wherein: include: The array substrate according to any one of claims 1 to 5 and 7 to 11.

14. A display device, wherein: Comprising the display panel as claimed in claim 13.

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