Display panel and preparation method therefor, and display apparatus

Abstract

A display panel, comprising: a peep-proof functional layer, the peep-proof functional layer comprising a first electrode layer, an electrochromic layer and a second electrode layer, which are arranged in sequence along a direction away from a base substrate. The display panel further comprises: a first overlapping wire and a second overlapping wire, which are located in a peripheral region and are arranged spaced apart from each other, the first overlapping wire being connected to the first electrode layer, and the second overlapping wire being connected to the second electrode layer. The display panel further comprises at least one of a first barrier dam, a second barrier dam and a third barrier dam, which are located in the peripheral region, a film layer at which the first barrier dam, the second barrier dam and the third barrier dam are located being disposed at a side of a film layer, facing away from the base substrate, where the first overlapping wire and the second overlapping wire are located.

Description

Display panel and manufacturing method thereof, and display device

[0001] This application claims priority to Chinese patent application No. 202410233194.3, filed on February 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0003] Organic Light-Emitting Diode (OLED) screens have attracted widespread attention due to their advantages such as self-luminescence, low power consumption, lightness, flexibility, brilliant colors, high contrast, and fast response rate. They have become the representative of the next generation of displays and are gradually replacing liquid crystal displays (LCD) screens.

[0004] Currently, mobile phones and car screens all use anti-peeping films to achieve anti-peeping functions. However, anti-peeping films are consumables and need to be replaced from time to time, which increases the cost of use. Especially for foldable phones, after applying anti-peeping films, creases will appear at the folding position, affecting the user experience. Summary of the Invention

[0005] On the one hand, a display panel is provided, which includes: a display area and a peripheral area surrounding the display area; the display panel also includes: a base substrate, a display function layer, an encapsulation structure layer and an anti-peep function layer; the anti-peep function layer includes: a first electrode layer, an electrochromic layer and a second electrode layer arranged in sequence along a direction away from the base substrate; a first strapping wire and a second strapping wire located in the peripheral area and spaced apart, the first strapping wire being connected to the first electrode layer for transmitting a first voltage signal to the first electrode layer; the second strapping wire being connected to the second electrode layer for transmitting a second voltage signal to the second electrode layer.

[0006] The display panel also includes: at least one of a first blocking dam, a second blocking dam and a third blocking dam arranged in the peripheral area; wherein the film layer where the first blocking dam, the second blocking dam and the third blocking dam are located is arranged on a side of the film layer where the first overlap line and the second overlap line are located away from the base substrate.

[0007] In some embodiments, the display panel includes the first barrier dam, the second barrier dam, and the third barrier dam; the first barrier dam, the second barrier dam, and the third barrier dam are arranged in a direction away from the display area; the first electrode layer is located on a side of the first barrier dam close to the display area, the electrochromic layer is located on a side of the second barrier dam close to the display area, and the second electrode layer is located on a side of the third barrier dam close to the display area.

[0008] In some embodiments, the display panel further includes a binding area located on a side of the peripheral area away from the display area; the peripheral area includes a first sub-area and a second sub-area that are connected and arranged, and the second sub-area is located between the display area and the binding area; in the second sub-area, the second blocking dam is merged with the third blocking dam.

[0009] In some embodiments, the first overlapping line includes a first electrode connection line, and the second overlapping line includes a second electrode connection line; the first electrode connection line is arranged around the display area; the second electrode connection line is located in the first sub-area of ​​the peripheral area; and in the first sub-area, the second electrode connection line is located on the side of the first electrode connection line away from the display area; the first electrode layer is connected to the first electrode connection line, and the second electrode layer is connected to the second electrode connection line.

[0010] In some embodiments, the first bonding wire further includes at least one first lead, and the second bonding wire further includes at least one second lead; the at least one first lead and the at least one second lead are located in the second sub-area of ​​the peripheral area; one end of the first lead is connected to the first electrode connecting wire, and the other end of the first lead is connected to the driving chip; one end of the second lead is connected to the second electrode connecting wire, and the other end of the second lead is connected to the driving chip.

[0011] In some embodiments, in the second sub-region, the first lead passes under the second barrier dam and the third barrier dam.

[0012] In some embodiments, the display panel further includes: a bending area located between the binding area of ​​the display panel and the second sub-area; the display function layer includes a source-drain electrode layer, and the display panel further includes at least one first signal line and at least one second signal line arranged in the source-drain electrode layer; one end of the first signal line is connected to the first lead, and the other end of the first signal line extends to the binding area through the bending area, and one end of the second signal line is connected to the second lead, and the other end of the second signal line extends to the binding area through the bending area.

[0013] In some embodiments, the first bonding wire includes two first leads, and the second bonding wire includes two second leads, where the two second leads are located on both sides of the two first leads.

[0014] In some embodiments, the third blocking dam includes: a first sublayer and a second sublayer; the first sublayer is located in the first sub-area of ​​the peripheral area; the second sublayer includes a first sub-portion and a second sub-portion that are connected and arranged, the first sub-portion is located in the first sub-area, and the first sub-portion covers the first sublayer; the second sub-portion is located in the second sub-area of ​​the peripheral area.

[0015] In some embodiments, the encapsulation structure layer includes: an organic encapsulation layer; the display panel also includes: a first retaining wall located in the peripheral area and surrounding the display area, the organic encapsulation layer is located on the side of the first retaining wall close to the display area; the second retaining dam covers the first retaining wall.

[0016] In some embodiments, the display panel further includes: a second retaining wall located in the peripheral area and surrounding the display area, the second retaining wall being located on a side of the first retaining wall close to the display area, and the organic encapsulation layer being located on a side of the second retaining wall close to the display area; in an orthographic projection onto the base substrate, the second retaining wall is located between the first retaining dam and the second retaining dam, or the first retaining dam covers the second retaining wall.

[0017] In some embodiments, the first overlapping line includes a first electrode connecting line, the second overlapping line includes a second electrode connecting line; the first blocking dam covers an edge portion of the first electrode connecting line away from the display area, the second blocking dam covers an edge portion of the second electrode connecting line close to the display area, and the third blocking dam covers an edge portion of the second electrode connecting line away from the display area.

[0018] In some embodiments, the display panel also includes: a raised layer arranged between the encapsulation structure layer and the anti-peek function layer, and a fourth blocking dam arranged in the peripheral area; the fourth blocking dam is located on the side of the first blocking dam close to the display area, and the raised layer is located on the side of the fourth blocking dam close to the display area; the fourth blocking dam covers the edge portion of the first electrode connecting line close to the display area.

[0019] In some embodiments, the thickness of the enhanced layer ranges from 20 μm to 100 μm.

[0020] In some embodiments, the display area includes multiple pixel opening areas; the display panel also includes: multiple focusing structures arranged between the boosting layer and the encapsulation structure layer, and the multiple focusing structures are arranged in a one-to-one correspondence with the multiple pixel opening areas.

[0021] In some embodiments, the display area includes a plurality of pixel opening areas and a separation area located between the plurality of pixel opening areas. The display panel further includes an anti-reflection layer disposed between the build-up layer and the encapsulation structure layer; the anti-reflection layer includes a light blocker and a color filter film, the light blocker being located in the separation area, and the color filter film being located in the plurality of pixel opening areas.

[0022] In some embodiments, the width of the first lap line ranges from 100 μm to 500 μm; the width of the second lap line ranges from 100 μm to 500 μm.

[0023] In some embodiments, the material of the electrochromic layer includes: polythiophenes and their derivatives, viologens, tetrathiafulvalene, metal phthalocyanine compounds, tungsten oxide, molybdenum oxide, and any oxide or hydrated oxide of any element among platinum, iridium, osmium, palladium, ruthenium, nickel and rhodium.

[0024] In some embodiments, the display area includes multiple pixel opening areas, and the anti-peeping functional layer also includes multiple light-transmitting structures arranged in a one-to-one correspondence with the multiple pixel opening areas; the light-transmitting structure is located between the first electrode layer and the second electrode layer, and the light-transmitting structure is in contact with the first electrode layer or the second electrode layer.

[0025] In some embodiments, the display panel further includes: a touch structure layer disposed on a side of the anti-peeping function layer away from the display panel, and an insulating layer disposed between the anti-peeping function layer and the touch structure layer.

[0026] On the other hand, a method for manufacturing a display panel is provided. The display panel includes a display area and a peripheral area surrounding the display area. The display area includes a plurality of pixel opening areas.

[0027] The preparation method of the display panel includes: providing a base substrate; forming a display function layer on one side of the base substrate; forming an encapsulation structure layer on a side of the display function layer away from the base substrate; forming a first overlap wire and a second overlap wire in the peripheral area on a side of the encapsulation structure layer away from the base substrate, the first overlap wire and the second overlap wire are arranged at intervals; forming at least one of a fourth blocking dam, a first blocking dam, a second blocking dam and a third blocking dam in the peripheral area on a side of the first overlap wire and the second overlap wire away from the base substrate; forming a boost layer on a side of the encapsulation structure layer away from the base substrate; forming a first electrode layer on a side of the boost layer away from the base substrate, the first electrode layer being connected to the first overlap wire; forming a plurality of light-transmitting structures and an electrochromic layer on a side of the first electrode layer away from the base substrate, the plurality of light-transmitting structures being arranged in a one-to-one correspondence with the plurality of pixel opening areas; forming a second electrode layer on a side of the electrochromic layer and the plurality of light-transmitting structures away from the base substrate, the second electrode layer being connected to the second overlap wire; and the light-transmitting structure is in contact with the first electrode layer or the second electrode layer.

[0028] On the other hand, a display device is provided, comprising: a display panel as described in any of the above embodiments; the display device also comprises: a driving chip, wherein the driving chip is configured to transmit a first voltage signal to a first electrode layer of an anti-peek function layer of the display panel, and to transmit a second voltage signal to a second electrode layer of the anti-peek function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, etc. involved in the embodiments of the present disclosure.

[0030] FIG1 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0031] FIG2 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0032] FIG3 is another structural diagram of a display panel according to some embodiments of the present disclosure;

[0033] FIG4 is a cross-sectional view of the display panel provided in FIG3 along the cross-sectional line CC;

[0034] FIG5 is a cross-sectional view of the display panel provided in FIG3 along the cross-sectional line CC in the anti-peeping mode;

[0035] FIG6 is another cross-sectional view of the display panel provided in FIG3 along the cross-sectional line CC;

[0036] FIG7 is a cross-sectional view of the display panel provided in FIG3 along the cross-sectional line FF;

[0037] FIG8 is another cross-sectional view of the display panel provided in FIG3 along the cross-sectional line CC;

[0038] FIG9 is another cross-sectional view of the display panel provided in FIG3 along the cross-sectional line CC;

[0039] FIG10 is another cross-sectional view of the display panel provided in FIG3 along the cross-sectional line CC;

[0040] FIG11 is another cross-sectional view of the display panel provided in FIG3 along the cross-sectional line CC;

[0041] FIG12 is a flow chart of a method for manufacturing a display panel according to some embodiments of the present disclosure;

[0042] FIG13 is a structural diagram corresponding to steps of a method for manufacturing a display panel according to some embodiments of the present disclosure;

[0043] FIG14 is another structural diagram of a display panel according to some embodiments of the present disclosure;

[0044] FIG15 is a cross-sectional view of the display panel provided in FIG14 along the cross-sectional line HH;

[0045] FIG16 is a cross-sectional view of the display panel provided in FIG3 along the cross-sectional line FF;

[0046] FIG17 is a structural diagram corresponding to steps of a method for manufacturing a display panel according to some embodiments of the present disclosure;

[0047] FIG18 is a structural diagram corresponding to steps of a method for manufacturing a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0049] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0050] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0051] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0052] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0053] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0054] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0057] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0058] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0059] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000 . Display device 1000 can be any device that displays either moving (e.g., video) or stationary (e.g., still images), and whether text or images. More specifically, it is contemplated that the embodiments described herein can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones (e.g., cell phones), wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry). FIG1 illustrates display device 1000 as a mobile phone.

[0060] Exemplarily, the display device 1000 may be an electroluminescent display device or a photoluminescent display device. In the case where the display device 1000 is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). In the case where the display device 1000 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device. The following uses the display device 1000 as an OLED display device as an example to schematically illustrate some embodiments of the present disclosure. However, the embodiments of the present disclosure include but are not limited to these, and any other display device may also be considered as long as the same technical concept is applied.

[0061] Continuing to refer to FIG. 1 , the display device 1000 includes a display panel 100 .

[0062] As shown in Figures 2 and 4, where Figure 4 is a cross-sectional view of the display panel 100 shown in Figure 3 along section line CC, the display panel 100 includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA includes a plurality of pixel opening areas A1 and separation areas A2 located between the plurality of pixel opening areas A1. The peripheral area BB is used for wiring.

[0063] The display area AA is provided with a plurality of sub-pixels, each corresponding one-to-one to the plurality of pixel opening areas A1. The sub-pixels include at least a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. For example, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, which are provided in sequence, form a pixel P.

[0064] It should be noted that the above means that the orthographic projections of A and B on the base substrate 10 overlap in a direction perpendicular to the plane where the base substrate 10 is located.

[0065] The multiple sub-pixels in the display area AA are arranged in an array. For example, as shown in FIG2 , a column of red sub-pixels R, a column of green sub-pixels G, and a column of blue sub-pixels B of the display panel 100 are alternately arranged in sequence. This is not limited to this in some embodiments of the present disclosure.

[0066] It should be noted that Figure 4 and Figures 6, 8, 9, 10 and 11 in the subsequent content are cross-sectional views obtained along a cross-sectional line of the display panel 100 of the four structures respectively, and the positions of the cross-sectional lines corresponding to Figures 4, 6, 8, 9, 10 and 11 in the display panel 100 are the same as the position of the cross-sectional line CC in the display panel 100 shown in Figure 3.

[0067] In some embodiments, as shown in FIG. 4 , the display panel 100 includes: a base substrate 10 , a display function layer 20 , and an encapsulation structure layer 30 , which are stacked in sequence.

[0068] Exemplarily, the base substrate 10 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The first flexible material layer and the second flexible material layer may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first inorganic material layer and the second inorganic material layer may be referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si).

[0069] Exemplarily, the display function layer 20 includes a pixel circuit stack (not shown in the figure) and a light-emitting device stack. For example, the pixel circuit stack includes: an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer, and a source / drain metal layer. The pixel circuit stack is formed with a plurality of pixel driving circuits. The pixel driving circuit can be a 7T1C, 8T1C, or 9T1C circuit, where T represents a transistor, the number in front of T represents the number of transistors, C represents a capacitor, and the number in front of C represents the number of capacitors. Exemplarily, 7T1C represents 7 transistors and 1 capacitor.

[0070] For example, the light-emitting device stack includes: multiple light-emitting devices (such as R, G, and B shown in Figure 4), a planarization layer 21, and a pixel definition layer 22 disposed on the side of the planarization layer 21 away from the base substrate 10. The pixel definition layer 22 is provided with multiple openings, and the light-emitting devices are disposed in the openings. The pixel driving circuit is used to drive the light-emitting devices to emit light, so that the display function layer 20 can realize the display function.

[0071] In other examples, the display function layer 20 includes an anode, a light-emitting layer, and a cathode arranged in sequence, but some embodiments of the present disclosure are not limited thereto.

[0072] Exemplarily, the encapsulation structure layer 30 is configured to reduce the risk of moisture and oxygen from the external environment entering the sub-pixels, thereby increasing the service life of the display panel 100. The encapsulation structure layer 30 can be an encapsulation film or an encapsulation substrate. For example, the encapsulation structure layer 30 can be an encapsulation film, and the encapsulation structure layer 30 can include a first inorganic encapsulation layer (not shown in the figure), an organic encapsulation layer 31, and a second inorganic encapsulation layer 32 stacked in sequence.

[0073] For example, the materials of the first and second inorganic encapsulation layers 32 include one or more of silicon nitride (SiNx), silicon dioxide (SiOx), and silicon oxynitride (SiON). The material of the organic encapsulation layer 31 includes one or more of an acrylic polymer, a silicon polymer, and an epoxy polymer.

[0074] In some examples, as shown in FIG. 4 , in the peripheral region BB of the display panel 100, the inorganic material layer of the base substrate 10 (e.g., including the first inorganic material layer and the second inorganic material layer), the inorganic material layer of the display function layer 20 (e.g., including the gate insulation layer and the interlayer insulation layer in the pixel circuit stack), and the inorganic material layer of the encapsulation structure layer 30 (e.g., including the first inorganic encapsulation layer) form an encapsulation stack 60. The encapsulation stack 60 can improve the encapsulation effect of the display panel 100, effectively preventing moisture and oxygen from entering the sub-pixels through the peripheral region BB, thereby increasing the service life of the display panel 100.

[0075] In some embodiments, privacy filters are commonly used to implement privacy protection on mobile phones. However, users may have different privacy protection needs in different usage scenarios. For example, sometimes users want to share certain information, while other times users need to carefully protect certain information to achieve active privacy protection.

[0076] 4 , the display panel 100 further includes an anti-peeping layer 50 , which includes a first electrode layer 51 , an electrochromic layer 52 , and a second electrode layer 53 , which are sequentially arranged in a direction away from the base substrate 10 .

[0077] At least the portion of the electrochromic layer 52 located in the pixel opening area A1 contacts only one of the first electrode layer 51 and the second electrode layer 53, and does not contact the other of the first electrode layer 51 and the second electrode layer 53. The portion of the electrochromic layer 52 located in the separation area A2 contacts both the first electrode layer 51 and the second electrode layer 53.

[0078] By applying different voltages to the first electrode layer 51 and the second electrode layer 53, the electrochromic layer 52 undergoes an electrochemical reaction under the action of an external electric field. By gaining and losing electrons, the electrochromic material of the electrochromic layer 52 undergoes a stable and reversible color change. This change is manifested in appearance as a reversible change in color and transmittance.

[0079] It should be noted that “contact” here includes direct contact and indirect contact.

[0080] For example, the portion of the electrochromic layer 52 located in the separation area A2 is in direct contact with both the first electrode layer 51 and the second electrode layer 53, that is, the surface of the first electrode layer 51 away from the base substrate 10 is in direct contact with the surface of the electrochromic layer 52 close to the base substrate 10, and the surface of the second electrode layer 53 close to the base substrate 10 is in direct contact with the surface of the electrochromic layer 52 away from the base substrate 10.

[0081] For example, the portion of the electrochromic layer 52 located in the partition A2 is in indirect contact with both the first electrode layer 51 and the second electrode layer 53. That is, the first electrode layer 51 is in indirect contact with the electrochromic layer 52 via the auxiliary electrode, and the second electrode layer 53 is in indirect contact with the electrochromic layer 52 via the auxiliary electrode. Of course, the indirect contact in the embodiment of the present disclosure can also be achieved using other structures, which will not be described one by one here.

[0082] The term "non-contact" herein can be understood as being insulated, staggered, or having a gap between the two. For example, at least the portion of the electrochromic layer 52 located in the pixel opening area A1 contacts only the first electrode layer 51, and the portion of the electrochromic layer 52 located in the pixel opening area A1 that contacts only the first electrode layer 51 is insulated from the second electrode layer 53. At least the portion of the electrochromic layer 52 located in the pixel opening area A1 contacts only the second electrode layer 53, and the portion of the electrochromic layer 52 located in the pixel opening area A1 that contacts only the second electrode layer 53 is insulated from the first electrode layer 51.

[0083] For example, as shown in Figure 5, the portion of the electrochromic layer 52 located in the pixel opening area A1 contacts only the second electrode layer 53 and does not contact the first electrode layer 51. The portion of the electrochromic layer 52 located in the separation area A2 contacts both the first electrode layer 51 and the second electrode layer 53. When an electric field is formed between the first electrode layer 51 and the second electrode layer 53, the color of the electrochromic layer 52 in contact with the first electrode layer 51 deepens, the light transmittance decreases, and the sub-pixel light output viewing angle is narrowed.

[0084] For example, as shown in FIG6 , which is a cross-sectional view of the display panel 100 shown in FIG3 along section line CC, the portion of the electrochromic layer 52 located in the pixel opening area A1 contacts only the first electrode layer 51 and does not contact the second electrode layer 53. The portion of the electrochromic layer 52 located in the separation area A2 contacts both the first electrode layer 51 and the second electrode layer 53. When an electric field is formed between the first electrode layer 51 and the second electrode layer 53, the color of the electrochromic layer 52 in contact with the second electrode layer 53 deepens, the transmittance decreases, and the sub-pixel light output viewing angle is narrowed.

[0085] 4 , when the first electrode layer 51 and the second electrode layer 53 are not energized, the light output viewing angle of each pixel opening area A1 is DD. At this time, the user can observe the display image at the front viewing angle, the side viewing angle, and the side viewing angle.

[0086] It should be noted that the viewing angle refers to the angle between the observer's line of sight and the direction perpendicular to the plane of the substrate 10 when the observer observes the display panel 100 from the light-emitting side E of the display panel 100. For example, a normal viewing angle refers to an observer observing the display panel 100 from the light-emitting side E of the display panel 100 in a direction perpendicular to the plane of the substrate 10, i.e., a viewing angle of 0°. For another example, a 30° viewing angle refers to an observer observing the display panel 100 from the light-emitting side E of the display panel 100 at an angle of 30° to the direction perpendicular to the plane of the substrate 10. A small viewing angle is, for example, less than or equal to 30°, and a large viewing angle is, for example, greater than 30°.

[0087] Referring to Figure 5 , when the first electrode layer 51 and the second electrode layer 53 are energized, the light output angle EE for each pixel opening area A1 is 0. When the first electrode layer 51 and the second electrode layer 53 are energized, the portion of the electrochromic layer 52 located in the pixel opening area A1 does not change color, allowing light to pass through the portion of the electrochromic layer 52 located in the pixel opening area A1. The portion of the electrochromic layer 52 located in the partition area A2 changes color. This portion of the electrochromic layer 52 located in the partition area A2 acts as a light-blocking layer, blocking the outgoing light. Therefore, the light in the partition area A2 is blocked, resulting in a light output angle EE that is smaller than the light output angle DD. In other words, the display panel 100 provided in the embodiments of the present disclosure reduces the light transmittance of the display panel 100 by energizing the first electrode layer 51 and the second electrode layer 53 to cause the portion of the electrochromic layer 52 located in the partition area A2 to change color. This not only effectively reduces the light output angle of the sub-pixels, achieving the active privacy protection function of the display panel 100, but also does not affect the display quality of the display panel 100 at normal viewing angles.

[0088] It can be understood that the portion of the electrochromic layer 52 located in the pixel opening area A1 is not in contact with the first electrode layer 51 or the second electrode layer 53, and the portion of the electrochromic layer 52 located in the pixel opening area A1 that is not in contact with the first electrode layer 51 is insulated from the first electrode layer 51, and the portion of the electrochromic layer 52 located in the pixel opening area A1 that is not in contact with the second electrode layer 53 is insulated from the second electrode layer 53, so it is difficult to load the electric field in this portion, so that light can pass through the electrochromic layer 52 located in the pixel opening area A1.

[0089] In some examples, as shown in Figures 4 and 6, the privacy protection layer 50 further includes a plurality of light-transmitting structures 54 disposed in a one-to-one correspondence with the plurality of pixel opening areas A1. The light-transmitting structures 54 are located between the first electrode layer 51 and the second electrode layer 53, and the light-transmitting structures 54 are in contact with the first electrode layer 51 or the second electrode layer 53.

[0090] Exemplarily, as shown in Figure 4, the light-transmitting structure 54 is arranged on the side of the electrochromic layer 52 close to the base substrate 10. The portion of the electrochromic layer 52 located in the pixel opening area A1 only contacts the second electrode layer 53 and does not contact the first electrode layer 51. The portion of the electrochromic layer 52 located in the separation area A2 contacts both the first electrode layer 51 and the second electrode layer 53.

[0091] Exemplarily, as shown in Figure 6, the light-transmitting structure 54 is arranged on the side of the electrochromic layer 52 away from the base substrate 10. The portion of the electrochromic layer 52 located in the pixel opening area A1 only contacts the first electrode layer 51 and does not contact the second electrode layer 53. The portion of the electrochromic layer 52 located in the separation area A2 contacts both the first electrode layer 51 and the second electrode layer 53.

[0092] For example, as shown in Figures 4 and 6 , the material of the light-transmitting structure 54 includes a negative photoresist, which does not affect the passage of light. Furthermore, the process conditions for forming the light-transmitting structure 54 using the negative photoresist are low-temperature conditions, which effectively avoids the impact of high-temperature process conditions on the light-emitting device.

[0093] The provision of the light-transmitting structure 54 enables the portion of the electrochromic layer 52 located in the pixel opening area A1 to contact only the first electrode layer 51 or the second electrode layer 53. The light-transmitting structure 54 makes it difficult to load the electric field on the portion of the electrochromic layer 52 located in the pixel opening area A1. Therefore, even if the first electrode layer 51 and the second electrode layer 53 are energized, the portion of the electrochromic layer 52 located in the pixel opening area A1 will not change color, or the portion of the electrochromic layer 52 located in the pixel opening area A1 will change color only slightly, allowing light to pass through the portion of the electrochromic layer 52 located in the pixel opening area A1.

[0094] In some embodiments, as shown in FIG4 , the material constituting the electrochromic layer 52 includes an organic electrochromic material or an inorganic electrochromic material. Organic electrochromic materials include polythiophenes and their derivatives, viologens, tetrathiafulvalene, and metal phthalocyanine compounds. Inorganic electrochromic materials include oxides or hydrated oxides of elements such as tungsten oxide, molybdenum oxide, platinum, iridium, osmium, palladium, ruthenium, nickel, and rhodium.

[0095] Exemplarily, the inorganic electrochromic material includes an anodic color-changing material or a cathodic color-changing material. Anodic color-changing materials include oxides or hydrated oxides of elements such as platinum, iridium, osmium, palladium, ruthenium, nickel, and rhodium, and cathodic color-changing materials include tungsten oxide and molybdenum oxide.

[0096] Correspondingly, when the voltage applied to the first electrode layer 51 is set to be greater than the voltage applied to the second electrode layer 53, the material of the electrochromic layer 52 adopts the above-mentioned organic electrochromic material or the anodic electrochromic material. When an electric field is formed between the first electrode layer 51 and the second electrode layer 53, the color of the electrochromic material in contact with the first electrode layer 51 will deepen, thereby reducing the light output viewing angle of the sub-pixel. When the voltage applied to the first electrode layer 51 is set to be less than the voltage applied to the second electrode layer 53, the material of the electrochromic layer 52 adopts the above-mentioned organic electrochromic material or the anodic electrochromic material. When an electric field is formed between the first electrode layer 51 and the second electrode layer 53, the color of the electrochromic material in contact with the first electrode layer 51 will deepen, thereby reducing the light output viewing angle of the sub-pixel, thereby achieving the anti-peeping function of the display panel 100.

[0097] When the material of the electrochromic layer 52 adopts the above-mentioned organic electrochromic material, no matter which is larger, the voltage loaded on the first electrode layer 51 and the voltage loaded on the second electrode layer 53, as long as there is a voltage difference between the voltage loaded on the first electrode layer 51 and the voltage loaded on the second electrode layer 53, the organic electrochromic material can change color, narrow the light output viewing angle of the sub-pixel, and realize the anti-peeping function of the display panel 100.

[0098] It should be noted that when power is applied to the first electrode layer 51 and the second electrode layer 53, the material constituting the electrochromic layer 52 exhibits a gradient color change across the thickness of the electrochromic layer 52. By employing a material that exhibits a gradient color change across the thickness of the electrochromic layer 52, the portion of the electrochromic layer 52 located in the pixel opening area A1 is prevented from changing color, allowing light to pass through the portion of the electrochromic layer 52 located in the pixel opening area A1.

[0099] In some embodiments, as shown in Figures 3 and 4, the display panel 100 includes a first overlap wire 71 and a second overlap wire 72 arranged at intervals in the peripheral area BB, the first overlap wire 71 is connected to the first electrode layer 51, and is used to transmit a first voltage signal to the first electrode layer 51, and the second overlap wire 72 is connected to the second electrode layer 53, and is used to transmit a second voltage signal to the second electrode layer 53.

[0100] In some examples, the width of the first overlap line 71 ranges from 100 μm to 500 μm. For example, the width of the first overlap line 71 is 100 μm, 200 μm, 300 μm, 400 μm, or 500 μm, etc., which is not limited here.

[0101] Illustratively, the width of the second overlap line 72 ranges from 100 μm to 500 μm. For example, the width of the second overlap line 72 is 100 μm, 200 μm, 300 μm, 400 μm, or 500 μm, etc., which is not limited here.

[0102] By setting the width range of the first overlap line 71 to 100μm~500μm and the width range of the second overlap line 72 to 100μm~500μm, it is ensured that the first overlap line 71 and the first electrode layer 51 have sufficient overlap area, thereby ensuring the stability of the first voltage signal transmission, and the second overlap line 72 and the second electrode layer 53 have sufficient overlap area, thereby ensuring the stability of the second voltage signal transmission.

[0103] In some examples, as shown in Figures 3 and 4, the display device 1000 (as shown in Figure 1) includes a driving chip, which is used to provide a first voltage signal to the first electrode layer 51, the voltage value of the first voltage signal is a first voltage, and provide a second voltage signal to the second electrode layer 53, the voltage value of the second voltage signal is a second voltage.

[0104] Exemplarily, the first voltage is greater than the second voltage. In this case, the voltage loaded on the first electrode layer 51 is greater than the voltage loaded on the second electrode layer 53 .

[0105] Exemplarily, the first voltage is lower than the second voltage. In this case, the voltage applied to the first electrode layer 51 is lower than the voltage applied to the second electrode layer 53 .

[0106] The structural arrangement of the first lap joint 71 and the second lap joint 72 is described below.

[0107] In some examples, as shown in Figure 3, the display panel 100 also includes a binding area 102 located on the side of the peripheral area BB away from the display area AA, and a bending area 101 located between the binding area 102 and the peripheral area BB of the display panel 100, and the peripheral area BB includes a first sub-area BB1 and a second sub-area BB2 that are connected.

[0108] For example, as shown in Figure 3, the first sub-area BB1 is located on the left, right, and top sides of the display area AA, and the second sub-area BB2 is located below the display area AA. Various signal lines within the display panel 100 extend through the second sub-area BB2, away from the display area AA, to the bending area 101 of the display panel 100, and then to the binding area 102. This connection between the signal lines in the display area AA of the display panel 100 and the driver chip is achieved through the binding area 102.

[0109] Continuing with Figure 3 , the first bonding wire 71 includes a first electrode connection line 71a and at least one first lead line 71b connected to the first electrode connection line 71a. The first electrode connection line 71a surrounds the display area AA, i.e., the first electrode connection line 71a is arranged in a ring shape. The first electrode layer 51 is connected to the first electrode connection line 71a. The first lead line 71b is located in the second sub-area BB2. One end of the first lead line 71b is connected to the first electrode connection line 71a, and the other end of the first lead line 71b is connected to the driver chip. The driver chip provides a first voltage signal to the first bonding wire 71 via the first lead line 71b.

[0110] Continuing with FIG3 , the second bonding line 72 includes a second electrode connection line 72a and at least one second lead line 72b connected to the second electrode connection line 72a. The second electrode connection line 72a is located in the first sub-area BB1, and the second electrode layer 53 is connected to the second electrode connection line 72a. A second lead line 72b is located in the second sub-area BB2. One end of the second lead line 72b is connected to the second electrode connection line 72a, and the other end of the second lead line 72b is connected to the driver chip. The driver chip provides a second voltage signal to the second bonding line 72 via the second lead line 72b.

[0111] For example, as shown in Figures 3 and 7, Figure 7 is a cross-sectional view of the display panel 100 shown in Figure 3 along the cross-sectional line FF. For example, the pixel circuit stack of the display function layer 20 includes a source-drain metal layer (not shown in the figure), and the display panel 100 includes at least one first signal line 83 and at least one second signal line 84 provided in the source-drain metal layer. The first lead 71b is connected to the first signal line 83 through a via K penetrating the package stack 60, and the second lead 72b is connected to the second signal line 84 through a via (not shown in the figure) penetrating the package stack 60. The first signal line 83 and the second signal line 84 are connected to the driver chip to achieve the connection between the first lead 71b and the second lead 72b and the driver chip.

[0112] For example, the pixel circuit stack of the display function layer 20 includes a gate metal layer (not shown in the figure), and the display panel 100 includes at least one first signal line 83 and at least one second signal line 84 provided in the gate metal layer. The first lead 71b is connected to the first signal line 83 through a via K penetrating the package stack 60, and the second lead 72b is connected to the second signal line 84 through a via (not shown in the figure) penetrating the package stack 60. The first signal line 83 and the second signal line 84 are connected to the driver chip to achieve the connection between the first lead 71b and the second lead 72b and the driver chip.

[0113] When the first bonding wire 71 provides a first voltage signal to the first electrode layer 51 and the second bonding wire 72 provides a second voltage signal to the second electrode layer 53, there is a voltage difference between the first voltage signal and the second voltage signal, and the electrochromic layer 52 located in the separation area A2 changes color, thereby reducing the light output viewing angle of the sub-pixel to achieve the anti-peeping function of the display panel 100.

[0114] For example, as shown in FIG3 , there are two first leads 71 ​​b and two second leads 72 b, with the two second leads 72 b disposed on either side of the two first leads 71 ​​b. The provision of multiple (including two) first leads 71 ​​b facilitates reducing the transmission voltage drop of the first voltage signal, while the provision of multiple (including two) second leads 72 b facilitates reducing the transmission voltage drop of the second voltage signal.

[0115] In some embodiments, as shown in Figures 3 and 4 , the display panel 100 further includes at least one barrier dam located in the peripheral area BB and surrounding the display area AA, for example, a first barrier dam 73, a second barrier dam 74, and a third barrier dam 75. The first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 are arranged in a direction away from the display area AA. The first electrode layer 51 is located on a side of the first barrier dam 73 closer to the display area AA, the electrochromic layer 52 is located on a side of the second barrier dam 74 closer to the display area AA, and the second electrode layer 53 is located on a side of the third barrier dam 75 closer to the display area AA.

[0116] It should be noted that the first electrode layer 51 is located on the side of the first barrier dam 73 close to the display area AA, which means that the first electrode layer 51 is located within the area enclosed by the first barrier dam 73, and the side of the first electrode layer 51 away from the display area AA can abut against the first barrier dam 73. The electrochromic layer 52 is located on the side of the second barrier dam 74 close to the display area AA, which means that the electrochromic layer 52 is located within the area enclosed by the second barrier dam 74, and the side of the electrochromic layer 52 away from the display area AA can abut against the second barrier dam 74. The second electrode layer 53 is located on the side of the third barrier dam 75 close to the display area AA, which means that the second electrode layer 53 is located within the area enclosed by the third barrier dam 75, and the side of the second electrode layer 53 away from the display area AA can abut against the third barrier dam 75.

[0117] In order to clearly introduce the structural arrangement of the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 and the first overlap line 71 and the second overlap line 72, the film layer farthest from the base substrate 10 in Figure 3 is the film layer where the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 are located, and the film layer on the side away from the base substrate 10 where the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 are located is omitted.

[0118] For example, as shown in Figures 3 and 4, the edge of the first electrode layer 51 away from the display area AA does not exceed the first blocking dam 73, the electrochromic layer 52 covers the first electrode layer 51 and the first blocking dam 73, the edge of the electrochromic layer 52 away from the display area AA does not exceed the second blocking dam 74, the second electrode layer 53 covers the electrochromic layer 52, and the edge of the second electrode layer 53 away from the display area AA does not exceed the third blocking dam 75.

[0119] Exemplarily, the material of the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 includes a negative photoresist. The process conditions for forming the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 using the negative photoresist are low temperature conditions, thereby avoiding the impact of high temperature process conditions on the light-emitting device when the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 are formed.

[0120] In some embodiments, as shown in FIG. 3 and FIG. 4 , the film layer where the first blocking dam 73 , the second blocking dam 74 and the third blocking dam 75 are located is disposed on a side of the film layer where the first and second overlapping lines 71 and 72 are located away from the base substrate 10 .

[0121] It can be understood that, as shown in Figure 3, since the film layer where the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 are located is arranged on the side of the film layer where the first lead 71b and the second lead 72b are located away from the base substrate 10, the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 do not affect the wiring of the first bonding wire 71 and the second bonding wire 72 in the peripheral area BB.

[0122] Specifically, as shown in FIG. 3 , in order to achieve connection between the first lead 71 b and the driving chip, the first lead 71 b needs to extend to a side of the third barrier dam 75 away from the display area AA.

[0123] For example, the first lead 71b needs to extend from the first barrier dam 73 to the side of the third barrier dam 75 away from the display area AA, and there is an overlapping area S1 between the first lead 71b and the first, second, and third barrier dams 73, 74, and 75. By disposing the first, second, and third barrier dams 73, 74, and 75 on the side of the first lead 71b away from the base substrate 10, the first, second, and third barrier dams 73, 74, and 75 cover the first lead 71b in the overlapping area S1. In other words, the first lead 71b passes under the second and third barrier dams 74, 75.

[0124] Similarly, as shown in FIG. 3 , in order to achieve connection between the second lead 72 b and the driving chip, the second lead 72 b needs to extend to a side of the third barrier dam 75 away from the display area AA.

[0125] For example, the second lead 72b extends from the third blocking dam 75 to the side of the third blocking dam 75 away from the display area AA, and there is an overlapping area S2 between the second lead 72b and the third blocking dam 75. By setting the third blocking dam 75 on the side of the second lead 72b away from the base substrate 10, the third blocking dam 75 covers the second lead 72b in the overlapping area S2 between the second lead 72b and the third blocking dam 75.

[0126] The first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 cover the first lead 71b, and the third barrier dam 75 covers the second lead 72b, so that the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 do not affect the routing of the first and second bonding wires 71 and 72 in the peripheral area BB. Because the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 all have slope angles, and when the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 are made of negative photoresist, they can be fabricated using low-temperature process conditions, resulting in larger slope angles for the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75. If the first lead 71b needs to cross the first barrier dam 73, the second barrier dam 74 and the third barrier dam 75, and the second lead 72b needs to cross the third barrier dam 75, there will be a risk of the first lead 71b breaking at the first barrier dam 73, the second barrier dam 74 or the third barrier dam 75, and the second lead 72b breaking at the third barrier dam 75.

[0127] That is to say, in the embodiment of the present disclosure, the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 are arranged in a direction away from the display area AA, and the film layer where the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 are located is arranged on the side of the film layer where the first overlapping line 71 and the second overlapping line 72 are located away from the base substrate 10, so that the first lead 71b does not need to cross the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75, and the second lead 72b does not need to cross the third blocking dam 75, thereby reducing the risk of circuit breakage.

[0128] 3 and 7 , the peripheral region BB includes a first sub-region BB1 and a second sub-region BB2 that are connected to each other. In the second sub-region BB2 , the second barrier dam 74 and the third barrier dam 75 are merged.

[0129] In the second sub-area BB2, the second barrier dam 74 and the third barrier dam 75 are merged into one. This means that, in the second sub-area BB2, the side of the second barrier dam 74 away from the display area AA is connected to the side of the third barrier dam 75 closer to the display area AA. This also means that, in the second sub-area BB2, only one barrier dam M1 is provided on the side of the first barrier dam 73 away from the display area AA. This barrier dam M1 connects not only to the portion of the second barrier dam 74 located in the first sub-area BB1, but also to the portion of the third barrier dam 75 located in the first sub-area BB1.

[0130] In the second sub-area BB2, since the second blocking dam 74 and the third blocking dam 75 are combined, the side of the electrochromic layer 52 away from the display area AA and the side of the second electrode layer 53 away from the display area AA can both offset the side of the blocking dam M1 close to the display area AA.

[0131] As shown in Figures 4, 3, and 7, in the second sub-area BB2, because the first lead 71b needs to extend from the first barrier dam 73 to the side of the third barrier dam 75 away from the display area AA, the portion of the first lead 71b located on the second barrier dam 74 near the display area AA is covered by the electrochromic layer 52. The second barrier dam 74 and the third barrier dam 75 are combined to ensure that the second electrode layer 53 does not extend beyond the second barrier dam 74. Therefore, on the side of the second barrier dam 74 away from the display area AA, the first lead 71b is not connected to the second electrode layer 53, thereby preventing a short circuit caused by the connection between the first bonding wire 71 and the second electrode layer 53.

[0132] In some embodiments, as shown in FIG. 4 , in the first sub-area BB1 , the second electrode connection line 72 a is located on a side of the first electrode connection line 71 a away from the display area AA.

[0133] Because the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 are arranged in a direction away from the display area AA, and the edge of the first electrode layer 51 away from the display area AA does not extend beyond the first barrier dam 73, the first electrode layer 51 needs to be connected to the first electrode connection line 71a, and the edge of the second electrode layer 53 away from the display area AA does not extend beyond the third barrier dam 75, and the second electrode layer 53 needs to be connected to the second electrode connection line 72a. Therefore, in the first sub-area BB1, the second electrode connection line 72a is located on the side of the first electrode connection line 71a away from the display area AA. This facilitates the connection between the first electrode layer 51 and the first electrode connection line 71a, and the connection between the second electrode layer 53 and the second electrode connection line 72a.

[0134] In some embodiments, as shown in Figures 3 and 4, the third barrier dam 75 includes a first sublayer 751 and a second sublayer 752. The first sublayer 751 is located in the first sub-region BB1. The second sublayer 752 includes a first sub-portion 752a and a second sub-portion 752b that are connected to each other. The first sub-portion 752a is located in the first sub-region BB1 and covers the first sublayer 751. The second sub-portion 752b is located in the second sub-region BB2.

[0135] That is to say, in the first sub-area BB1, the third blocking dam 75 is provided with two layers, so that the height of the portion of the third blocking dam 75 located in the first sub-area BB1 can be increased, thereby improving the blocking performance of the third blocking dam 75 on the material of the second electrode layer 53, so that the second electrode layer 53 will not exceed the third blocking dam 75 away from the edge of the display area AA.

[0136] It is understood that the barrier dam M1 and the second sub-portion 752b represent the same structure, that is, the barrier dam M1 and the second sub-portion 752b can both represent the structure of the second barrier dam 74 and the third barrier dam 75 located in the second sub-area BB2 combined.

[0137] Since the first sublayer 751 is formed before the first and second bonding lines 71 and 72, the details can be found in the description of the display panel manufacturing method and will not be described in detail here. In the second sub-area BB2, the third barrier dam 75 is not provided with the first sublayer 751 to prevent the first sublayer 751 from interfering with the routing of the first and second bonding lines 71 and 72, thereby avoiding circuit breakage caused by the first and second bonding lines 71 and 72 crossing this layer.

[0138] In some embodiments, as shown in FIG4 , the encapsulation structure layer 30 includes an organic encapsulation layer 31. The display panel 100 further includes a first retaining wall 79 located in the peripheral area BB and surrounding the display area AA. The organic encapsulation layer 31 is located on a side of the first retaining wall 79 close to the display area AA. The second retaining dam 74 covers the first retaining wall 79.

[0139] It should be noted that the organic encapsulation layer 31 is located on the side of the first retaining wall 79 close to the display area AA, which means that the organic encapsulation layer 31 is located in the area surrounded by the first retaining wall 79, and the side of the organic encapsulation layer 31 away from the display area AA can be against the first retaining wall 79.

[0140] As shown in FIG. 4 , in the first sub-area BB1 , the second barrier dam 74 covers the first barrier wall 79 , which increases the height of the second barrier dam 74 and improves the blocking effect of the second barrier dam 74 on the electrochromic layer 52 .

[0141] As shown in FIG7 , in the second sub-area BB2, the second blocking dam 74 and the third blocking dam 75 are merged into a blocking dam M1, and the blocking dam M1 covers the first blocking wall 79. The first blocking wall 79 can increase the height of the blocking dam M1 and improve the blocking effect of the blocking dam M1 on the electrochromic layer 52 and the second electrode layer 53, so that the electrochromic layer 52 and the second electrode layer 53 will not exceed the blocking dam M1 away from the edge of the display area AA.

[0142] In some embodiments, as shown in FIG4 , the display panel 100 further includes: a second retaining wall 78 located in the peripheral area BB and surrounding the display area AA, the second retaining wall 78 being located on a side of the first retaining wall 79 close to the display area AA, and the organic encapsulation layer 31 being located on a side of the second retaining wall 78 close to the display area AA.

[0143] It should be noted that the organic encapsulation layer 31 is located on the side of the second retaining wall 78 close to the display area AA, which means that the organic encapsulation layer 31 is located in the area surrounded by the second retaining wall 78, and the side of the organic encapsulation layer 31 away from the display area AA can be against the second retaining wall 78.

[0144] Exemplarily, the material of the second retaining wall 78 includes positive photoresist, and the material of the first retaining wall 79 includes positive photoresist. The first retaining wall 79 and the second retaining wall 78 can be prepared under high temperature process conditions, and the slope angles of the formed first retaining wall 79 and the second retaining wall 78 are both relatively small.

[0145] It should be noted that, as shown in FIG7 , in the second sub-area BB2, the film layer where the first retaining wall 79 and the second retaining wall 78 are located is located on the side of the film layer where the first bonding line 71 is located that is closer to the base substrate 10. That is, the first retaining wall 79 and the second retaining wall 78 are formed before the first bonding line 71. In other words, the first bonding line 71 needs to span both the second retaining wall 78 and the first retaining wall 79. Typically, the material of the second retaining wall 78 and the first retaining wall 79 is generally positive photoresist. Because the slope angles of the first retaining wall 79 and the second retaining wall 78 are both relatively low, the first retaining wall 79 and the second retaining wall 78 do not affect the continuity of the first bonding line 71, and the first bonding line 71 does not become disconnected due to spanning the first retaining wall 79 and the first retaining wall 78.

[0146] For example, the edge of the organic encapsulation layer 31 does not exceed the first retaining wall 79, or the edge of the organic encapsulation layer 31 does not exceed the second retaining wall 78. The provision of the second retaining wall 78 and the first retaining wall 79 can provide a good barrier effect on the organic encapsulation layer 31, effectively preventing the material forming the organic encapsulation layer 31 from overflowing to the side of the first retaining wall 79 away from the display area AA, thereby ensuring that the display panel 100 has a good encapsulation effect.

[0147] In some examples, as shown in FIG4 and FIG8 , where FIG8 is a cross-sectional view of the display panel 100 shown in FIG3 along the cross-sectional line CC, in an orthographic projection onto the base substrate 10 , the second barrier wall 78 is located between the first barrier dam 73 and the second barrier dam 74 , or the first barrier dam 73 covers the second barrier wall 78 .

[0148] Exemplarily, as shown in FIG. 4 , in an orthographic projection onto the base substrate 10 , the second barrier wall 78 is located between the first barrier dam 73 and the second barrier dam 74 .

[0149] 8 , in an orthographic projection onto the base substrate 10 , the first barrier dam 73 covers the second barrier wall 78 , thereby increasing the height of the first barrier dam 73 .

[0150] In some embodiments, as shown in Figure 4, the display panel 100 also includes: a raised layer 40 arranged between the encapsulation structure layer 30 and the anti-peek function layer 50, and a fourth blocking dam 76 arranged in the peripheral area BB, the fourth blocking dam 76 is located on the side of the first blocking dam 73 close to the display area AA, and the raised layer 40 is located on the side of the fourth blocking dam 76 close to the display area AA.

[0151] It should be noted that the raised layer 40 is located on the side of the fourth barrier dam 76 close to the display area AA, which means that the raised layer 40 is located in the area surrounded by the fourth barrier dam 76 and the side of the raised layer 40 away from the display area AA can abut against the fourth barrier dam 76.

[0152] For example, as shown in FIG. 4 , the material of the building-up layer 40 may be an inorganic material or an organic material, such as photoresist, and the building-up layer 40 may be transparent to light.

[0153] Providing the raised layer 40 between the encapsulation structure layer 30 and the privacy protection layer 50 can increase the distance between the display function layer 20 and the privacy protection layer 50. The closer the distance between the display function layer 20 and the privacy protection layer 50, the wider the visible viewing angle in privacy protection mode, and the poorer the privacy protection effect. Conversely, the farther the distance between the display function layer 20 and the privacy protection layer 50, the narrower the visible viewing angle in privacy protection mode, and the better the privacy protection effect. In other words, the provision of the raised layer 40 can affect the visible viewing angle in privacy protection mode, thereby affecting the privacy protection effect of the display panel 100.

[0154] In some embodiments, as shown in Figure 4, the fourth blocking dam 76 covers the edge portion of the first electrode connecting line 71a close to the display area AA, the first blocking dam 73 covers the edge portion of the first electrode connecting line 71a away from the display area AA, the second blocking dam 74 covers the edge portion of the second electrode connecting line 72a close to the display area AA, and the third blocking dam 75 covers the edge portion of the second electrode connecting line 72a away from the display area AA.

[0155] That is, the edge portions of the first electrode connecting line 71 a on both sides of the extending direction thereof are covered, and the edge portions of the second electrode connecting line 72 a on both sides of the extending direction thereof are covered.

[0156] The fourth barrier dam 76 and the first barrier dam 73 cover the edge of the first electrode connecting line 71 a, so that the fourth barrier dam 76 and the first barrier dam 73 protect the first electrode connecting line 71 a. The second barrier dam 74 and the third barrier dam 75 cover the edge of the second electrode connecting line 72 a, so that the second barrier dam 74 and the third barrier dam 75 protect the second electrode connecting line 72 a.

[0157] For example, when a patterning process is used to form the fourth barrier dam 76, the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75, an alkaline solution is required during the development step. The fourth barrier dam 76 and the first barrier dam 73 cover the edge of the first electrode connecting line 71a, thereby preventing the alkaline solution from corroding the edge of the first electrode connecting line 71a, thereby protecting the first electrode connecting line 71a. The second barrier dam 74 and the third barrier dam 75 cover the edge of the second electrode connecting line 72a, thereby preventing the alkaline solution from corroding the edge of the second electrode connecting line 72a, thereby protecting the second electrode connecting line 72a.

[0158] It should be noted that the “patterning process” generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping.

[0159] For example, as shown in FIG. 4 , the thickness h1 of the raised layer 40 ranges from 20 μm to 100 μm.

[0160] It should be noted that the thickness h1 of the raised layer 40 refers to the dimension of the raised layer 40 in a direction perpendicular to the plane of the base substrate 10. Furthermore, the raised layer 40 is used to enhance the privacy protection of the display panel 100. Therefore, the thickness h1 of the raised layer 40, which ranges from 20 μm to 100 μm, refers to the thickness h1 of the raised layer 40 located in the display area AA.

[0161] For example, the thickness h1 of the raised layer 40 is 20 μm, 40 μm, 60 μm, 70 μm, 80 μm, or 100 μm, etc., which is not limited here.

[0162] By setting the thickness h1 of the raised layer 40 to be in the range of 20 μm to 100 μm, the anti-peeping effect of the display panel 100 is improved.

[0163] In some embodiments, as shown in FIG. 3 , the intervals between adjacent fourth barrier dams 76 , first barrier dams 73 , second barrier dams 74 , and third barrier dams 75 are substantially equal.

[0164] Illustratively, the distance d1 between the fourth barrier dam 76 and the first barrier dam 73, the distance d2 between the first barrier dam 73 and the second barrier dam 74, and the distance d3 between the second barrier dam 74 and the third barrier dam 75 may be d1<d2<d3, or may be approximately equal, i.e., d1≈d2≈d3.

[0165] In some embodiments, as shown in Figure 9, Figure 9 is a cross-sectional view of the display panel 100 shown in Figure 3 along the section line CC, and the display panel 100 also includes: a plurality of light-concentrating structures 81 arranged between the boosting layer 40 and the encapsulation structure layer 30, and the plurality of light-concentrating structures 81 are arranged in a one-to-one correspondence with the plurality of pixel opening areas A1.

[0166] Exemplarily, the light-focusing structure 81 includes a prism, which can fully utilize reflected light and refracted light, thereby greatly improving the brightness of the display panel 100 and improving the light extraction efficiency of the display panel 100 .

[0167] In some embodiments, as shown in FIG10 , which is a cross-sectional view of the display panel 100 shown in FIG3 along section line CC, the display panel 100 further includes an anti-reflection layer 82 disposed between the build-up layer 40 and the encapsulation structure layer 30. The anti-reflection layer 82 includes a light blocker 82 a and a color filter film 82 b. The light blocker 82 a is located in the partition area A2, and the color filter film 82 b is located in the plurality of pixel opening areas A1.

[0168] In some examples, as shown in FIG10 , an anti-reflection layer 82 is disposed on a side of the encapsulation structure layer 30 away from the base substrate 10 , forming a COE (Color Filter on Encapsulation) structure. The anti-reflection layer 82 exhibits excellent anti-reflection properties, enhancing the display quality of the display panel 100 .

[0169] For example, the color filter 82b may include a first filter 821, a second filter 822, and a third filter 823. In an orthographic projection onto the substrate 10, the first filter 821 covers the red sub-pixel R, the second filter 822 covers the green sub-pixel G, and the third filter 823 covers the blue sub-pixel B. The color filter 82b can filter out noise in ambient light.

[0170] The light blocker 82 a may be a black matrix, and is configured to prevent light from different sub-pixels from interfering with each other, thereby ensuring the color purity of light emitted from the region where each sub-pixel is located, thereby improving the display effect of the display panel 100 .

[0171] In some embodiments, as shown in FIG11 , which is a cross-sectional view of the display panel 100 shown in FIG3 along section line CC, the display panel 100 further includes a touch structure layer 92 disposed on a side of the privacy protection layer 50 away from the base substrate 10 , and a first insulating layer 91 disposed between the privacy protection layer 50 and the touch structure layer 92 .

[0172] Exemplarily, the touch structure layer 92 can be a flexible multi-layer on cell (FMLOC) structure. The touch structure layer 92 can include a first touch insulation layer (not shown in the figure), a first metal grid layer 921, a second touch insulation layer 922, a second metal grid layer 923 and a third touch insulation layer (not shown in the figure). The first touch insulation layer can be located on the side of the first metal grid layer 921 close to the base substrate 10, the second touch insulation layer 922 can be located on the side of the first metal grid layer 921 away from the base substrate 10, the second metal grid layer 923 can be located on the side of the second touch insulation layer 922 away from the base substrate 10, and the third touch insulation layer can be located on the side of the second metal grid layer 923 away from the base substrate 10, so that the display panel 100 can realize the touch function.

[0173] Exemplarily, the thickness of the first insulating layer 91 ranges from 8 μm to 50 μm. For example, the thickness h3 of the first insulating layer 91 is 8 μm, 15 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, or 50 μm, etc., which is not limited here.

[0174] The first insulating layer 91 with a thickness h3 ranging from 8 μm to 50 μm can effectively prevent the first voltage signal of the first electrode layer 51 and the second voltage signal of the second electrode layer 53 from influencing the touch signal of the touch structure layer 92 .

[0175] An embodiment of the present disclosure further provides a method for manufacturing a display panel. As shown in FIG12 , the method for manufacturing a display panel includes steps R1 to R9.

[0176] R1. As shown in FIG13 , a base substrate 10 is provided.

[0177] For example, the base substrate 10 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier.

[0178] R2. As shown in FIG. 13 , a display function layer 20 is formed on one side of the base substrate 10 .

[0179] Exemplarily, the display function layer 20 includes a pixel circuit stack (not shown in the figure) and a light emitting device stack.

[0180] For example, the pixel circuit stack includes: an active layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a source / drain metal layer.

[0181] For example, the light-emitting device stack includes a planarization layer 21 and a pixel-defining layer 22 disposed on the side of the planarization layer 21 away from the base substrate 10. The pixel-defining layer 22 has multiple openings, and the light-emitting devices are disposed in the openings. The light-emitting device includes an anode, a light-emitting layer, and a cathode, which are sequentially disposed away from the base substrate 10. The anode provides holes to the light-emitting layer, and the cathode provides electrons to the light-emitting layer. The electrons and holes recombine in the light-emitting layer to form excitons, which emit light.

[0182] Exemplarily, the display function layer 20 further includes a support layer disposed on a side of the pixel defining layer 22 away from the base substrate 10 .

[0183] Exemplarily, during the step of forming the pixel defining layer 22, the second retaining wall 78 and the first retaining wall 79 are simultaneously formed, and in the first sub-area BB1, the first sub-layer 751 of the third barrier dam 75 is formed. The second retaining wall 78 and the first retaining wall 79 are spaced apart in a direction away from the display area AA. In the first sub-area BB1, the second retaining wall 78, the first retaining wall 79, and the first sub-layer 751 of the third barrier dam 75 are spaced apart in a direction away from the display area AA.

[0184] For example, the distance h2 between the first sublayer 751 of the third barrier dam 75 and the edge L of the peripheral region BB away from the display area AA is in a range of 50 μm to 200 μm. For example, the distance h2 between the first sublayer 751 of the third barrier dam 75 and the edge L of the peripheral region BB away from the display area AA is 50 μm, 70 μm, 100 μm, 150 μm, or 200 μm, etc., without limitation.

[0185] R3. As shown in FIG. 13 , a packaging structure layer 30 is formed on a side of the display function layer 20 away from the base substrate 10 .

[0186] For example, the encapsulation structure layer 30 may include a first inorganic encapsulation layer (not shown), an organic encapsulation layer 31, and a second inorganic encapsulation layer 32 stacked in sequence. The organic encapsulation layer 31 is located on a side of the second barrier rib 78 close to the display area AA.

[0187] In the peripheral area BB of the display panel 100 , the inorganic material layer (eg, including the first inorganic material layer and the second inorganic material layer) of the base substrate 10 and the inorganic material layer (eg, including the first inorganic encapsulation layer) of the encapsulation structure layer 30 form an encapsulation stack 60 .

[0188] R4. As shown in FIG. 13 to FIG. 15 , in the peripheral area BB, a first bonding line 71 and a second bonding line 72 are formed on a side of the packaging structure layer 30 away from the base substrate 10 , and the first bonding line 71 and the second bonding line 72 are spaced apart.

[0189] It should be noted that the structural diagram corresponding to step R4 in FIG13 is a cross-sectional view of the display panel 100 shown in FIG14 along section line GG, and FIG15 is a cross-sectional view of the display panel 100 shown in FIG14 along section line HH. To clearly illustrate the structural arrangement of the first and second bonding lines 71 and 72, the film layer farthest from the base substrate 10 in FIG14 is the film layer where the first and second bonding lines 71 and 72 are located, and the film layers on the side of the first and second bonding lines 71 and 72 away from the base substrate 10 are omitted.

[0190] Exemplarily, as shown in Figures 14 and 15, the first bonding wire 71 includes: a first electrode connecting wire 71a and two first leads 71b connected to the first electrode connecting wire 71a, the first electrode connecting wire 71a is arranged in a ring shape around the display area AA, one end of the two first leads 71b is connected to the first electrode connecting wire 71a, and the other end of the two first leads 71b is connected to the signal line of the source and drain metal layer through a via K passing through the packaging stack 60, and the signal line of the source and drain metal layer is connected to the driving chip, so that the first bonding wire 71 is connected to the driving chip.

[0191] The second bonding wire 72 includes: a second electrode connection line 72a and two second leads 72b connected to the second electrode connection line 72a. The second electrode connection line 72a is located in the first sub-area BB1. In the first sub-area BB1, the second electrode connection line 72a is located on the side of the first electrode connection line 71 away from the display area AA. The second lead 72b is located in the second sub-area BB2. One end of the second electrode connection line 72a is connected to one end of a second lead 72b, and the other end of the second electrode connection line 72a is connected to one end of another second lead 72b. The second lead 72b is connected to the signal line of the source and drain metal layer through a via (not shown in the figure) that passes through the package stack 60. The signal line of the source and drain metal layer is connected to the driver chip, thereby connecting the second bonding wire 72 to the driver chip. In addition, in the second sub-area BB2, the two first leads 71b are located between the two second leads 72b.

[0192] Exemplarily, the width of the first bonding line 71 is equal to the width of the second bonding line 72 . For example, the width of the first bonding line 71 and the width of the second bonding line 72 are both 120 μm.

[0193] R5. As shown in Figures 3, 13 and 16, in the peripheral area BB, at least one of the fourth blocking dam 76, the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 is formed on the side of the first overlapping line 71 and the second overlapping line 72 away from the base substrate 10, and the fourth blocking dam 76, the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 are arranged in a direction away from the display area AA.

[0194] It should be noted that the structural diagram corresponding to step R5 in FIG13 is a cross-sectional view of the display panel 100 shown in FIG3 along the cross-sectional line CC, and FIG16 is a cross-sectional view of the display panel 100 shown in FIG3 along the cross-sectional line FF.

[0195] For example, taking the formation of the fourth barrier dam 76, the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 as an example, a negative photoresist is used to form the second sublayer 752 of the fourth barrier dam 76, the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75. For example, the second sublayer 752 of the fourth barrier dam 76, the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 is formed using the same mask through a single patterning process. It should be noted that a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. In other words, the second sublayer 752 of the fourth barrier dam 76, the first barrier dam 73, the second barrier dam 74, and the third barrier dam 75 may have different heights or different thicknesses.

[0196] As shown in FIG3 and FIG13 , in the first sub-region BB1 , the second sub-layer 752 covers the first sub-layer 751 to form a third barrier dam 75 . The second barrier dam 74 covers the first barrier wall 79 .

[0197] In addition, the fourth barrier dam 76 covers the edge portion of the first electrode connecting line 71a close to the display area AA, the first barrier dam 73 covers the edge portion of the first electrode connecting line 71a away from the display area AA, the second barrier dam 74 covers the edge portion of the second electrode connecting line 72a close to the display area AA, and the third barrier dam 75 covers the edge portion of the second electrode connecting line 72a away from the display area AA.

[0198] As shown in Figures 3 and 16, in the second sub-area BB2, only one blocking dam M1 is provided on the side of the first blocking dam 73 away from the display area AA. The blocking dam M1 is connected not only to the portion of the second blocking dam 74 located in the first sub-area BB1, but also to the portion of the third blocking dam 75 located in the first sub-area BB1, and the blocking dam M1 covers the first retaining wall 79.

[0199] R6. As shown in FIG. 13 , a raised layer 40 is formed on a side of the packaging structure layer 30 away from the base substrate 10 .

[0200] Exemplarily, the raised layer 40 is located on a side of the fourth barrier dam 76 close to the display area AA.

[0201] Illustratively, the rising layer 40 is formed by an inkjet printing process, and the fourth barrier dam 76 is used to prevent the material forming the rising layer 40 from overflowing to the side of the fourth barrier dam 76 away from the display area AA.

[0202] For example, the thickness of the raised layer 40 is 30 μm.

[0203] For example, as shown in FIG9 , before forming the riser layer 40, a plurality of light-concentrating structures 81 may be formed on the side of the encapsulation structure layer 30 away from the base substrate 10, for example, by using a patterning process or an inkjet printing process to form the light-concentrating structures 81. Alternatively, as shown in FIG10 , before forming the riser layer 40, an anti-reflection layer 82 may be formed on the side of the encapsulation structure layer 30 away from the base substrate 10, for example, by using a patterning process or an inkjet printing process to form the anti-reflection layer 82. For an introduction to the light-concentrating structures 81 and the anti-reflection layer 82, reference may be made to the above content and will not be repeated here.

[0204] R7. As shown in FIG. 17 , a first electrode layer 51 is formed on a side of the raised layer 40 away from the base substrate 10 , and the first electrode layer 51 is connected to the first bonding wire 71 .

[0205] Exemplarily, the first electrode layer 51 is located on a side of the first barrier dam 73 close to the display area AA.

[0206] Exemplarily, the first electrode layer 51 is formed using a sputtering process or an inkjet printing process. The portion of the first electrode layer 51 near the edge of the first barrier dam 73 covers the first electrode connection line 71a of the first bonding line 71, thereby connecting the first electrode layer 51 to the first bonding line 71. The first barrier dam 73 is used to prevent the material forming the first electrode layer 51 from overflowing to the side of the first barrier dam 73 away from the display area AA.

[0207] For example, the material of the first electrode layer 51 may include, but is not limited to, phosphorescent nanomaterials, conductive nanowires, nanoparticles, graphene, and the like. Phosphorescent nanomaterials have better conductivity than indium tin oxide (ITO) materials at the same thickness, and are thinner and lighter at the same conductivity. Furthermore, phosphorescent nanomaterials have higher transmittance than indium tin oxide (ITO), thereby improving the luminous flux of the light-emitting device.

[0208] Exemplarily, the thickness of the first electrode layer 51 ranges from 0.5 μm to 10 μm. For example, the thickness of the first electrode layer 51 is 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 8 μm, 9 μm or 10 μm, etc., which is not limited here.

[0209] R8. As shown in FIG. 17 and FIG. 18 , a plurality of light-transmitting structures 54 and an electrochromic layer 52 are formed on a side of the first electrode layer 51 away from the base substrate 10 . The plurality of light-transmitting structures 54 are arranged in one-to-one correspondence with the plurality of pixel opening areas A1 .

[0210] Illustratively, the electrochromic layer 52 is located on a side of the second barrier dam 74 close to the display area AA.

[0211] In some examples, as shown in FIG17 , a plurality of light-transmitting structures 54 are formed on a side of the first electrode layer 51 away from the base substrate 10, and then an electrochromic layer 52 is formed on a side of the plurality of light-transmitting structures 54 away from the base substrate 10. In this case, the portion of the electrochromic layer 52 located in the pixel opening area A1 contacts only the second electrode layer 53 and does not contact the first electrode layer 51, while the portion of the electrochromic layer 52 located in the separation area A2 contacts both the first electrode layer 51 and the second electrode layer 53.

[0212] Exemplarily, the material of the light-transmitting structure 54 includes negative photoresist.

[0213] Exemplarily, a negative photoresist is used to form an initial light-transmitting layer on the side of the first electrode layer 51 away from the base substrate 10, and the initial light-transmitting layer is patterned to form a plurality of light-transmitting structures 54 arranged one-to-one corresponding to the plurality of pixel opening areas A1. After the plurality of light-transmitting structures 54 are formed, the first electrode layer 51 located in the separation area A2 is exposed.

[0214] In some examples, as shown in FIG6 , an electrochromic layer 52 is formed on a side of the first electrode layer 51 away from the base substrate 10, and a plurality of light-transmitting structures 54 are formed on a side of the electrochromic layer 52 away from the base substrate 10. In this case, the portion of the electrochromic layer 52 located in the pixel opening area A1 contacts only the first electrode layer 51 and does not contact the second electrode layer 53, while the portion of the electrochromic layer 52 located in the separation area A2 contacts both the first electrode layer 51 and the second electrode layer 53.

[0215] Exemplary materials of the electrochromic layer 52 include organic electrochromic materials, such as polythiophenes and their derivatives, viologens, tetrathiafulvalene, and metal phthalocyanine compounds. For example, the electrochromic layer 52 is formed using an inkjet printing process or a patterning process.

[0216] Exemplary materials for the electrochromic layer 52 include inorganic electrochromic materials. Examples of inorganic electrochromic materials include oxides or hydrated oxides of elements such as tungsten oxide, molybdenum oxide, platinum, iridium, osmium, palladium, ruthenium, nickel, and rhodium. For example, the electrochromic layer 52 is formed using a sputtering and etching process.

[0217] Exemplarily, the thickness of the electrochromic layer 52 ranges from 0.1 μm to 20 μm. For example, the thickness of the electrochromic layer 52 is 0.1 μm, 0.5 μm, 1 μm, 3 μm, 5 μm, 8 μm, 10 μm, 15 μm, 18 μm or 20 μm, etc., which is not limited here.

[0218] R9. As shown in FIG. 18 , a second electrode layer 53 is formed on a side of the electrochromic layer 52 and the plurality of light-transmitting structures 54 away from the base substrate 10 . The second electrode layer 53 is connected to the second bonding wire 72 .

[0219] Exemplarily, the second electrode layer 53 is located on a side of the third barrier dam 75 close to the display area AA.

[0220] Exemplarily, the second electrode layer 53 is formed using a sputtering process or an inkjet printing process. The portion of the second electrode layer 53 near the edge of the third barrier dam 75 covers the second electrode connection line 72a of the second bonding line 72, thereby connecting the first electrode layer 51 to the second bonding line 72. The third barrier dam 75 is used to prevent the material forming the second electrode layer 53 from overflowing to the side of the third barrier dam 75 away from the display area AA.

[0221] Exemplary materials for the second electrode layer 53 include, but are not limited to, phosphorescent nanomaterials, conductive nanowires, nanoparticles, and graphene. Phosphorescent nanomaterials offer better conductivity than indium tin oxide (ITO) materials at the same thickness, and are thinner and lighter at the same thickness. Furthermore, phosphorescent nanomaterials offer higher transmittance than indium tin oxide (ITO), thereby increasing the luminous flux of the light-emitting device.

[0222] Exemplarily, the thickness of the second electrode layer 53 ranges from 0.5 μm to 10 μm. For example, the thickness of the second electrode layer 53 is 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 8 μm, 9 μm or 10 μm, etc., which is not limited here.

[0223] The display panel 100 including the anti-peeping functional layer 50 is prepared through the above steps R1 to R10. By energizing the first electrode layer 51 and the second electrode layer 53, the part of the electrochromic layer 52 located in the separation area A2 will change color. At the same time, energizing the first electrode layer 51 and the second electrode layer 53 will not cause the part of the electrochromic layer 52 located in the pixel opening area A1 to change color, or will cause the part of the electrochromic layer 52 located in the pixel opening area A1 to change color weakly, so that as much light as possible can pass through without affecting the display effect of the display panel 100 at a normal viewing angle.

[0224] Moreover, the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 are arranged in a direction away from the display area AA, and the film layer where the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75 are located is arranged on the side of the film layer where the first overlapping line 71 and the second overlapping line 72 are located away from the base substrate 10, so that the first lead 71b does not need to cross the first blocking dam 73, the second blocking dam 74 and the third blocking dam 75, and the second lead 72b does not need to cross the third blocking dam 75, thereby reducing the risk of circuit breakage.

[0225] In some embodiments, as shown in FIG. 11 , the method for manufacturing the display panel 100 further includes forming a touch structure layer 92 on a side of the anti-peeping function layer 50 away from the base substrate 10 .

[0226] Illustratively, the touch structure layer 92 includes: a first touch insulating layer (not shown), a first metal mesh layer 921 , a second touch insulating layer 922 , a second metal mesh layer 923 and a third touch insulating layer (not shown) arranged in sequence.

[0227] A touch structure layer 92 is formed on the side of the anti-peek function layer 50 away from the base substrate 10, including: forming a first insulating layer 91 on the side of the second electrode layer 53 away from the base substrate 10, and sequentially forming a first touch insulating layer, a first metal mesh layer 921, a second touch insulating layer 922, a second metal mesh layer 923 and a third touch insulating layer on the side of the first insulating layer 91 away from the base substrate 10.

[0228] For example, the edge of the first insulating layer 91 away from the display area AA and the edge of the touch structure layer 92 away from the display area AA may offset the third barrier dam 75 .

[0229] Illustratively, the first insulating layer 91 , the first touch insulating layer, the second touch insulating layer 922 , and the third touch insulating layer are formed by a coating process.

[0230] Illustratively, the first metal grid layer 921 and the second metal grid layer 923 are formed by a patterning process.

[0231] By forming a touch structure layer 92 on the side of the anti-peeping function layer 50 away from the base substrate 10 , the display panel 100 can achieve a touch function.

[0232] As shown in FIG1 and FIG4 , some embodiments of the present disclosure provide a display device 1000, comprising: a display panel 100 as described in any of the above embodiments; and a driver chip configured to drive the display panel 100 to perform display. The driver chip is configured to transmit a first voltage signal to a first electrode layer 51 of an anti-peeping layer 50 of the display panel 100, and to transmit a second voltage signal to a second electrode layer 53 of the anti-peeping layer 50, thereby driving the anti-peeping layer 50 of the display panel 100 to implement an anti-peeping function.

[0233] The display device 1000 may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, a wearable display device, or the like. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the display device 1000. The display device 1000 includes the display panel 100 provided in any of the above embodiments. Therefore, the display device 1000 provided in the embodiments of the present disclosure has all the beneficial effects of the display panel 100 provided in any of the above embodiments, and further description thereof will not be given here.

[0234] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: a display area and a peripheral area surrounding the display area; The display panel further includes: A base substrate, a display function layer, an encapsulation structure layer, and an anti-peeping function layer; the anti-peeping function layer comprises: a first electrode layer, an electrochromic layer, and a second electrode layer sequentially arranged in a direction away from the base substrate; a first bonding wire and a second bonding wire located in the peripheral area and spaced apart from each other, the first bonding wire being connected to the first electrode layer and configured to transmit a first voltage signal to the first electrode layer; and the second bonding wire being connected to the second electrode layer and configured to transmit a second voltage signal to the second electrode layer; at least one of a first barrier dam, a second barrier dam, and a third barrier dam disposed in the peripheral area; The film layer where the first blocking dam, the second blocking dam and the third blocking dam are located is arranged on a side of the film layer where the first overlapping line and the second overlapping line are located away from the base substrate.

2. The display panel according to claim 1, wherein The display panel includes the first barrier dam, the second barrier dam, and the third barrier dam; The first barrier dam, the second barrier dam and the third barrier dam are arranged in a direction away from the display area; the first electrode layer is located on a side of the first barrier dam close to the display area, the electrochromic layer is located on a side of the second barrier dam close to the display area, and the second electrode layer is located on a side of the third barrier dam close to the display area.

3. The display panel according to claim 1 or 2, wherein: The display panel further includes a binding area located on a side of the peripheral area away from the display area; the peripheral area includes a first sub-area and a second sub-area that are connected to each other, and the second sub-area is located between the display area and the binding area; In the second sub-region, the second barrier dam is merged with the third barrier dam.

4. The display panel according to any one of claims 1 to 3, wherein: The first bonding wire includes a first electrode connection wire, and the second bonding wire includes a second electrode connection wire; The first electrode connection line is arranged around the display area; The second electrode connection line is located in the first sub-area of ​​the peripheral area; and in the first sub-area, the second electrode connection line is located on a side of the first electrode connection line away from the display area; The first electrode layer is connected to the first electrode connecting line, and the second electrode layer is connected to the second electrode connecting line.

5. The display panel according to claim 4, wherein: The first bonding wire further comprises at least one first lead wire, and the second bonding wire further comprises at least one second lead wire; the at least one first lead wire and the at least one second lead wire are located in the second sub-region of the peripheral region; One end of the first lead is connected to the first electrode connection line, and the other end of the first lead is connected to the driving chip; One end of the second lead is connected to the second electrode connection line, and the other end of the second lead is connected to the driving chip. The display panel according to claim 5 , wherein: In the second sub-region, the first lead passes under the second barrier dam and the third barrier dam.

7. The display panel according to claim 5 or 6, further comprising: a bending area between the binding area of ​​the display panel and the second sub-area; The display function layer includes a source-drain electrode layer, and the display panel also includes at least one first signal line and at least one second signal line arranged in the source-drain electrode layer; one end of the first signal line is connected to the first lead, and the other end of the first signal line extends to the binding area through the bending area, and one end of the second signal line is connected to the second lead, and the other end of the second signal line extends to the binding area through the bending area.

8. The display panel according to any one of claims 5 to 7, wherein: The first bonding wire includes two first leads, and the second bonding wire includes two second leads, wherein the two second leads are located on both sides of the two first leads.

9. The display panel according to any one of claims 1 to 8, wherein: The third barrier dam includes: a first sublayer and a second sublayer; The first sub-layer is located in the first sub-region of the peripheral region; The second sub-layer includes a first sub-portion and a second sub-portion that are connected to each other. The first sub-portion is located in the first sub-region and covers the first sub-layer. The second sub-portion is located in the second sub-region of the peripheral region.

10. The display panel according to any one of claims 1 to 9, wherein: The encapsulation structure layer includes: an organic encapsulation layer; The display panel further includes: a first barrier wall located in the peripheral area and surrounding the display area, the organic encapsulation layer being located on a side of the first barrier wall close to the display area; the second barrier dam covering the first barrier wall; and / or, The display panel also includes: a second retaining wall located in the peripheral area and surrounding the display area, the second retaining wall is located on a side of the first retaining wall close to the display area, and the organic encapsulation layer is located on a side of the second retaining wall close to the display area; in an orthographic projection onto the base substrate, the second retaining wall is located between the first retaining dam and the second retaining dam, or the first retaining dam covers the second retaining wall.

11. The display panel according to any one of claims 1 to 10, wherein: The first bonding wire includes a first electrode connection wire, and the second bonding wire includes a second electrode connection wire; The first barrier dam covers the edge portion of the first electrode connection line away from the display area, the second barrier dam covers the edge portion of the second electrode connection line close to the display area, and the third barrier dam covers the edge portion of the second electrode connection line away from the display area.

12. The display panel according to claim 11, further comprising: a raised layer disposed between the encapsulation structure layer and the anti-peeping function layer, and a fourth blocking dam disposed in the peripheral area; The fourth barrier dam is located on a side of the first barrier dam close to the display area, and the raised layer is located on a side of the fourth barrier dam close to the display area; The fourth barrier dam covers an edge portion of the first electrode connecting line close to the display area.

13. The display panel according to claim 12, wherein: The thickness of the increased layer ranges from 20 μm to 100 μm.

14. The display panel according to claim 12 or 13, wherein: The display area includes a plurality of pixel opening areas and a separation area located between the plurality of pixel opening areas; The display panel further includes: a plurality of light-concentrating structures disposed between the raising layer and the encapsulation structure layer, wherein the plurality of light-concentrating structures are disposed in a one-to-one correspondence with the plurality of pixel opening areas; or, The display panel further includes an anti-reflection layer disposed between the boosted layer and the encapsulation structure layer; the anti-reflection layer includes a light blocker and a color filter film, the light blocker is located in the separation area, and the color filter film is located in the plurality of pixel opening areas.

15. The display panel according to any one of claims 1 to 14, wherein: The width of the first overlap line ranges from 100 μm to 500 μm; The width of the second lap line ranges from 100 μm to 500 μm.

16. The display panel according to any one of claims 1 to 15, wherein: The material of the electrochromic layer includes: polythiophene and its derivatives, viologens, tetrathiafulvalene, metal phthalocyanine compounds, tungsten oxide, molybdenum oxide and any oxide or hydrated oxide of any element among platinum, iridium, osmium, palladium, ruthenium, nickel and rhodium.

17. The display panel according to any one of claims 1 to 16, wherein: The display area includes a plurality of pixel opening areas, and the anti-peeping functional layer further includes a plurality of light-transmitting structures arranged in a one-to-one correspondence with the plurality of pixel opening areas; The light-transmitting structure is located between the first electrode layer and the second electrode layer, and the light-transmitting structure is in contact with the first electrode layer or the second electrode layer.

18. The display panel according to any one of claims 1 to 17, further comprising: A touch structure layer is provided on a side of the anti-peeping function layer away from the display panel, and an insulating layer is provided between the anti-peeping function layer and the touch structure layer.

19. A method for manufacturing a display panel, the display panel comprising a display area and a peripheral area surrounding the display area, the display area comprising a plurality of pixel opening areas; the method comprising: providing a substrate; forming a display function layer on one side of the base substrate; forming a packaging structure layer on a side of the display function layer away from the base substrate; In the peripheral area, a first bonding line and a second bonding line are formed on a side of the packaging structure layer away from the base substrate, wherein the first bonding line and the second bonding line are spaced apart; In the peripheral region, at least one of a fourth blocking dam, a first blocking dam, a second blocking dam, and a third blocking dam is formed on a side of the first and second bonding lines away from the base substrate; forming a raised layer on a side of the packaging structure layer away from the substrate; forming a first electrode layer on a side of the raised layer away from the base substrate, wherein the first electrode layer is connected to the first bonding wire; forming a plurality of light-transmitting structures and an electrochromic layer on a side of the first electrode layer away from the base substrate, wherein the plurality of light-transmitting structures are arranged in a one-to-one correspondence with the plurality of pixel opening areas; A second electrode layer is formed on a side of the electrochromic layer and the plurality of light-transmitting structures away from the base substrate, the second electrode layer is connected to the second bonding wire; and the light-transmitting structure is in contact with the first electrode layer or the second electrode layer.

20. A display device comprising: The display panel according to any one of claims 1 to 18; The driving chip is configured to transmit a first voltage signal to the first electrode layer of the anti-peeping function layer of the display panel, and transmit a second voltage signal to the second electrode layer of the anti-peeping function layer.

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