Semiconductor device with an integrated heterojunction diode and method for manufacturing

Abstract

The invention relates to a semiconductor device (10) with an integrated heterojunc- tion diode (12) comprising: - a substrate (14) of a first conductive type acting as drain region, - a first crystalline layer (16) of a second conductivity type formed on the sub- strate (14) and acting as drift region, and - a source structure (18) provided on the first crystalline layer (16), the source structure (18) comprising a p-well region (20), an n+source region (22), and a p+short region (24), wherein a recess (26) comprising a bottom crystalline layer (28) is formed in the source structure (18), the recess (26) extending vertically through the p+short region (24) such that for forming the integrated heterojunction diode (12) the bottom crys- talline layer (28) of the recess (26) is in contact with a) the first crystalline layer (16), or b) an additional semiconductor layer (42) being formed on the first crystalline layer (16), and wherein the additional semiconductor layer (42) is of the same conductivity type as the first crystalline layer (16). Furthermore, the invention relates to a method for manufacturing the above semi- conductor device (10).

Description

[0001] -Description

[0002] Semiconductor device with an integrated heterojunction diode and method for manufacturing

[0003] Technical Field

[0004] The invention relates to a semiconductor device with an integrated heterojunction diode.

[0005] Furthermore, the invention relates to a method for manufacturing a semiconductor device with an integrated heterojunction diode.

[0006] Background Art

[0007] Power semiconductor devices are used as switches controlling the current flow through various electronic systems. Many power semiconductor devices make use of a metal-oxide-sem iconductor (MOS) structure. Devices that comprise a MOS structure are for example a power MOS field-effect transistor (MOSFET) designed to handle significant power levels or an insulated-gate bipolar transistor (IGBT).

[0008] While silicon (Si) is a very common semiconductor material for power semiconductor devices, power semiconductor devices formed with wide-bandgap semiconductor materials as substrate such as a silicon carbide substrate (SiC substrate) composed of silicon (Si) and carbon (C) bonded to each other at a composition ratio of 1 :1 are becoming more and more important, in particular for MOSFETs.

[0009] For example, SiC offers a number of attractive characteristics for high-voltage power semiconductors when compared to commonly used Si. Exemplarily the much higher breakdown field strength and a high thermal conductivity of SiC in principle allow creating devices which outperform by far the corresponding Si devices and enable reaching otherwise unattainable efficiency levels. SiC based power MOSFETs may offer superior dynamic performance over conventional Si based power MOSFETs. In other words, the advantageous electro-thermal properties of SiC can provided significant improvements to the design trade-off between the transistor’s specific on- state resistance Ron* and its breakdown voltage (BV). At the same time, the continuous advances in the control of the gate and the unipolar character of these devices have allowed for operation at higher switching frequencies than in Silicon, hence facilitating reductions in the size of the passive components.

[0010] Nevertheless, the wide-range adoption of SiC in MOSFETs has been impeded by some limitations. Due to the large (~ 3 V) built-in voltage of the SiC p-n junction, the slow removal of minority carriers during reverse recovery, and the negative impacts of bipolar degradation on Ron*, operation of the body diode as a freewheeling diode appears to be unattractive for SiC based power semiconductor devices rated below ~ 4.5 kV.

[0011] For this reason, designs based on the integration of a heterojunction diode in conventional planar SiC MOSFETs have been proposed. These designs aim specifically to delay the activation of the body diode to higher reverse current values by using the heterojunction as a freewheeling diode with a lower turn-on voltage than the p-n junction of the body diode instead. In addition, their other primary goal is to reduce the leakage current through the body diode and hence resolve the issues seen in SiC Schottky diodes. Although MOSFETs with integrated heterojunction diodes may improve some of these aspects of operation, they also have some drawbacks:

[0012] However, one particular problem is that the integrated heterojunction diode cannot handle efficiently very high reverse currents close to or above the transistor’s rated value, which can appear during fault conditions. In addition, the use of the heterojunction diode as the main blocking junction will expose the heterojunction diode to high electric fields, which can amplify the leakage current.

[0013] Furthermore, the heterojunction diode may not be able to efficiently collect the holes that are generated during the off-state through impact ionisation because it is positioned far from the body diode of the semiconductor device. Instead, the entire hole current is forced to flow through the p-well. At avalanche conditions the hole current can create a sizeable voltage drop across the p-well and thus cause latch-up of the MOSFET’s parasitic bipolar junction transistor (BJT).

[0014] Summary of invention

[0015] It is an object of the invention to provide means to improve the performance of semiconductor devices having an integrated heterojunction diode. Furthermore, it is an object of the invention to improve the high temperature reliability of the semiconductor device and / or to enhance the suppression of the MOSFET’s parasitic BJT. It is a further objection of the invention to enable a delayed activation of the body diode towards larger reverse currents and / or to decrease the reverse recovery losses over a wide operating range of the semiconductor device.

[0016] The object of the invention is solved by the features of the independent claims. Modified embodiments are detailed in the dependent claims.

[0017] Thus, the object is solved by a semiconductor device with an integrated heterojunction diode comprising:

[0018] - a substrate of a first conductive type acting as drain region,

[0019] - a first crystalline layer of a second conductivity type formed on the substrate and acting as drift region, and

[0020] - a source structure provided on the first crystalline layer, the source structure comprising a p-well region, an n+source region, and a p+short region, wherein a recess comprising a bottom crystalline layer is formed in the source structure, the recess extending vertically through the p+short region such that for forming the integrated heterojunction diode the bottom crystalline layer of the recess is in contact with a) the first crystalline layer, or b) an additional semiconductor layer being formed on the first crystalline layer, and wherein the additional semiconductor layer is of the same conductivity type as the first crystalline layer.

[0021] Additionally, the object is solved by a method for manufacturing a semiconductor device with an integrated heterojunction diode comprising the steps of - providing a substrate of a first conductive type acting as drain region,

[0022] - forming a first crystalline layer of a second conductivity type on the substrate, wherein the first crystalline layer acts as drift region,

[0023] - forming a source structure on the first crystalline layer, the source structure comprising a p-well region, an n+source region, and a p+short region,

[0024] - forming the integrated heterojunction diode by etching a recess into the source structure, extending vertically through the p+short region, and forming a bottom crystalline layer on a bottom of the etched recess, such that the formed bottom crystalline layer is in contact with a) the first crystalline layer, or b) an additional semiconductor layer that has been formed on the first crystalline layer, wherein the additional semiconductor layer is of the same conductivity type as the first crystalline layer.

[0025] One aspect of the invention is that the integrated heterojunction diode is not formed on the very top of the semiconductor device. Instead, the semiconductor device comprises a recess, e.g. in the form of a trench generated by etching, in the source structure and the integrated heterojunction diode is formed by the bottom crystalline layer of said recess and a) the vertically adjacent first crystalline layer, or b) the vertically adjacent additional semiconductor layer.

[0026] In other words, the integrated heterojunction diode is recessed in the direction of the drift region due to the use of the trench. This provides a number of important advantages:

[0027] The vertically lower position of the integrated heterojunction diode (compared to forming the integrated heterojunction diode on the very top of the semiconductor device) allows the activation of the body diode of the semiconductor device to be delayed to larger reverse currents Isd (where Isd > 0). As a result, unipolar conduction can be maintained over a wider range of operating conditions of the semiconductor device. This allows the switching losses that are incurred during the reverse recovery of the semiconductor device’s freewheeling integrated heterojunction diode to be reduced at these additional operating points. The position of the integrated heterojunction diode further has a direct impact on the off-state reliability of the semiconductor device at high temperatures. One of the key weaknesses of semiconductor devices, in particular power MOSFETs, is their susceptibility to latch-up of the parasitic BJT as a result of the voltage drop that the hole current leaves across the resistance of the p-well at avalanche conditions.

[0028] MOSFETs have a body diode and a parasitic bipolar junction transistor (BJT) as an integral part of their structure: Regarding the body diode, the body diode is formed by the p-n junction formed by the p-well region and the drain region.

[0029] Regarding the BJT, the BJT is formed by the p-well region that serves as the base, the n+source region that serves as the emitter and the drain region that serves as the collector. It is important to keep this BJT off for all time of the operation of the MOSFET by keeping the potential of the base as close to the emitter potential as possible. Otherwise, the potential at the base would turn on the BJT and lead the MOSFET into the latch-up condition, which could destroy the MOSFET.

[0030] The problem of the parasitic BJT becomes especially acute at higher operating temperatures due to the concomitant reduction of the turn-on voltage of the junction formed by the p-well region and the n+source region. However, due to the recessed integrated heterojunction diode, a considerable proportion of the holes generated as a result of impact ionisation can be collected not through the body diode of the semiconductor device, but instead through the integrated heterojunction diode. Thus, the hole current through the resistance of the p-well region can be reduced, and hence the danger of bipolar latch-up of the semiconductor device can be alleviated.

[0031] In other words, semiconductor device according to the invention can provide a superior high temperature reliability compared to semiconductor devices also featuring a built-in heterojunction diode through the enhanced suppression of the MOSFET’s parasitic BJT. In addition, the semiconductor device according to the invention allows the activation of the body diode to be delayed to larger reverse currents and hence makes it possible to decrease the reverse recovery losses over a wider op- erating range than in prior art semiconductor devices also featuring a built-in heterojunction diode.

[0032] The semiconductor device has several layers on top of each other - e.g. the first crystalline layer being provided on the substrate and the source structure being provided on the first crystalline layer. In the context of this application the vertical direction of the semiconductor device is the direction from the substrate towards the source structure. “Up”, “upwards”, or “on top” means a location or direction closer to the source, while “down”, “downwards”, or “below” specifies a location or direction closer to the substrate.

[0033] Regarding the first crystalline layer and the additional semiconductor layer, these two layers are of the same conductivity type. Furthermore, these two layers are preferably of the same material and are preferably formed in the same growing step.

[0034] Preferably the semiconductor device is a power semiconductor device. Further preferably the power semiconductor device is a 0.65 kV to 15 kV volt class power semiconductor device. Further preferably the power semiconductor device is configured for current ratings of 5 A to 600 A in a temperature range of 25 °C to 175 °C. According to another preferred embodiment of the invention the semiconductor device is configured as a MOSFET, a MISFET (metal insulator semiconductor field-effect transistor), a JFET (junction field-effect transistor), an IGBT, or a BIGT (bi-mode insulated gate transistor). Particularly preferably, the semiconductor device is a power MOSFET.

[0035] According to a preferred embodiment of the invention, the semiconductor device is of a semiconductor material having a bandgap equal to or greater than the bandgap of silicon. Particularly preferably, the bandgap is greater than that of silicon. Further preferably, the bandgap of the semiconductor material is greater than 1.5 eV and further preferably greater than 2 eV.

[0036] Regarding the material of the semiconductor device and according to another preferred embodiment of the invention, the semiconductor device is of a semiconductor material selected from the group consisting of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium(lll) oxide (Ga2O3), aluminium nitride (AIN), aluminium gallium nitride (AlxGai-xN), gallium arsenide (GaAs), and diamond. Preferably, the substrate, the first crystalline layer, as well as the source structure are based on the above-mentioned semiconductor materials. Preferably, the semiconductor material is SiC or GaN, and most preferably the semiconductor material is SiC. Particularly preferably, the semiconductor device is a SiC power MOSFET.

[0037] Preferably, the integrated heterojunction diode is an anti-parallel heterojunction diode. The integrated heterojunction diode can in principle be formed by choosing a different material for the bottom crystalline layer and the first crystalline layer, or regarding variant b) by choosing a different material for the bottom crystalline layer and the additional semiconductor layer.

[0038] However, according to a preferred embodiment of the invention the bottom crystalline layer is of the same material as the first crystalline layer, but of a different polytype than the first crystalline layer. Polytypes are variations of the same chemical compound that are identical in two dimensions and differ in the third, in this case in the vertical dimension. Examples of polytypes of SiC, for which more than 250 polytypes exist, are for example 6H, 15R, 4H, or 3C. The letters C, H, and R denote the overall lattice type as being cubic (C), hexagonal (H), or rhombohedral (R). Preferably, the polytype of the bottom crystalline layer of SiC is 3C. Further preferably the polytype of the first crystalline layer of SiC and / or the additional semiconductor layer of SiC is 4H.

[0039] As already mentioned, the integrated heterojunction diode is recessed in the direction of the drift region. In connection to this and according to another preferred embodiment of the invention, the additional semiconductor layer has a thickness in the vertical direction of no more than 75 % of the source structure, and preferably no more than 50 % of the source structure. Furthermore, it is preferred that the thickness in the vertical direction of the additional semiconductor layer is such that an upper surface of the additional semiconductor layer is on a lower vertical level than a lower end of the p+short region. Thus, the additional semiconductor layer preferably has horizontally contact to the p-well region of the source structure. Regarding the bottom crystalline layer and according to another preferred embodiment of the invention, a semiconductor device is provided wherein the bottom crystalline layer is a p-type or an n-type doped layer. It is possible that the bottom crystalline layer is a doped p-type layer, or a doped n-type layer. Further alternatively, it is also possible that the bottom crystalline layer is of alternate p-type and n-type doping. Further preferably, a thickness of the bottom crystalline layer is in a range of 5 nm to 5000 nm. Most preferably doping and / or thickness of the bottom crystalline layer is such that a reliable blocking performance of the integrated heterojunction diode during the off-state of the semiconductor device is achieved.

[0040] According to another preferred embodiment of the invention a band offset of the conduction band of the bottom crystalline layer to the conduction band of the first crystalline layer or to the conduction band of the additional semiconductor layer in the integrated heterojunction diode is smaller than the bandgap of the semiconductor material of the substrate. Preferably, the band offset between the two conduction bands is at least 25 meV.

[0041] While the integrated heterojunction diode blocks the conduction of electrons during the off-state of the semiconductor device, the integrated heterojunction diode allows holes to pass through it. Thus, the holes that are generated in the drift region at a large reverse bias through impact ionisation can reach a source contact by passing not only through the p-well region but also via the integrated heterojunction diode. The effectiveness of the hole extraction is higher the closer the integrated heterojunction diode is positioned to the body diode of the semiconductor device.

[0042] According to another preferred embodiment of the invention a semiconductor device is provided wherein the semiconductor device further comprises a planar gate structure, comprising an electrically conductive gate layer and a gate insulating layer, and wherein the gate insulating layer at least partially covers the n+source region and the p-well region of the source structure. In other words, the semiconductor device is preferably of the planar type, having the advantage that as the gate structure is on the surface, electrodes can be attached to the surface after processing. However, also the channels of the semiconductor device are arranged horizontally giving each individual cell of the semiconductor device a rather large cell area.

[0043] According to another preferred embodiment of the invention the semiconductor device further comprises as source contact an Ohmic contact formed with the n+source region and the p+short region of the source structure. Preferably, the Ohmic contact is formed with the n+source region and the p+short region by depositing a layer of metal, preferably aluminium and / or titanium, on top of the source structure.

[0044] In connection to this and according to another preferred embodiment of the invention, the Ohmic contact further contacts the bottom crystalline layer. It is preferred to also bias the bottom crystalline layer through the Ohmic contact in order to minimize the forward voltage drop of the semiconductor device.

[0045] Alternatively, and according to another preferred embodiment of the invention, the semiconductor device further comprises a Schottky contact formed with the bottom crystalline layer by an intermediate metal between the bottom crystalline layer and the source contact. In other words, in this preferred alternative a Schottky contact is formed with the bottom crystalline layer in order to improve the blocking performance of the semiconductor device during the off-state and raise the turn-on voltage of the integrated heterojunction diode Vh-th, to ~ 1 V. For this purpose, preferably an intermediate untreated metal, for example nickel, is deposited in between the source contact and the bottom crystalline layer.

[0046] It is further possible to make use of multiple metal layers or other semiconductor layers above the bottom crystalline layer, which can respectively form additional Schottky contacts and / or Ohmic contacts and / or further heterojunctions.

[0047] According to another embodiment of the invention a semiconductor device is provided wherein the n+source region is arranged on top of the p+short region. Due to the vertical arrangement of the n+source region and p+short region on top of each other (instead of next to each other) a wider contact window for the integrated heterojunction diode can be made available by etching the recess through the entire part of the p+short region. Moreover, the larger geometrical dimensions of the contact window can also simplify the fabrication of the semiconductor device by loosening the tolerances required by the processing technology. In order to avoid compromising the reliability of the semiconductor device by the wider contact window, the p+short region is positioned right below the n+source region. The p+short region - i.e. the region of high p-type doping - can preferably be achieved by means of a tilted implant through the recess for the integrated heterojunction diode. The biasing of the p-well region can hence be performed along the vertical portion of the Ohmic contact formed as source contact. In this preferred embodiment it is further preferred that an upper surface of the bottom crystalline layer is on the same vertical level as a lower end of the p+short region.

[0048] According to an alternative preferred embodiment of the invention, the n+source region and the p+short region are arranged next to each other on the same vertical level. In contrast to the variant described above, where the n+source region is arranged vertically on top of the p+short region, in this preferred embodiment the n+source region and the p+short region are arranged horizontally next to each other.

[0049] Independent of the arrangement of the n+source region and the p+short region to each other (vertically on top of each other or horizontally next to each other) and according to another preferred embodiment of the invention a semiconductor device is provided wherein the upper surface of the bottom crystalline layer is vertically at the same level or below the lower end of the p+short region. Like this the bottom crystalline layer preferably has horizontally contact to the p-well region of the source structure.

[0050] In case the n+source region is arranged on top of the p+short region, it is preferred that the upper surface of the bottom crystalline layer is on the same vertical level as a lower end of the p+short region.

[0051] Furthermore, in case the n+source region and the p+short region are arranged horizontally next to each other, it is preferred that the upper surface of the bottom crystalline layer is vertically below the lower end of the p+short region. In another further preferred embodiment of the invention the semiconductor device comprises additional p+type layers. In this regard it is preferred that the semiconductor device further comprises one or more additional p+type layers positioned vertically below the integrated heterojunction diode, adjacent to the crystalline bottom layer and within the first crystalline layer or within the additional semiconductor layer. The additional p+type layers are most preferred for the embodiment of the semiconductor device where the n+source region is arranged on top of the p+short region.

[0052] The additional p+type layers have the advantage that they give the integrated heterojunction diode a protection from high electric fields near the body diode. By inserting the additional p+type layers below the integrated heterojunction diode, the high electric field will be shifted to the bottom comers of the additional p+type layers, while the field at the integrated heterojunction diode will be reduced. As a result, the leakage current through the integrated heterojunction diode is decreased. In addition, the additional p+type layers can provide a low-resistance path for the holes generated at avalanche conditions. Thus, the additional p+type layers aid the extraction of holes through the recessed heterojunction diode and further reduce the danger of a latch-up of the BJT. In other words, the additional p+type layers reduce the leakage current through the integrated heterojunction diode and at the same improve the extraction of holes at avalanche condition. Preferably, the additional p+type layers are highly doped. This has the advantage that a full depletion of the additional p+type layer is avoided before avalanche breakdown conditions.

[0053] In connection to this and according to another preferred embodiment of the invention an Ohmic contact is formed with the additional p+type layers and the source contact. In other words, the additional p+type layers are preferably effectively biased to the source contact via the Ohmic contact. Thus, the additional p+type layers are preferably not floating. The connection of the additional p+type layers to the source contact further helps to avoid a full depletion of the additional p+type layers as the integrated heterojunction diode allows in the off-state the holes to move freely form the drift region to the source contact, however not the other way around. Thus, if the additional p+type layers were left floating below the integrated heterojunction diode, they could get fully depleted of holes during the off-state. This in turn would leave only the negatively charged acceptor dopants behind, thereby causing an increase in the electric field near the integrated heterojunction diode.

[0054] According to another preferred embodiment of the invention, the semiconductor device has a stripe design. In other words, the semiconductor device preferably does not make use a cellular structure, but of the stripe design, where the layout of the gate structure constitutes of parallel stripes. Even though the stripe design is less efficient than a cellular structure of equivalent resolution in terms of channel density, it can cope with smaller pitch. Another advantage of the planar stripe structure is that it is less susceptible to failure during avalanche breakdown in which the parasitic BJT turns on from sufficient forward bias.

[0055] According to an alternative preferred embodiment of the invention, where no stripe design is used, the semiconductor device has rotational symmetry, with a rotation axis being perpendicular to the first crystalline layer, and wherein the rotation axis is arranged in a centre of a gate insulating layer of a planar gate structure. The rotational symmetry can for example be a 6-fold, 8-fold-12-fold, or 24-fold rotational symmetry. Alternatively, it is also possible to have a very high-fold rotational symmetry that can - within manufacturing tolerances - be described as infinite rotation symmetry. Such an ALL design, has the advantage that it has as a proportion of the total active area an increased area for the integrated heterojunction diode compared to the stripe design.

[0056] Further characteristics and advantages of semiconductor device are evident to the skilled person by the following description of the method for manufacturing the semiconductor device and the further description of the specific embodiments.

[0057] As already mentioned, the invention is also directed to the method for manufacturing the semiconductor device with an integrated heterojunction diode comprising the steps of

[0058] - providing the substrate of the first conductive type acting as drain region,

[0059] - forming the first crystalline layer of the second conductivity type on the substrate, wherein the first crystalline layer acts as drift region,

[0060] - forming the source structure on the first crystalline layer, the source structure comprising the p-well region, the n+source region, and the p+short region,

[0061] - forming the integrated heterojunction diode by etching the recess into the source structure, extending vertically through the p+short region, and forming the bottom crystalline layer on the bottom of the etched recess, such that the formed bottom crystalline layer is in contact with a) the first crystalline layer, or b) the additional semiconductor layer that has been formed on the first crystalline layer, wherein the additional semiconductor layer is of the same conductivity type as the first crystalline layer.

[0062] Regarding the first crystalline layer and the additional semiconductor layer, these two layers are preferably not only of the same conductivity type, but also formed in the same growing step. In other words, it is preferred that the step of forming the first crystalline layer of the second conductivity type on the substrate, comprises forming the first crystalline layer and the additional semiconductor layer of the second conductivity type on the substrate.

[0063] According to another preferred embodiment of the invention the step of forming the first crystalline layer of the second conductivity type on the substrate comprises epitaxially growing the first crystalline layer on the substrate. Epitaxially growing the first crystalline layer ensures that the first crystalline layer has a well-defined orientation. As mentioned above, this preferably also means that the additional semiconductor layer is preferably formed by epitaxially growing.

[0064] According to another preferred embodiment of the invention the step of forming the bottom crystalline layer on the bottom of the etched recess comprises selective epitaxially growing the bottom crystalline layer on the first crystalline layer or on the additional semiconductor layer.

[0065] Selective area epitaxy is the local growth of epitaxial layer through a patterned amorphous dielectric mask deposited on the surface of the bottom of the etched recess. Growth conditions are selected to ensure epitaxial growth on the exposed surface, but not on the dielectric mask. In other words, after the recess is etched, the inte- grated heterojunction diode is formed at its bottom - which is either the first crystalline layer or the additional semiconductor layer depending to the vertical depth of the etching step - by selectively epitaxially growing the bottom crystalline layer. The bottom crystalline layer may further be doped p-type or n-type, and its thickness can be controlled in order to guarantee a reliable blocking performance during the off- state.

[0066] Particularly preferably, the first crystalline layer and the additional semiconductor layer are 4H-SiC and the integrated heterojunction diode is formed at the bottom of the etched recess by growing a layer of 3C-SiC at a sufficiently low temperature around 1100°C.

[0067] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0068] In the drawings:

[0069] Fig. 1 schematically shows a semiconductor device with an integrated heterojunction diode according to a preferred embodiment of the invention,

[0070] Fig. 2 schematically shows a semiconductor device with an integrated heterojunction diode according to another preferred embodiment of the invention, where a recess is less deep as in the embodiment of figure 1 ,

[0071] Fig. 3 schematically shows a semiconductor device with an integrated heterojunction diode according to a third preferred embodiment of the invention, where an n+source region is arranged on top of a p+short region,

[0072] Fig. 4 schematically shows a semiconductor device with an integrated heterojunction diode according to a fourth preferred embodiment of the invention, where a recess is less deep as in the embodiment of figure 3,

[0073] Fig. 5 schematically shows a semiconductor device with an integrated heterojunction diode according to a fifth preferred embodiment of the invention, where an additional p+type layer is positioned vertically below the integrated heterojunction diode,

[0074] Fig. 6 schematically shows a semiconductor device with an integrated heterojunction diode according to a further preferred embodiment of the invention, where two additional p+type layers are positioned vertically below the integrated heterojunction diode,

[0075] Fig. 7 schematically shows two views of a semiconductor device with an integrated heterojunction diode according to a further preferred embodiment of the invention, where the semiconductor device has rotational symmetry, and

[0076] Fig. 8 schematically shows in a) a TCAD model of an 1 -dimensional 3C-SiC / 4H- SiC heterojunction diode and in b) its on-state performance predicted by simulations for different doping levels in the 3C-SiC layer and different source contact designs compared with a conventional 4H-SiC PiN diode and compared with a conventional 4H-SiC Schottky diode.

[0077] Description of embodiments

[0078] Figure 1 schematically shows a half unit cell cross-section of a semiconductor device 10 with an integrated heterojunction diode 12 according to a preferred embodiment of the invention. In this embodiment the semiconductor device 10 is a MOSFET and comprises a substrate 14 of a first conductive type - in this case of N type - acting as drain region, a first crystalline layer 16 of a second conductivity type formed on the substrate 14 and acting as drift region, and a source structure 18 provided on the first crystalline layer 16. The source structure 18 comprises a p-well region 20, an n+source region 22, and a p+short region 24. In this embodiment the n+source region 22 and the p+short region 24 are arranged next to each other on the same vertical level. A recess 26 comprising a bottom crystalline layer 28 is formed in the source structure 18. The recess 26 extends vertically through the p+short region 24 such that for forming the integrated heterojunction diode 12 the bottom crystalline layer 28 of the recess 26 is in contact with the first crystalline layer 16.

[0079] Regarding the vertical depth of the recess 26 it can be seen in figure 1 , that in this embodiment the n+source region 22 and the p+short region 24 are arranged in the top portion of the p-well region 20 and that the upper surface of the bottom crystalline layer 28 is vertically below the lower end of the p+short region 24.

[0080] In this embodiment the semiconductor device 10 is based on silicon carbide as semiconductor material. The first crystalline layer 16 is generated by epitaxial growth on the substrate 14, such that the polytype 4H-SiC is formed. After the recess 26 is etched the integrated heterojunction diode 12 is formed at the bottom of the recess 26 by growing the bottom crystalline layer 28. The bottom crystalline layer 28 is of the same material as the first crystalline layer 16, but of a different polytype - in this case 3C-SiC. The bottom crystalline layer 28 is formed by selective epitaxially growing the bottom crystalline layer 28 on the first crystalline layer 16 at temperature at - 1100 °C.

[0081] As can be seen in figure 1 , the semiconductor device 10 further comprises a planar gate structure 30 comprising an electrically conductive gate layer 32 and a gate insulating layer 34. The gate insulating layer 34 at least partially covers the n+source region 22 and the p-well region 20 of the source structure 18. Furthermore, next to the source structure 18, on top of the first crystalline layer 16 and horizontally adjacent to the p-well region 20, the semiconductor device 10 comprises an n+JFET- like region 36, which is also covered by the gate insulating layer 34.

[0082] Regarding the source structure 18, figure 1 shows that the semiconductor device 10 comprises as source contact 38 a Ohmic contact formed with the n+source region 22 and the p+short region 24. In this embodiment the Ohmic contact is formed with the n+source region 22 and p+short region 24 by depositing a layer of Al / Ti on top of the source area and then annealing it at - 1000 °C.

[0083] In this embodiment the bottom crystalline layer 28 is not biased through the Ohmic contact formed as source contact 38. Instead, a Schottky contact is formed with the bottom crystalline layer 28 by an intermediate metal 40 - in this case nickel - between the bottom crystalline layer 28 and the source contact 38.

[0084] Figure 2 schematically shows a half unit cell cross-section of a semiconductor device 10 with an integrated heterojunction diode 12 according to another preferred embodiment of the invention, where the recess 26 is less deep as in the embodiment of figure 1 .

[0085] Comparable to figure 1 , in the embodiment shown in figure 2 the semiconductor device 10 is a MOSFET and has a very similar structure to the embodiment shown in figure 1 . Thus, in the following the differences are explained:

[0086] As well as in the embodiment in figure 1 the recess 26 comprising the bottom crystalline layer 28 is formed in the source structure 18. However, different to the embodiment shown in figure 1 , the recess 26 extends vertically through the p+short region 24 such that for forming the integrated heterojunction diode 12 the bottom crystalline layer 28 of the recess 26 is in contact with an additional semiconductor layer 42 being formed on the first crystalline layer 16. The additional semiconductor layer 42 in this embodiment is not only of the same conductivity type as the first crystalline layer 16, but also grown in the same growth step together with the first crystalline layer 16.

[0087] Regarding the vertical depth of the recess 26 it can be seen in figure 2, that comparable to figure 1 the upper surface of the bottom crystalline layer 28 formed on the additional semiconductor layer 42 is vertically below the lower end of the p+short region 24.

[0088] Figure 3 schematically shows a half unit cell cross-section of a semiconductor device 10 with an integrated heterojunction diode 12 according to a third preferred embodiment of the invention, where the n+source region 22 is arranged on top of the p+short region 24. Comparable to figure 1 , in the embodiment shown in figure 3 the semiconductor device 10 is a MOSFET and has a very similar structure to the embodiment of figure 1. Thus, in the following the differences are explained: In this embodiment the vertical arrangement of the n+source region 22 and p+short region 24 on top of each other (instead of next to each other as in figures 1 and 2) leads to a wider contact window 44 for the integrated heterojunction diode 12. As is also visible in figure 3 is that the biasing of the p-well region 20 is performed along the vertical portion of the Ohmic contact formed as source contact 38.

[0089] Figure 4 schematically shows a half unit cell cross-section of a semiconductor device 10 with an integrated heterojunction diode 12 according to a fourth preferred embodiment of the invention. In this embodiment the arrangement of the n+source region 22 and p+short region 24 is the same as in the embodiment shown in figure 3. However, comparable to figure 2, in the embodiment shown in figure 4, the recess 26 extends vertically through the p+short region 24 such that for forming the integrated heterojunction diode 12 the bottom crystalline layer 28 of the recess 26 is in contact with the additional semiconductor layer 42 being formed on the first crystalline layer 16.

[0090] Regarding the vertical depth of the recess 26 it can be seen in figure 4, that the upper surface of the bottom crystalline layer 28 formed on the additional semiconductor layer 42 is vertically at the same level as the lower end of the p+short region 24.

[0091] Figures 5 and 6 both schematically show a half unit cell cross-section of a semiconductor device 10 with an integrated heterojunction diode 12 according to a fifth and sixth preferred embodiment of the invention. In these two embodiments the semiconductor device 10 comprises one (figure 5) or two (figure 6) additional p+type layers 46 vertically below the integrated heterojunction diode 12.

[0092] As can be seen in figures 5 and 6 the arrangement of the n+source region 22 and p+short region 24 is the same as in the embodiment shown in figures 3 and 4, where the n+source region 22 is arranged on top of the p+short region 24. Furthermore, even though the recess 26 in the semiconductor devices 10 of the embodiments shown in figures 5 and 6 is etched down to the lower end of the p-well region 20, such that the bottom crystalline layer 28 is in contact with the first crystalline layer 16 (and not with the additional semiconductor layer 42 as in figure 4) the upper surface of the bottom crystalline layer 28 is nevertheless vertically at the same level as the lower end of the p+short region 24 - just as in figure 4.

[0093] Regarding the additional p+type layer 46, as can be seen in figures 5 the additional p+type layer 46 is biased to the source contact 38 via an Ohmic contact. In contrast to the embodiments shown in figures 1 to 4, where the source contact 38 does not reach down to the upper surface of the first crystalline layer 16 but ends at the intermediate metal 40 that is on top of the bottom crystalline layer 28, in the embodiment in figure 5, the intermediate metal 40 is on the same vertical level as the bottom crystalline layer 28 and the source contact 38 reaches down towards the additional p+type layer 46 below the bottom crystalline layer 28.

[0094] In the embodiment shown in figure 6, where two additional p+type layers 46 are formed vertically below the integrated heterojunction diode 12, both additional p+type layers 46 are biased to the source contact 38 via an Ohmic contact.

[0095] All embodiments shown in figures 1 to 6 show MOSFETs in a stripe design, where the layout of the gate structure 30 constitutes of parallel stripes. With regard to the figures the stripes extend in a plane perpendicular to the plane of paper.

[0096] In contrast to the stripe design, figure 7 schematically shows two views of a semiconductor device 10 with an integrated heterojunction diode 12 according to a further preferred embodiment, where the semiconductor device 10 has rotational symmetry. In figure 7a) the half unit cell cross-section of a semiconductor device 10 is shown - which is identical to the embodiment shown in figure 1. Figure 7b) shows however a top view, where the gate structure 30 (with the electrically conductive gate layer 32 and the gate insulating layer 34), the source contact 38, the intermediate metal 40, as well as the bottom crystalline layer 28 are not shown. As can be seen in figure 7b) the semiconductor device 10 has a rotation axis 48 being perpendicular to the first crystalline layer 16. Furthermore, the rotation axis 48 is arranged in the centre of the gate insulating layer 34 of the planar gate structure 30.

[0097] Figure 8 schematically shows in a) a TCAD model (technology computer aided design model) of an 1 -dimensional 3C-SiC / 4H-SiC heterojunction diode 12 and in b) its on-state performance predicted by simulations for different doping levels in the bottom crystalline layer 28 being formed by 3C-SiC and different designs of the source contact 38 compared with a conventional 4H-SiC PiN diode and compared with a conventional 4H-SiC Schottky diode.

[0098] In figure 8a) it can be seen, that the TCAD model specifies that the substrate 14 has an n+doping with a doping concentration of 1018cm’3and that the substrate is biased to a cathode (cathode not shown). On top of the substrate 14 there is the first crystalline layer 16 being of 4H-SiC polytype and having a doping concentration of 1016cm’3. A transition region 50 between the substrate 14 and the first crystalline layer 16, where the concentration gradually decreases has a thickness of 1 pm. The thickness of the first crystalline layer 16 is specified in the model to be 10 pm. On top of the first crystalline layer 16 there is the bottom crystalline layer 28 being of 3C-SiC polytype and being biased to an anode (anode not shown). The thickness of the bottom crystalline layer 28 is specified to be 60 nm.

[0099] Figure 8b) shows the on-state performance of the model predicted by simulations for different doping levels in the bottom crystalline layer 28 and different source contact designs. An x-axis 52 of the diagram of figure 8b) denotes the applied anode voltage in V, while the y-axis 54 shows the resulting current density in A / cm2of the model.

[0100] The curve 56 depicts the simulation result for an n-type doping concentration of 1016cm’3in the bottom crystalline layer 28 with an Ohmic contact being formed to the bottom crystalline layer 28 at the anode.

[0101] The curve 58 depicts the simulation result for an n-type doping concentration of 1018cm’3in the bottom crystalline layer 28 with a Schottky contact being formed to the bottom crystalline layer 28 at the anode.

[0102] The curve 60 depicts the simulation result for an n-type doping concentration of 1016cm’3in the bottom crystalline layer 28 with a Schottky contact being formed to the bottom crystalline layer 28 at the anode. Also depicted in figure 8b) are simulation results of a reference model: curve 62’ depicts the simulation result for a conventional 4H-SiC Schottky barrier diode, while curve 64’ depicts the simulation result for a conventional 4H-SiC PiN diode.

[0103] The simulation results show that the conduction in the heterojunction diode 12 (curves 56, 58, 60) is strictly unipolar and occurs by means of thermionic emission of electrons from the first crystalline layer 16 forming the drift region to the anode side of the heterojunction diode 12 at forward voltages above the threshold voltage Vh-th. The turn-on voltage can be increased to « 1 V by forming a Schottky contact (curves 58 and 60), instead of an Ohmic contact (curve 56), to the bottom crystalline layer 28 at the anode. For the simulations, it has been assumed that the Schottky contacts are formed using Nickel.

[0104] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosed, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting scope.

[0105] Reference signs list

[0106] 10 sem iconductor device

[0107] 12 integrated heterojunction diode

[0108] 14 substrate, drain region

[0109] 16 first crystalline layer, drift region

[0110] 18 source structure

[0111] 20 p-well region

[0112] 22 n+source region

[0113] 24 p+short region

[0114] 26 recess

[0115] 28 bottom crystalline layer

[0116] 30 gate structure

[0117] 32 electrically conductive gate layer

[0118] 34 gate insulating layer

[0119] 36 n+JFET-like region

[0120] 38 source contact

[0121] 40 intermediate metal

[0122] 42 additional semiconductor layer

[0123] 44 contact window of integrated heterojunction diode

[0124] 46 additional p+type layer

[0125] 48 rotation axis

[0126] 50 transition region

[0127] 52 x-axis (anode voltage in Volts)

[0128] 54 y-axis (current density in A / cm2)

[0129] 56 curve showing simulation results for a preferred embodiment

[0130] 58 curve showing simulation results for a preferred embodiment

[0131] 60 curve showing simulation results for a preferred embodiment

[0132] 62’ curve showing simulation results for reference 4H-SiC Schottky barrier diode

[0133] 64’ curve showing simulation results for reference 4H-SiC PiN diode

Claims

Claims1 . A semiconductor device (10) with an integrated heterojunction diode (12) comprising:- a substrate (14) of a first conductive type acting as drain region,- a first crystalline layer (16) of a second conductivity type formed on the substrate (14) and acting as drift region, and- a source structure (18) provided on the first crystalline layer (16), the source structure (18) comprising a p-well region (20), an n+source region (22), and a p+short region (24), wherein a recess (26) comprising a bottom crystalline layer (28) is formed in the source structure (18), the recess (26) extending vertically through the p+short region (24) such that for forming the integrated heterojunction diode (12) the bottom crystalline layer (28) of the recess (26) is in contact with a) the first crystalline layer (16), or b) an additional semiconductor layer (42) being formed on the first crystalline layer (16), and wherein the additional semiconductor layer (42) is of the same conductivity type as the first crystalline layer (16).

2. The semiconductor device (10) according to claim 1 , wherein the semiconductor device (10) is configured as a MOSFET, a MISFET, a JFET, an IGBT, or a BIGT.

3. The semiconductor device (10) according to any of the preceding claims, wherein the semiconductor device (10) is of a semiconductor material having a bandgap equal to or greater than the bandgap of silicon.

4. The semiconductor device (10) according to any of the preceding claims, wherein the semiconductor device (10) is of a semiconductor material selected from the group consisting of Si, SiC, GaN, Ga2O3, AIN, AlxGai-xN, GaAs, and diamond.

5. The semiconductor device (10) according to any of the preceding claims,wherein the bottom crystalline layer (28) is of the same material as the first crystalline layer (16), but of a different polytype than the first crystalline layer (16).

6. The semiconductor device (10) according to any of the preceding claims, wherein the additional semiconductor layer (42) has a thickness in the vertical direction of no more than 75 % of the source structure (18), preferably no more than 50 % of the source structure (18), and / or wherein the thickness in the vertical direction of the additional semiconductor layer (42) is such that an upper surface of the additional semiconductor layer (42) is on a lower vertical level than a lower end of the p+short region (24).

7. The semiconductor device (10) according to any of the preceding claims, wherein the bottom crystalline layer (28) is a p-type or an n-type doped layer; and / or wherein a thickness of the bottom crystalline layer (28) is in a range of 5 nm to 5000 nm.

8. The semiconductor device (10) according to any of the preceding claims, wherein a band offset of a conduction band of the bottom crystalline layer (28) to the conduction band of the first crystalline layer (16) or to the conduction band of the additional semiconductor layer (42) in the integrated heterojunction diode (12) is smaller than the bandgap of the semiconductor material of the substrate (14).

9. The semiconductor device (10) according to any of the preceding claims, wherein the semiconductor device (10) further comprises a planar gate structure (30), comprising an electrically conductive gate layer (32) and a gate insulating layer (34), and wherein the gate insulating layer (34) at least partially covers the n+source region (22) and the p-well region (20) of the source structure (18).

10. The semiconductor device (10) according to any of the preceding claims, wherein the semiconductor device (10) further comprises as source contact (38) an Ohmic contact formed with the n+source region (22) and the p+short region11. The semiconductor device (10) according to claim 10, wherein the Ohmic contact further contacts the bottom crystalline layer (28).

12. The semiconductor device (10) according to claim 10, wherein the semiconductor device (10) further comprises a Schottky contact formed with the bottom crystalline layer (28) by an intermediate metal (40) between the bottom crystalline layer (28) and the source contact (38).

13. The semiconductor device (10) according to any of the preceding claims, wherein the n+source region (22) is arranged on top of the p+short region (24).

14. The semiconductor device (10) according to any of claims 1 to 12, wherein the n+source region (22) and the p+short region (24) are arranged next to each other on the same vertical level.

15. The semiconductor device (10) according to any of the preceding claims wherein the upper surface of the bottom crystalline layer (28) is vertically at the same level or below the lower end of the p+short region (24).

16. The semiconductor device (10) according to any of the preceding claims, wherein the semiconductor device (10) further comprises one or more additional p+type layers (46) positioned vertically below the integrated heterojunction diode (12), adjacent to the crystalline bottom layer (28) and within the first crystalline layer (16) or within the additional semiconductor layer (46).

17. The semiconductor device (10) according to claim 16, wherein an Ohmic contact is formed with the additional p+type layers (46) and the source contact (38).

18. The semiconductor device (10) according to any of the preceding claims, wherein the semiconductor device (10) has a stripe design.

19. The semiconductor device (10) according to any of claims 1 to 17, wherein the semiconductor device (10) has rotational symmetry, with a rotation axis (48) being perpendicular to the first crystalline layer (16), and wherein the rotation axis (48) is arranged in a centre of a gate insulating layer (34) of a planar gatestructure (30).

20. Method for manufacturing a semiconductor device (10) with an integrated heterojunction diode (12) comprising the steps of- providing a substrate (14) of a first conductive type acting as drain region,- forming a first crystalline layer (16) of a second conductivity type on the substrate (14), wherein the first crystalline layer (16) acts as drift region,- forming a source structure (18) on the first crystalline layer (16), the source structure (18) comprising a p-well region (20), an n+source region (22), and a p+short region (24),- forming the integrated heterojunction diode (12) by etching a recess (26) into the source structure (18), extending vertically through the p+short region (24), and forming a bottom crystalline layer (28) on a bottom of the etched recess (26), such that the formed bottom crystalline layer (28) is in contact with a) the first crystalline layer (16), or b) an additional semiconductor layer (42) that has been formed on the first crystalline layer (16), wherein the additional semiconductor layer (42) is of the same conductivity type as the first crystalline layer (16).21 . The method according to claim 20, wherein the step of forming the first crystalline layer (16) of the second conductivity type on the substrate (14) comprises epitaxially growing the first crystalline layer (16) on the substrate (14).

22. The method according to claims 20 or 21 , wherein the step of forming the bottom crystalline layer (28) on the bottom of the etched recess (26) comprises selective epitaxially growing the bottom crystalline layer (28) on the first crystalline layer (16) or on the additional semiconductor layer (42).

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