Imaging device and camera system

Abstract

This imaging device comprises: a first semiconductor substrate; a pixel array that is located on a first surface of the semiconductor substrate and includes a plurality of pixels; a plurality of through electrodes that each penetrate the first semiconductor substrate and are located outside the pixel array in plan view; and a plurality of wires that electrically connect the pixel array and the plurality of respective through electrodes. In plan view, a triangle having the centers of three through electrodes which are adjacent to each other among the plurality of through electrodes as vertices is an acute-angled triangle TRI.

Description

Imaging device and camera system

[0001] The present disclosure relates to an imaging device and a camera system.

[0002] Imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital cameras, etc. As such imaging devices, imaging devices having a structure in which a semiconductor substrate on which a pixel array consisting of a plurality of pixels is formed and a semiconductor substrate on which a circuit connected to the pixel array is formed are stacked have been proposed.

[0003] For example, Patent Document 1 discloses a solid-state imaging device having a structure in which a first semiconductor substrate on which a pixel section in which pixels are arranged is formed, and a second semiconductor substrate and a third semiconductor substrate on which circuits having predetermined functions are formed are stacked.

[0004] JP 2023-57137 A

[0005] In imaging devices, there is a demand for reducing the area of ​​the substrate in a plan view and for miniaturization. As in the technology disclosed in Patent Document 1, stacking multiple semiconductor substrates allows circuits to be formed separately on the multiple semiconductor substrates, which is advantageous for miniaturization, but in recent years, there has been a growing demand for even further miniaturization.

[0006] The present disclosure provides an imaging device and the like that can be made smaller.

[0007] An imaging device according to one aspect of the present disclosure comprises a first semiconductor substrate, a pixel array located on a first surface of the first semiconductor substrate and including a plurality of pixels, a plurality of through electrodes each penetrating the first semiconductor substrate, the plurality of through electrodes being located outside the pixel array in a planar view, and a plurality of wirings electrically connecting the pixel array to each of the plurality of through electrodes, wherein in a planar view, a triangle having vertices at the centers of three adjacent through electrodes among the plurality of through electrodes is an acute triangle.

[0008] A camera system according to one aspect of the present disclosure includes the imaging device described above.

[0009] According to the present disclosure, it is possible to provide an imaging device or the like that can be made smaller.

[0010] FIG. 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment. FIG. 2 is a schematic cross-sectional view showing an example of a device structure of the imaging device according to the first embodiment. FIG. 3 is a schematic view showing an example of a planar layout of a first substrate of the imaging device according to the first embodiment. FIG. 4 is a schematic view showing an example of a planar layout of a second substrate of the imaging device according to the first embodiment. FIG. 5 is a plan view of a plurality of through electrodes according to the first embodiment. FIG. 6 is a plan view showing an example of a planar layout of a plurality of through electrodes according to the first embodiment. FIG. 7 is a plan view for explaining parasitic capacitance between adjacent through electrodes. FIG. 8 is a plan view for explaining a positional relationship between a plurality of through electrodes and a pixel array according to the first embodiment. FIG. 9 is a plan view showing a first example of a planar layout of a plurality of through electrodes according to the first embodiment. FIG. 10 is a plan view showing a second example of a planar layout of a plurality of through electrodes according to the first embodiment. FIG. 11 is a plan view showing a third example of a planar layout of a plurality of through electrodes according to the first embodiment. FIG. 12 is a schematic cross-sectional view showing an example of a device structure of an imaging device according to a first modification of the first embodiment. FIG. 13 is a schematic cross-sectional view showing an example of a device structure of an imaging device according to Modification 2 of Embodiment 1. FIG. 14 is a schematic diagram showing an example of a planar layout of a first substrate of an imaging device according to Modification 2 of Embodiment 1. FIG. 15 is a schematic diagram showing an example of a planar layout of a third substrate of an imaging device according to Modification 2 of Embodiment 1. FIG. 16 is a schematic diagram showing an example of a planar layout of a second substrate of an imaging device according to Modification 2 of Embodiment 1. FIG. 17 is a schematic cross-sectional view showing an example of a device structure of an imaging device according to Modification 3 of Embodiment 1. FIG. 18 is a schematic diagram showing an example of a planar layout of a third substrate of an imaging device according to Modification 3 of Embodiment 1. FIG. 19 is a schematic diagram showing an example of a planar layout of a first substrate of an imaging device according to Modification 3 of Embodiment 1. FIG. 20 is a schematic diagram showing an example of a planar layout of a second substrate of an imaging device according to Modification 3 of Embodiment 1. FIG. 21 is a block diagram showing an example of a configuration of a camera system according to Embodiment 2.

[0011] (How an Aspect of the Present Disclosure Was Achieved) The inventors of the present application have discovered that the following problems arise with the conventional imaging devices described in the "Background Art" section.

[0012] When a semiconductor substrate on which a pixel array is formed and a semiconductor substrate on which a circuit connected to the pixel array is formed are stacked, the pixel array and the circuit are electrically connected via a through electrode that penetrates the semiconductor substrate.

[0013] In recent years, the number of wirings connected to a pixel array has been increasing as imaging devices have become more highly functional, such as with higher resolution. Therefore, when semiconductor substrates are stacked as described above, the number of through-electrodes electrically connected to the pixel array also increases. As a result, the area occupied by the region in which the through-electrodes are formed on the semiconductor substrate also increases, which can make it difficult to sufficiently miniaturize the imaging device. For example, increasing the number of pixels constituting the pixel array also increases the area of ​​the region in which the through-electrodes are formed. Therefore, when semiconductor substrates are stacked, the area of ​​the semiconductor substrate increases by more than the increase in the area of ​​the pixel array as the resolution increases.

[0014] In view of the above-mentioned problems, the inventors of the present application have noticed that by increasing the coverage rate of the through electrodes in the through electrode group and reducing the area of ​​the region in which the through electrode group is formed, it is possible to miniaturize imaging devices, etc., and have arrived at one aspect of the present disclosure.

[0015] (Summary of the Present Disclosure) As an overview of one aspect of the present disclosure, examples of an imaging device and a camera system according to the present disclosure are described below.

[0016] For example, an imaging device according to a first aspect of the present disclosure includes a first semiconductor substrate, a pixel array located on a first surface of the first semiconductor substrate and including a plurality of pixels, a plurality of through electrodes each penetrating the first semiconductor substrate, the plurality of through electrodes being located outside the pixel array in a planar view, and a plurality of wirings electrically connecting the pixel array to each of the plurality of through electrodes, wherein in a planar view, a triangle having vertices at the centers of three adjacent through electrodes among the plurality of through electrodes is an acute triangle.

[0017] This allows the height of the acute triangle to be shorter than the distance between the centers of adjacent through electrodes among the three through electrodes. Therefore, the through electrodes can be arranged at a distance shorter than the distance between the centers of adjacent through electrodes in the height direction of the acute triangle. This increases the coverage ratio of the multiple through electrodes and reduces the area in which the multiple through electrodes are formed. This allows for a more compact imaging device. Furthermore, since the triangle with the centers of three adjacent through electrodes as its vertex is an acute triangle, the distance between adjacent through electrodes can be made more uniform compared to a right-angled triangle or an acute-angled triangle, thereby reducing the variation in parasitic capacitance between adjacent through electrodes. This reduces the variation in the effect of parasitic capacitance on signals passing through the through electrodes, thereby improving image quality.

[0018] Also, for example, an imaging device according to a second aspect of the present disclosure is an imaging device according to the first aspect, in which a first wiring among the plurality of wirings extends between two of the three through electrodes and is electrically connected to one through electrode that is farther from the pixel array than the two of the three through electrodes.

[0019] This allows the first wiring to be disposed between the through electrodes, thereby enabling the imaging device to be made smaller.

[0020] Furthermore, for example, an imaging device according to a third aspect of the present disclosure is an imaging device according to the first or second aspect, in which, in a planar view, one side of the acute triangle is perpendicular to the side that is adjacent to the three through electrodes among the sides that form the outer edge of the pixel array.

[0021] This allows any of the wiring electrically connected to the three through electrodes to be connected to the pixel array over the shortest distance without colliding with the three through electrodes.

[0022] Also, for example, an imaging device according to a fourth aspect of the present disclosure is an imaging device according to the third aspect, in which the height of the acute triangle when the one side of the acute triangle is taken as the base is shorter than the length of the base.

[0023] This makes it possible to further increase the coverage ratio of the plurality of through electrodes, and further reduce the area of ​​the region where the plurality of through electrodes are formed.

[0024] Furthermore, for example, an imaging device according to a fifth aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, in which, in a planar view, the plurality of through electrodes are arranged in a plurality of columns extending along a direction perpendicular to the side that is adjacent to the three through electrodes among the sides that form the outer edge of the pixel array, and in a planar view, the positions in the direction of the through electrodes arranged in adjacent columns among the plurality of columns are different from each other.

[0025] This allows all of the wiring lines electrically connected to the through electrodes to be connected to the pixel array in the shortest distance without colliding with the through electrodes.

[0026] Furthermore, for example, an imaging device according to a sixth aspect of the present disclosure is an imaging device according to any one of the first to fifth aspects, in which, in a planar view, the centers of the multiple through electrodes are located on lattice points of a triangular lattice having the acute triangle as a unit lattice.

[0027] This allows a plurality of through electrodes to be arranged regularly, facilitating the layout of a plurality of wirings.

[0028] Also, for example, an imaging device according to a seventh aspect of the present disclosure is an imaging device according to any one of the first to sixth aspects, wherein each of the plurality of pixels includes a photoelectric conversion unit including a first electrode, a second electrode opposite to the first electrode, and a photoelectric conversion layer located between the first electrode and the second electrode, the second electrodes of the plurality of pixels are electrically connected to each other, and a second wiring among the plurality of wirings is electrically connected to the second electrode.

[0029] This makes it possible to supply a voltage to the second electrode via the through electrode.

[0030] Also, for example, an imaging device according to an eighth aspect of the present disclosure is an imaging device according to any one of the first to seventh aspects, further comprising a second semiconductor substrate stacked on a second surface side opposite the first surface of the first semiconductor substrate, and a circuit formed on the second semiconductor substrate, and the circuit being electrically connected to the plurality of through electrodes.

[0031] This allows the pixel array to be electrically connected to the circuit formed on the second semiconductor substrate via the through electrodes.

[0032] Also, for example, an imaging device according to a ninth aspect of the present disclosure is the imaging device according to any one of the first to eighth aspects, wherein the acute triangle is an equilateral triangle.

[0033] This increases the coverage ratio of the plurality of through electrodes, thereby reducing the area of ​​the region in which the plurality of through electrodes are formed. In addition, the distances between adjacent through electrodes become equal, and the parasitic capacitances of the three through electrodes are equalized.

[0034] Furthermore, for example, an imaging device according to a tenth aspect of the present disclosure is an imaging device according to any one of the first to ninth aspects, wherein the plurality of through electrodes include a first through electrode that is one of the three through electrodes and six second through electrodes that include the remaining two through electrodes of the three through electrodes, and the six second through electrodes are adjacent to the first through electrode and arranged equidistant from each other from the first through electrode in a planar view, and a hexagon with vertices at the centers of the six second through electrodes is a regular hexagon in a planar view.

[0035] This increases the coverage ratio of the plurality of through electrodes, thereby reducing the area of ​​the region in which the plurality of through electrodes are formed. In addition, the intervals between adjacent through electrodes become uniform, and the parasitic capacitances of the first through electrode and the six second through electrodes are equalized.

[0036] Also, for example, a camera system according to an eleventh aspect of the present disclosure includes the imaging device according to any one of the first to tenth aspects.

[0037] As a result, the camera system according to this aspect can be made smaller because it includes the imaging device described above.

[0038] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components not recited in independent claims are described as optional components. In each drawing, components having substantially the same functions are designated by common reference symbols, and redundant descriptions may be omitted or simplified.

[0039] Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from the actual objects. In other words, each drawing is a schematic diagram and is not necessarily an accurate depiction. Therefore, for example, the scales of the drawings do not necessarily match.

[0040] Furthermore, in this specification, terms indicating the relationship between elements, such as perpendicular or parallel, terms indicating the shape of elements, such as circular or rectangular, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0041] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in the stacked structure. Specifically, the light-receiving side of the imaging device is referred to as "upper," and the side opposite the light-receiving side is referred to as "lower." Similarly, the "upper surface" and "lower surface" of each component refer to the light-receiving side of the imaging device as the "upper surface" and the side opposite the light-receiving side as the "lower surface." Note that the terms "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device during use. Furthermore, the terms "upper" and "lower" apply not only to cases where two components are arranged with a gap between them and another component is present between them, but also to cases where two components are arranged closely together and in contact with each other. In this specification, the term "plan view" refers to a view from a direction perpendicular to the semiconductor substrate (in other words, the thickness direction of the semiconductor substrate).

[0042] In this specification and the drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a three-dimensional Cartesian coordinate system. In the following embodiments, the Z-axis direction corresponds to the thickness direction of the semiconductor substrate and the stacking direction of the semiconductor substrate. The negative side of the Z-axis corresponds to the "downward" direction, and the positive side of the Z-axis corresponds to the "upward" direction.

[0043] In addition, in this specification, the expression "components are located on a certain surface of a semiconductor substrate" refers not only to the case where all of the components are located on a certain surface, but also to the case where some of the components are provided in the semiconductor substrate.

[0044] In this specification, the expression "a transistor is disposed on a certain surface of a semiconductor substrate" means that the gate, source, and drain of the transistor are disposed across the certain surface.

[0045] In this specification, not only visible light but also invisible light such as ultraviolet light and near-infrared light will be referred to as "light" for convenience.

[0046] First Embodiment An imaging device according to a first embodiment will be described.

[0047] [Configuration] First, an overview of the configuration of an imaging device according to this embodiment will be described. Fig. 1 is a block diagram showing an example of the configuration of an imaging device 100 according to this embodiment.

[0048] As shown in FIG. 1, the imaging device 100 includes a first substrate 10, a pixel array 30 formed on the first substrate 10, a second substrate 20, and an AD (Analog to Digital) conversion circuit 41, a memory 42, a logic circuit 43, a vertical scanning circuit 44, and a voltage supply circuit 45 formed on the second substrate 20.

[0049] As will be described in detail later, the first substrate 10 and the second substrate 20 are stacked on top of each other and electrically connected.

[0050] The pixel array 30 includes a plurality of pixels arranged two-dimensionally. Each of the plurality of pixels includes a photoelectric conversion unit that converts light into an electric charge, and outputs a signal in response to the light incident on the photoelectric conversion unit.

[0051] The AD conversion circuit 41 is connected to the pixel array 30 via an output signal line L1 provided for each column of the pixel array 30, and converts into a digital signal an analog signal output for each column of the pixel array 30. The AD conversion circuit 41 may perform noise suppression signal processing, represented by correlated double sampling, before AD conversion.

[0052] The memory 42 temporarily stores the digital signal converted by the AD conversion circuit 41 .

[0053] The logic circuit 43 includes a data processing circuit 43a, an output buffer circuit 43b, and a control circuit 43c.

[0054] The data processing circuit 43a processes the data stored in the memory 42 as necessary, and outputs the data to the outside via the output buffer circuit 43b at an appropriate timing.

[0055] The output buffer circuit 43b outputs the data from the data processing circuit 43a to the outside.

[0056] The control circuit 43c controls the driving of the imaging device 100. The control circuit 43c controls the driving of at least one of the AD conversion circuit 41, the memory 42, the data processing circuit 43a, the output buffer circuit 43b, the vertical scanning circuit 44, and the voltage supply circuit 45, for example.

[0057] In the example shown in FIG. 1, the data processing circuit 43a and the control circuit 43c are shown as separate blocks, but the data processing circuit 43a and the control circuit 43c may be realized by a single processor or the like.

[0058] The vertical scanning circuit 44 is connected to the pixel array 30 via a control signal line L2 provided for each row of the pixel array 30, and performs operations such as reading and resetting of pixel signals for each row of the pixel array 30. For example, a plurality of control signal lines L2 are provided for each row of the pixel array 30.

[0059] The voltage supply circuit 45 is connected to the pixel array 30 via a voltage line L3 and supplies a voltage required to drive the pixel array 30.

[0060] 1 is an example, and the imaging device 100 may not include, for example, some of the components formed on the second substrate 20. For example, the circuits subsequent to the AD conversion circuit 41 may be provided in a device separate from the imaging device 100, and the imaging device 100 may be a device that outputs a digital signal converted by the AD conversion circuit 41. Furthermore, some of the components formed on the second substrate 20 may be formed on the first substrate 10.

[0061] Next, a detailed configuration of the imaging device 100 according to this embodiment will be described with reference to FIGS. 2 to 4. FIG.

[0062] Fig. 2 is a schematic cross-sectional view showing an example of the device structure of the imaging device 100 according to the present embodiment. Fig. 3 is a schematic diagram showing an example of the planar layout of the first substrate 10 of the imaging device 100 according to the present embodiment. Fig. 4 is a schematic diagram showing an example of the planar layout of the second substrate 20 of the imaging device 100 according to the present embodiment. Note that in Fig. 2, for ease of viewing, the shading indicating the cross section of some components such as the interlayer insulating layers 12 and 22 has been omitted. This also applies to the subsequent cross-sectional views.

[0063] 2, the first substrate 10 and the second substrate 20 are stacked on top of each other. The first substrate 10 and the second substrate 20 have, for example, the same shape and size in a plan view, and their outer edges coincide.

[0064] The first substrate 10 has a semiconductor substrate 11, an interlayer insulating layer 12 arranged above the semiconductor substrate 11, an insulating layer 13 arranged above the interlayer insulating layer 12, and an insulating layer 14 arranged above the insulating layer 13.

[0065] The second substrate 20 has a semiconductor substrate 21 and an interlayer insulating layer 22 arranged above the semiconductor substrate 21. The semiconductor substrate 21 is stacked on the lower surface s12 side of the semiconductor substrate 11, opposite the upper surface s11. In the example shown in Fig. 2, the second substrate 20 is stacked on the first substrate 10 so that the interlayer insulating layer 22 is sandwiched between the semiconductor substrate 11 and the semiconductor substrate 21. The top and bottom of the second substrate 20 may be reversed from the example shown in Fig. 2.

[0066] The semiconductor substrates 11 and 21 are, for example, p-type or n-type semiconductor substrates in which various impurity regions are formed. The semiconductor substrate 11 is an example of a first semiconductor substrate, and the semiconductor substrate 21 is an example of a second semiconductor substrate.

[0067] A wiring structure is formed inside each of the interlayer insulating layers 12 and 22. The wiring structure includes, for example, a plurality of wiring layers in which various types of wiring are formed.

[0068] The interlayer insulating layers 12 and 22 and the insulating layers 13 and 14 are made of, for example, silicon dioxide (SiO ２ ) or other insulating materials.

[0069] 3, a pixel array 30, a through electrode group 50, and a pad group 60 are formed on the first substrate 10. Also, as shown in Fig. 4, an AD conversion circuit 41, a memory 42, a logic circuit 43, a vertical scanning circuit 44, a voltage supply circuit 45, a through electrode group 50, and a pad group 61 are formed on the second substrate 20.

[0070] As shown in FIG. 3 , the pixel array 30 includes a plurality of pixels 31 arranged in a plurality of rows and columns in a planar view. The pixel array 30 has a rectangular shape in a planar view. In the example shown in FIG. 3 , the plurality of pixels 31 are arranged in a matrix of a plurality of rows extending in the X-axis direction and a plurality of columns extending in the Y-axis direction. The number and arrangement of the pixels 31 are not limited to the example shown. For example, although the center of each pixel 31 is located on a lattice point of a square lattice, the arrangement of the pixels 31 does not have to be such. For example, the plurality of pixels 31 may be arranged so that each center is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. Furthermore, in the example shown in FIG. 3 , the plurality of pixels 31 are illustrated as being spatially separated from one another, but this is merely for convenience of explanation, and the plurality of pixels 31 may also be arranged continuously without any gaps between them.

[0071] The pixel array 30 is located on the upper surface s11 of the semiconductor substrate 11. The upper surface s11 is an example of a first surface. While an example in which one pixel 31 is located on the upper surface s11 of the semiconductor substrate 11 is illustrated in FIG. 2 , all of the multiple pixels 31 that make up the pixel array 30 are located on the upper surface s11 of the semiconductor substrate 11.

[0072] 2, each of the pixels 31 includes a photoelectric conversion unit 32 and a pixel circuit 35 connected to the photoelectric conversion unit 32.

[0073] The photoelectric conversion unit 32 is disposed above the first substrate 10. The photoelectric conversion unit 32 generates positive and negative charges upon receiving incident light. In other words, the photoelectric conversion unit 32 converts light into charges. The photoelectric conversion unit 32 includes a pixel electrode 32a formed on the first substrate 10, a counter electrode 32b facing the pixel electrode 32a, and a photoelectric conversion layer 32c located between the pixel electrode 32a and the counter electrode 32b. The pixel electrode 32a is an example of a first electrode, and the counter electrode 32b is an example of a second electrode.

[0074] The photoelectric conversion layer 32c includes an organic semiconductor material or an inorganic semiconductor material such as amorphous silicon, and generates positive and negative charges by photoelectric conversion when it receives light incident through the counter electrode 32b. The positive and negative charges are, for example, hole-electron pairs. The photoelectric conversion layer 32c is, for example, formed continuously across multiple pixels 31. The photoelectric conversion layer 32c is shared by multiple pixels 31. The photoelectric conversion layer 32c may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0075] The counter electrode 32b is formed of a transparent conductive material such as ITO (Indium Tin Oxide) and is disposed on the light-receiving surface side of the photoelectric conversion layer 32c. The counter electrode 32b is formed continuously across the plurality of pixels 31, similar to the photoelectric conversion layer 32c. In other words, the counter electrodes 32b of the plurality of pixels 31 are electrically connected to each other. The counter electrode 32b may be provided separately for each pixel 31 or for each block of two or more pixels 31.

[0076] The pixel electrode 32a is an electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to provide conductivity. The pixel electrode 32a collects one of the positive and negative charges generated in the photoelectric conversion layer. The pixel electrode 32a is spatially separated from the pixel electrodes 32a of other adjacent pixels 31, and is thereby electrically isolated from the pixel electrodes 32a of other pixels 31.

[0077] The pixel circuit 35 is connected to the pixel electrode 32a of the photoelectric conversion unit 32. The pixel circuit 35 includes, for example, a charge accumulation region that accumulates the charge generated by the photoelectric conversion unit 32 and a charge detection circuit that detects the charge accumulated in the charge accumulation region. The charge detection circuit includes, for example, an amplifier transistor that amplifies and outputs a voltage corresponding to the charge accumulated in the charge accumulation region, a selection transistor that reads the output of the amplifier transistor of the pixel in the selected row to an output signal line L1, and a reset transistor that resets the potential of the charge accumulation region. FIG. 2 shows only some of the transistors included in the charge accumulation region and the charge detection circuit. The transistors in the charge detection circuit are disposed on the upper surface s11 of the semiconductor substrate 11. Control signals for driving the selection transistor and the reset transistor are supplied from the vertical scanning circuit 44 via a control signal line L2.

[0078] 2, the pixel 31 further includes a color filter 33 and a microlens 34. The color filter 33 is disposed above the counter electrode 32b. The color filter 33 is formed, for example, as an on-chip color filter by patterning, and is made of a photosensitive resin or the like in which a dye or pigment is dispersed. The microlens 34 is disposed above the color filter 33, and has a light-condensing function of collecting light on the photoelectric conversion unit 32. The microlens 34 is formed, for example, as an on-chip microlens, and is made of an ultraviolet-sensitive material or the like.

[0079] 2, a peripheral circuit 40 is formed on the second substrate 20. The peripheral circuit 40 includes, for example, the above-mentioned AD conversion circuit 41, memory 42, logic circuit 43, vertical scanning circuit 44, and voltage supply circuit 45. The peripheral circuit 40 includes a plurality of transistors, and FIG. 2 illustrates some of the transistors of the peripheral circuit 40 located on the upper surface s21 of the semiconductor substrate 21.

[0080] 3 and 4 , the imaging device 100 includes three through electrode groups 50. As shown in FIG. 3 , each through electrode group 50 is located on the first substrate 10 outside the pixel array 30 in a planar view. Each through electrode group 50 is arranged outside the pixel array 30, for example, in the X-axis direction or the Y-axis direction in which the plurality of pixels 31 are arranged. Two of the three through electrode groups 50 are arranged outside the pixel array 30 in the X-axis direction, which is the row direction of the pixel array 30, so as to sandwich the pixel array 30 therebetween. The remaining one of the three through electrode groups 50 is arranged outside the pixel array 30 in the Y-axis direction, which is the column direction of the pixel array 30. The number and arrangement of the through electrode groups 50 included in the imaging device 100 are not particularly limited, and it is sufficient that at least one through electrode group 50 is arranged outside the pixel array 30 in a planar view.

[0081] As shown in FIG. 4 , on the second substrate 20, the AD conversion circuit 41, the memory 42, the logic circuit 43, and the voltage supply circuit 45 are arranged in a position surrounded by three through electrode groups 50 in a plan view. Therefore, in a plan view, the AD conversion circuit 41, the memory 42, the logic circuit 43, and the voltage supply circuit 45 are arranged in a position overlapping with the pixel array 30. Furthermore, in a plan view, the AD conversion circuit 41, the memory 42, and the logic circuit 43 are arranged in this order along the Y-axis direction. Furthermore, in the example shown in FIG. 4 , the vertical scanning circuit 44 is arranged between the through electrode groups 50 and the outer edge of the second substrate 20 in a plan view. Therefore, in a plan view, the vertical scanning circuit 44 is arranged in a position that does not overlap with the pixel array 30. Note that the arrangement of each component on the second substrate 20 is not particularly limited. For example, the vertical scanning circuit 44 may be arranged in a position overlapping with the pixel array 30 in a plan view. Furthermore, a portion of at least one of the AD conversion circuit 41, the memory 42, the logic circuit 43, the vertical scanning circuit 44, and the voltage supply circuit 45 may overlap the through electrode group 50 in a plan view.

[0082] The through electrode group 50 is composed of a plurality of through electrodes 51. As shown in FIG. 2 , each of the plurality of through electrodes 51 extends in the Z-axis direction, penetrates the semiconductor substrate 11, and is connected to the first substrate 10 and the second substrate 20. The plurality of through electrodes 51 is formed across the first substrate 10 and the second substrate 20. Note that at least some of the plurality of through electrodes 51 may only be in contact with the upper surface of the second substrate 20. The plurality of through electrodes 51 are electrically connected to the peripheral circuit 40, which is a circuit formed on the semiconductor substrate 21, on the second substrate 20. In the example shown in FIG. 2 , each of the plurality of through electrodes 51 reaches the upper surface of the interlayer insulating layer 12. Note that FIG. 2 illustrates some of the through electrodes 51 of the plurality of through electrodes 51 of the through electrode group 50 located on the positive side of the pixel array 30 in the X-axis direction. Furthermore, the center-to-center distance between adjacent through electrodes 51 shown in FIG. 2 may actually be larger than the sizes of the other components shown in FIG. 2 . For example, in a plan view, the distance between the centers of adjacent through electrodes 51 is larger than the distance between the centers of adjacent pixels 31. This also applies to the subsequent cross-sectional views.

[0083] An insulating film is formed on the outer peripheral surface of the portion of the through electrode 51 that penetrates the semiconductor substrate 11, and the through electrode 51 is separated from the semiconductor substrate 11 via the insulating film. The through electrode 51 is formed from, for example, a metal such as copper or tungsten, polysilicon doped with impurities, or a metal compound such as a metal nitride or a metal oxide.

[0084] The number of through electrodes 51 included in the through electrode group 50 may be 100 or more. When the through electrode group 50 includes a through electrode 51 electrically connected to an output signal line L1 as described below, the number of through electrodes 51 included in the through electrode group 50 is equal to or greater than the number of columns in the pixel array 30. When the through electrode group 50 includes a through electrode 51 electrically connected to a control signal line L2, the number of through electrodes 51 included in the through electrode group 50 is equal to or greater than n times the number of rows in the pixel array 30, where n is the number of control signal lines L2 connected to one pixel 31.

[0085] 2, the imaging device 100 further includes a plurality of wirings 55, a plurality of conductive layers 56, and a plurality of plugs 57. The plurality of wirings 55, the plurality of conductive layers 56, and the plurality of plugs 57 are each formed from a metal such as copper or tungsten.

[0086] Each of the plurality of wirings 55 corresponds one-to-one to the plurality of through electrodes 51, and electrically connects the pixel array 30 to the plurality of through electrodes 51. In Fig. 2, portions of the wirings 55 that do not appear in the cross section shown in Fig. 2 are indicated by dashed lines. This also applies to the subsequent cross-sectional views.

[0087] The plurality of wirings 55 are disposed in the interlayer insulating layer 12. The plurality of wirings 55 includes wirings 55 electrically connected to the pixel circuits 35. The plurality of wirings 55 includes, for example, wirings 55 constituting at least a portion of the above-described output signal lines L1, control signal lines L2, and voltage lines L3. The plurality of wirings 55 may also include wirings 55 constituting at least a portion of wirings other than the output signal lines L1, control signal lines L2, and voltage lines L3, such as voltage lines for supplying a reset voltage.

[0088] One of the multiple wirings 55 shown in FIG. 2 is at least a part of the voltage line L3 and is electrically connected to the counter electrode 32b. The wiring 55, which is at least a part of the voltage line L3, is an example of a second wiring. The voltage line L3 is electrically connected to the voltage supply circuit 45 via the through-electrode 51. During operation of the imaging device 100, the potential of the voltage line L3 is controlled to make the potential of the counter electrode 32b different from the potential of the pixel electrode 32a, thereby allowing the pixel electrode 32a to collect signal charges generated by photoelectric conversion. For example, the voltage supply circuit 45 supplies a voltage to the counter electrode 32b via the through-electrode 51 and the voltage line L3 so that the potential of the counter electrode 32b is higher than the potential of the pixel electrode 32a. This allows the pixel electrode 32a to collect holes, of the hole-electron pairs generated in the photoelectric conversion layer 32c, as signal charges. Furthermore, sensitivity can be adjusted by adjusting the magnitude of the voltage supplied by the voltage supply circuit 45 to the counter electrode 32b. When electrons are used as signal charges, a voltage is applied to the counter electrode 32b so that the potential of the counter electrode 32b is lower than the potential of the pixel electrode 32a.

[0089] Furthermore, the voltage supply circuit 45 may supply a voltage to the counter electrode 32b that does not substantially move the signal charge to the pixel electrode 32a, thereby making it possible to define a period for simultaneously collecting signal charge for all pixels 31 by the voltage supplied to the counter electrode 32b by the voltage supply circuit 45, thereby realizing a global shutter function.

[0090] 2 , the through electrode 51 is connected to the wiring 55 via a conductive layer 56 and a plug 57. The conductive layer 56 is disposed in an insulating layer 13 on the interlayer insulating layer 12. The upper surface of the conductive layer 56 is covered with an insulating layer 14 and is not exposed. The through electrode 51 and the plug 57 are connected to different positions on the lower surface of the conductive layer 56. The plug 57 connects the wiring 55 and the conductive layer 56.

[0091] Each of the pad groups 60 and 61 is composed of a plurality of pad electrodes. Each pad electrode of the pad groups 60 and 61 is connected to an external power supply, device, element, etc. External power, control signals, clocks, etc. are supplied to each circuit formed on the first substrate 10 and the second substrate 20 via the pad groups 60 and 61. The pad group 60 is arranged on the upper surface of the first substrate 10. The plurality of pad electrodes that make up the pad group 60 are arranged, for example, along the edge of the upper surface of the first substrate 10. The pad group 61 is arranged on the lower surface of the second substrate 20. The plurality of pad electrodes that make up the pad group 61 are arranged, for example, along the edge of the lower surface of the second substrate 20. Note that the number and arrangement of the pad electrodes that make up the pad groups 60 and 61 are not particularly limited.

[0092] [Planar Layout of Multiple Through Electrodes] Next, the planar layout of the multiple through electrodes 51 that make up the through electrode group 50 will be described. Fig. 5 is a plan view of the multiple through electrodes 51. In Fig. 5, patterns are applied to the multiple through electrodes 51 for ease of viewing. Fig. 5 also shows the arrangement of the multiple through electrodes 51 on the upper surface s11 of the first substrate 10. This also applies to the subsequent plan views showing the multiple through electrodes 51. In this specification, the arrangement of the multiple through electrodes 51 in a plan view is the arrangement when the semiconductor substrate 11 is sliced ​​at the upper surface s11.

[0093] As shown in FIG. 5 , the plurality of through electrodes 51 are arranged two-dimensionally in a planar view. The plurality of through electrodes 51 are arranged at equal intervals in the arrangement direction. In a planar view, a triangle having the centers of three adjacent through electrodes 51 among the plurality of through electrodes 51 as vertices is an acute triangle TRI. In other words, the plurality of through electrodes 51 includes three adjacent through electrodes 51 centered at the vertices of the acute triangle TRI in a planar view. The three adjacent through electrodes 51 refer to, for example, a certain through electrode 51, a through electrode 51 adjacent to the certain through electrode 51 in a first arrangement direction, and a through electrode 51 adjacent to the certain through electrode 51 in a second arrangement direction different from the first arrangement direction, among the plurality of through electrodes 51 arranged two-dimensionally. In the acute triangle TRI, for example, the height is shorter than the length of the base, regardless of which side of the acute triangle TRI is used as the base.

[0094] 5, in a plan view, the centers of the plurality of through electrodes 51 are located on lattice points of a triangular lattice having an acute triangle TRI as a unit lattice, thereby arranging the plurality of through electrodes 51 regularly and facilitating the layout of the plurality of wirings 55.

[0095] Next, a detailed planar layout of three adjacent through electrodes 51 will be described. Fig. 6 is a plan view showing an example of the planar layout of the plurality of through electrodes 51. Fig. 6 shows an excerpt of the plurality of through electrodes 51. Fig. 6 also shows the through electrodes 51 included in the through electrode group 50 located outside the pixel array 30 in the X-axis direction.

[0096] As shown in FIG. 6 , in a plan view, an acute triangle TRI having its vertex at the center of three adjacent through electrodes 51 is an equilateral triangle. Therefore, when the length of one side of the acute triangle TRI, which is the arrangement pitch of the through electrodes 51 in a plan view, is R, the height of the acute triangle TRI is √3R / 2. Since the triangle having its vertex at the center of three adjacent through electrodes 51 is an acute triangle TRI, the height of the acute triangle TRI can be made shorter than the distance between the centers of adjacent through electrodes 51. For example, when the acute triangle TRI is an equilateral triangle, the height of the acute triangle TRI is √3 / 2 times (≒0.87 times) the distance between the centers of adjacent through electrodes 51. When the through electrodes 51 are arranged at equal intervals, the distance between the centers of adjacent through electrodes 51 is the arrangement pitch of the plurality of through electrodes 51.

[0097] In contrast, when multiple through electrodes are arranged in a square lattice pattern as disclosed in Patent Document 1, a triangle with vertices at the centers of three adjacent through electrodes is a right-angled isosceles triangle. Therefore, the height of the right-angled isosceles triangle is the same as the arrangement pitch of the multiple through electrodes. On the other hand, as shown in FIG. 6 , by making the height of the acute triangle TRI shorter than the arrangement pitch of the multiple through electrodes 51, the through electrodes 51 can be arranged at a distance shorter than the arrangement pitch of the multiple through electrodes 51 in the height direction of the acute triangle TRI. This increases the coverage rate of the through electrodes 51 in the through electrode group 50, thereby reducing the area of ​​the region where the through electrode group 50 is formed. This allows the imaging device 100 to be miniaturized.

[0098] 6 , the plurality of through electrodes 51 includes a first through electrode 51a, which is one of the three adjacent through electrodes 51, and six second through electrodes 51b, which include the remaining two of the three adjacent through electrodes 51. The six second through electrodes 51b are adjacent to the first through electrode 51a and are arranged equidistant from each other from the first through electrode 51a. In plan view, a hexagon with vertices at the centers of the six second through electrodes 51b is a regular hexagon (HEX). This further increases the coverage rate of the through electrodes 51 in the through electrode group 50, thereby further reducing the area of ​​the region in which the through electrode group 50 is formed.

[0099] Furthermore, since the plurality of through electrodes 51 have the planar layout shown in FIG. 6 , it is possible to equalize the parasitic capacitance between adjacent through electrodes 51. FIG. 7 is a plan view for explaining the parasitic capacitance SC between adjacent through electrodes 51. FIG. 7 schematically shows the parasitic capacitance SC between adjacent through electrodes 51. As described above, when the acute triangle TRI is an equilateral triangle, the distance between adjacent through electrodes 51 is the same for any combination of adjacent through electrodes 51 in three adjacent through electrodes 51. As a result, the parasitic capacitance SC between adjacent through electrodes 51 is equalized, and the variation in the influence of the parasitic capacitance SC on signals can be suppressed, thereby enabling improvement in image quality.

[0100] Next, the positional relationship between the plurality of through electrodes 51 and the pixel array 30 will be described. FIG. 8 is a plan view for explaining the positional relationship between the plurality of through electrodes 51 and the pixel array 30. FIG. 8 shows a part of the pixel array 30 and some of the plurality of through electrodes 51 in the through electrode group 50 located on the positive side of the pixel array 30 in the X-axis direction. FIG. 8 also shows a plurality of wirings 55 that electrically connect the pixel array 30 to each of the plurality of through electrodes 51. As described above, the wirings 55 are provided in a one-to-one correspondence with the through electrodes 51, but for ease of viewing, FIG. 8 shows only the wirings 55 electrically connected to some of the through electrodes 51.

[0101] 8 , a first wiring 55a, which is one wiring 55 of the plurality of wirings 55, extends between two of three adjacent through electrodes 51 and is electrically connected to one through electrode 51 that is farther from the pixel array 30 than the two through electrodes 51 of the three adjacent through electrodes 51. This allows the wiring 55 to be arranged between the through electrodes 51, thereby enabling the imaging device 100 to be miniaturized.

[0102] 8 , in a plan view, one side of an acute triangle TRI having vertices at the centers of three adjacent through electrodes 51 is perpendicular to a side of the outer edge of the pixel array 30 that is adjacent to the three through electrodes 51. This allows the three wirings 55 electrically connected to the three through electrodes 51 to be connected to the pixel array 30 in the shortest distance without colliding with the three through electrodes 51. For example, the three wirings 55 electrically connected to the three through electrodes 51 can connect the pixel array 30 and the through electrodes 51 without meandering.

[0103] Furthermore, when the above-mentioned one side of the acute triangle TRI is set as a base B, the height h of the acute triangle TRI is shorter than the length of the base B. This makes it possible to further increase the coverage rate of the through electrodes 51 in the through electrode group 50 and further reduce the area of ​​the region where the through electrode group 50 is formed.

[0104] 8 , the side on the positive side in the X-axis direction of the pixel array 30 is perpendicular to the X-axis direction in which rows of the pixels 31 of the pixel array 30 are arranged. Therefore, one side of the acute triangle TRI in the through electrode group 50 located outside the pixel array 30 in the X-axis direction is parallel to the X-axis direction in which rows of the pixels 31 are arranged. Note that the acute triangle TRI does not necessarily have to include a side perpendicular to the side of the pixel array 30.

[0105] 8 , the plurality of through electrodes 51 are arranged in a plurality of columns extending in a direction perpendicular to the side adjacent to the three through electrodes 51 among the sides constituting the outer edge of the pixel array 30 (the X-axis direction) in a plan view. Furthermore, in a plan view, the positions of the through electrodes 51 arranged in adjacent columns among the plurality of columns in the arrangement direction are different from each other. This allows the plurality of wirings 55 electrically connected to the plurality of through electrodes 51 to be connected to the pixel array 30 over the shortest distance without colliding with the through electrodes 51.

[0106] In addition, in the through electrode group 50 located on the positive side of the Y axis direction of the pixel array 30, the planar layout of the plurality of through electrodes 51 shown in FIG. 8 is rotated by 90°.

[0107] [Another example of planar layout of multiple through electrodes] The planar layout of the multiple through electrodes 51 is not limited to the example described above, and is not particularly limited as long as the multiple through electrodes 51 are arranged so as to include three adjacent through electrodes 51 centered on the vertex of an acute triangle in plan view.

[0108] For example, the planar layout of the plurality of through electrodes 51 may be as shown in Fig. 9 to Fig. 11 . Fig. 9 is a plan view showing a first example of a planar layout of the plurality of through electrodes 51. Fig. 10 is a plan view showing a second example of a planar layout of the plurality of through electrodes 51. Fig. 11 is a plan view showing a third example of a planar layout of the plurality of through electrodes 51. Figs. 9 to 11 show an excerpt of some of the plurality of through electrodes 51. Figs. 9 to 11 also show through electrodes 51 included in a through electrode group 50 located outside the pixel array 30 in the X-axis direction.

[0109] 9 , the plurality of through electrodes 51 include three adjacent through electrodes 51 centered at the vertices of an acute triangle TRI1, which is an isosceles triangle that is not an equilateral triangle in plan view. One side of the acute triangle TRI1 is parallel to the X-axis direction and is shorter than the other two sides of the acute triangle TRI1. This makes it easier to arrange wiring 55 between the through electrodes 51.

[0110] 10 , the plurality of through electrodes 51 includes, in plan view, not only three adjacent through electrodes 51 centered on the vertex of an acute-angled triangle TRI2, but also a combination of three adjacent through electrodes 51 centered on the vertex of an obtuse-angled triangle TRI3. Furthermore, in the example shown in FIG. 11 , the plurality of through electrodes 51 includes, in plan view, not only three adjacent through electrodes 51 centered on the vertex of an acute-angled triangle TRI4, but also a combination of three adjacent through electrodes 51 centered on the vertex of an obtuse-angled triangle TRI5. As in these examples, when considering a combination of three adjacent through electrodes 51 including one through electrode 51 in a through electrode group 50, it is sufficient that the triangle having a vertex at the center of the three through electrodes 51 in at least one combination is an acute-angled triangle in plan view.

[0111] 10, the through electrodes 51 are arranged in a plurality of rows extending in the X-axis direction and in a zigzag pattern along the Y-axis direction. In the example shown in Fig. 11, the through electrodes 51 are arranged in a plurality of rows extending in the X-axis direction and in a plurality of rows extending in a direction inclined with respect to both the X-axis direction and the Y-axis direction.

[0112] [Modification 1] Next, a description will be given of Modification 1 of Embodiment 1. The following description will focus on the differences from Embodiment 1, and the description of the commonalities will be omitted or simplified.

[0113] FIG. 12 is a schematic cross-sectional view showing an example of the device structure of an imaging device 100A according to this modification.

[0114] As shown in FIG. 12, an imaging device 100A according to this modification differs from the imaging device 100 according to the first embodiment in that it does not include the conductive layer 56 and the plug 57.

[0115] In the imaging device 100A, the through electrodes 51 do not completely penetrate the interlayer insulating layer 12, and the through electrodes 51 and the wiring 55 are directly connected in the interlayer insulating layer 12. This allows the length of the through electrodes 51 to be shortened.

[0116] [Modification 2] Next, a description will be given of Modification 2 of Embodiment 1. The following description will focus on the differences between Embodiment 1 and Modification 1 of Embodiment 1, and description of commonalities will be omitted or simplified.

[0117] Fig. 13 is a schematic cross-sectional view showing an example of the device structure of the imaging device 200 according to this modification. Fig. 14 is a schematic diagram showing an example of the planar layout of the first substrate 10 of the imaging device 200 according to this modification. Fig. 15 is a schematic diagram showing an example of the planar layout of the third substrate 20A of the imaging device 200 according to this modification. Fig. 16 is a schematic diagram showing an example of the planar layout of the second substrate 20 of the imaging device 200 according to this modification.

[0118] As shown in Figures 13 to 16, the imaging device 200 of this modified example differs from the imaging device 100 of embodiment 1 mainly in that it further includes a third substrate 20A, a memory 46, a plurality of through electrodes 52, and a plurality of wirings 58.

[0119] 13, the first substrate 10, the third substrate 20A, and the second substrate 20 are stacked. The third substrate 20A is disposed between the first substrate 10 and the second substrate 20. For example, the first substrate 10, the third substrate 20A, and the second substrate 20 have the same shape and size in a plan view, and their outer edges coincide. Note that the positions of the second substrate 20 and the third substrate 20A may be interchanged.

[0120] The third substrate 20A has a semiconductor substrate 21A and an interlayer insulating layer 22A disposed above the semiconductor substrate 21A. The semiconductor substrate 21A is located between the semiconductor substrate 11 and the semiconductor substrate 21. In the example shown in FIG. 13 , the third substrate 20A is stacked on the first substrate 10 and the second substrate 20 so that the interlayer insulating layer 22A is sandwiched between the semiconductor substrate 11 and the semiconductor substrate 21A. The top and bottom of the third substrate 20A may be reversed from the example shown in FIG. 13 . The semiconductor substrate 21A is, for example, a p-type or n-type semiconductor substrate in which various impurity regions are formed.

[0121] A wiring structure is formed inside the interlayer insulating layer 22A. The wiring structure includes, for example, a plurality of wiring layers in which various types of wiring are formed. The interlayer insulating layer 22A is formed of, for example, an insulating material such as silicon dioxide.

[0122] 14, in the imaging device 200, a pixel array 30 and a through electrode group 50 are formed on a first substrate 10. Note that a pad group 60 may also be formed on the first substrate 10.

[0123] 15 , the third substrate 20A is formed with a memory 46 and a through electrode group 50. The through electrode group 50 is located outside the memory 46 in a plan view. The memory 46 is disposed at a position overlapping with the pixel array 30 in a plan view.

[0124] 16 , in the imaging device 200, a peripheral circuit 40 and a group of through electrodes 50 are formed on the second substrate 20. In the example shown in FIG. 16 , all of the circuits in the peripheral circuit 40 are arranged so as to be surrounded by three groups of through electrodes 50 in a plan view, but some of the circuits in the peripheral circuit 40 may be arranged between the groups of through electrodes 50 and the outer edge of the second substrate 20. Furthermore, some of the circuits in the peripheral circuit 40 may be formed on the third substrate 20A. Furthermore, a group of pads 61 may be formed on the second substrate 20.

[0125] As shown in FIG. 13 , in the imaging device 200 , each of the plurality of through electrodes 51 penetrates not only the semiconductor substrate 11 but also the interlayer insulating layer 22A and the semiconductor substrate 21A to reach the second substrate 20 .

[0126] The memory 46 is electrically connected to the peripheral circuit 40 via a plurality of wirings 58 and a plurality of through electrodes 52. The memory 46 is used, for example, as a frame memory and temporarily stores digital signals converted by the AD conversion circuit 41 after signal processing by the logic circuit 43 as necessary. The memory 46 stores, for example, reset signals corresponding to the reset levels of the pixels 31 before exposure and, as necessary, pixel signals corresponding to the signal levels of the pixels 31 after exposure. The data processing circuit 43a generates, for example, differential signals between the reset signals and the pixel signals and outputs the differential signals to the outside. As a result, a differential signal is output in which reset noise generated by resetting the pixels 31 has been removed from the pixel signals. The memory 46 is, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a magnetoresistive random access memory (MRAM), or a flash memory.

[0127] Each of the plurality of through electrodes 52 extends in the Z-axis direction, penetrates the semiconductor substrate 21A, and is connected to the third substrate 20A and the second substrate 20. In the second substrate 20, the through electrodes 52 are electrically connected to the peripheral circuit 40 formed on the second substrate 20. The through electrodes 52 are formed from, for example, a metal such as copper or tungsten, polysilicon doped with impurities, or a metal compound such as a metal nitride or a metal oxide.

[0128] The plurality of wirings 58 are disposed in the interlayer insulating layer 22A. The plurality of wirings 58 correspond one-to-one to the plurality of through electrodes 52, and electrically connect the memory 46 to the plurality of through electrodes 52. The plurality of wirings 58 are formed of a metal such as copper or tungsten, for example.

[0129] Even if the imaging device 200 includes the memory 46, the area can be reduced because the third substrate 20A on which the memory 46 is formed is stacked on the first substrate 10 and the second substrate 20.

[0130] [Modification 3] Next, a description will be given of Modification 3 of Embodiment 1. The following description will focus on the differences from Embodiment 1 and Modifications 1 and 2 of Embodiment 1, and description of commonalities will be omitted or simplified.

[0131] Fig. 17 is a schematic cross-sectional view showing an example of the device structure of an imaging device 300 according to this modification. Fig. 18 is a schematic diagram showing an example of the planar layout of a third substrate 10A of the imaging device 300 according to this modification. Fig. 19 is a schematic diagram showing an example of the planar layout of a first substrate 10 of the imaging device 300 according to this modification. Fig. 20 is a schematic diagram showing an example of the planar layout of a second substrate 20 of the imaging device 300 according to this modification.

[0132] As shown in Figures 17 to 20, the imaging device 300 of this modified example differs from the imaging device 100A of modified example 1 of embodiment 1 mainly in that it further includes a third substrate 10A, and that it includes a pixel array 30A including a plurality of pixels 31A instead of the pixel array 30 including a plurality of pixels 31.

[0133] 17 , the third substrate 10A, the first substrate 10, and the second substrate 20 are stacked. The third substrate 10A faces the second substrate 20 with the first substrate 10 interposed therebetween. The third substrate 10A is located above the first substrate 10 and the second substrate 20. The third substrate 10A, the first substrate 10, and the second substrate 20 have, for example, the same shape and size in a plan view, and their outer edges coincide.

[0134] The third substrate 10A has a semiconductor substrate 11A and an interlayer insulating layer 12A disposed below the semiconductor substrate 11A. The semiconductor substrate 11A faces the semiconductor substrate 21 via the semiconductor substrate 11. The semiconductor substrate 11A is located above the semiconductor substrates 11 and 21. The third substrate 10A is stacked on the first substrate 10 so that the interlayer insulating layer 12A is sandwiched between the interlayer insulating layer 12 and the semiconductor substrate 11A. The semiconductor substrate 11A is, for example, a p-type or n-type semiconductor substrate in which various impurity regions are formed.

[0135] A wiring structure is formed inside the interlayer insulating layer 12A. The wiring structure includes, for example, a plurality of wiring layers in which various types of wiring are formed. The interlayer insulating layer 12A is bonded to the interlayer insulating layer 12. The interlayer insulating layer 12A is formed of, for example, an insulating material such as silicon dioxide.

[0136] 18 , a pixel array 30A and a through electrode group 50 are formed on the third substrate 10A. The through electrode group 50 is located outside the pixel array 30A in a plan view. A pad group 60 may also be formed on the third substrate 10A.

[0137] As shown in FIG. 19, in the imaging device 300, a pixel array 30A and a through electrode group 50 are formed on a first substrate 10.

[0138] 20, in the imaging device 300, a peripheral circuit 40 and a through electrode group 50 are formed on the second substrate 20, similar to the imaging device 200. The peripheral circuit 40 overlaps with the pixel array 30A in a plan view.

[0139] The pixel array 30A includes a plurality of pixels 31A arranged in a plurality of rows and columns in a plan view. The pixel array 30A has a configuration in which the pixels 31 of the pixel array 30 are replaced with the pixels 31A. The pixel array 30A is formed across the first substrate 10 and the third substrate 10A.

[0140] The pixel array 30A is located on the upper surface s11 of the semiconductor substrate 11. Although an example in which one pixel 31A is located on the upper surface s11 of the semiconductor substrate 11 is illustrated in Fig. 17, all of the multiple pixels 31A that make up the pixel array 30A are located on the upper surface s11 of the semiconductor substrate 11.

[0141] 17 , the pixel 31A has a configuration in which the photoelectric conversion unit 32 and the pixel circuit 35 of the pixel 31 are replaced with a photoelectric conversion unit 36 ​​and a pixel circuit 37.

[0142] The photoelectric conversion unit 36 ​​is a photodiode formed in the semiconductor substrate 11A.

[0143] The pixel circuit 37 includes, for example, in addition to the configuration of the pixel circuit 35, a transfer transistor that transfers the charge generated in the photoelectric conversion unit 36 ​​to the charge accumulation region. A control signal for driving the transfer transistor is supplied from the vertical scanning circuit 44 via a control signal line L2. The transfer transistor is disposed on the lower surface s11A of the semiconductor substrate 11A. In the imaging device 300, some transistors of the charge detection circuit may be located on the lower surface s11A of the semiconductor substrate 11A.

[0144] In the imaging device 300, a plurality of wirings 55 are arranged in the interlayer insulating layer 12 and the interlayer insulating layer 12A. The plurality of wirings 55 includes wirings 55 electrically connected to the pixel circuits 37.

[0145] The imaging device 300 is configured such that the photoelectric conversion section 36 is formed within the semiconductor substrate 11A, but the third substrate 10A including the semiconductor substrate 11A is stacked on the first substrate 10 and the second substrate 20, making it possible to reduce the area.

[0146] (Embodiment 2) Next, a description will be given of embodiment 2. In embodiment 2, a camera system including an imaging device according to the present disclosure will be described.

[0147] FIG. 21 is a block diagram showing an example of the configuration of a camera system 400 according to this embodiment.

[0148] 21 , camera system 400 according to this embodiment includes lens optical system 601, imaging device 602, system controller 603, and camera signal processing circuit 604. Camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0149] The lens optical system 601 focuses light onto an imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The imaging device 602 may be, for example, an imaging device according to any one of the above-described first embodiment and modifications 1 to 3 of the first embodiment.

[0150] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0151] The camera signal processing circuit 604 has a function of processing an output signal from the image capture device 602. The camera signal processing circuit 604 receives output data from the image capture device 602 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The image capture device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 602 as a part thereof.

[0152] While the imaging device and camera system according to the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments, as well as other forms constructed by combining some of the components of the embodiments, are also included within the scope of the present disclosure.

[0153] For example, in the above embodiment, the imaging device includes the first substrate 10 and the second substrate 20, but is not limited to this. The imaging device according to the present disclosure may include only the first substrate 10 as a substrate, and the pixel circuit 35 or 37 may be connected to a device or element, etc., separate from the imaging device according to the present disclosure via the through electrode 51.

[0154] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0155] The imaging device and camera system according to the present disclosure are useful, for example, as an image sensor, a digital camera, etc. The imaging device and camera system according to the present disclosure can be used as a medical camera, a robot camera, a security camera, a camera mounted on a vehicle, etc.

[0156] 10 First substrate 10A, 20A Third substrate 11, 11A, 21, 21A Semiconductor substrate 12, 12A, 22, 22A Interlayer insulating layer 13, 14 Insulating layer 20 Second substrate 30, 30A Pixel array 31, 31A Pixel 32, 36 Photoelectric conversion unit 32a Pixel electrode 32b Counter electrode 32c Photoelectric conversion layer 33 Color filter 34 Microlens 35, 37 Pixel circuit 40 Peripheral circuit 41 AD conversion circuit 42, 46 Memory 43 Logic circuit 43a Data processing circuit 43b Output buffer circuit 43c Control circuit 44 Vertical scanning circuit 45 Voltage supply circuit 50 Through electrode group 51, 52 Through electrode 51a First through electrode 51b Second through electrode 55, 58 Wiring 55a First wiring 56 Conductive layer 57 Plug 60, 61 Pad group 100, 100A, 200, 300, 602 Imaging device 400 Camera system 601 Lens optical system 603 System controller 604 Camera signal processing circuit L1 Output signal line L2 Control signal line L3 Voltage line s11, s21 Upper surface s12, s11A Lower surface

Claims

1. An imaging device comprising: a first semiconductor substrate; a pixel array located on a first surface of the first semiconductor substrate and including a plurality of pixels; a plurality of through electrodes each penetrating the first semiconductor substrate and located outside the pixel array in a planar view; and a plurality of wirings electrically connecting the pixel array to each of the plurality of through electrodes, wherein in a planar view, a triangle having vertices at the centers of three adjacent through electrodes among the plurality of through electrodes forms an acute triangle.

2. The imaging device described in claim 1, wherein a first wiring of the plurality of wirings extends between two of the three through electrodes and is electrically connected to one through electrode that is farther from the pixel array than the two through electrodes of the three through electrodes.

3. The imaging device according to claim 1, wherein, in a plan view, one side of the acute triangle is perpendicular to the sides that are adjacent to the three through electrodes among the sides that form the outer edge of the pixel array.

4. The imaging device according to claim 3, wherein when the one side of the acute triangle is taken as a base, the height of the acute triangle is shorter than the length of the base.

5. An imaging device as described in claim 1, wherein, in a planar view, the plurality of through electrodes are arranged in a plurality of columns extending along a direction perpendicular to one of the sides constituting the outer edge of the pixel array that is adjacent to the three through electrodes, and in a planar view, the positions in the direction of the through electrodes arranged in adjacent columns of the plurality of columns are different from each other.

6. The imaging device according to claim 1, wherein, in a plan view, centers of the plurality of through electrodes are located on lattice points of a triangular lattice having the acute triangle as a unit lattice.

7. The imaging device described in claim 1, wherein each of the plurality of pixels includes a photoelectric conversion unit including a first electrode, a second electrode facing the first electrode, and a photoelectric conversion layer located between the first electrode and the second electrode, the second electrodes of the plurality of pixels are electrically connected to each other, and a second wiring of the plurality of wirings is electrically connected to the second electrode.

8. The imaging device according to claim 1, further comprising: a second semiconductor substrate stacked on a second surface side of the first semiconductor substrate opposite to the first surface; and a circuit formed on the second semiconductor substrate, the circuit being electrically connected to the plurality of through electrodes.

9. The imaging device according to claim 1, wherein the acute triangle is an equilateral triangle.

10. The imaging device described in claim 1, wherein the plurality of through electrodes include a first through electrode that is one of the three through electrodes and six second through electrodes including the remaining two through electrodes of the three through electrodes, the six second through electrodes being adjacent to the first through electrode and arranged equidistant from the first through electrode in a planar view, and wherein a hexagon having vertices at the centers of the six second through electrodes is a regular hexagon in a planar view.

11. A camera system comprising the imaging device according to any one of claims 1 to 10.

Images