Semiconductor chip, semiconductor device, information processing system, and semiconductor chip control method

Abstract

The present invention suppresses an increase in surface area and power consumption of a nonvolatile storage unit in a semiconductor chip for backing up and recovering data.　A bank switching control unit designates, as an executing bank, one bank from among a plurality of nonvolatile banks that does not correspond to a backup bank. When context is to be backed up, a normal backup and recovery processing unit performs backup processing for writing data read from a volatile storage unit to the executing bank and, when context is to be recovered, the normal backup and recovery processing unit performs recovery processing for writing, to the volatile storage unit and a backup bank, data read from the executing bank or from a recovery target bank designated by context switching. A power drop backup and recovery processing unit performs the backup processing when the power supply voltage has dropped to a value lower than a first threshold, and when the dropped power supply voltage has risen to a value higher than a second threshold, swaps the backup bank and the executing bank and then performs the recovery processing.

Description

Semiconductor chip, semiconductor device, information processing system, and semiconductor chip control method

[0001] The present technology relates to a semiconductor chip, and more particularly to a semiconductor chip, a semiconductor device, an information processing system, and a method for controlling a semiconductor chip that saves and restores data.

[0002] Conventionally, in various semiconductor chips, data evacuation and restoration processes may be performed when a power drop, an interruption, etc. For example, a processor has been proposed in which a nonvolatile memory bank for saving data from a volatile memory is duplicated, and while one of the duplicated nonvolatile memory banks is in use, the other bank backs up the data (see, for example, Non-Patent Document 1).

[0003] Shota Nakabeppu and two others, "Nonstop Processor Using Nonvolatile Elements," IEICE Technical Report, Vol. 120, No. 435, pp. 97-102

[0004] In the above-mentioned conventional technology, while one of the duplicated nonvolatile memory banks is in use, data is backed up to the other, thereby realizing normal operation when power is restored from a power outage. However, because the above-mentioned conventional technology requires duplication of the nonvolatile memory bank, the problem arises that the area and power consumption of the nonvolatile memory increase as the address space increases.

[0005] This technology was developed in light of these circumstances, and aims to suppress increases in the area and power consumption of non-volatile memory units in semiconductor chips that save and restore data.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof relates to a non-volatile memory device including a volatile memory unit, a non-volatile memory unit including a plurality of non-volatile banks, one of which is designated as a backup bank, a bank switching control unit that designates one of the plurality of non-volatile banks that does not correspond to the backup bank as an active bank, and a bank switching control unit that performs a save process of writing data read from the volatile memory unit to the active bank when saving a context, and when not performing context switching when restoring the context, writes data read from the active bank to the volatile memory unit and the non-volatile memory unit. A semiconductor chip and a control method thereof include a normal save / restore processing unit that performs a restoration process of writing data to the backup bank and, when a context switch is performed to restore the context, reading data from a bank to be restored specified by the context switch and writing the data to the volatile memory unit and the backup bank, and a power-down save / restore processing unit that performs the save process when a power supply voltage drops to a value lower than a first threshold, and swaps the backup bank and the active bank before performing the restoration process when the dropped power supply voltage rises to a value higher than a second threshold, thereby suppressing increases in the area and power consumption of the non-volatile memory unit.

[0007] In addition, in this first aspect, the memory device may further include a write processing unit that writes write data to the same address in the volatile memory unit and the active bank, and a read processing unit that reads data from the address in the volatile memory unit as first read data and reads data from the address in the active bank as second read data, wherein the normal save / restore processing unit and the power-down save / restore processing unit write the first read data to an address of all addresses in the active bank where the corresponding second read data does not match the first read data during the save processing, and the read processing unit performs the processing for a read that does not involve a write, thereby reducing rush current.

[0008] In this first aspect, the write processing unit may write the write data using a first write pulse, and the normal save / restore processing unit and the power drop save / restore processing unit may write the first read data using a second write pulse having a pulse width and / or voltage greater than that of the first write pulse, thereby suppressing write errors.

[0009] In addition, in this first aspect, the volatile memory unit may hold tag bits of initial values ​​for each address, the write processing unit may write the write data to the address using the first write pulse and update the corresponding tag bits to a value different from the initial value, the read processing unit may update the corresponding tag bits to the initial value if the first read data and the second read data match, and the normal save / recovery processing unit and the power drop save / recovery processing unit may write the first read data to an address of all the addresses whose corresponding tag bits are different from the initial value using the second write pulse. This brings about an effect of determining whether or not there is a mismatch based on the tag bits.

[0010] In the first aspect, the system may further include a register for storing bank numbers of the active bank and the backup bank, and the power failure save / restore processor may update the register to swap the backup bank and the active bank. This provides the advantage that, when there are two tasks, the bank numbers are managed appropriately.

[0011] In addition, in the first aspect, the system may further include a virtual / real bank number management table that stores a correspondence between virtual bank numbers assigned to interrupt processes or tasks and real bank numbers assigned to each of the plurality of non-volatile banks, and the power-down save / restore processing unit may swap the backup bank and the active bank by updating the register and the virtual / real bank number management table. This provides the effect of appropriately managing bank numbers even when there are three or more tasks.

[0012] In this first aspect, each of the volatile memory unit and the non-volatile memory unit may include at least one of a general-purpose register, a stack pointer register, a program counter register, a saved program counter register, a processor status word register, a saved status register, a procedure register, a multiplication register, a base register, a vector base register, a read data buffer register, and a write data buffer register, thereby suppressing increases in the area and power consumption of non-volatile general-purpose registers, etc.

[0013] In addition, in this first aspect, the volatile memory unit may include a volatile shared resource that stores shared data shared by a plurality of entities and a volatile non-shared resource that stores data other than the shared data, and the plurality of non-volatile banks may include a pair of non-volatile shared banks that store the shared data and a plurality of non-volatile non-shared banks that store data other than the shared data, thereby achieving an effect of efficient memory utilization.

[0014] A second aspect of the present technology is a memory device including: a detection circuit that detects when a power supply voltage drops to a value lower than a first threshold and when the power supply voltage rises to a value higher than a second threshold; a volatile storage unit; a non-volatile storage unit including a plurality of non-volatile banks, one of which is designated as a backup bank; a bank switching control unit that designates one of the plurality of non-volatile banks that is not the backup bank as an active bank; and a memory device that performs a saving process of writing data read from the volatile storage unit to the active bank when saving a context, and writes data read from the active bank when not performing context switching when restoring the context. a normal save / restore processing unit that performs a restoration process of writing data to the volatile memory unit and the backup bank, and, when a context switch is performed to restore the context, writing data read from a restoration target bank designated by the context switch to the volatile memory unit and the backup bank, and a power drop save / restore processing unit that performs the save process when the power supply voltage drops to a value lower than the first threshold, and, when the dropped power supply voltage rises to a value higher than the second threshold, swaps the backup bank and the active bank and then performs the restoration process, thereby achieving the effect of reducing power consumption of the semiconductor device.

[0015] A third aspect of the present technology is an information processing device that converts source code into object code, a volatile storage unit, a non-volatile storage unit including a plurality of non-volatile banks, one of which is designated as a backup bank, a bank switching control unit that designates one of the plurality of non-volatile banks that does not correspond to the backup bank as an active bank, and a bank switching control unit that performs a save process based on the object code when saving a context, in which data read from the volatile storage unit is written to the active bank, and when context switching is not performed when restoring the context, writes the data read from the active bank. and a power-down save / restore processor that performs the save process when a power supply voltage drops below a first threshold, and swaps the backup bank and the active bank before performing the recovery process when the dropped power supply voltage rises above a second threshold.This information processing system is equipped with a semiconductor chip that includes a normal save / restore processor that performs a recovery process of writing data to the volatile storage unit and the backup bank, and, when a context switch is performed to restore the context, reading data from a bank to be restored that is specified by the context switch and writing it to the volatile storage unit and the backup bank.This has the effect of reducing power consumption of the information processing system.

[0016] In addition, in this third aspect, the information processing device may merge code blocks into which the source code is divided using a checkpoint insertion method, thereby providing the effect of saving and restoring data for each code block.

[0017] In addition, in this third aspect, the information processing device may analyze data dependencies for each of the code blocks and identify variables to be saved in the saving process based on the dependencies, thereby reducing the number of write commands, read commands, and verify commands.

[0018] 1 is a block diagram showing an example of a configuration of a semiconductor chip according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example of a configuration of a digital signal processing unit according to the first embodiment of the present technology. FIG. 3 is a block diagram showing an example of a configuration of a CPU (Central Processing Unit) system compatible with power interruption recovery according to the first embodiment of the present technology. FIG. 4 is a block diagram showing an example of a configuration of a non-volatile register file according to the first embodiment of the present technology. FIG. 5 is a block diagram showing an example of a configuration of a volatile register file according to the first embodiment of the present technology. FIG. 6 is a circuit diagram showing an example of a configuration of a non-volatile register according to the first embodiment of the present technology. FIG. 7 is a circuit diagram showing an example of a configuration of a volatile register according to the first embodiment of the present technology. FIG. 8 is a diagram showing an example of a signal list according to the first embodiment of the present technology. FIG. 9 is a diagram showing an example of a configuration of a BN register configured of a non-volatile register or non-volatile memory in which read verification is performed until writing is successful according to the first embodiment of the present technology. FIG. 10 is a flowchart showing an example of a write process according to the first embodiment of the present technology. FIG. 11 is a flowchart showing an example of a read process according to the first embodiment of the present technology. FIG. 12 is a flowchart showing an example of a normal save and restore process according to the first embodiment of the present technology. FIG. 13 is a flowchart showing another example of a normal save and restore process according to the first embodiment of the present technology. FIG. 14 is a flowchart showing an example of a save and restore process during a power drop according to the first embodiment of the present technology. Fig. 1 is a flowchart showing another example of save and restore processing during power failure in the first embodiment of the present technology. Fig. 2 is a diagram for explaining an example of normal save and restore processing in the first embodiment of the present technology. Fig. 3 is a diagram for explaining an example of save and restore processing during power failure in the first embodiment of the present technology. Fig. 4 is a block diagram showing an example of a configuration of a CPU system compatible with power interruption and restoration in a first modified example of the first embodiment of the present technology. Fig. 5 is a diagram showing an example of a configuration of a virtual / real bank number management table in a first modified example of the first embodiment of the present technology. Fig. 6 is a circuit diagram showing an example of a configuration of a non-volatile register constituting the virtual / real bank number management table in the first modified example of the first embodiment of the present technology.1 is a diagram showing an example of updating a virtual / real bank number management table and a BN register configured as a nonvolatile register or nonvolatile memory in which read verification is performed until writing is successful in a first modified example of the first embodiment of the present technology. FIG. 2 is a flowchart showing another example of save / restore processing during power drop in a first modified example of the first embodiment of the present technology. FIG. 3 is a diagram showing an example of a configuration of a BN register configured as a nonvolatile register or nonvolatile memory in which read verification is performed until writing is successful in a second modified example of the first embodiment of the present technology. FIG. 4 is a diagram showing an example of a configuration of an associative memory in a second modified example of the first embodiment of the present technology. FIG. 5 is a block diagram showing an example of a configuration of a CPU system compatible with power interruption recovery in a second embodiment of the present technology. FIG. 6 is a diagram showing a list of registers in a second embodiment of the present technology. FIG. 7 is a block diagram showing an example of a configuration of a storage unit in a second embodiment of the present technology. FIG. 8 is a block diagram showing an example of a configuration of a storage unit in a third embodiment of the present technology. FIG. 9 is a block diagram showing an example of a configuration of a volatile memory in a third embodiment of the present technology. FIG. 10 is a diagram showing an example of a configuration of a BN register configured as a nonvolatile register or nonvolatile memory in which read verification is performed until writing is successful in a third embodiment of the present technology. FIG. 1 is a block diagram showing a configuration example of a semiconductor device according to a fourth embodiment of the present technology. FIG. 2 is a block diagram showing a configuration example of an information processing system according to a fifth embodiment of the present technology. FIG. 3 is a diagram showing an example of source code according to the fifth embodiment of the present technology. FIG. 4 is a diagram showing an example of a code block according to the fifth embodiment of the present technology. FIG. 5 is a diagram showing an example of a revision of a code block according to the fifth embodiment of the present technology. FIG. 6 is a diagram showing an example of a set of assignment statements according to the fifth embodiment of the present technology. FIG. 7 is a diagram showing an example of variables to be read and verified according to the fifth embodiment of the present technology. FIG. 8 is a diagram showing an example of a checkpoint function to be replaced according to the fifth embodiment of the present technology. FIG. 9 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 10 is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit.

[0019] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order: 1. First embodiment (example of swapping an active bank and a backup bank) 2. Second embodiment (example of swapping an active bank and a backup bank in a CPU register file) 3. Third embodiment (example of providing shared resources and non-shared resources and swapping an active bank and a backup bank) 4. Fourth embodiment (example of swapping an active bank and a backup bank according to the detection result of a power rise) 5. Fifth embodiment (example of swapping an active bank and a backup bank according to a code) 6. Application example to a mobile body

[0020] 1 is a block diagram showing an example of the configuration of a semiconductor chip 200 according to an embodiment of the present technology. The semiconductor chip 200 is a CIS (CMOS Image Sensor) and includes a vertical drive circuit 211, a timing control unit 212, a DAC (Digital to Analog Converter) 213, and a pixel array unit 214. The semiconductor chip 200 further includes a column signal processing unit 215, a horizontal transfer control unit 216, and a digital signal processing unit 220.

[0021] A plurality of pixels are arranged in a two-dimensional lattice in the pixel array section 214. The vertical drive circuit 211 sequentially selects rows in the pixel array section 214, drives each pixel in that row, and outputs an analog signal to the column signal processing section 215.

[0022] The timing control section 212 controls the operation timing of each of the vertical drive circuit 211 , the DAC 213 , the column signal processing section 215 and the horizontal transfer control section 216 .

[0023] The DAC 213 generates a sawtooth ramp signal by DA (Digital to Analog) conversion and supplies it to the column signal processing unit 215 .

[0024] An ADC (Analog to Digital Converter) is arranged in the column signal processing unit 215 for each column of the pixel array unit 214. The ADC converts an analog signal from the corresponding column into a digital signal and supplies the digital signal to the digital signal processing unit 220 under the control of the horizontal transfer control unit 216.

[0025] The horizontal transfer control unit 216 controls the column signal processing unit 215 to output the digital signals of each column in sequence.

[0026] The digital signal processing unit 220 performs various signal processing such as white balance correction and demosaic processing on the digital signal from the column signal processing unit 215. The digital signal processing unit 220 outputs image data after processing.

[0027] 2 is a block diagram showing an example of the configuration of the digital signal processing unit 220 according to the first embodiment of the present technology. The digital signal processing unit 220 includes an external setting input / output interface 221, an external setting nonvolatile register group 222, and a power interruption recovery compatible CPU system 300.

[0028] The external setting input / output interface 221 receives data for initial setting and mid-setting changes from the outside and stores the data in the external setting nonvolatile register group 222. The external setting input / output interface 221 also transmits data read from the external setting nonvolatile register group 222 to the outside.

[0029] The power interruption recovery compatible CPU system 300 saves data when the power supply voltage drops, and restores the data when the power supply voltage is restored.

[0030] 3 is a block diagram showing an example of a configuration of a power interruption recovery support CPU system 300 according to the first embodiment of the present technology. The power interruption recovery support CPU system 300 includes an access control unit 310, a BN register 340, and a storage unit 400.

[0031] The access control unit 310 includes a write processing unit 311, a read processing unit 312, a bank switching control unit 313, a normal save / restore processing unit 314, and a power drop save / restore processing unit 315. The memory unit 400 includes a non-volatile register file 410 and a volatile register file 450.

[0032] Although the figure uses a nonvolatile register file 410 and a volatile register file 450, volatile memory and nonvolatile memory can be used instead. For example, a combination of static random access memory (SRAM) and nonvolatile RAM, or a combination of dynamic random access memory (DRAM) and nonvolatile RAM can be used. Furthermore, a magnetic memory can be used as the nonvolatile memory. For example, a spin transfer torque (STT)-magnetoresistive random access memory (MRAM) can be used as this magnetic memory. Furthermore, the magnetic memory is not limited to STT-MRAM, and new magnetic memories such as voltage-controlled magnetic anisotropy (VCMA)-MRAM and spin-orbit torque (SOT)-MRAM can also be used.

[0033] Furthermore, the nonvolatile register file 410 is an example of a nonvolatile storage unit as defined in the claims, and the volatile register file 450 is an example of a volatile storage unit as defined in the claims.

[0034] The details of the processing performed by the write processing unit 311, the read processing unit 312, the bank switching control unit 313, the normal save / restore processing unit 314, and the power drop save / restore processing unit 315 will be described later.

[0035] It should be noted that a power interruption recovery support system having the same functions as the power interruption recovery support CPU system 300 can be provided independently in an AE (Auto Exposure) control unit external to the digital signal processing unit 220. In this case, the power interruption recovery support system in the AE control unit performs recovery operations after a power interruption independently of the power interruption recovery support CPU system 300 in accordance with user settings.

[0036] Furthermore, although the power interruption recovery compatible CPU system 300 is disposed within the semiconductor chip 200, which is a CIS, the present invention is not limited to this configuration. The power interruption recovery compatible CPU system 300 can also be disposed within various semiconductor chips other than a CIS.

[0037] 4 is a block diagram showing an example of the configuration of a nonvolatile register file 410 according to the first embodiment of the present technology. The nonvolatile register file 410 includes an address decoder 411, a bank number decoder 412, a nonvolatile register group 413, and an output selector 414. The nonvolatile register group 413 includes K (K is an integer equal to or greater than 2) nonvolatile registers 420. Each of the nonvolatile registers 420 has an address ADDR ＮＶ is assigned.

[0038] Furthermore, the nonvolatile register group 413 is divided into N+1 (N is an integer equal to or greater than 2) nonvolatile register banks 415. The volatile register file 450 and the N+1 nonvolatile register banks 415 have the same size and number of addresses. Here, N of the N+1 banks are accessible to the CPU. Therefore, if the size of each nonvolatile register bank 415 is B (B is an integer) bits, the size of the address space accessible to the CPU is N×B bits. Of the N+1 banks, one extra bank is designated as a data backup destination. This backup destination bank will be referred to as the "backup bank" hereinafter.

[0039] The bank number of the backup bank is held in the BN register 340. This bank number of the backup bank is not a fixed value but is variable. An example of the timing at which the bank number of the backup bank is changed will be described later.

[0040] The address decoder 411 receives the address ADDR from the access control unit 310. ＮＶ The address decoder 411 receives the address ADDR ＮＶ is decoded to obtain a K-bit one-hot signal DEC Ａ Generates one-hot signal DEC Ａ Among them, the address ADDR ＮＶ Only the bit corresponding to the one-hot signal DEC is set to logic value "1", and the remaining bits are set to logic value "0". Ａ to the nonvolatile register group 413 and the output selector 414.

[0041] The address ADDR from the access control unit 310 ＮＶ If it is out of range, the address decoder 411 outputs a one-hot signal DEC Ａ may be output.

[0042] The bank number decoder 412 decodes the bank number BN from the access control unit 310 and outputs an N-bit one-hot signal DEC Ｂ This bank number BN indicates the number of the currently active bank among the N accessible banks. This currently active bank will be referred to as the "active bank" hereinafter. The bank switching control unit 313 designates one of the N nonvolatile register banks 415 that do not correspond to the backup banks as the active bank, and switches between them as necessary.

[0043] Also, the N-bit one-hot signal DEC Ｂ Only the bit corresponding to the bank number BN is set to a logical value of "1", and the remaining bits are set to a logical value of "0". Ｂ are supplied to the nonvolatile register group 413 and the output selector 414.

[0044] The output selector 414 outputs the one-hot signal DEC Ａ and DEC Ｂ The output selector 414 selects one of the nonvolatile register output signals NVQ of each register based on the one-hot signal DEC. Ｂ , the nonvolatile register bank 415 corresponding to the bit with the logic value "1" is selected, and the one-hot signal DEC Ａ , the nonvolatile register 420 corresponding to the bit with the logic value “1.” The output selector 414 then outputs the nonvolatile register output signal NVQ from the selected nonvolatile register 420 to the volatile register file 450.

[0045] 5 is a block diagram showing an example of the configuration of the volatile register file 450 according to the first embodiment of the present technology. The volatile register file 450 includes an address decoder 451, a volatile register group 452, an output selector 453, and a comparator 454. The volatile register group 452 has K volatile registers 460 arranged therein. Each of these volatile registers 460 has an address ADDR Ｖ is assigned.

[0046] The volatile register group 452 also stores an address ADDR Ｖ A one-bit tag bit TAG (not shown) is held for each.

[0047] The address decoder 451 receives the address ADDR Ｖ and generates a K-bit one-hot signal DEC, which is output to the volatile register group 452 and the output selector 453 .

[0048] The output selector 453 selects one of the volatile register output signals VQ from each of the volatile registers 460 based on the one-hot signal DEC. The output selector 453 selects a signal corresponding to a bit with a logical value of "1" from the one-hot signal DEC and outputs it to the comparator 454.

[0049] The comparator 454 compares the nonvolatile register output signal NVQ from the nonvolatile register file 410 with the volatile register output signal VQ from the output selector 453. The comparator 454 supplies a comparison result signal CMP_OUT indicating the comparison result to the volatile register group 452.

[0050] 6 is a circuit diagram showing an example of the configuration of the nonvolatile register 420 according to the first embodiment of the present technology. The nonvolatile register 420 receives DEC from the address decoder 411 and the bank number decoder 412. Ａ [k] and DEC Ｂ [n] is input to the nonvolatile register 420. The access control signal R / W, data input signal D, register save enable signal REN, and clock signal CK are also input to the nonvolatile register 420 from the access control unit 310. The volatile register output signal VQ and tag bit TAG from the volatile register file 450 are also input to the nonvolatile register 420. The nonvolatile register 420 then outputs the nonvolatile register output signal NVQ to the volatile register file 450 and the output selector 414.

[0051] DEC Ａ [k] is the one-hot signal DEC Ａ and is input to the kth nonvolatile register 420 in the nonvolatile register bank 415. Ｂ [n] is the one-hot signal DEC Ｂ , and is input to the nth nonvolatile register bank 415.

[0052] The access control signal R / W is a signal that indicates either a read without a write or a write. For example, the access control signal R / W is set to a logical value "0" when reading without a write, and to a logical value "1" when writing.

[0053] The data input signal D indicates write data to be written to the nonvolatile register 420 and the volatile register 460. The data size of this write data is assumed to be J bits (J is an integer).

[0054] The volatile register output signal VQ indicates read data read from the volatile register 460 in the volatile register file 450. The data size of this read data is also J bits. The volatile register output signal VQ is an example of the first read data described in the claims.

[0055] The tag bit TAG is a signal indicating the status of writing to the corresponding nonvolatile register 420. For example, when there is no writing to the nonvolatile register 420 (in other words, the initial state) or when writing is completed, the corresponding tag bit TAG is set to a logical value of "0" as an initial value, and when writing is temporarily performed, a logical value of "1" is set.

[0056] The register save enable signal REN is a signal indicating whether or not the function of saving from the volatile register 460 to the non-volatile register 420 is enabled. For example, when disabled, the register save enable signal REN is set to a logical value of "0," and when enabled, the signal is set to a logical value of "1."

[0057] The nonvolatile register output signal NVQ indicates the read data read from the nonvolatile register 420. The nonvolatile register output signal NVQ is an example of the second read data set forth in the claims.

[0058] Here, K addresses ADDR on the nonvolatile side ＮＶ and K addresses ADDR in each bank on the volatile side Ｖ and have a one-to-one correspondence. The volatile register output signal VQ and tag bit TAG from the kth volatile register 460 are input to the kth non-volatile register 420 in the active bank. The non-volatile register output signal NVQ from the kth non-volatile register 420 in the active bank is output to the kth volatile register 460 and the output selector 414.

[0059] The nonvolatile register 420 also includes AND (logical product) gates 421 , 422 and 423 , selectors 424 and 425 , and a nonvolatile multi-bit flip-flop 426 .

[0060] AND gate 421 is Ａ [k] and DEC Ｂ The logical product with [n] is output to the selector 424 .

[0061] The AND gate 422 outputs the logical product of the access control signal R / W and the output signal of the AND gate 421 to the selector 424 .

[0062] The selector 424 selects the output signal of the AND gate 422 when the register save enable signal REN is a logical value “0”, and selects the tag bit TAG and outputs it to the AND gate 423 when the register save enable signal REN is a logical value “1”.

[0063] The AND gate 423 outputs the logical product of the output signal of the selector 424 and the clock signal CK to the clock terminal of the nonvolatile multi-bit flip-flop 426 .

[0064] The selector 425 selects the data input signal D when the register save enable signal REN is a logical value "0", and selects the volatile register output signal VQ when the register save enable signal REN is a logical value "1", and outputs it to the input terminal of the non-volatile multi-bit flip-flop 426.

[0065] The nonvolatile multi-bit flip-flop 426 holds the output signal of the selector 424. The size of this nonvolatile multi-bit flip-flop 426 is J bits. The nonvolatile multi-bit flip-flop 426 outputs the held signal as a nonvolatile register output signal NVQ.

[0066] The configuration shown in the figure realizes the following operation. First, the case where the register save enable signal REN is disabled will be described. In this case, R / W is a logical value "1" indicating a write, and DEC Ａ [k] and DEC ＢConsider the case where [n] is a logical value of "1" (i.e., the kth address in the nth bank is selected). At this time, the nonvolatile register 420 at that address writes the data input signal D to the nonvolatile multi-bit flip-flop 426. The R / W pulse of "1" during this write is called write pulse P1. If this condition is not met, the nonvolatile register 420 retains the previous value.

[0067] Next, a case where the register save enable signal REN is enabled will be described. In this case, when the tag bit TAG from the kth volatile register 460 is a logical value "1," the kth nonvolatile register 420 writes the VQ from that volatile register 460 to the nonvolatile multi-bit flip-flop 426. If the write pulse used in this write is designated P2, at least one of the pulse width and voltage of P2 is greater than P1. The pulse width and voltage of the write pulse P2 are set to values ​​that ensure 100% successful writing. Note that the write pulses P1 and P2 are examples of the first and second write pulses defined in the claims.

[0068] Furthermore, after writing during backup, the access control unit 310 reads data from the volatile register 460 and the nonvolatile register 420, determines whether they match, and repeatedly rewrites the data until they match. Note that the nonvolatile multi-bit flip-flop 426 always outputs the stored value, and if the value is updated, the updated value is reflected in the output signal from the cycle following the write cycle.

[0069] 7 is a circuit diagram showing an example of the configuration of the volatile register 460 according to the first embodiment of the present technology. The volatile register 460 receives the DEC[k] signal from the address decoder 411, the access control signal R / W, the data input signal D, and the register restore signal REST from the access control unit 310, and the clock signal CK. The volatile register 460 also receives the nonvolatile register output signal NVQ from the nonvolatile register file 410 and the comparison result signal CMP_OUT from the comparator 454. The volatile register 460 then outputs the volatile register output signal VQ to the nonvolatile register file 410 and the output selector 453. The volatile register 460 also outputs the tag bit TAG to the nonvolatile register file 410.

[0070] The comparison result signal CMP_OUT is a signal that indicates whether or not the read data of the non-volatile register 420 matches the read data of the corresponding volatile register 460. For example, if the read data matches, the comparison result signal CMP_OUT is set to a logical value of "1," and if they do not match, the logical value is set to "0."

[0071] The register restore signal REST is a signal indicating whether or not to write (in other words, restore) data from the nonvolatile register 420 to the corresponding volatile register 460 after saving. For example, if restoration is to be performed, the register restore signal REST is set to a logical value of "1," and if restoration is not to be performed, the register restore signal REST is set to a logical value of "0."

[0072] Volatile register 460 also includes AND gates 461 to 464 , logic gates 465 and 466 , an OR (logical sum) gate 467 , a selector 468 , a volatile multi-bit flip-flop 469 , and a one-bit flip-flop 470 .

[0073] The AND gate 461 outputs the logical product of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal to the OR gate 467 .

[0074] The OR gate 467 outputs the logical sum of the register restore signal REST and the output signal of the AND gate 461 to the AND gate 462 .

[0075] The AND gate 462 outputs the logical product of the output signal of the OR gate 467 and the clock signal CK to the clock terminal of the volatile multi-bit flip-flop 469 .

[0076] The selector 468 selects the data input signal D when the register recovery signal REST is a logical value "0", and selects the non-volatile register output signal NVQ when the register recovery signal REST is a logical value "1", and outputs it to the input terminal of the volatile multi-bit flip-flop 469.

[0077] The volatile multi-bit flip-flop 469 holds the output signal of the selector 468. The size of this volatile multi-bit flip-flop 469 is J bits. The volatile multi-bit flip-flop 469 outputs the held signal as a volatile register output signal VQ.

[0078] The logic gate 466 outputs to the logic gate 465 the logical product of the inverted value of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal.

[0079] The logic gate 465 calculates the logical product of the inverted value of the clock signal CK, the comparison result signal CMP_OUT, and the output signal of the logic gate 466 , and outputs the logical sum of this logical product and the register restore signal REST to the 1-bit flip-flop 470 .

[0080] The AND gate 464 outputs to the AND gate 463 the logical product of the access control signal R / W and the k-th bit DEC[k] of the one-hot signal.

[0081] The AND gate 463 inputs the logical product of the output signal of the AND gate 464 and the clock signal CK to the clock terminal of the 1-bit flip-flop 470 .

[0082] The one-bit flip-flop 470 is volatile and holds the tag bit TAG. A high level (i.e., a logical value "1") is input to a set terminal S of the one-bit flip-flop 470. An inverted value of the output signal of the logic gate 465 is input to a reset terminal R of the one-bit flip-flop 470. The input to the reset terminal R of the one-bit flip-flop 470 takes priority in determining the output value. The one-bit flip-flop 470 also outputs the tag bit TAG to the non-volatile register file 410.

[0083] The configuration illustrated in the figure achieves the following operations. First, we will explain the case where the register restore signal REST is disabled. In this case, when R / W is a logical value "1" indicating a write and DEC[k] is a logical value "1," the volatile register 460 writes the data input signal D to the volatile multi-bit flip-flop 469 and updates the one-bit flip-flop 470 to a logical value "1." Also, when R / W is a logical value "0" indicating a read and DEC[k] is a logical value "1," the volatile register 460 initializes the one-bit flip-flop 470 to a logical value "0" while the clock signal CK is "0" if the comparison result signal CMP_OUT is a logical value "1." If these conditions are not met, the volatile register 460 retains its previous value.

[0084] Next, a case where the register restore signal REST is enabled will be described. In this case, the volatile register 460 writes the nonvolatile register output signal NVQ from the nonvolatile register 420 having the same DEC[k] to the volatile multi-bit flip-flop 469 and initializes the one-bit flip-flop 470 to a logical value of "0."

[0085] Fig. 8 is a diagram showing an example of a signal list according to the first embodiment of the present technology, which lists the signal names and descriptions of the signals described above with reference to Figs.

[0086] 9 is a diagram showing an example of the configuration of the BN register 340 according to the first embodiment of the present technology. The BN register 340 includes a BN1 register, a BN2 register, and a BN3 register. The size of each register is, for example, 16 bits.

[0087] For simplicity, the interrupt numbers are assumed to be, for example, 1 to 15. A fixed priority system is used, where the larger the interrupt number, the higher the interrupt priority. Note that a round-robin system may be used instead of the fixed priority system.

[0088] Furthermore, HE01 to HE15, which set whether to allow or prohibit bank use for each interrupt number, are assigned to bits 1 to 15 of the BN1 register. Each of HE01 to HE15 is set to a logical value of "0" when the corresponding bank is prohibited from use, and a logical value of "1" when the bank is permitted to be used. Bit 0 of the BN1 register is a reserved bit.

[0089] The BN2 register also has a field for holding a bank enable BNE and a field for holding the bank number BN of the active bank.

[0090] The size of the bank enable BNE is, for example, 2 bits. If the use of a bank is prohibited for all interrupts, the bank enable BNE is set to "00" in binary. If the use of a bank is permitted for all interrupts except for NMI (Non Maskable Interrupt), the bank enable BNE is set to "01" in binary. If the permission or prohibition of bank use follows the setting of the BN1 register, the bank enable BNE is set to "11" in binary. The value "10" in binary is reserved for the bank enable BNE.

[0091] The bank number BN field holds the bank number currently being executed or the first address of the currently being executed bank. For simplicity, we will assume that there are 16 banks, and that the bank numbers correspond to the interrupt numbers. Bank number "0" is assigned, for example, to initialization processing from startup before an interrupt is accepted.

[0092] The BN3 register has a field for holding an access flag bit AF, a field for holding a recovery flag bit BF, a field for holding an evacuation flag bit EF, and a field for holding a backup bank number BBN.

[0093] The initial value of the access flag bit AF is a logical value "0", and a logical value "1" is set at the first write to the volatile register file 450 after the completion of restoration of the non-volatile register bank 415. Furthermore, at the start of saving, the access flag bit AF is initialized to a logical value "0".

[0094] The recovery flag bit BF is two bits, and its initial value is binary "00." When recovery of the nonvolatile register bank 415 begins, the recovery flag bit BF is set to binary "01," and when recovery is complete, the recovery flag bit BF is set to binary "10." Furthermore, when the bank number BN of the BN2 register is changed, the recovery flag bit BF is initialized to binary "00."

[0095] The save flag bit EF is two bits, and its initial value is binary "00." When saving of the nonvolatile register bank 415 begins, the save flag bit EF is set to binary "01," and when saving is complete, the save flag bit EF is set to binary "10." Furthermore, when the bank number BN of the BN2 register is changed, the save flag bit EF is initialized to binary "00."

[0096] The backup bank number BBN is the bank number of the backup bank used for fallback in the event of an instantaneous power outage during task execution or bank evacuation processing.

[0097] [Example of Operation of Semiconductor Chip] Next, the operation of the CPU system 300 for recovery from power interruption will be described with reference to Figures 10 to 13. Write and read commands are issued by executing various programs in the CPU system 300 for recovery from power interruption. The order of write and read commands and the timing of the commands are determined depending on the contents of the programs and the processing status. When a write command is issued, the write process of Figure 10 is executed, and when a read command without a write is issued, the read process of Figure 11 is executed.

[0098] In addition, when an interrupt occurs, a task switch occurs, or a power failure occurs, a save command is issued to save and restore the CPU state (i.e., context). When the context is saved due to a reason other than a power failure, such as an interrupt or a task switch, the normal save and restore process shown in FIG. 12 is executed. In addition, when the power supply voltage exceeds the threshold V ｌоｗ If it drops to a lower value, the power down save and restore process of FIG. 13 is executed to save the context.

[0099] 10 illustrates processing corresponding to a write instruction to both the volatile register file 450 and the non-volatile register file 410. FIG. 12 illustrates processing corresponding to a read instruction with comparison from both the volatile register file 450 and the non-volatile register file 410. FIGS. 13 and 16 illustrate processing corresponding to a save instruction. In addition to these three instructions, a write instruction to only the volatile register file 450 and a read instruction without comparison from both the volatile register file 450 and the non-volatile register file 410 can also be added. What instructions are assigned to which writes and reads, and the timing of inserting the save instructions are determined at compile time.

[0100] 10 is a flowchart illustrating an example of a write process according to the first embodiment of the present technology. The write processing unit 311 in the power interruption recovery compatible CPU system 300 writes write data to the same address of the volatile register file 450 and the active bank corresponding to the bank number BN by using a write pulse P1 (step S901).

[0101] For example, the kth volatile address ADDR is used as the write destination. Ｖ If the address is specified, the address and the kth address ADDR in the active bank are used. ＮＶ The same write data is written to both.

[0102] The write processing unit 311 also updates the tag bit corresponding to the address of the access destination to a logical value of "1" (step S902), and ends the write processing.

[0103] 11 is a flowchart illustrating an example of a read process without writing according to the first embodiment of the present technology. The read processing unit 312 in the power interruption recovery compatible CPU system 300 reads data from the same address as both the volatile register file 450 and the active bank indicated by BN (step S911).

[0104] For example, the kth volatile side address ADDR is used as the read destination. Ｖ If the address is specified, the address and the kth address ADDR in the active bank are used. ＮＶ The read data on the volatile side corresponds to the volatile register output signal VQ described above, and the read data on the nonvolatile side corresponds to the nonvolatile register output signal NVQ described above.

[0105] The comparator 454 in the volatile register file 450 determines whether the volatile read data (VQ) and the non-volatile read data (NVQ) match (step S912).

[0106] If the read data matches (step S912: Yes), the read processing unit 312 updates the tag bit of the access destination to the logical value "0" (step S913). If the read data does not match (step S912: No), or after step S913, the read processing unit 312 ends the read process.

[0107] 10 and 11 , the access control unit 310 can also execute the following process. For example, the access control unit 310 periodically checks the tag bits of the volatile register file 450, and if any of them contain a logical value of "1," it performs revisions such as gradually increasing the voltage or lengthening the write pulse width up to the upper limit of the period corresponding to the frequency. The access control unit 310 then writes data at an address where the tag bit has a logical value of "1" from the volatile register file 450 to the non-volatile register file 410 using the revised high voltage and long write pulse width. The access control unit 310 then clears the tag bit to a logical value of "0" after writing is complete.

[0108] If all tag bits become logical "0," the access control unit 310 may store the voltage and write pulse width in nonvolatile memory and use them as default values ​​thereafter. When a logical "1" appears in the tag bit value, the access control unit 310 performs an additional update. This allows for stable writing at a low voltage and short write pulse width appropriately selected according to the operating conditions of the chip, rather than the voltage and write pulse width that are previously set to ensure 100% successful writing.

[0109] 12 is a flowchart showing an example of normal save / restore processing in the first embodiment of the present technology. The normal save / restore processing unit 314 in the power interruption recovery-compatible CPU system 300 specifies an address to access when saving a context (step S921), and determines whether the tag bit of the address is logical "1" (step S922).

[0110] If the tag bit is logical "1" (step S922: Yes), the normal save / restore processing unit 314 writes the read data (VQ) from the volatile register 460 to the active bank indicated by BN using a high-voltage write pulse P2 (step S923).

[0111] For example, the kth nonvolatile address ADDR ＮＶ If the corresponding k-th tag bit is a logical "1", then the k-th volatile side address ADDR Ｖ The read data (VQ) is at its address ADDR ＮＶ is written to.

[0112] If the tag bit is logical "0" (step S922: No), or after step S923, the normal save / restore processor 314 determines whether all addresses have been specified (step S924). If all addresses have not been specified (step S924: No), the normal save / restore processor 314 repeats step S921 and subsequent steps. The processes from step S921 to S924 correspond to the save process. Furthermore, as described below, all data corresponding to a group of addresses on the volatile side where the tag bit has a logical value of "1" may be written at once to the same corresponding group of addresses on the non-volatile side.

[0113] If all addresses have been specified (step S924: Yes), the normal save / restore processor 314 determines whether it is time to restore the context (step S925). If it is not time to restore the context (step S925: No), the normal save / restore processor 314 returns to step S925.

[0114] If it is time for recovery (step S925: Yes), the normal save / recovery processor 314 specifies the address of the access destination in the active bank indicated by BN (step S926).

[0115] The normal save / restore processor 314 writes the read data (NVQ) from the specified address in the active bank to the corresponding volatile register 460 and the backup bank indicated by the BBN (step S927).The normal save / restore processor 314 then updates the tag bit corresponding to the write destination address to a logical value of "1" (step S928).

[0116] Then, the normal save / restore processor 314 determines whether all addresses have been specified (step S929). If all addresses have not been specified (step S929: No), the normal save / restore processor 314 repeats step S926 and subsequent steps. Furthermore, as will be described later, all data corresponding to all address groups on the non-volatile side may be written at once to the same corresponding address groups on the volatile side.

[0117] If all addresses have been specified (step S929: Yes), the normal save / restore processor 314 ends the save / restore process. The processes from step S926 to step S929 correspond to the restore process.

[0118] Alternatively, the normal save / restore processing unit 314 can perform the normal save / restore processing illustrated in FIG. 13 . The normal save / restore processing unit 314 determines whether to perform save (step S921) or restore (step S922). If it determines to perform save (step S921: Yes), the normal save / restore processing unit 314 writes all data corresponding to the volatile side address group whose tag bit has a logical value of “1” to the corresponding same address group on the nonvolatile side at once with a high voltage (step S923). If it determines to perform restore (step S922: Yes), the normal save / restore processing unit 314 writes all data corresponding to all nonvolatile side address groups to the corresponding same address group on the volatile side at once (step S924). If neither of these conditions is met (steps S921 and S922: No), the normal save / restore processing unit 314 performs neither save processing nor restore processing.

[0119] In the first embodiment, task switching is not performed by an OS (Operation System) kernel, although a configuration in which task switching is performed by an OS kernel will be described later.

[0120] 12 and 13, when saving, the nonvolatile read data (NVQ) is written to an address where the nonvolatile read data (VQ) does not match the volatile read data (VQ) among all addresses of the nonvolatile register bank 415. This makes it possible to reduce rush current during saving compared to when data is written to all nonvolatile addresses during saving.

[0121] Furthermore, by writing with write pulse P2, which has a voltage and / or pulse width greater than write pulse P1, during the save operation, write errors can be reduced compared to when writing with P1. When writing before the save operation, by writing with P1, which has a voltage lower than P2 or a pulse width shorter than P2, stable writing can be achieved with an appropriate voltage and pulse width according to the operating status of the chip, and power consumption can be reduced.

[0122] Furthermore, even when write pulse P1 is used during saving, a method of suppressing write errors can be considered by duplicating the nonvolatile register file 410 as described in Japanese Patent Application Laid-Open No. 2018-0215777. However, this method increases the area and power consumption of the nonvolatile register file 410 due to the duplication. In contrast, in the first embodiment, in which writing is performed using write pulse P2 during saving, duplication is not necessary. Therefore, while suppressing write errors, it is possible to reduce the area and power consumption of the nonvolatile register file 410 compared to Japanese Patent Application Laid-Open No. 2018-0215777.

[0123] 14 is a flowchart illustrating an example of a save / restore process when the power supply voltage drops below a threshold V ｌоｗ If the voltage drops to a lower value, the power drop save / recovery processor 315 executes the save process from steps S921 to S924. However, the power drop save / recovery processor 315 performs verification every time writing is performed with the write pulse P2 in step S923, and repeats the write and verify process until successful. Also, as described below, all data corresponding to a group of addresses on the volatile side where the tag bit has a logical value of "1" may be written at once at a high voltage to the same corresponding group of addresses on the non-volatile side.

[0124] The power-down save / recovery processor 315 can also start writing with the write pulse P1 instead of the write pulse P2. In this case, the power-down save / recovery processor 315 performs verification every time writing is performed, and if the verification fails, it increases the write voltage and repeats writing and verifying until it succeeds.

[0125] Then, the power drop save / recovery processing unit 315 determines whether the dropped power supply voltage is equal to or exceeds the threshold V ｈｉｇｈ It is determined whether the power supply voltage has risen to a higher value than the threshold V (step S931). ｈｉｇｈ If the threshold value V has not increased to a higher value (step S931: No), the power drop save / recovery processor 315 returns to step S931. ｌоｗ is an example of the first threshold value described in the claims, and the threshold value V ｈｉｇｈ is an example of the second threshold value described in the claims.

[0126] Here, it is assumed that the device or system in which the semiconductor chip 200 is placed has a capacitor, but does not have an auxiliary power source (such as an energy harvester) that can maintain the power supply voltage for a long enough time, and there is a risk that the power supply will be cut off during the evacuation process when the power supply drops.

[0127] The power supply voltage is the threshold V ｈｉｇｈ If it has risen to a higher value (step S931: Yes), the power drop save / recovery processor 315 swaps the active bank indicated by BN with the backup bank indicated by BNN (step S932).

[0128] In step S932, the power failure save / restore processor 315 first writes the value of BN to the temporary register T2 and the value of BBN to the temporary register T1. Next, the power failure save / restore processor 315 writes the value of the temporary register T2 to the BBN field and the value of the temporary register T1 to the BN field.

[0129] The above-mentioned write is implemented to correspond to writing to nonvolatile memory, so that the write is read and verified after writing until the write is successful, and if the write fails, the write voltage is repeatedly increased. Alternatively, the write is implemented by using a high-voltage, wide-pulse write pulse P2, and the write is read and verified after writing repeatedly until the write is successful.

[0130] After swapping BN and BBN, the power failure save / recovery processor 315 executes the recovery process from steps S926 to S929, and re-swaps the active bank indicated by BN with the backup bank indicated by BNN (step S930). Also, as will be described later, all data corresponding to all addresses of the nonvolatile register specified by the BN field may be written at once to all addresses of the nonvolatile register specified by the BBN field and to the same corresponding addresses on the volatile side.

[0131] The power-down save / restore processor 315 can also perform the power-down save / restore process illustrated in Fig. 15. The power-down save / restore processor 315 writes all data corresponding to the address group on the volatile side where the tag bit has a logical value of "1" to the corresponding address group on the non-volatile side at a high voltage at once (step S921). Then, the power-down save / restore processor 315 checks whether the dropped power supply voltage exceeds the threshold V ｈｉｇｈ It is determined whether the power supply voltage has risen to a higher value than the threshold V (step S922). ｈｉｇｈ If the power supply voltage has not risen to a higher value (step S922: No), the power supply drop save / recovery processor 315 returns to step S921. ｈｉｇｈIf the value has risen to a higher value (step S922: Yes), the power-down save / restore processor 315 swaps the active bank indicated by BN with the backup bank indicated by BNN (step S923).The power-down save / restore processor 315 then writes all data corresponding to all addresses in the nonvolatile register specified by the BN field to all addresses in the nonvolatile register specified by the BBN field and to the corresponding addresses in the volatile register (step S924).The power-down save / restore processor 315 then re-swaps the active bank indicated by BN with the backup bank indicated by BNN (step S925).

[0132] FIG. 16 is a diagram illustrating an example of normal save / restore processing according to the first embodiment of the present technology.

[0133] For ease of explanation, assume that there are four nonvolatile register banks 415, each assigned a bank number from "1" to "4." One of these banks is designated as a backup bank. The bank switching control unit 313 designates one of the three banks that does not correspond to a backup bank as the active bank and sets this in the BN register 340. For example, assume that the BN held by the BN register 340 is "1" and the BBN is "4." The destinations of the dashed arrows a and b in the figure indicate the active bank and the backup bank.

[0134] When saving a context due to an interrupt or task switching, as shown in the example of a in the figure, the normal save / restore processing unit 314 performs a save process in which data read from the volatile register file 450 is written to the active bank indicated by BN. The destinations of the solid arrows a and b in the figure indicate the save and restore destinations of the data.

[0135] When a context switch is performed to restore a context, the normal save / restore processor 314 performs a restoration process in which data read from the active bank indicated by BN is written to the volatile register file 450 and the backup bank indicated by BBN, as illustrated in b in the figure. Furthermore, when a context switch is not performed to restore a context, the normal save / restore processor 314 writes data read from the restoration target bank specified by the context switch to the volatile register file 450 and the backup bank indicated by BBN.

[0136] When the first task among the multiple tasks is executed, the normal save / restore processing unit 314 performs only the save process and does not perform the restore process. When switching to the second or subsequent task, the normal save / restore processing unit 314 performs the save process and the restore process described above.

[0137] 17 is a diagram for explaining an example of a save / restore process during a power drop according to the first embodiment of the present technology. After the save process and the restore process illustrated in FIG. 16 , the power supply voltage is lowered to a threshold V ｌоｗ It is assumed that the value has dropped to a lower value.

[0138] As illustrated in FIG. 17A, the power-down save / restore processing unit 315 does not perform any save processing to write data read from the volatile register file 450 to the active bank indicated by BN.

[0139] Then, the dropped power supply voltage reaches the threshold V ｈｉｇｈ If the value rises to a higher value, the power failure save / recovery processor 315 swaps the active bank and the backup bank by updating the BN register 340, as shown in b in the figure. Here, the BN is updated from "1" to "4," and the BBN is updated from "4" to "1."

[0140] After the swap, the power-down save / restore processor 315 performs a restore process of writing the data read from the active bank indicated by BN to the volatile register file 450 and the backup bank indicated by BBN.

[0141] As mentioned above, devices and systems incorporating the semiconductor chip 200 do not have auxiliary power sources other than capacitors, and there is a risk that the power supply will be cut off during the backup process in the event of a power failure. This can cause the backup process to end prematurely due to a power outage, resulting in a write error to the "1" bank. If this happens, and data is restored from the "1" bank without swapping, the CPU will be unable to properly perform the rollback process.

[0142] Therefore, as illustrated in FIG. 16 b, the power-down save / restore processing unit 315 swaps the active bank ("1") and the backup bank ("4") when the power supply rises, and then performs a restore process. In the restore process after the swap, the data in the active bank "4" (i.e., the backup bank before the swap) is written to the volatile register file 450. The data in the "1" bank was backed up in the restore process illustrated in FIG. 16 b. Therefore, by restoring from the "4" bank, even if power is interrupted during the restore process, the CPU can normally perform the rollback process. Furthermore, because restore is not performed from the "1" bank, unlike an interrupt or task switch, no save is performed to the "1" bank of the volatile register. In the restore process from the "4" bank, all data in the "4" bank is written to the "1" bank, the BN register 340 is updated again, and the active bank and the backup bank are swapped. Here, BN is updated again from "4" to "1", and BBN is updated from "1" to "4". That is, the backup number BBN is returned to "4" before the start of execution.

[0143] As described in Non-Patent Document 1, it is also possible to cope with a power interruption during the save process by duplicating each of the N non-volatile register banks 415. However, in this case, the number of banks needs to be 2×N.

[0144] In contrast, in the first embodiment, there is only one backup bank and the number of banks is N+1, so the area and power consumption of the non-volatile register file 410 can be reduced compared to the non-patent document.

[0145] If the power is cut off before the completion of the restoration process of b in FIG. 16, the backup is not completed and the CPU must restart the process from the beginning after the power is restored.

[0146] As described above, according to the first embodiment of the present technology, when the power supply voltage rises, the semiconductor chip 200 swaps the backup bank and the active bank before performing the recovery process, so that the number of banks is only N+1. This allows the area and power consumption of the non-volatile register file 410 to be reduced compared to the non-patent document in which the number of banks is 2×N.

[0147] [First Modification] In the first embodiment described above, the non-volatile bank number specified by the backup number BBN during the power failure save / restore process is swapped and changed once, but is then swapped again before execution to become a fixed bank number. If the backup non-volatile bank is fixed, multiple reads and writes will occur only in that bank, which could result in degradation of the non-volatile elements. To mitigate this risk of degradation, it is desirable to extend the backup number so that it is variable. Therefore, the semiconductor chip 200 in this first modification of the first embodiment differs from the first embodiment in that it assigns virtual bank numbers to interrupt processes and tasks and adds a management table that associates virtual bank numbers with real bank numbers.

[0148] 18 is a block diagram showing an example of a configuration of a power interruption recovery support CPU system 300 according to a first modified example of the first embodiment of the present disclosure. The power interruption recovery support CPU system 300 according to the first modified example of the first embodiment differs from the first embodiment in that it further includes a virtual / real bank number management table 360.

[0149] The virtual / real bank number management table 360 ​​associates virtual bank numbers assigned to interrupt processes and tasks with real bank numbers assigned to the nonvolatile register bank 415. This virtual / real bank number management table 360 ​​is stored in a nonvolatile memory or register.

[0150] 19 is a diagram showing an example of the configuration of a virtual / real bank number management table 360 ​​according to a first modification of the first embodiment of the present technology. For example, an extended associative memory is used as the virtual / real bank number management table 360. This memory includes an address decoder 361, multiple non-volatile registers 370, a volatile register 362, and an encoder 363.

[0151] The number of nonvolatile registers 370 is the same as the number of nonvolatile register banks 415, that is, N+1. Address ADDR of nonvolatile register 370 ＣＡＭ and the real bank number of the nonvolatile register bank 415 are in one-to-one correspondence. For example, the nth address ADDR ＣＡＭ corresponds to the real bank number "n." In the figure, "(R)" indicates that the number is a real bank number.

[0152] The address decoder 361 receives the address ADDR from the access control unit 310. ＣＡＭ The address decoder 361 receives the address ADDR ＣＡＭ is decoded to obtain an N+1-bit one-hot signal DEC ＣＡＭ This one-hot signal DEC ＣＡＭ The n-th bit of is input to the n-th non-volatile register 370 .

[0153] The nonvolatile register 370 stores the virtual bank number. The size of the data indicating the virtual bank number is S bits (S is an integer). When storing the virtual bank number in association with the real bank number, the access control unit 310 receives an access control signal indicating a write, S-bit data indicating the virtual bank number, and an address ADDR corresponding to the real bank number. ＣＡＭ and supply.

[0154] Furthermore, the nonvolatile register 370 outputs the data it holds to the access control unit 310 in accordance with the access control signal. When reading out a virtual bank number corresponding to a real bank number, the access control unit 310 receives an access control signal indicating a read and an address ADDR corresponding to the real bank number. ＣＡＭ and supply.

[0155] The volatile register 362 holds S-bit inquiry search data indicating a virtual bank number. The volatile register 362 compares the held data with the inquiry search data and outputs the comparison result CMP ｎ to the encoder 363. For example, if the data held in the n-th nonvolatile register 370 matches the query search data, the comparison result CMP ｎ A logical value of "1" is set to only the comparison result, and a logical value of "0" is set to the remaining comparison results.

[0156] The encoder 363 selects the address ADDR of the nonvolatile register 370 with the logical value "1" from the N+1 comparison results. ＣＡＭ into data of the actual bank number corresponding to that address. The encoder 363 outputs the converted data to the access control unit 310.

[0157] When converting a virtual bank number into a real bank number, the access control unit 310 supplies inquiry search data indicating the virtual bank number and receives real bank number data from the encoder 363 .

[0158] Furthermore, when swapping, the power-down save / restore processor 315 reads data at an address corresponding to BN from the virtual / real bank number management table 360 ​​and writes the data to temporary register T2. The power-down save / restore processor 315 also reads data at an address corresponding to BBN and writes the data to temporary register T1. Next, the power-down save / restore processor 315 writes the value of temporary register T2 to the address corresponding to BBN in the virtual / real bank number management table 360, and writes the value of temporary register T1 to the address corresponding to BN.

[0159] The above-mentioned writing and registration correspond to writing to nonvolatile memory, so they are implemented by reading and verifying after writing until the writing is successful, and if the writing fails, by repeatedly increasing the write voltage. Alternatively, they are implemented by writing using a high-voltage, long-pulse-width write pulse P2, and then reading and verifying after writing until the writing is successful.

[0160] 20 is a circuit diagram showing a configuration example of a nonvolatile register 370 according to a first modified example of the first embodiment of the present technology. The nonvolatile register 370 includes AND gates 371 and 372, S nonvolatile flip-flops 373, S XOR (exclusive OR) gates 374, and a NOR (negative OR) gate 375.

[0161] The AND gate 371 receives the access control signal R / W from the access control unit 310. ＣＡＭ and DEC from the address decoder 361 ＣＡＭ The logical product of this with [n] is output to the AND gate 372. ＣＡＭ is set to a logical "1" when writing or reading, and is set to a logical "0" otherwise. ＣＡＭ [n] indicates the n-th bit of the one-hot signal of the address decoder 361 .

[0162] The AND gate 372 supplies the logical product of the output signal of the AND gate 371 and the clock signal CK to each clock terminal of the nonvolatile flip-flop 373 .

[0163] Each nonvolatile flip-flop 373 holds one bit. The sth bit of the S-bit data indicating the virtual bank number is input to the input terminal of the sth (s is an integer from 1 to S) nonvolatile flip-flop 373. The sth nonvolatile flip-flop 373 outputs the held bit to the sth XOR gate 374 and the access control unit 310.

[0164] The sth bit of the S-bit query search data and the output bit of the sth nonvolatile flip-flop 373 are input to the sth XOR gate 374. The XOR gate 374 outputs the exclusive OR of these bits to the NOR gate 375.

[0165] The NOR gate 375 compares the NOR of the output signals of the S XOR gates 374 to obtain a comparison result CMP ｎ The signal is output to the encoder 363 as follows.

[0166] 21 is a diagram illustrating an example of updating the virtual / real bank number management table 360 ​​and the BN register 340 in the first modified example of the first embodiment of the present technology. In the figure, numbers with "(R)" attached are real bank numbers, and numbers with "(V)" attached are virtual bank numbers.

[0167] It is assumed that interrupt numbers and task numbers are uniquely renumbered in ascending order from 1 to N+1, and that the same values ​​are used as virtual bank numbers. The virtual bank numbers corresponding to each real bank number are stored in the virtual / real bank number management table 360. For ease of explanation, N is assumed to be "3" (i.e., the number of banks is four). The real bank number BN of the active bank and the real bank number BBN of the backup bank are stored in the BN register 340.

[0168] During period Pd1, the virtual / real bank number management table 360 ​​and the BN register 340 are in their initial states. For example, real bank numbers "1(R)" through "4(R)" are associated with virtual bank numbers of the same number and stored. In addition, in the initial state, BN is "1(R)" and BBN is "N+1 (i.e., "4(R)")."

[0169] Then, during period Pd2, a context switch from task number "1" to task number "2" is assumed. The task number is assumed to be used as the virtual bank number. The access control unit 310 performs a save process to write data from the volatile register file 450 to BN ("1(R)"), reads the real bank number "2(R)" corresponding to the virtual bank number "2(V)" from the virtual / real bank number management table 360, and updates BN in the BN register 340 to that number. In the figure, the gray areas indicate updated data.

[0170] Furthermore, the access control unit 310 performs a recovery process of writing data from BN("2(R)") to the volatile register file 450 and BBN("4(R)").

[0171] Then, assume that during period Pd3, power is cut off while the task with task number "2" is being executed. The access control unit 310 swaps BN and BBN when power is turned on. Specifically, the BN field in the BN register 340 is updated from "2(R)" to "4(R)", and the BBN field is updated from "4(R)" to "2(R)". After the swap, the access control unit 310 performs recovery processing, writing data from BN ("4(R)") to the volatile register file 450 and BBN ("2(R)").

[0172] Then, assume that a context switch from task number "2" to task number "3" occurs during period Pd4. The access control unit 310 performs a save process to write data from the volatile register file 450 to BN ("4(R)"), and updates the real bank number "4(R)" in the BN field to the real bank number "3(R)" that corresponds to the virtual bank number "3(V)."

[0173] Furthermore, the access control unit 310 performs a recovery process of writing data from BN("3(R)") to the volatile register file 450 and BBN("2(R)").

[0174] Then, assume that during period Pd5, power is cut off while the task with task number "3" is being executed. The access control unit 310 swaps BN and BBN when power is turned on. Specifically, the BN field in the BN register 340 is updated from "3(R)" to "2(R)", and the BBN field is updated from "2(R)" to "3(R)". After the swap, the access control unit 310 performs recovery processing, writing data from BN ("2(R)") to the volatile register file 450 and BBN ("3(R)").

[0175] Then, assume that a context switch from task number "3" to task number "1" occurs during period Pd6. The access control unit 310 performs a save process to write data from the volatile register file 450 to BN ("2(R)"), and updates the real bank number "2(R)" in the BN field to the real bank number "1(R)" corresponding to the virtual bank number "1(V)."

[0176] Furthermore, the access control unit 310 performs a recovery process of writing data from BN("1(R)") to the volatile register file 450 and BBN("3(R)").

[0177] Then, assume that power is cut off during period Pd7 while the task with task number "1" is being executed. The access control unit 310 swaps BN and BBN when power is turned on. Specifically, the BN field in the BN register 340 is updated from "1(R)" to "3(R)", and the BBN field is updated from "3(R)" to "1(R)". After the swap, the access control unit 310 performs recovery processing by writing data from BN ("3(R)") to the volatile register file 450 and BBN ("1(R)").

[0178] Then, assume that a context switch from task number "1" to task number "3" occurs during period Pd8. The access control unit 310 performs a save process to write data from the volatile register file 450 to BN ("3(R)"), and updates the real bank number "3(R)" in the BN field to the real bank number "2(R)" corresponding to the virtual bank number "3(V)."

[0179] Furthermore, the access control unit 310 performs a recovery process of writing data from BN("2(R)") to the volatile register file 450 and BBN("1(R)").

[0180] Then, assume that during period Pd9, power is cut off while the task with task number "3" is being executed. The access control unit 310 swaps BN and BBN when power is turned on. Specifically, the BN field in the BN register 340 is updated from "2(R)" to "1(R)", and the BBN field is updated from "1(R)" to "2(R)". After the swap, the access control unit 310 performs recovery processing, writing data from BN ("1(R)") to the volatile register file 450 and BBN ("2(R)").

[0181] As shown in the figure, when there are three or more tasks, the value of the BN field does not necessarily match the interrupt number or task number (i.e., the virtual bank number). Therefore, it is necessary to use the virtual / real bank number management table 360 ​​to manage the real bank numbers stored in the BN field.

[0182] For example, if the task number is switched from "1" to "3" during period Pd8, the task number after the switch (i.e., the virtual bank number) will be "3 (V)," while the real bank number of BN will be "2 (R)."Even if the task number and the real bank number of BN do not match in this way, the real bank numbers can be managed appropriately by using the virtual / real bank number management table 360.

[0183] In the first modification of the first embodiment, the power-down save / restore processor 315 can also perform the power-down save / restore process illustrated in Fig. 22. The power-down save / restore processor 315 writes all data corresponding to the addresses on the volatile side where the tag bit has a logical value of "1" to the corresponding addresses on the non-volatile side at a high voltage at once (step S921). Then, the power-down save / restore processor 315 performs a write operation when the dropped power supply voltage reaches a threshold V ｈｉｇｈ It is determined whether the power supply voltage has risen to a higher value than the threshold V (step S922). ｈｉｇｈ If the power supply voltage has not risen to a higher value (step S922: No), the power supply drop save / recovery processor 315 returns to step S921. ｈｉｇｈ If the value has increased to a higher value (step S922: Yes), the power-down save / restore processor 315 swaps the active bank indicated by BN with the backup bank indicated by BNN (step S923).The power-down save / restore processor 315 then writes all of the data corresponding to all of the addresses in the nonvolatile register specified by the BN field to all of the corresponding addresses in the nonvolatile register specified by the BBN field and to all of the corresponding addresses in the volatile register at once with a high voltage (step S924).

[0184] As described above, according to the first modification of the first embodiment of the present technology, a virtual / real bank number management table 360 ​​that associates virtual bank numbers with real bank numbers is further provided, so that real bank numbers can be appropriately managed even when there are three or more tasks.

[0185] [Second Modification] The first modification of the first embodiment described above does not support task switching by the OS kernel, but is not limited to this configuration. The semiconductor chip 200 in the second modification of the first embodiment differs from the first modification of the first embodiment in that it also supports task switching by the OS kernel.

[0186] 23 is a diagram showing an example configuration of the BN register 340 in a second modified example of the first embodiment of the present technology. The BN register 340 in this second modified example of the first embodiment includes an associative memory BN0, a BN1 register, a BN(i) sub-register, a BN2 register, and a BN3 register. i is an integer from 0 to 15. The data size of each of the BN1 register, the BN(i) sub-register, the BN2 register, and the BN3 register is, for example, 16 bits.

[0187] For simplicity, the hardware interrupt numbers range from 1 to 15, and the OS interrupt numbers range from 1 to 255. The higher the number, the higher the interrupt priority, and hardware interrupts have higher priority than OS interrupts. A fixed priority system is used between hardware interrupts and between OS interrupts, but a round-robin system can also be used.

[0188] For each interrupt number, permission or prohibition of bank use is set. HE01 to HE15 are assigned to bits 1 to 15 of the BN1 register, and OSE1 to OSE255 are assigned to each bit of the 16 BN1(i) sub-registers.

[0189] Each of HE01 to HE15 is set to a logical value "0" when the corresponding bank is prohibited from use, and to a logical value "1" when the bank is permitted to be used. The 0th bit of the BN1 register is a reserved bit.

[0190] Each of OSE1 to OSE255 is set to a logical value "0" when the corresponding bank is prohibited from use, and to a logical value "1" when the bank is permitted to be used. The 0th bit of the BN1(0) sub-register is a reserved bit.

[0191] The BN2 register also has a field for holding a bank enable BNE and a field for holding the actual bank number BN currently being executed.

[0192] The size of the bank enable BNE is, for example, 2 bits. If the use of a bank is prohibited for all interrupts, the bank enable BNE is set to "00" in binary. If the use of a bank is permitted for all interrupts except NMI, the bank enable BNE is set to "01" in binary. If the permission or prohibition of bank use follows the settings of the BN1 register and the BN(i) subregister, the bank enable BNE is set to "11" in binary. The value "10" in binary is reserved for the bank enable BNE.

[0193] The bank number BN field holds the actual bank number currently being executed or the leading address of the bank currently being executed.

[0194] For simplicity, let us assume that there are 272 banks, and for example, of the virtual bank numbers 0 to 271, numbers 1 to 15 correspond to hardware interrupt numbers, and numbers 17 to 271 correspond to OS interrupt numbers. The hardware interrupt numbers and the values ​​obtained by adding 16 to the OS interrupt numbers are used as virtual bank numbers.

[0195] Real bank number 0 always matches virtual bank number 0, and is assigned, for example, initialization processing from startup before interrupt acceptance and initialization processing before OS startup. Real bank number 16 always matches virtual bank number 16, and is assigned, for example, processing from OS startup until task execution begins.

[0196] The configuration of the BN3 register in the second modified example of the first embodiment is the same as that in the first embodiment.

[0197] The associative memory BN0 is a memory for registering task numbers used in task switching in the OS kernel as additional interrupt numbers.

[0198] 24 is a diagram illustrating an example of a configuration of an associative memory BN0 according to a second modified example of the first embodiment of the present technology. The associative memory BN0 includes 255 non-volatile registers 351, a volatile register 352, and an encoder 353.

[0199] The bank switching control unit 313 can store (in other words, register) task numbers in each of the 255 nonvolatile registers 351. OS interrupt numbers ranging from 1 to 255 correspond to the addresses of each of these nonvolatile registers 351. The bank switching control unit 313 can also generate query search data that specifies one of the nonvolatile registers 351 and store it in the volatile register 352. The encoder 353 outputs the address of the nonvolatile register 351 that matches the query search data as the corresponding OS interrupt number. In the case of a fixed priority system, the priority of a task number can be changed by changing the registration address of the task number.

[0200] With the configuration shown in the figure, the bank switching control unit 313 can convert a task number into an OS interrupt number using the content addressable memory BN0. The OS interrupt number plus 16 is used as the virtual bank number. The real bank number corresponding to the virtual bank number can be obtained by using the virtual / real bank number management table 360 ​​described above.

[0201] As described above, according to the second modified example of the first embodiment of the present technology, the BN(i) sub-register and the associative memory BN0 are added to the BN register 340, thereby enabling task switching by the OS kernel to be supported.

[0202] 2. Second Embodiment In the second modification of the first embodiment described above, non-volatile register file 410 and volatile register file 450 are provided, but these can be used as CPU register files within the CPU. Semiconductor chip 200 in this second embodiment differs from the second modification of the first embodiment in that non-volatile register file 410 and volatile register file 450 are used as CPU register files.

[0203] 25 is a block diagram showing an example of a configuration of a CPU system 300 for recovering from power interruption according to the second embodiment of the present technology. The CPU system 300 for recovering from power interruption according to the second embodiment includes a program ROM (Read Only Memory) 331, a data save / recovery / bank switching sequencer 332, an instruction fetch decoder 333, an address calculation circuit 334, a storage unit 400, and a calculation circuit 335.

[0204] The storage unit 400 in the second embodiment includes a non-volatile register file 410 and a volatile register file 450, similar to the first embodiment, which are used as CPU register files.

[0205] The program ROM 331 stores programs executed by the CPU.

[0206] The data save / restore / bank switching sequencer 332 performs data save and restore processes and bank switching. A detection signal, an interrupt number, and an OS task number are input to the data save / restore / bank switching sequencer 332. The detection signal includes a power drop detection signal indicating the result of power drop detection and a power rise detection signal indicating the result of power rise detection. The save and restore processes executed by the data save / restore / bank switching sequencer 332 are the same as those described in the first embodiment.

[0207] When an interrupt number or OS task number is input, the data save / restore / bank switching sequencer 332 compares the priority of that number with the priority of the interrupt number (hardware interrupt number or OS interrupt number) corresponding to the BN in the BN2 register. If the priority of the input number is higher, the data save / restore / bank switching sequencer 332 selects the bank corresponding to that number as the active bank and performs data save processing, restoration processing, and bank switching.

[0208] On the other hand, if the input number has a lower priority, the data save / restore / bank switching sequencer 332 waits for the completion of the currently running process corresponding to the BN before switching to the bank corresponding to the input number. Alternatively, the data save / restore / bank switching sequencer 332 does not accept interrupt nesting. Alternatively, the data save / restore / bank switching sequencer 332 may accept interrupt nesting and store the number in a FIFO (First In, First Out) buffer.

[0209] Furthermore, upon receiving a detection signal of a drop or rise in the power supply voltage, the data save / restore / bank switching sequencer 332 performs the save process and the swap and restore process described above.

[0210] The instruction fetch decoder 333 fetches and decodes instructions from the program ROM 331. The instruction fetch decoder 333 obtains the access control signal R / W and the address of the access destination by decoding an instruction instructing writing or reading, and supplies them to the storage unit 400.

[0211] The address calculation circuit 334 obtains the address of the register file by decoding an instruction.

[0212] The arithmetic circuit 335 performs various calculations as necessary. This arithmetic circuit 335 supplies initial value data and data obtained by calculations as write data to the storage unit 400. The arithmetic circuit 335 also receives read data from the storage unit 400 and performs various calculations on the read data.

[0213] The configuration illustrated in this figure makes it possible to realize the functions of the access control unit 310 illustrated in FIG. 3 and FIG.

[0214] 26 is a diagram showing a list of registers according to the second embodiment of the present technology. At least some of the registers shown in the diagram are arranged in each of the non-volatile register file 410 and the volatile register file 450.

[0215] For example, general-purpose registers, stack pointer registers, program counter registers, saved program counter registers, processor status word registers, and saved status registers are used. In addition, procedure registers, multiplication registers, base registers, vector base registers, read data buffer registers, and write data buffer registers can also be used.

[0216] General-purpose register R ０ From R ｎ－２ is a register that can be used as both an address register and a data register. The stack pointer register SP is a register that indicates the address of the stack area that can be stacked. For example, R ｎ－１ can be used as the SP. The program counter register PC is a register that indicates the address of the instruction executed by the CPU. The saved program counter register BPC is a register that saves the program counter when a general exception request or interrupt request is accepted. The processor status word register PSW is a status register that stores the results of instruction execution and the status of the CPU. The saved status register BPSW is a register that saves the PSW when a general exception request or interrupt request is accepted.

[0217] The procedure register PR is a register that stores the return address when a subroutine is called. The multiplication registers MACH and MACL are registers that store the results of multiplication and multiply-accumulate operations. The base register GBR is a register that stores the base address for the indirect addressing mode. The vector base register VBR is a register that stores the base address of the exception processing handler. The read data buffer register RDR is a register that stores read data from memory. The write data buffer register WDR is a register that stores write data to memory.

[0218] In the second embodiment, the CPU may be configured in the following manner.

[0219] First, in the interrupt vector method, the BN register 340 and the interrupt vector are configured as nonvolatile registers such as nonvolatile multi-bit registers. The access control unit 310 repeats writing and read verification until the writing is successful. In addition, the control registers related to access to the nonvolatile memory are also configured as similar nonvolatile registers.

[0220] Next, when an interrupt is executed with an interrupt number that is disallowed by the BN register 340, the program is executed using only the volatile registers. This can be used, for example, to execute a restart handler that is kicked off by an interrupt caused by a voltage rise detection signal when power is restored from a power cut. In the case of a single register, an interrupt number is not assigned, so a control register that registers the interrupt number, which involves accessing non-volatile memory, is installed in the storage unit 400.

[0221] Consider a case where the program resumes from the program context where the power interruption occurred. In this case, control and status registers in the I / O peripherals, DMA (Direct Memory Access) controller, and interrupt controller that may be set up until the context is reached are located in the storage unit 400. These control and status registers may be implemented using either the method proposed in FIGS. 4 and 5 or a nonvolatile memory method that repeats writing and reading verification until the writing is successful.

[0222] The BN register 340 can also have three fields for specifying the following for each bank. The first field is a field that can specify whether to allow or disallow interrupt numbers. If all are disallowed, the program will be executed using only volatile memory.

[0223] The second field is a field for specifying whether or not to allow a task switching interrupt by registering a task number used in task switching in the OS kernel as an additional interrupt number in the content addressable memory.

[0224] The third field is the BN field. In the case of a register file, the BN value is used to specify a bank number, and in the case of a scratchpad memory or main memory, the BN value is used as the starting address of the bank.

[0225] 27 is a block diagram showing an example of a configuration of the storage unit 400 according to the second embodiment of the present technology. As shown in the figure, each of the N+1 nonvolatile register banks 415 includes, for example, a general-purpose register R ０ From R ｎ－２ and a stack pointer register SP. Furthermore, each of the non-volatile register banks 415 includes a program counter register PC, a processor status word register PSW, a procedure register PR, a base register GBR, and a vector base register VBR. The volatile register file 450 includes R ０ From R ｎ－２ In addition to the SP, PC, PSW, PR, GBR, and VBR, each register holds a tag bit TAG.

[0226] As described above, in the second embodiment, nonvolatile register file 410 and volatile register file 450 are used as CPU register files, thereby realizing a multitasking CPU that can recover normally even if a write error to nonvolatile memory occurs due to a power outage during a save process.

[0227] As described above, according to the second embodiment of the present technology, the non-volatile register file 410 and the volatile register file 450 are used as CPU register files, thereby realizing a multitasking CPU that can cope with power interruptions during the save process.

[0228] 3. Third Embodiment In the second embodiment described above, the nonvolatile register file 410 has a multi-bank configuration, but in the case of main memory, scratch pad memory, etc., memory may be shared by multiple entities. The semiconductor chip 200 in this third embodiment differs from the second embodiment in that shared resources are provided for both the volatile memory and the nonvolatile memory.

[0229] 28 is a block diagram showing a configuration example of the storage unit 400 according to the third embodiment of the present technology. In the storage unit 400 according to the third embodiment, a non-volatile memory 430 and a volatile memory 480 are arranged instead of the non-volatile register file 410 and the volatile register file 450.

[0230] The nonvolatile memory 430 includes a nonvolatile memory shared resource 441 and a nonvolatile memory unshared resource 442. Note that the address decoders and output selectors in each resource are omitted in the figure.

[0231] The non-volatile memory shared resource 441 is a memory area that holds shared data shared by multiple entities (tasks, interrupt handlers, etc.), and includes two non-volatile memory shared banks 443. The real bank number of one of these is set to "1," and the real bank number of the other is set to "2."

[0232] The non-volatile memory unshared resource 442 is a memory area that stores data that does not fall under the category of shared data, and includes N+1 non-volatile memory unshared banks 444. Note that instead of the non-volatile memory, a non-volatile register file may be configured as a multi-bank.

[0233] The nonvolatile shared memory bank 443 is an example of a nonvolatile shared bank as defined in the claims. The nonvolatile unshared memory bank 444 is an example of a nonvolatile unshared bank as defined in the claims.

[0234] 29 is a block diagram showing a configuration example of a volatile memory 480 according to the third embodiment of the present technology. The volatile memory 480 according to the third embodiment includes a volatile memory shared resource 481 and a volatile memory non-shared resource 482. Note that address decoders and output selectors in each resource are omitted in the figure.

[0235] The volatile memory shared resource 481 is a memory area that stores shared data, and the volatile memory non-shared resource 482 is a memory area that stores data that does not fall under the category of shared data. Note that a volatile register file can be used instead of a volatile memory to provide volatile shared resources and non-shared resources.

[0236] Furthermore, the size and number of addresses of the volatile memory shared resource 481 are the same as those of each of the nonvolatile memory shared banks 443. The size and number of addresses of the volatile memory unshared resource 482 are also the same as those of each of the nonvolatile memory unshared banks 444.

[0237] The volatile memory shared resource 481 is an example of a volatile shared resource as defined in the claims, and the volatile memory non-shared resource 482 is an example of a volatile non-shared resource as defined in the claims.

[0238] 30 is a diagram illustrating an example of a configuration of a BN register 340 according to the third embodiment of the present technology. The BN register 340 according to the third embodiment differs from the second embodiment in that the BN register 340 further includes a field for holding a shared setting bit CF.

[0239] The shared setting bit CF is a bit for setting which of the two shared nonvolatile memory banks 443 is to be the backup bank. When the shared nonvolatile memory bank 443 with bank number "1" is the active bank and the shared nonvolatile memory bank 443 with bank number "2" is the backup bank, the shared setting bit CF is set to a logical value of "0." When the shared nonvolatile memory bank 443 with bank number "2" is the active bank and the shared nonvolatile memory bank 443 with bank number "1" is the backup bank, the shared setting bit CF is set to a logical value of "1."

[0240] 31 is a block diagram showing an example configuration of a CPU system 300 for recovery from power interruption according to a third embodiment of the present technology. The CPU system 300 for recovery from power interruption according to the third embodiment includes a program ROM 331, a data save / restore / bank switching sequencer 332, an instruction fetch decoder 333, an address calculation circuit 334, and an arithmetic circuit 335. The CPU system 300 for recovery from power interruption also includes a volatile memory shared resource addressing register 336, a non-volatile memory shared resource 441, and a non-volatile memory unshared resource 442. The CPU system 300 also includes a volatile memory shared resource 481, a volatile memory unshared resource 482, an address converter 337, a data bus 338, and an address bus 339.

[0241] As described above, the non-volatile memory non-shared resource 442 has a multi-bank configuration, and each register (such as a program counter register) in the CPU register file described above can be placed in each bank and in the volatile memory non-shared resource 482. Furthermore, the volatile memory shared resource 481 and the volatile memory non-shared resource 482 hold a tag bit for each address.

[0242] As described above, the nonvolatile memory shared resource 441 also has a multi-bank configuration, and bank switching within the nonvolatile memory unshared resource 442 and bank switching within the nonvolatile memory shared resource 441 are executed synchronously.

[0243] To achieve this, the address calculation circuit 334 obtains the conversion result of the address decoder corresponding to BF and BBN as an offset. Based on the offset, the address converter 337 calculates the start addresses of the non-volatile active bank and backup bank corresponding to the volatile memory non-shared resource 482. This enables synchronized bank switching and appropriate write and read accesses.

[0244] Furthermore, the BBN in the BN3 register is converted to the start address of an appropriate nonvolatile backup bank by address conversion. Therefore, bank swapping within the nonvolatile memory shared resource 441 when recovering from a power outage is also performed in synchronization with bank swapping within the nonvolatile memory unshared resource 442.

[0245] The address converter 337 may be implemented as a combinational circuit with a flip-flop output. Alternatively, the address converter 337 may be implemented as a register file or SRAM in which the first address of the non-volatile memory unshared bank 444 is registered using the interrupt number as an address. The address converter 337 may perform address conversion using an address conversion mechanism in the number of cycles required for data transmission and reception via the bus.

[0246] The volatile memory shared resource address specification register 336 stores the initial value of the leading address of the volatile memory shared resource 481 .

[0247] Furthermore, when a detection signal, an interrupt number, or an OS task number is input, the data save / restore / bank switching sequencer 332 performs the data save processing, restoration processing, and bank switching described above with reference to FIGS.

[0248] The data backup / restore / bank switching sequencer 332 can also periodically perform data backup processing. For example, the data backup / restore / bank switching sequencer 332 periodically checks the tag bit of the volatile memory and writes data at an address where the tag bit has a logical value of "1" from the volatile memory to the nonvolatile memory while gradually increasing the voltage of the write pulse. The data backup / restore / bank switching sequencer 332 then checks whether the read data matches, clears the tag bit for which writing has been completed to a logical value of "0," and stops increasing the voltage when the writing has been successful for all bits.

[0249] The above-described configuration makes it possible to recover from power outages in a multitasking environment even if a write error occurs in the nonvolatile memory.

[0250] As described above, shared data is managed by the volatile memory shared resource 481 and the nonvolatile memory shared resource 441, and other data is managed by the volatile memory unshared resource 482 and the nonvolatile memory shared bank 443. This ensures the consistency of common data in the shared resources.

[0251] As described above, according to the third embodiment of the present technology, the volatile memory 480 and the non-volatile memory 430 are each provided with shared resources and non-shared resources, so that the memory can be used more efficiently.

[0252] 4. Fourth Embodiment In the second modification of the first embodiment described above, the semiconductor chip 200 performs data saving and restoration processes in response to a detection signal indicating a drop or rise in the power supply voltage, assuming that there is no auxiliary power supply other than a capacitor. The semiconductor chip 200 in this fourth embodiment differs from the second modification of the first embodiment in that it is disposed within a semiconductor device provided with a power supply drop / rise detection circuit.

[0253] 32 is a block diagram showing a configuration example of a semiconductor device 100 according to the fourth embodiment of the present technology. The semiconductor device 100 includes a power drop / rise detection circuit 110, a semiconductor chip 200, a power control unit 120, and a capacitor 130. The semiconductor device 100 is expected to be a smartphone, an in-vehicle camera, or the like.

[0254] The power supply voltage drop / rise detection circuit 110 detects whether the power supply voltage is below a threshold V ｌоｗ The power supply voltage has dropped to a lower value and the dropped power supply voltage is below the threshold V ｈｉｇｈ The power supply drop / rise detection circuit 110 supplies detection signals (power supply drop detection signal and power supply rise detection signal) indicating the detection results to the semiconductor chip 200. The threshold value V ｈｉｇｈ is the threshold V ｌоｗ is a value different from the threshold V ｈｉｇｈ For example, a threshold value V ｌоｗ The higher value is set.

[0255] In addition, the threshold value V ｌоｗ is an example of the first threshold value described in the claims, and the threshold value V ｈｉｇｈ is an example of the second threshold value described in the claims.

[0256] The configuration of the semiconductor chip 200 of the fourth embodiment is the same as that of the second modified example of the first embodiment. However, the semiconductor chip 200 of the fourth embodiment holds a power-off nonvolatile flag bit in a nonvolatile register or memory. The initial value of this power-off nonvolatile flag bit is initialized to a logical value of "0" at the first startup.

[0257] The power supply control unit 120 controls the power supply voltage of the semiconductor device 100 .

[0258] The capacitor 130 holds the power supply voltage for a certain period of time when the power supply voltage drops. The time from when the power supply voltage drops to when the saving process is completed is not necessarily constant, but the longest time is T ｍａｘ The time that the power supply voltage is held by the capacitor 130 is T ｍａｘ It is assumed that the power supply voltage may be cut off during the saving process.

[0259] The power supply voltage is the threshold V ｌоｗ When the voltage drops to a lower value, the power supply drop / rise detection circuit 110 supplies a power supply drop detection signal to the semiconductor chip 200 .

[0260] When the semiconductor chip 200 receives the voltage drop detection signal, it performs the above-described save process and updates the power-off nonvolatile flag bit to a logical value of "1." This power-off nonvolatile flag bit is initialized to a logical value of "0" when the power supply voltage rises.

[0261] Then, the dropped power supply voltage reaches the threshold V ｈｉｇｈ When the voltage rises to a higher value, the power supply voltage drop / rise detection circuit 110 supplies a power supply voltage rise detection signal to the semiconductor chip 200 .

[0262] When the power-down save / restore processor 315 in the semiconductor chip 200 receives the power-up detection signal, it starts a restart handler and checks the power-down non-volatile flag bit. If the power-down non-volatile flag bit is set to the logical value "0," the power-down save / restore processor 315 executes a normal restart sequence that involves initializing the BN register 340 and the virtual / real bank number management table 360.

[0263] On the other hand, if the power-off nonvolatile flag bit is logically "1", the power-down save / restore processor 315 checks the values ​​of AF, BF, and EF in the BN3 register and determines whether the following formula is true: AF="1" V EF="01" V EF="10"...Equation 1 In the above formula, "V" indicates a logical sum.

[0264] If Expression 1 is true, it indicates that a power outage occurred during task processing, or during save processing, or immediately after save processing was completed. In this case, the power drop save / restore processing unit 315 clears the power-off nonvolatile flag bit to the logical value "0" and performs restore processing after swapping the active bank and backup bank as described above. If Expression 1 is not true, that is, if AF = "0" ∧ EF = "00" ... Expression 2 is true, restore processing is performed without swapping the active bank and backup bank. Here, "∧" indicates a logical product.

[0265] Here, it is assumed that the program for performing the above-mentioned processing is stored in a non-volatile memory and executed on that memory.

[0266] As described above, the power drop / rise detection circuit 110 detects a drop or rise in the power supply voltage, and the semiconductor chip 200 can perform the save process and restore process at an appropriate timing in response to the detection signal.

[0267] The fourth embodiment can be adapted to the third embodiment, which includes shared and non-shared resources. In this case, the power-failure save / restore processor 315 inverts the shared setting bit CF during the restoration process. The power-failure save / restore processor 315 then writes the data in the active bank in the non-volatile memory shared resource 441 indicated by the shared setting bit CF to the volatile memory shared resource 481 and the backup bank indicated by CF.

[0268] Next, a process specific to when a CIS is used as the semiconductor chip 200 will be described.

[0269] First, regarding the register settings of the digital signal processing unit 220, these are implemented in nonvolatile memory, and are set to repeat read verify and rewrite until writing is completed at the time of setting in preparation for power shutdown. Also, after the power supply voltage rises, the CIS checks the power shutdown nonvolatile flag bit in the resume handler, and if the value is logical "1", it does nothing and performs the initial setting process.

[0270] The line memory for storing image data is not arranged in the storage unit 400 but is implemented as a volatile memory because frame synchronization is essential.

[0271] Similarly, the frame memory for storing image data is not arranged within the storage unit 400 but is implemented as a volatile memory.

[0272] Next, consider the case where an AE control unit is installed. In this case, the CIS writes statistical processing result information used for adjusting the analog and digital gains in AE control to the volatile memory 480 and the nonvolatile memory 430. After rebooting, the user can select, by register setting, whether to use the statistical processing result information stored in the nonvolatile memory 430 or a separately set default value for gain adjustment.

[0273] Upon receiving the voltage drop detection signal, the CIS saves the statistical processing result information stored in the AE control unit. As described above, the CIS writes data at addresses in the volatile memory 480 where the tag bit is set to a logical value of "1" to the nonvolatile register bank 415 using write pulse P2, and clears the tag bit to a logical value of "0" once the write is complete. The CIS also retains a statistical information nonvolatile flag bit, and if all writes are successful, writes a logical value of "1" to the statistical information nonvolatile flag bit. If the power-off nonvolatile flag bit is set to a logical value of "0," the statistical information nonvolatile flag bit is initialized to a logical value of "0." If the power-off nonvolatile flag bit is set to a logical value of "1," the statistical information nonvolatile flag bit is cleared to a logical value of "0" after reading it. In other words, if the writing of the logical value "1" is not completed within the power supply period from the auxiliary power supply, the statistical information nonvolatile flag bit remains at a logical value of "0."

[0274] Then, after power is restored, the CIS checks the power shutdown non-volatile flag bit in the resume handler. If the power shutdown non-volatile flag bit is a logical value of "0," the CIS uses the default value for gain adjustment regardless of the register setting value set by the user and initializes the statistical processing result information. If the power shutdown non-volatile flag bit is a logical value of "1," the CIS checks the statistical information non-volatile flag bit. If the statistical information non-volatile flag bit is a logical value of "0," the CIS uses the default value for gain adjustment regardless of the register setting value set by the user and initializes the statistical processing result information. If the statistical information non-volatile flag bit value is a logical value of "1," the CIS uses either the statistical processing result information or a separately set default value for gain adjustment according to the register setting value set by the user.

[0275] The above-described processing makes it possible to realize a CIS that can recover from a power outage appropriately and quickly.

[0276] Thus, according to the fourth embodiment of the present technology, the power supply drop / rise detection circuit 110 detects a drop and rise in the power supply voltage, and the semiconductor chip 200 can perform backup and recovery processes at appropriate times in response to the detection signal.

[0277] 5. Fifth Embodiment In the above-described fourth embodiment, the semiconductor chip 200 performs data saving and restoration processes when the power supply drops, etc., but it is preferable to optimize the code processed by the semiconductor chip 200. The information processing system in this fifth embodiment differs from the fourth embodiment in that the code executed by the semiconductor chip 200 is optimized.

[0278] 33 is a block diagram showing an example of a configuration of an information processing system according to the fifth embodiment of the present technology. The information processing system includes an information processing device 500 and a semiconductor device 100.

[0279] The information processing device 500 converts source code into object code that can be executed by the semiconductor chip 200 .

[0280] The configuration of the semiconductor device 100 of the fifth embodiment is the same as that of the fourth embodiment. The semiconductor chip 200 in this semiconductor device 100 performs the above-mentioned save processing and restore processing based on the object code from the information processing device 500.

[0281] FIG. 34 is a diagram illustrating an example of source code according to the fifth embodiment of the present technology.

[0282] Fig. 35 is a diagram showing an example of a code block according to the fifth embodiment of the present technology. The information processing device 500 divides the source code shown in Fig. 34 into multiple code blocks shown in Fig. 35 by using the checkpoint insertion method described in, for example, Non-Patent Document 2 below. Non-Patent Document 2: LI, C.-C., AND FUCHS, W. "Catch-compiler-assisted techniques for checkpointing," In Proceeding of International Symposium on Fault-Tolerant Computing, 1990.

[0283] In FIG. 35, the information processing device 500 divides the modified code into code blocks that include all paths starting from the point immediately after the checkpoint function call to the next checkpoint function call, for example.

[0284] The information processing device 500 may define the obtained code block as a task, or may define a continuous block of code consisting of multiple code blocks as a task. In this case, the information processing device 500 redefines the block of code as a code block, leaving only the final checkpoint function, and modifies variables saved to non-volatile memory by other checkpoint functions so that they are also saved by the final checkpoint function. Non-Patent Document 2 prohibits redefining a block of code as a code block because this redefinition would change the code processing results when re-executed from a checkpoint after recovery from a power interruption during code execution. The recovery processing method disclosed in this patent, using a non-volatile multi-bank configuration and a power drop save / recovery processor, ensures that the code processing results will not change when re-executed from a checkpoint after recovery from a power interruption during code execution after the redefinition.

[0285] 36 is a diagram illustrating an example of a revision of a code block according to the fifth embodiment of the present technology. In the figure, the source code is a code block CB １ and C.B. ２ The following explains how to process these code blocks.

[0286] First, the information processing device 500 calculates a set of variables WVar ａｌｌ This set is expressed by the following formula: ａｌｌ = {A, B, C, D, R １ , R ２ , R ３ , R ４}...Formula 3

[0287] Then, the information processing device 500 identifies the variables on the left side of the assignment statements in each code block that should be written to the nonvolatile register file 410. For example, １ The set of variables on the left side of the assignment statement in １ ) and the code block CB ２ The set of variables on the left side of the assignment statement in ２), they are expressed by the following formula: LHSVar(CB １ ) = {a, b, c, A, B, C, D, R １ , R ２ , R ３ , R ４}...Formula 4 LHSVar(CB ２ ) = {b, c, B, D, R １ , R ２ , R ４} ...Formula 5

[0288] After calculating Equation 3 and Equation 4, the information processing device 500 calculates the code block CB ｉ The set of LHSVar(CB ｉ ), and for each code block, the set WLHSVar(CB ｉ ) is calculated based on the following equation, where i is a number that identifies the code block. １ ) and WLHSVar(CB ２ ) is calculated. １ )=LHSVar(CB １ ) ∧ WVar ａｌｌ = {A, B, C, D, R １ , R ２ , R ３ , R ４} ...Formula 6 WLHSVar(CB ２ )=LHSVar(CB ２ ) ∧ WVar ａｌｌ = {B, C, D, R １ , R ２ , R ４} ...Equation 7 In Equations 6 and 7, "^" indicates a logical product.

[0289] Here, the set WLHSVar(CB ｉ ) elements to LHSvar(CB ｉ After the calculation of Expressions 6 and 7, the information processing device 500 determines the maximal WLHSVar(CB ｉ) is a set of assignment statements Stmt(LHS ｖａｒ (CB ｉ This analysis can be performed by a standard data dependency analysis called a compiler variable live range analysis or def-use analysis.

[0290] As shown in FIG. 37A, the code block CB １ By analyzing the above, a set of assignment statements Stmt (LHS ｖａｒ (CB １ )) is obtained. Also, as shown in FIG. ２ By analyzing the above, a set of assignment statements Stmt (LHS ｖａｒ (CB ２ )) is obtained.

[0291] Stmt (LHS ｖａｒ (CB １ The information processing device 500 converts only the write instruction obtained from the Stmt into a write instruction to both the volatile register file 450 and the non-volatile register file 410 to which the same address space is assigned.

[0292] After conversion into a write instruction, the information processing device 500 identifies variables that are referenced in each code block and that should be read from the nonvolatile register file 410 and verified by the following procedure. First, the information processing device 500 identifies variables that are referenced in each code block CBi and that should be read from the nonvolatile register file 410 and verified by the following procedure. ｖａｒ Next, the information processing device 500 obtains a set of variables that appear after the assignment statement included in WLHSVar(CB ｉ ) is referenced without writing to a variable, only the read instruction is replaced with a read and verify instruction.

[0293] The part surrounded by the dotted line in a in FIG. １ The area enclosed by the dotted line in the figure is the code block CB ２ indicates the variables to be read and verified.

[0294] As shown in FIG. 1B, the code block CB ２ So, "R ２ =B" writes to R2 and "b=R2+1" writes to R ２ However, the last "R ２ =B" and R ２ is overwritten, this overwritten value only needs to be stored in the nonvolatile register file 410, and no read or verify instructions are assigned before that. In this way, it is confirmed that the number of reads and verify operations is reduced. This type of analysis can also be performed by a standard data dependency analysis called a def-use analysis of compiler variables.

[0295] Furthermore, write instructions required for the following execution are converted into write instructions that write to both the volatile register file 450 and the non-volatile register file 410, which are assigned the same address space. Read instructions that do not involve writing and that are required for the following execution are replaced with read and verify instructions: Function call and return Entering an interrupt handler and returning from that handler Operations on the stack pointer, program counter, saved program counter, processor status word register, saved status word register, procedure register, base register, and vector base register

[0296] After the read and replacement with the verify instruction, the information processing device 500 replaces the checkpoint function with a save instruction that saves data from the volatile register file 450 to the non-volatile register bank 415 indicated by the BN register. Here, the save instruction saves only the data of registers whose tag bits have a logical value of "1" to the active bank.

[0297] 39 is a diagram illustrating an example of a checkpoint function to be replaced in the fifth embodiment of the present technology. The dotted line portion a in the figure indicates a code block CB １ The dotted line part b in the figure indicates the checkpoint function that is replaced with the save instruction. ２indicates the checkpoint function that is replaced by the save instruction.

[0298] As shown in the figure, writing to and saving from the nonvolatile register bank are performed at the instruction level, so the only code increase is the saving. Therefore, even when using the checkpoint insertion technique together, the increase in code size and the number of execution cycles is small.

[0299] 38, the information processing device 500 analyzes the data dependency for each code block and identifies variables to be saved in the save process based on the dependency. This makes it possible to reduce the number of writes and reads to the non-volatile register file 410 and the number of verify commands when used in conjunction with the checkpoint insertion technique.

[0300] As described above, according to the fifth embodiment of the present technology, the information processing device 500 divides the code into code blocks by the checkpoint insertion method and identifies variables to be saved. This makes it possible to reduce the number of writes and reads to the nonvolatile register file 410 and the number of verify instructions.

[0301] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0302] FIG. 40 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0303] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 40, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0304] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0305] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0306] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0307] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0308] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0309] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0310] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0311] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0312] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 40, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0313] FIG. 41 is a diagram showing an example of the installation position of the imaging unit 12031.

[0314] In FIG. 41, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0315] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0316] 41 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0317] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0318] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0319] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0320] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0321] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the semiconductor chip 200 in FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to reduce the power consumption of the imaging unit 12031.

[0322] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0323] The processing procedures described in the above embodiments may be considered as a method having a series of these procedures, or as a program for causing a computer to execute the series of procedures, or as a recording medium for storing the program. Examples of such a recording medium include a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, and a Blu-ray (registered trademark) Disc.

[0324] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0325] The present technology may also be configured as follows: (1) A semiconductor chip including: a volatile storage unit; a non-volatile storage unit including a plurality of non-volatile banks, one of which is designated as a backup bank; a bank switching control unit that designates one of the plurality of non-volatile banks that does not correspond to the backup bank as an active bank; a normal save / restore processing unit that performs a save process of writing data read from the volatile storage unit to the active bank when saving a context, and writes data read from the active bank to the volatile storage unit and the backup bank when context switching is not performed when restoring the context, and writes data read from a bank to be restored that is designated by context switching to the volatile storage unit and the backup bank when context switching is performed when restoring the context; and a power drop save / restore processing unit that performs the save process when a power supply voltage drops to a value lower than a first threshold, and swaps the backup bank and the active bank before performing the restore process when the dropped power supply voltage rises to a value higher than a second threshold. (2) The semiconductor chip according to (1), further comprising: a write processing unit that writes write data to the same address in the volatile memory unit and the active bank; and a read processing unit that reads data from the address in the volatile memory unit as first read data and reads data from the address in the active bank as second read data, wherein the normal save / restore processing unit and the power-down save / restore processing unit write the first read data to an address among all addresses of the active bank where the corresponding second read data does not match the first read data during the save processing. (3) The semiconductor chip according to (2), wherein the write processing unit writes the write data using a first write pulse, and the normal save / restore processing unit and the power-down save / restore processing unit write the first read data using a second write pulse having at least one of a pulse width and a voltage greater than that of the first write pulse.(4) The semiconductor chip according to any of (1) to (4), further comprising a register for storing bank numbers of the active bank and the backup bank, and wherein the power-down save / restore processor updates the register to store the ... (6) The semiconductor chip according to any one of (1) to (6), further comprising a virtual / real bank number management table that stores a correspondence between virtual bank numbers assigned to interrupt processes or tasks and real bank numbers assigned to each of the plurality of non-volatile banks, and the power-down save / restore processing unit swaps the backup bank and the active bank by updating the register and the virtual / real bank number management table. (7) The semiconductor chip according to any one of (1) to (6), further comprising a virtual / real bank number management table that stores a correspondence between virtual bank numbers assigned to interrupt processes or tasks and real bank numbers assigned to each of the plurality of non-volatile banks, and the power-down save / restore processing unit swaps the backup bank and the active bank by updating the register and the virtual / real bank number management table. (7) The semiconductor chip according to any one of (1) to (6),(8) The semiconductor chip according to any one of (1) to (7), wherein the volatile memory unit includes a volatile shared resource that stores shared data shared by a plurality of entities, and a volatile non-shared resource that stores data other than the shared data, and the plurality of non-volatile banks include a pair of non-volatile shared banks that store the shared data, and a plurality of non-volatile non-shared banks that store data other than the shared data. (9) The semiconductor chip according to any one of (1) to (7), wherein the volatile memory unit includes a pair of non-volatile shared banks that store the shared data, and a plurality of non-volatile non-shared banks that store data other than the shared data. (9) A detection circuit that detects when a power supply voltage drops to a value lower than a first threshold and when the power supply voltage rises to a value higher than a second threshold, a bank switching control unit that designates one of the plurality of non-volatile banks that does not correspond to the backup bank as an active bank; a normal save / restore processing unit that performs a save process of writing data read from the volatile memory unit to the active bank when saving a context, and writes data read from the active bank to the volatile memory unit and the backup bank when context switching is not performed when restoring the context, and writes data read from a bank to be restored that is designated by context switching to the volatile memory unit and the backup bank when context switching is performed when restoring the context; and a power drop save / restore processing unit that performs the save process when the power supply voltage drops to a value lower than the first threshold, and swaps the backup bank and the active bank before performing the restore process when the dropped power supply voltage rises to a value higher than the second threshold.(10) An information processing device that converts source code into object code; a semiconductor chip comprising: a volatile storage unit; a nonvolatile storage unit including a plurality of nonvolatile banks, one of which is designated as a backup bank; a bank switching control unit that designates one of the plurality of nonvolatile banks that is not the backup bank as an active bank; a normal save / restore processing unit that, when saving a context, performs a save process of writing data read from the volatile storage unit to the active bank based on the object code; when restoring the context, writes data read from the active bank to the volatile storage unit and the backup bank if context switching is not performed when restoring the context; and, when context switching is performed when restoring the context, writes data read from the restoration target bank designated by context switching to the volatile storage unit and the backup bank; and a power drop save / restore processing unit that performs the save process when a power supply voltage drops to a value lower than a first threshold, and, when the dropped power supply voltage rises to a value higher than a second threshold, swaps the backup bank and the active bank and then performs the restore process. (11) The information processing system according to (10), wherein the information processing device merges code blocks resulting from dividing the source code into multiple blocks using a checkpoint insertion method. (12) The information processing system according to (11), wherein the information processing device analyzes data dependencies for each code block and identifies variables to be saved in the saving process based on the dependencies.(13) A method for controlling a semiconductor chip, comprising: a bank switching control procedure for designating, as an active bank, one of a plurality of non-volatile banks, any of which is designated as a backup bank, that is not the backup bank; a normal save / restore procedure for performing a save process of writing data read from a volatile memory unit to the active bank when saving a context, and writing data read from the active bank to the volatile memory unit and the backup bank when context switching is not performed when restoring the context, and performing a restore process of writing data read from a bank to be restored designated by context switching to the volatile memory unit and the backup bank when context switching is performed when restoring the context; and a save / restore procedure for power drop, for performing the save process when a power supply voltage drops to a value lower than a first threshold, and for swapping the backup bank and the active bank before performing the restore process when the dropped power supply voltage rises to a value higher than a second threshold.

[0326] 100 Semiconductor device 110 Power supply drop / rise detection circuit 120 Power supply control unit 130 Capacitor 200 Semiconductor chip 211 Vertical drive circuit 212 Timing control unit 213 DAC 214 Pixel array unit 215 Column signal processing unit 216 Horizontal transfer control unit 220 Digital signal processing unit 221 External setting input / output interface 222 External initial setting non-volatile register group 300 Power interruption recovery compatible CPU system 310 Access control unit 311 Write processing unit 312 Read processing unit 313 Bank switching control unit 314 Normal save / restore processing unit 315 Save / restore processing unit during power drop 331 Program ROM 332 Data save / restore / bank switching sequencer 333 Instruction fetch decoder 334 Address calculation circuit 335 Calculation circuit 336 Volatile memory shared resource address specification register 337 Address converter 338 Data bus 339 Address bus 340 BN register 351, 370, 420 Non-volatile register 352, 362, 460 Volatile register 353, 363 Encoder 360 Virtual / real bank number management table 361, 411, 451 Address decoder 371, 372, 421 to 423, 461 to 464 AND (logical product) gate 373 Non-volatile flip-flop 374 XOR (exclusive OR) gate 375 NOR (negative OR) gate 400 Storage unit 410 Non-volatile register file 412 Bank number decoder 413 Non-volatile register group 414, 453 Output selector 415 Non-volatile register bank 424, 425, 468 Selector 426 Non-volatile multi-bit flip-flop 430 Non-volatile memory 441 Non-volatile memory shared resource 442 Non-volatile memory unshared resource 443 Non-volatile memory shared bank 444 Non-volatile memory unshared bank 450 Volatile register file 452 Volatile register group 454 Comparator 465, 466 Logic gate 467 OR (logical sum) gate 469 Volatile multi-bit flip-flop 470 1-bit flip-flop 480 Volatile memory481 Volatile memory shared resource 482 Volatile memory non-shared resource 500 Information processing device 12031 Imaging unit

Claims

a bank switching control unit that designates one of the non-volatile banks that is not a backup bank as an active bank; a normal save / restore processing unit that performs a save process to write data read from the volatile memory unit to the active bank when saving a context, and writes data read from the active bank to the volatile memory unit and the backup bank when context switching is not performed when restoring the context, and writes data read from the bank to be restored that is designated by context switching to the volatile memory unit and the backup bank when context switching is performed when restoring the context; and a power drop save / restore processing unit that performs the save process when a power supply voltage drops to a value lower than a first threshold, and swaps the backup bank and the active bank before performing the restoration process when the dropped power supply voltage rises to a value higher than a second threshold.

2. A semiconductor chip as described in claim 1, further comprising: a write processing unit that writes write data to the same address in the volatile memory unit and the active bank; and a read processing unit that reads data from the address in the volatile memory unit as first read data and reads data from the address in the active bank as second read data, wherein the normal save / restore processing unit and the power-down save / restore processing unit write the first read data to an address among all addresses of the active bank where the corresponding second read data does not match the first read data during the save processing, and the read processing unit performs the above processing for a read that does not involve a write.

3. The semiconductor chip according to claim 2, wherein the write processing unit writes the write data using a first write pulse, and the normal save / restore processing unit and the power-down save / restore processing unit write the first read data using a second write pulse having at least one of a pulse width and a voltage greater than that of the first write pulse.

4. The semiconductor chip of claim 3, wherein the volatile memory unit holds an initial value of a tag bit for each address; the write processing unit writes the write data to the address using the first write pulse and updates the corresponding tag bit to a value different from the initial value; the read processing unit updates the corresponding tag bit to the initial value if the first read data and the second read data match; and the normal save / restore processing unit and the power-down save / restore processing unit write the first read data to an address of all addresses where the corresponding tag bit is different from the initial value using the second write pulse.

5. The semiconductor chip according to claim 1, further comprising a register for holding the bank numbers of the active bank and the backup bank, and wherein the power-down save / restore processing unit swaps the backup bank and the active bank by updating the register.

6. The semiconductor chip according to claim 5, further comprising a virtual / real bank number management table that stores a correspondence between virtual bank numbers assigned to interrupt processes or tasks and real bank numbers assigned to each of the plurality of non-volatile banks, and the power-down save / restore processing unit swaps the backup bank and the active bank by updating the register and the virtual / real bank number management table.

7. The semiconductor chip according to claim 1, wherein each of the volatile storage unit and the non-volatile storage unit includes at least one of a general-purpose register, a stack pointer register, a program counter register, a saved program counter register, a processor status word register, a saved status register, a procedure register, a multiplication register, a base register, a vector base register, a read data buffer register, and a write data buffer register.

8. The semiconductor chip according to claim 1, wherein the volatile memory unit includes a volatile shared resource that stores shared data shared by multiple entities, and a volatile non-shared resource that stores data that does not fall under the shared data, and the multiple non-volatile banks include a pair of non-volatile shared banks that store the shared data, and multiple non-volatile non-shared banks that store data that does not fall under the shared data.

9. A detection circuit for detecting when the power supply voltage drops below a first threshold and when the power supply voltage rises above a second threshold; a bank switching control unit that designates one of the plurality of non-volatile banks that does not correspond to the backup bank as an active bank; a normal save / restore processing unit that performs a save process of writing data read from the volatile memory unit to the active bank when saving a context, and writes data read from the active bank to the volatile memory unit and the backup bank when context switching is not performed when restoring the context, and writes data read from a bank to be restored that is designated by context switching to the volatile memory unit and the backup bank when context switching is performed when restoring the context; and a power drop save / restore processing unit that performs the save process when the power supply voltage drops to a value lower than the first threshold, and swaps the backup bank and the active bank before performing the restore process when the dropped power supply voltage rises to a value higher than the second threshold.

10. An information processing device that converts source code into object code; a nonvolatile storage unit that includes a plurality of nonvolatile banks, one of which is designated as a backup bank; a bank switching control unit that designates one of the plurality of nonvolatile banks that is not the backup bank as an active bank; a normal save / restore processing unit that, when saving a context, performs a save process of writing data read from the volatile storage unit to the active bank based on the object code, and, when context switching is not performed when restoring the context, writes data read from the active bank to the volatile storage unit and the backup bank, and, when context switching is performed when restoring the context, writes data read from the bank to be restored that is designated by context switching to the volatile storage unit and the backup bank; and a power drop save / restore processing unit that performs the save process when a power supply voltage drops to a value lower than a first threshold, and, when the dropped power supply voltage rises to a value higher than a second threshold, swaps the backup bank and the active bank and then performs the restore process. An information processing system comprising:

11. The information processing system according to claim 10, wherein the information processing device merges the code blocks into which the source code is divided by a checkpoint insertion method.

12. The information processing system according to claim 11, wherein said information processing device analyzes data dependencies for each of said code blocks and identifies variables to be saved in said saving process based on said dependencies.

13. A control method for a semiconductor chip comprising: a bank switching control procedure for designating, as the active bank, one of a plurality of non-volatile banks, any of which is designated as a backup bank; a normal save / restore procedure for performing a save process in which, when saving a context, data is read from a volatile memory unit and written to the active bank; and, if a context switch is not performed when restoring the context, performing a restore process in which data is read from the active bank and written to the volatile memory unit and the backup bank; and a power drop save / restore procedure for performing the save process when a power supply voltage drops to a value lower than a first threshold, and, if the dropped power supply voltage rises to a value higher than a second threshold, swapping the backup bank and the active bank before performing the restore process.

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