Asymmetric interpolation of sub-pixels for motion compensation

Abstract

Methods and apparatuses for motion compensation are disclosed. A method includes interpolating a sub-pixel value at a first location using a first asymmetric interpolation filter having a first number of taps on a first side of the first location and a second number of taps on a second side of the first location, wherein a difference between the first number and the second number is two or greater. The first number of taps may be determined based on a number of pixels between the first location and a block boundary or an edge of a reference area. The method may include decoding a block in a current frame using the interpolated sub-pixel value. A video decoding apparatus and a video encoding apparatus implement the method. A non-transitory computer readable medium includes instructions to carry out the method or an encoded bitstream encoded by or decodable using the method.

Description

Atty. Doc. No. GOGL-2243-A-WO PATENTASYMMETRIC INTERPOLATION OF SUB-PIXELS FOR MOTION COMPENSATIONBACKGROUND

[0001] Digital images and video can be used, for example, on the internet, for remote business meetings via video conferencing, high-definition video entertainment, video advertisements, or sharing of user-generated content. Due to the large amount of data involved in transferring and processing image and video data, high-performance compression may be advantageous for transmission and storage. Accordingly, it would be advantageous to provide high-resolution image and video transmitted over communications channels having limited bandwidth.SUMMARY

[0002] This application relates to encoding and decoding of image data, video stream data, or both for transmission, storage, or both. Disclosed herein are aspects of systems, methods, and apparatuses for encoding and decoding using asymmetric interpolation of sub-pixels for motion compensation.

[0003] An aspect is a method for motion compensation. The method includes interpolating a sub-pixel value at a first location using a first asymmetric interpolation filter having a first number of taps on a first side of the first location and a second number of taps on a second side of the first location, wherein a difference between the first number and the second number is two or greater. The first asymmetric interpolation filter may be a linear filter that operates on a row or column of pixels. The first number of taps may be determined based on a number of pixels between the first location and a block boundary. The first number of taps may be determined based on a distance between the first location and an edge of a reference area. Interpolating the sub-pixel value may be performed according to a requirement of a first video decoding standard and the reference area may be determined based on a requirement of a second video decoding standard. Tap weights for the first side may be different from tap weights for the second side. The first number of taps may be determined based on a difference between a motion vector for a first block and a motion vector for a second block. The method may include decoding a third block in a current frame, including decoding a motion vector for the third block, the motion vector indicating a displacement to a predictionblock in a reference frame and determining a pixel value of the third block based on the subpixel value. The method may include displaying a decoded video including the decoded third block. The method may include interpolating an intermediate value at a second location using a second asymmetric interpolation filter having a third number of taps on a first side of the second location and a fourth number of taps on a second side of the second location, where a difference between the third number and the fourth number is two or greater, wherein the subpixel value is interpolated using the intermediate value.

[0004] An aspect is a method for motion compensation. The method may include interpolating a sub-pixel value at a first location using a first asymmetric interpolation filter having a first number of taps on a first side of the first location and a second number of taps on a second side of the first location, wherein the first number of taps depends on a number of pixels between the first location and an edge of a reference area. The first asymmetric interpolation filter may be a linear filter that operates on a row or column of pixels. The difference between the first number and the second number may be two or greater. The edge of the reference area may be outside a block in which the first location is located. Interpolating the sub-pixel value may be performed according to a requirement of a first video decoding standard and the reference area may be determined based on a requirement of a second video decoding standard. The tap weights for the first side may be different from tap weights for the second side. The first number of taps is based on a difference between a motion vector for a first block and a motion vector for a second block. The method may include decoding a third block in a current frame including decoding a motion vector for the third block, the motion vector indicating a displacement to a prediction block in a reference frame and determining a pixel value of the third block based on the sub-pixel value. The method may include displaying a decoded video including the decoded third block. The method may include interpolating an intermediate value at a second location using a second asymmetric interpolation filter having a third number of taps on a first side of the second location and a fourth number of taps on a second side of the second location, where the third number of taps depends on a number of pixels between the first location and an edge of a reference area.

[0005] An aspect is a video decoding apparatus according to one of the foregoing methods. An aspect is a video encoding apparatus according to one of the foregoing methods. An aspect is a computer readable medium according to one of the foregoing methods.

[0006] An aspect is a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out steps according to one ofthe foregoing methods.

[0007] An aspect is a non-transitory computer readable medium including an encoded bitstream that was encoded using any of the foregoing methods or is decodable using any of the foregoing methods. An aspect is a computer media product including an encoded bitstream encoded using the method of any of the foregoing methods or that is decodable using the method of any of the foregoing methods.

[0008] Variations in these and other aspects will be described in additional detail hereafter.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout the several views unless otherwise noted or otherwise clear from context.

[0010] FIG. 1 is a diagram of a computing device in accordance with implementations of this disclosure.

[0011] FIG. 2 is a diagram of a computing and communications system in accordance with implementations of this disclosure.

[0012] FIG. 3 is a diagram of a video stream for use in encoding and decoding in accordance with implementations of this disclosure.

[0013] FIG. 4 is a block diagram of an encoder in accordance with implementations of this disclosure.

[0014] FIG. 5 is a block diagram of a decoder in accordance with implementations of this disclosure.

[0015] FIG. 6 is a block diagram of a representation of a portion of a frame in accordance with implementations of this disclosure.

[0016] FIG. 7 is a diagram of an interpolation operation according to implementations of this disclosure.

[0017] FIG. 8 is a diagram of motion vectors representing full and sub-pixel motion according to implementations of this disclosure.

[0018] FIGS. 9 A and 9B are diagrams of generating a prediction block according to implementations of this disclosure.

[0019] FIG. 10 is a flow diagram of an example of motion compensation using an asymmetric interpolation filter according to implementations of this disclosure.

[0020] FIG. 11 is a diagram of a block and a reference area according to implementations of this disclosure.

[0021] FIG. 12 is a diagram of available pixels used to interpolate a sub-pixel value within a reference area according to implementations of this disclosure.DETAILED DESCRIPTION

[0022] Compression schemes related to coding video streams may include breaking images into blocks and generating a digital video output bitstream using one or more techniques to limit the information included in the output. A received bitstream can be decoded to re-create the blocks and the source images from the limited information. Encoding a video stream, or a portion thereof, such as a frame or a block, can include using temporal or spatial similarities in the video stream to improve coding efficiency. For example, a current block of a video stream may be encoded based on identifying a difference (residual) between certain pixel values in a previously coded frame and those in the current block. In this way, only the residual and parameters used to generate it need be added to the bitstream instead of including the entirety of the current block. This technique may be referred to as interprediction. The residual may be encoded using a lossy quantization step. Decoding (i.e., reconstructing) an encoded block from such a residual often results in a distortion between the original and the reconstructed block.

[0023] Motion compensation is the process of considering spatial displacement when performing inter-prediction. One of the parameters in inter-prediction is a motion vector that represents a spatial displacement of a previously coded block relative to the current block. The motion vector can be identified using a method of motion estimation, such as motion search. In the motion search, a portion of a reference frame (e.g., a reference or prediction block) is identified and is subtracted from a current block in a current frame to form a residual. The reference block can be in a different location than the current block, e.g., translated in a first direction and a second direction. The first direction and the second direction can be, respectively, the horizontal direction and the vertical direction, or vice versa. The horizontal and / or vertical translations identifying the reference block having is the motion vector. Bits representing the motion vector can be included in the encoded bitstream to permit a decoder to decode the motion vector and identify the reference block.

[0024] In some situations, the prediction block may not correspond exactly with pixels in the reference frame. For example, the motion vector may point to a location that is between pixels of blocks in the reference frame. In this case, motion compensated prediction at the sub-pixel level is utilized. Motion compensated prediction may involve the use of a sub-pixel interpolation filter (also referred to as “interpolation filter” or “interpolation filter type”) thatgenerates approximations of sub-pixel values at locations between the full pixels (also called integer pixels) of the reference frame along rows, columns, or both. In some implementations, the interpolation filter is a close approximation of an ideal low-pass filter in the frequency domain designed such that only frequencies in the original image are recovered (as opposed to artifacts that may be introduced because of video compression). The interpolation filter may be one of a number of interpolation filters available for use in motion compensated prediction, where each of the interpolation filters has a different frequency profile or response.

[0025] Some video formats use different interpolation filter types. For example, three interpolation filter types named according to their different frequency profiles may be used: a smooth filter, a normal filter, and a sharp filter. The interpolation filter to be used by a decoder to generate a prediction block may be signaled in the encoded bitstream.

[0026] An interpolation filter can include a filter size (i.e., number of taps) that can correspond to the number (i.e., cardinality) of pixels and / or coefficients (i.e., weights) used by an interpolation operation using the interpolation filter. For example, the interpolation filters may be 8-tap filters. That is, the interpolation filters are of size 8 or have 8 filter coefficients. In some cases, a filter size with an odd number may be used if the sub-pixel location is not directly in between the two closest pixels. In such a case, there would be one more tap on the side of the closest pixel.

[0027] Interpolation filters with a larger filter size can produce more accurate approximations of sub-pixels. For example, a 12-tap or 14-tap interpolation filter may produce better results than an 8-tap interpolation filter. Longer interpolation filters may be designed to be closer to an ideal filter and may provide more flat frequency response in the pass band and the stop band. For example, larger sized interpolation filters may produce better approximation for a high frequency video signal. However, a problem with using larger sized interpolation filters is that more pixels must be made available on each side of the pixel being approximated. For example, with hardware implementations, a requirement to load additional pixels may impact hardware footprint, cost, and power consumption. It may prove difficult and costly to support a new video coding standard that utilizes more taps and requires more pixels than existing video coding standards because of the requirement to fetch and store the additional pixels. For example, new hardware video decoder modules may need to be developed which may result in a proliferation of hardware video decoder modules to maintain and manufacture, may result in the usage of more complex hardware video decoder modules (which may increase footprint, cost, and power consumption) for devices that do notsupport or otherwise would not support the new video coding standard, or combinations thereof. An alternative to loading additional pixels is to use a placeholder value for some of the pixels (e.g., by padding the available pixels), but this approach increases computational complexity and reduces the accuracy of the resulting value.

[0028] Implementations of this disclosure solve problems such as these by utilizing asymmetric interpolation filters having a different number of taps on either side of the subpixel that is being approximated by the interpolation filter. For example, such an implementation may fetch and make available a smaller number of pixels than what may be required by a larger interpolation filter, such as a 12-tap or 14-tap filter. For example, loaded pixels may be limited to a reference area of pixels surrounding the reference or prediction block having a border of 3 or 4 pixels wide — for example the number of pixels that would be required for an 8-tap filter. With only, e.g., 4 pixels available extending from the prediction block, a typical 12-tap or 14-tap filter cannot be used to approximate a pixel at the edge of the prediction block. Instead, a filter can be used with 4 taps on one side and 6 or 7 taps on the other to increase the number of taps utilized in approximating the sub-pixel (and thus the accuracy of the result) while not increasing the size of the reference area or introducing the use of placeholder values.

[0029] In other words, the size of the interpolation filter on either side of the sub-pixel is decoupled to enable an asymmetric filter that has a different number of taps on either side of the sub-pixel. The number of taps on a given side of the asymmetric interpolation filter may be constrained based on the number of pixels or distance between sub-pixel being approximated and the edge of the reference area, the prediction or reference block boundary, or a combination thereof. The difference between the number of taps on either side of the sub-pixel can be two or greater. In some implementations, the number of taps utilized by the asymmetric interpolation filter may not vary based on the relative distance of a sub-pixel to adjacent integer pixels (e.g., !4, *6, % locations). In some implementations, the number of taps utilized by the asymmetric interpolation filter may be based on a number of pixels between the pixel being approximated and the block boundary, for example where there is a discontinuity at the block boundary, or the adjacent block is determined to be a part of a different moving object. For example, the number of taps may differ based on a difference between motion vectors for adjacent reference blocks (e.g., as compared to a threshold) and the number of taps may be constrained based on a block boundary between the reference blocks. In some implementations, the number of taps utilized by the interpolation filter maybe based on a number of pixels between the pixel being approximated and a discontinuity between pixels within the prediction block.

[0030] To produce a sub-pixel prediction, an asymmetric interpolation filter may be applied in a first direction to pixel values of the reference frame (or reference block) to produce an intermediate reference block of intermediate pixel values. An asymmetric interpolation filter is applied to the intermediate pixel values in a second direction to generate the pixel values of the prediction block. As indicated above, the first direction and the second direction can be, respectively, the horizontal direction and the vertical direction. Alternatively, the first direction and the second direction can be, respectively, the vertical direction and the horizontal direction. When operating in the horizontal direction, the interpolation filter operates on a row of pixels and when operating in the vertical direction the interpolation filter operates on a column of pixels.

[0031] In the foregoing example, the asymmetric filter used for respective vertical and horizontal directions may vary based on the respective locations for each intermediate pixel and prediction (sub-pixel) locations within the prediction block and / or reference area. In other words, the number of pixels and / or distance between a given pixel and the block boundary and / or edge of the reference area may be different in the vertical and horizontal directions and thus may result in a different number of taps being utilized respectively in the horizontal and vertical directions.

[0032] In some implementations, an asymmetric filter may be used in a first direction and a symmetric filter (e.g., a filter with the same number of taps on each side of the approximated pixel) for a second direction. For example, the number of taps may be constrained in the first direction and not the second direction because the approximated pixel may be closer to the edge of the prediction block in the first direction as compared to the second direction. Alternatively, or additionally, asymmetric interpolation filters may be configured to be available in one direction but not the other, or the length of filters used may be different in one direction or the other, each of which may affect whether the conditions for using an asymmetric filter will be met.

[0033] FIG. 1 is a diagram of a computing device 100 in accordance with implementations of this disclosure. The computing device 100 shown includes a memory 110, a processor 120, a user interface (UI) 130, an electronic communication unit 140, a sensor 150, a power source 160, and a bus 170. As used herein, the term “computing device” includes any unit, or a combination of units, capable of performing any method, or any portion or portions thereof, disclosed herein.

[0034] The computing device 100 may be a stationary computing device, such as a personal computer (PC), a server, a workstation, a minicomputer, or a mainframe computer; or a mobile computing device, such as a mobile telephone, a personal digital assistant (PDA), a laptop, or a tablet PC. Although shown as a single unit, any one element or elements of the computing device 100 can be integrated into any number of separate physical units. For example, the user interface 130 and processor 120 can be integrated in a first physical unit and the memory 110 can be integrated in a second physical unit.

[0035] The memory 110 can include any non-transitory computer-usable or computer- readable medium, such as any tangible device that can, for example, contain, store, communicate, or transport data 112, instructions 114, an operating system 116, or any information associated therewith, for use by or in connection with other components of the computing device 100. The non-transitory computer-usable or computer-readable medium can be, for example, a solid-state drive, a memory card, removable media, a read-only memory (ROM), a random-access memory (RAM), any type of disk including a hard disk, a floppy disk, an optical disk, a magnetic or optical card, an application- specific integrated circuits (ASICs), or any type of non-transitory media suitable for storing electronic information, or any combination thereof.

[0036] Although shown as a single unit, the memory 110 may include multiple physical units, such as one or more primary memory units, such as random-access memory units, one or more secondary data storage units, such as disks, or a combination thereof. For example, the data 112, or a portion thereof, the instructions 114, or a portion thereof, or both, may be stored in a secondary storage unit and may be loaded or otherwise transferred to a primary storage unit in conjunction with processing the respective data 112, executing the respective instructions 114, or both. In some implementations, the memory 110, or a portion thereof, may be removable memory.

[0037] The data 112 can include information, such as input audio data, encoded audio data, decoded audio data, or the like. The instructions 114 can include directions, such as code, for performing any method, or any portion or portions thereof, disclosed herein. The instructions 114 can be realized in hardware, software, or any combination thereof. For example, the instructions 114 may be implemented as information stored in the memory 110, such as a computer program, which may be executed by the processor 120 to perform any of the respective methods, algorithms, aspects, or combinations thereof, as described herein.

[0038] Although shown as included in the memory 110, in some implementations, the instructions 114, or a portion thereof, may be implemented as a special purpose processor, orcircuitry, that can include specialized hardware for carrying out any of the methods, algorithms, aspects, or combinations thereof, as described herein. Portions of the instructions 114 can be distributed across multiple processors on the same machine or different machines or across a network such as a local area network, a wide area network, the Internet, or a combination thereof.

[0039] The processor 120 can include any device or system capable of manipulating or processing a digital signal or other electronic information now-existing or hereafter developed, including optical processors, quantum processors, molecular processors, or a combination thereof. For example, the processor 120 can include a special purpose processor, a central processing unit (CPU), a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessor in association with a DSP core, a controller, a microcontroller, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a programmable logic array, programmable logic controller, microcode, firmware, any type of integrated circuit (IC), a state machine, or any combination thereof. As used herein, the term “processor” includes a single processor or multiple processors.

[0040] The user interface 130 can include any unit capable of interfacing with a user, such as a virtual or physical keypad, a touchpad, a display, a touch display, a speaker, a microphone, a video camera, a sensor, or any combination thereof. For example, the user interface 130 may be an audio-visual display device, and the computing device 100 may present audio, such as decoded audio, using the user interface 130 audio-visual display device, such as in conjunction with displaying video, such as decoded video. Although shown as a single unit, the user interface 130 may include one or more physical units. For example, the user interface 130 may include an audio interface for performing audio communication with a user, and a touch display for performing visual and touch-based communication with the user.

[0041] The electronic communication unit 140 can transmit, receive, or transmit and receive signals via a wired or wireless electronic communication medium 180, such as a radio frequency (RF) communication medium, an ultraviolet (UV) communication medium, a visible light communication medium, a fiber optic communication medium, a wireline communication medium, or a combination thereof. For example, as shown, the electronic communication unit 140 is operatively connected to an electronic communication interface 142, such as an antenna, configured to communicate via wireless signals.

[0042] Although the electronic communication interface 142 is shown as a wireless antenna in FIG. 1, the electronic communication interface 142 can be a wireless antenna, asshown, a wired communication port, such as an Ethernet port, an infrared port, a serial port, or any other wired or wireless unit capable of interfacing with a wired or wireless electronic communication medium 180. Although FIG. 1 shows a single electronic communication unit 140 and a single electronic communication interface 142, any number of electronic communication units and any number of electronic communication interfaces can be used.

[0043] The sensor 150 may include, for example, an audio-sensing device, a visible lightsensing device, a motion sensing device, or a combination thereof. For example, the sensor 150 may include a sound-sensing device, such as a microphone, or any other sound-sensing device now existing or hereafter developed that can sense sounds in the proximity of the computing device 100, such as speech or other utterances, made by a user operating the computing device 100. In another example, the sensor 150 may include a camera, or any other image-sensing device now existing or hereafter developed that can sense an image such as the image of a user operating the computing device. Although a single sensor 150 is shown, the computing device 100 may include a number of sensors 150. For example, the computing device 100 may include a first camera oriented with a field of view directed toward a user of the computing device 100 and a second camera oriented with a field of view directed away from the user of the computing device 100.

[0044] The power source 160 can be any suitable device for powering the computing device 100. For example, the power source 160 can include a wired external power source interface; one or more dry cell batteries, such as nickel-cadmium (NiCd), nickel-zinc (NiZn), nickel metal hydride (NiMH), lithium-ion (Ei-ion); solar cells; fuel cells; or any other device capable of powering the computing device 100. Although a single power source 160 is shown in FIG. 1, the computing device 100 may include multiple power sources 160, such as a battery and a wired external power source interface.

[0045] Although shown as separate units, the electronic communication unit 140, the electronic communication interface 142, the user interface 130, the power source 160, or portions thereof, may be configured as a combined unit. For example, the electronic communication unit 140, the electronic communication interface 142, the user interface 130, and the power source 160 may be implemented as a communications port capable of interfacing with an external display device, providing communications, power, or both.

[0046] One or more of the memory 110, the processor 120, the user interface 130, the electronic communication unit 140, the sensor 150, or the power source 160, may be operatively coupled via a bus 170. Although a single bus 170 is shown in FIG. 1, a computing device 100 may include multiple buses. For example, the memory 110, the processor 120, theuser interface 130, the electronic communication unit 140, the sensor 150, and the bus 170 may receive power from the power source 160 via the bus 170. In another example, the memory 110, the processor 120, the user interface 130, the electronic communication unit 140, the sensor 150, the power source 160, or a combination thereof, may communicate data, such as by sending and receiving electronic signals, via the bus 170.

[0047] Although not shown separately in FIG. 1, one or more of the processor 120, the user interface 130, the electronic communication unit 140, the sensor 150, or the power source 160 may include internal memory, such as an internal buffer or register. For example, the processor 120 may include internal memory (not shown) and may read data 112 from the memory 110 into the internal memory (not shown) for processing.

[0048] Although shown as separate elements, the memory 110, the processor 120, the user interface 130, the electronic communication unit 140, the sensor 150, the power source 160, and the bus 170, or any combination thereof can be integrated in one or more electronic units, circuits, or chips.

[0049] FIG. 2 is a diagram of a computing and communications system 200 in accordance with implementations of this disclosure. The computing and communications system 200 shown includes computing and communication devices 100A, 100B, 100C, access points 210A, 210B, and a network 220. For example, the computing and communication system 200 can be a multiple access system that provides communication, such as voice, audio, data, video, messaging, broadcast, or a combination thereof, to one or more wired or wireless communicating devices, such as the computing and communication devices 100A, 100B, 100C. Although, for simplicity, FIG. 2 shows three computing and communication devices 100A, 100B, 100C, two access points 210A, 210B, and one network 220, any number of computing and communication devices, access points, and networks can be used.

[0050] A computing and communication device 100A, 100B, 100C can be, for example, a computing device, such as the computing device 100 shown in FIG. 1. For example, the computing and communication devices 100A, 100B may be user devices, such as a mobile computing device, a laptop, a thin client, or a smartphone, and the computing and communication device 100C may be a server, such as a mainframe or a cluster. Although the computing and communication device 100A and the computing and communication device 100B are described as user devices, and the computing and communication device 100C is described as a server, any computing and communication device may perform some or all of the functions of a server, some, or all, of the functions of a user device, or some or all of the functions of a server and a user device. For example, the server computing andcommunication device 100C may receive, encode, process, store, transmit, or a combination thereof video data and one or both of the computing and communication device 100A and the computing and communication device 100B may receive, decode, process, store, present, or a combination thereof the video data.

[0051] Each computing and communication device 100A, 100B, 100C, which may include a user equipment (UE), a mobile station, a fixed or mobile subscriber unit, a cellular telephone, a personal computer, a tablet computer, a server, consumer electronics, or any similar device, can be configured to perform wired or wireless communication, such as via the network 220. For example, the computing and communication devices 100A, 100B, 100C can be configured to transmit or receive wired or wireless communication signals. Although each computing and communication device 100A, 100B, 100C is shown as a single unit, a computing and communication device can include any number of interconnected elements.

[0052] Each access point 210A, 210B can be any type of device configured to communicate with a computing and communication device 100A, 100B, 100C, a network 220, or both via wired or wireless communication links 180A, 180B, 180C. For example, an access point 210A, 210B can include a base station, a base transceiver station (BTS), a Node- B, an enhanced Node-B (eNode-B), a Home Node-B (HNode-B), a wireless router, a wired router, a hub, a relay, a switch, or any similar wired or wireless device. Although each access point 210A, 210B is shown as a single unit, an access point can include any number of interconnected elements.

[0053] The network 220 can be any type of network configured to provide services, such as voice, data, applications, voice over internet protocol (VoIP), or any other communications protocol or combination of communications protocols, over a wired or wireless communication link. For example, the network 220 can be a local area network (LAN), wide area network (WAN), virtual private network (VPN), a mobile or cellular telephone network, the Internet, or any other means of electronic communication. The network can use a communication protocol, such as the transmission control protocol (TCP), the user datagram protocol (UDP), the internet protocol (IP), the real-time transport protocol (RTP) the HyperText Transport Protocol (HTTP), or a combination thereof.

[0054] The computing and communication devices 100A, 100B, 100C can communicate with each other via the network 220 using one or more a wired or wireless communication links, or via a combination of wired and wireless communication links. For example, as shown the computing and communication devices 100A, 100B can communicate via wireless communication links 180A, 180B, and computing and communication device 100C cancommunicate via a wired communication link 180C. Any of the computing and communication devices 100A, 100B, 100C may communicate using any wired or wireless communication link, or links. For example, a first computing and communication device 100A can communicate via a first access point 210A using a first type of communication link, a second computing and communication device 100B can communicate via a second access point 21 OB using a second type of communication link, and a third computing and communication device 100C can communicate via a third access point (not shown) using a third type of communication link. Similarly, the access points 210A, 210B can communicate with the network 220 via one or more types of wired or wireless communication links 230A, 230B. Although FIG. 2 shows the computing and communication devices 100A, 100B, 100C in communication via the network 220, the computing and communication devices 100A, 100B, 100C can communicate with each other via any number of communication links, such as a direct wired or wireless communication link.

[0055] In some implementations, communications between one or more of the computing and communication device 100A, 100B, 100C may omit communicating via the network 220 and may include transferring data via another medium (not shown), such as a data storage device. For example, the server computing and communication device 100C may store audio data, such as encoded audio data, in a data storage device, such as a portable data storage unit, and one or both of the computing and communication device 100A or the computing and communication device 100B may access, read, or retrieve the stored audio data from the data storage unit, such as by physically disconnecting the data storage device from the server computing and communication device 100C and physically connecting the data storage device to the computing and communication device 100A or the computing and communication device 100B.

[0056] Other implementations of the computing and communications system 200 are possible. For example, in an implementation, the network 220 can be an ad-hoc network and can omit one or more of the access points 210A, 210B. The computing and communications system 200 may include devices, units, or elements not shown in FIG. 2. For example, the computing and communications system 200 may include many more communication devices, networks, and access points.

[0057] FIG. 3 is a diagram of a video stream 300 for use in encoding and decoding in accordance with implementations of this disclosure. A video stream 300, such as a video stream captured by a video camera or a video stream generated by a computing device, may include a video sequence 310. The video sequence 310 may include a sequence of adjacentframes 320. Although three adjacent frames 320 are shown, the video sequence 310 can include any number of adjacent frames 320.

[0058] A frame 330 from the adjacent frames 320 may represent a single image from the video stream. Although not shown in FIG. 3, a frame 330 may include one or more segments, tiles, or planes, which may be coded, or otherwise processed, independently, such as in parallel. A frame 330 may include one or more tiles 340. A tile 340 may be a rectangular region of the frame that can be coded independently. Tiles 340 may include respective blocks 350. Although not shown in FIG. 3, a block can include pixels. For example, a block can include a 16x16 group of pixels, an 8x8 group of pixels, an 8x16 group of pixels, or any other group of pixels. Unless otherwise indicated herein, the term ‘block’ can include a superblock, a macroblock, a segment, a slice, or any other portion of a frame. A frame, a block, a pixel, or a combination thereof can include display information, such as luminance information, chrominance information, or any other information that can be used to store, modify, communicate, or display the video stream or a portion thereof.

[0059] Some implementations may include additional or fewer components than described with respect to FIG. 3. For example, some implementations may not utilize tiles. For example, some implementations may utilize slices or some other intermediate partitioning of a frame instead of tiles. For example, some implementations may utilize different block structures. For example, some implementations may utilize variable block sizes. For example, some implementations may utilize a hierarchical block structure with two or more levels of blocks with different sizes (e.g., in a quad-tree type structure) where different information is coded at different block levels.

[0060] FIG. 4 is a block diagram of an encoder 400 in accordance with implementations of this disclosure. Encoder 400 can be implemented in a device, such as the computing device 100 shown in FIG. 1 or the computing and communication devices 100A, 100B, 100C shown in FIG. 2, as, for example, a computer software program stored in a data storage unit, such as the memory 110 shown in FIG. 1. The computer software program can include machine instructions that may be executed by a processor, such as the processor 120 shown in FIG. 1, and may cause the device to encode video data as described herein. The encoder 400 can be implemented as specialized hardware included, for example, in computing device 100.

[0061] The encoder 400 can encode an input video stream 402, such as the video stream 300 shown in FIG. 3, to generate an encoded (compressed) bitstream 404. In some implementations, the encoder 400 may include a forward path for generating the compressed bitstream 404. The forward path may include an intra / inter prediction unit 410, a transformunit 420, a quantization unit 430, an entropy encoding unit 440, or any combination thereof. In some implementations, the encoder 400 may include a reconstruction path (indicated by the broken connection lines) to reconstruct a frame for encoding of further blocks. The reconstruction path may include a dequantization unit 450, an inverse transform unit 460, a reconstruction unit 470, a filtering unit 480, or any combination thereof. Other structural variations of the encoder 400 can be used to encode the video stream 402.

[0062] For encoding the video stream 402, each frame within the video stream 402 can be processed in units of blocks. Thus, a current block may be identified from the blocks in a frame, and the current block may be encoded.

[0063] At the intra / inter prediction unit 410, the current block can be encoded using either intra-frame prediction, which may be within a single frame, or inter-frame prediction, which may be from frame to frame. Intra-prediction may include generating a prediction block from samples in the current frame that have been previously encoded and reconstructed. Interprediction may include generating a prediction block from samples in one or more previously constructed reference frames. Generating a prediction block for a current block in a current frame may include performing motion estimation to generate a motion vector indicating an appropriate reference portion of the reference frame. The motion vector may be generated at a sub-pixel precision. In such a case, interpolation may be utilized to approximate the pixels of the prediction block based on decoded pixels in the reference frame. Implementations of this interpolation process are further described elsewhere in this specification.

[0064] The intra / inter prediction unit 410 may subtract the prediction block from the current block (raw block) to produce a residual block. The transform unit 420 may perform a block-based transform, which may include transforming the residual block into transform coefficients in, for example, the frequency domain. Examples of block-based transforms include the Karhunen-Loeve Transform (KLT), the Discrete Cosine Transform (DCT), the Singular Value Decomposition Transform (SVD), and the Asymmetric Discrete Sine Transform (ADST). In an example, the DCT may include transforming a block into the frequency domain. The DCT may include using transform coefficient values based on spatial frequency, with the lowest frequency (i.e., DC) coefficient at the top-left of the matrix and the highest frequency coefficient at the bottom-right of the matrix.

[0065] The quantization unit 430 may convert the transform coefficients into discrete quantized values, which may be referred to as quantized transform coefficients or quantization levels. The quantized transform coefficients can be entropy encoded by the entropy encoding unit 440 to produce entropy-encoded coefficients. Entropy encoding caninclude using a probability distribution metric. The entropy-encoded coefficients and information used to decode the block, which may include the type of prediction used, motion vectors, and quantizer values, can be output to the compressed bitstream 404. The compressed bitstream 404 can be formatted using various techniques, such as run-length encoding (RLE) and zero -run coding.

[0066] The reconstruction path can be used to maintain reference frame synchronization between the encoder 400 and a corresponding decoder, such as the decoder 500 shown in FIG. 5. The reconstruction path may be similar to the decoding process discussed below and may produce an output equivalent to that produced by the decoding process to enable prediction at both the encoder and the decoder to produce the same results. The reconstruction process may include decoding the encoded frame, or a portion thereof, which may include decoding an encoded block, which may include dequantizing the quantized transform coefficients at the dequantization unit 450 and inverse transforming the dequantized transform coefficients at the inverse transform unit 460 to produce a derivative residual block. The reconstruction unit 470 may add the prediction block generated by the intra / inter prediction unit 410 to the derivative residual block to create a decoded block. The filtering unit 480 can be applied to the decoded block to generate a reconstructed block, which may reduce distortion, such as blocking artifacts. Although one filtering unit 480 is shown in FIG. 4, filtering the decoded block may include loop filtering, deblocking filtering, or other types of filtering or combinations of types of filtering. The reconstructed block may be stored or otherwise made accessible as a reconstructed block, which may be a portion of a reference frame, for encoding another portion of a current frame, another frame, or both, as indicated by the broken line at 482. Coding information, such as deblocking threshold index values, for the frame may be encoded, included in the compressed bitstream 404, or both, as indicated by the broken line at 484.

[0067] Other variations of the encoder 400 can be used to encode the compressed bitstream 404. For example, a non-transform-based encoder 400 can quantize the residual block directly without the transform unit 420. In some implementations, the quantization unit 430 and the dequantization unit 450 may be combined into a single unit.

[0068] FIG. 5 is a block diagram of a decoder 500 in accordance with implementations of this disclosure. The decoder 500 can be implemented in a device, such as the computing device 100 shown in FIG. 1 or the computing and communication devices 100A, 100B, 100C shown in FIG. 2, as, for example, a computer software program stored in a data storage unit, such as the memory 110 shown in FIG. 1. The computer software program can includemachine instructions that may be executed by a processor, such as the processor 120 shown in FIG. 1, and may cause the device to decode video data as described herein. The decoder 500 can be implemented as specialized hardware included, for example, in computing device 100.

[0069] The decoder 500 may receive a compressed bitstream 502, such as the compressed bitstream 404 shown in FIG. 4, and may decode the compressed bitstream 502 to generate an output video stream 504. The decoder 500 may include an entropy decoding unit 510, a dequantization unit 520, an inverse transform unit 530, an intra / inter prediction unit 540, a reconstruction unit 550, a filtering unit 560, or any combination thereof. Other structural variations of the decoder 500 can be used to decode the compressed bitstream 502.

[0070] The entropy decoding unit 510 may decode data elements within the compressed bitstream 502 using, for example, Context Adaptive Binary Arithmetic Decoding, to produce a set of quantized transform coefficients. The dequantization unit 520 can dequantize the quantized transform coefficients, and the inverse transform unit 530 can inverse transform the dequantized transform coefficients to produce a derivative residual block, which may correspond to the derivative residual block generated by the inverse transform unit 460 shown in FIG. 4. Using header information decoded from the compressed bitstream 502, the intra / inter prediction unit 540 may generate a prediction block corresponding to the prediction block created in the encoder 400. At the reconstruction unit 550, the prediction block can be added to the derivative residual block to create a decoded block. The filtering unit 560 can be applied to the decoded block to reduce artifacts, such as blocking artifacts, which may include loop filtering, deblocking filtering, or other types of filtering or combinations of types of filtering, and which may include generating a reconstructed block, which may be output as the output video stream 504.

[0071] Other variations of the decoder 500 can be used to decode the compressed bitstream 502. For example, the decoder 500 can produce the output video stream 504 without the filtering unit 560.

[0072] A video coding standard may specify the requirements to produce a compliant decoder. Such a standard may not specify how to make a video encoder or may provide only certain requirements as to what must be included in a compliant encoder. Instead, an encoder is compliant if it produced a video bitstream that is capable of being decoded by a compliant video decoder. Accordingly, certain tools are implemented to produce the same results in both the encoder and decoder, such as interpolation filters for sub-pixel motion compensation.

[0073] FIG. 6 is a block diagram of a representation of a portion 600 of a frame, such as the frame 330 shown in FIG. 3, in accordance with implementations of this disclosure. Asshown, the portion 600 of the frame includes four 64x64 blocks 610, in two rows and two columns in a matrix or Cartesian plane. In some implementations, a 64x64 block may be a maximum coding unit, N=64. Each 64x64 block may include four 32x32 blocks 620. Each 32x32 block may include four 16x16 blocks 630. Each 16x16 block may include four 8x8 blocks 640. Each 8x8 block 640 may include four 4x4 blocks 650. Each 4x4 block 650 may include 16 pixels, which may be represented in four rows and four columns in each respective block in the Cartesian plane or matrix. The pixels may include information representing an image captured in the frame, such as luminance information, color information, and location information. In some implementations, a block, such as a 16xl6-pixel block as shown, may include a luminance block 660, which may include luminance pixels 662; and two chrominance blocks 670, 680, such as a U or Cb chrominance block 670, and a V or Cr chrominance block 680. The chrominance blocks 670, 680 may include chrominance pixels 690. For example, the luminance block 660 may include 16x16 luminance pixels 662 and each chrominance block 670, 680 may include 8x8 chrominance pixels 690 as shown. Although one arrangement of blocks is shown, any arrangement may be used. Although FIG. 6 shows NxN blocks, in some implementations, NxM blocks may be used. For example, 32x64 blocks, 64x32 blocks, 16x32 blocks, 32x16 blocks, or any other size blocks may be used. In some implementations, Nx2N blocks, 2NxN blocks, or a combination thereof may be used.

[0074] In some implementations, video coding may include ordered block-level coding. Ordered block-level coding may include coding blocks of a frame in an order, such as rasterscan order, wherein blocks may be identified and processed starting with a block in the upper left comer of the frame, or portion of the frame, and proceeding along rows from left to right and from the top row to the bottom row, identifying each block in turn for processing. For example, the 64x64 block in the top row and left column of a frame may be the first block coded and the 64x64 block immediately to the right of the first block may be the second block coded. The second row from the top may be the second row coded, such that the 64x64 block in the left column of the second row may be coded after the 64x64 block in the rightmost column of the first row.

[0075] In some implementations, coding a block may include using quad-tree coding, which may include coding smaller block units within a block in raster- scan order. For example, the 64x64 block shown in the bottom left comer of the portion of the frame shown in FIG. 6, may be coded using quad-tree coding wherein the top left 32x32 block may be coded, then the top right 32x32 block may be coded, then the bottom left 32x32 block maybe coded, and then the bottom right 32x32 block may be coded. Each 32x32 block may be coded using quad- tree coding wherein the top left 16x16 block may be coded, then the top right 16x16 block may be coded, then the bottom left 16x16 block may be coded, and then the bottom right 16x16 block may be coded. Each 16x16 block may be coded using quad- tree coding wherein the top left 8x8 block may be coded, then the top right 8x8 block may be coded, then the bottom left 8x8 block may be coded, and then the bottom right 8x8 block may be coded. Each 8x8 block may be coded using quad-tree coding wherein the top left 4x4 block may be coded, then the top right 4x4 block may be coded, then the bottom left 4x4 block may be coded, and then the bottom right 4x4 block may be coded. In some implementations, 8x8 blocks may be omitted for a 16x16 block, and the 16x16 block may be coded using quad-tree coding wherein the top left 4x4 block may be coded, then the other 4x4 blocks in the 16x16 block may be coded in raster- scan order.

[0076] In some implementations, video coding may include compressing the information included in an original, or input, frame by, for example, omitting some of the information in the original frame from a corresponding encoded frame. For example, coding may include reducing spectral redundancy, reducing spatial redundancy, reducing temporal redundancy, or a combination thereof.

[0077] In some implementations, reducing spectral redundancy may include using a color model based on a luminance component (Y) and two chrominance components (U and V or Cb and Cr), which may be referred to as the YUV or YCbCr color model, or color space. Using the YUV color model may include using a relatively large amount of information to represent the luminance component of a portion of a frame and using a relatively small amount of information to represent each corresponding chrominance component for the portion of the frame. For example, a portion of a frame may be represented by a high- resolution luminance component, which may include a 16x16 block of pixels, and by two lower resolution chrominance components, each of which represents the portion of the frame as an 8x8 block of pixels. A pixel may indicate a value, for example, a value in the range from 0 to 255, and may be stored or transmitted using, for example, eight bits. Although this disclosure is described in reference to the YUV color model, any color model may be used.

[0078] In some implementations, reducing spatial redundancy may include transforming a block into the frequency domain using, for example, a discrete cosine transform (DCT). For example, a unit of an encoder, such as the transform unit 420 shown in FIG. 4, may perform a DCT using transform coefficient values based on spatial frequency.

[0079] In some implementations, reducing temporal redundancy may include usingsimilarities between frames to encode a frame using a relatively small amount of data based on one or more reference frames, which may be previously encoded, decoded, and reconstructed frames of the video stream. For example, a block or pixel of a current frame may be similar to a spatially corresponding block or pixel of a reference frame. In some implementations, a block or pixel of a current frame may be similar to block or pixel of a reference frame at a different spatial location and reducing temporal redundancy may include generating motion information indicating the spatial difference, or translation, between the location of the block or pixel in the current frame and corresponding location of the block or pixel in the reference frame.

[0080] In some implementations, reducing temporal redundancy may include identifying a portion of a reference frame that corresponds to a current block or pixel of a current frame. For example, a reference frame, or a portion of a reference frame, which may be stored in memory, may be searched to identify a portion for generating a prediction to use for encoding a current block or pixel of the current frame with maximal efficiency. For example, the search may identify a portion of the reference frame for which the difference in pixel values between the current block and a prediction block generated based on the portion of the reference frame is minimized and may be referred to as motion searching. In some implementations, the portion of the reference frame searched may be limited. For example, the portion of the reference frame searched, which may be referred to as the search area, may include a limited number of rows of the reference frame. In an example, identifying the portion of the reference frame for generating a prediction may include calculating a cost function, such as a sum of absolute differences (SAD), between the pixels of portions of the search area and the pixels of the current block.

[0081] In some implementations, the spatial difference between the location of the portion of the reference frame for generating a prediction in the reference frame and the current block in the current frame may be represented as a motion vector. The difference in pixel values between the prediction block and the current block may be referred to as differential data, residual data, a prediction error, or as a residual block. In some implementations, generating motion vectors may be referred to as motion estimation, and a pixel of a current block may be indicated based on location using Cartesian coordinates as / x,y. Similarly, a pixel of the search area of the reference frame may be indicated based on location using Cartesian coordinates as rx,y. A motion vector (MV) for the current block may be determined based on, for example, a SAD between the pixels of the current frame and the corresponding pixels of the referenceframe.

[0082] Although described herein with reference to matrix or Cartesian representation of a frame for clarity, a frame may be stored, transmitted, processed, or any combination thereof, in any data structure such that pixel values may be efficiently represented for a frame or image. For example, a frame may be stored, transmitted, processed, or any combination thereof, in a two-dimensional data structure such as a matrix as shown, or in a onedimensional data structure, such as a vector array. In an implementation, a representation of the frame, such as a two-dimensional representation as shown, may correspond to a physical location in a rendering of the frame as an image. For example, a location in the top left corner of a block in the top left comer of the frame may correspond with a physical location in the top left corner of a rendering of the frame as an image.

[0083] In some implementations, block-based coding efficiency may be improved by partitioning input blocks into one or more prediction partitions, which may be rectangular, including square, partitions for prediction coding. In some implementations, video coding using prediction partitioning may include selecting a prediction partitioning scheme from among multiple candidate prediction partitioning schemes. For example, in some implementations, candidate prediction partitioning schemes for a 64x64 coding unit may include rectangular size prediction partitions ranging in sizes from 4x4 to 64x64, such as 4x4, 4x8, 8x4, 8x8, 8x16, 16x8, 16x16, 16x32, 32x16, 32x32, 32x64, 64x32, or 64x64. In some implementations, video coding using prediction partitioning may include a full prediction partition search, which may include selecting a prediction partitioning scheme by encoding the coding unit using each available candidate prediction partitioning scheme and selecting the best scheme, such as the scheme that produces the least rate-distortion error.

[0084] In some implementations, encoding a video frame may include identifying a prediction partitioning scheme for encoding a current block, such as block 610. In some implementations, identifying a prediction partitioning scheme may include determining whether to encode the block as a single prediction partition of maximum coding unit size, which may be 64x64 as shown, or to partition the block into multiple prediction partitions, which may correspond with the sub-blocks, such as the 32x32 blocks 620 the 16x16 blocks 630, or the 8x8 blocks 640, as shown, and may include determining whether to partition into one or more smaller prediction partitions. For example, a 64x64 block may be partitioned into four 32x32 prediction partitions. Three of the four 32x32 prediction partitions may be encoded as 32x32 prediction partitions and the fourth 32x32 prediction partition may be further partitioned into four 16x16 prediction partitions. Three of the four 16x16 predictionpartitions may be encoded as 16x16 prediction partitions and the fourth 16x16 prediction partition may be further partitioned into four 8x8 prediction partitions, each of which may be encoded as an 8x8 prediction partition. In some implementations, identifying the prediction partitioning scheme may include using a prediction partitioning decision tree.

[0085] In some implementations, video coding for a current block may include identifying an optimal prediction coding mode from multiple candidate prediction coding modes, which may provide flexibility in handling video signals with various statistical properties and may improve the compression efficiency. For example, a video coder may evaluate each candidate prediction coding mode to identify the optimal prediction coding mode, which may be, for example, the prediction coding mode that minimizes an error metric, such as a rate-distortion cost, for the current block. In some implementations, the complexity of searching the candidate prediction coding modes may be reduced by limiting the set of available candidate prediction coding modes based on similarities between the current block and a corresponding prediction block. In some implementations, the complexity of searching each candidate prediction coding mode may be reduced by performing a directed refinement mode search. For example, metrics may be generated for a limited set of candidate block sizes, such as 16x16, 8x8, and 4x4, the error metric associated with each block size may be in descending order, and additional candidate block sizes, such as 4x8 and 8x4 block sizes, may be evaluated.

[0086] In some implementations, block-based coding efficiency may be improved by partitioning a current residual block into one or more transform partitions, which may be rectangular, including square, partitions for transform coding. In some implementations, video coding, such as video coding using transform partitioning, may include selecting a uniform transform partitioning scheme. For example, a current residual block, such as block 610, may be a 64x64 block and may be transformed without partitioning using a 64x64 transform.

[0087] Although not expressly shown in FIG. 6, a residual block may be transform partitioned using a uniform transform partitioning scheme. For example, a 64x64 residual block may be transform partitioned using a uniform transform partitioning scheme including four 32x32 transform blocks, using a uniform transform partitioning scheme including sixteen 16x16 transform blocks, using a uniform transform partitioning scheme including sixty-four 8x8 transform blocks, or using a uniform transform partitioning scheme including 256 4x4 transform blocks.

[0088] In some implementations, video coding, such as video coding using transform partitioning, may include identifying multiple transform block sizes for a residual block using multiform transform partition coding. In some implementations, multiform transform partition coding may include recursively determining whether to transform a current block using a current block size transform or by partitioning the current block and multiform transform partition coding each partition. For example, the bottom left block 610 shown in FIG. 6 may be a 64x64 residual block, and multiform transform partition coding may include determining whether to code the current 64x64 residual block using a 64x64 transform or to code the 64x64 residual block by partitioning the 64x64 residual block into partitions, such as four 32x32 blocks 620, and multiform transform partition coding each partition. In some implementations, determining whether to transform partition the current block may be based on comparing a cost for encoding the current block using a current block size transform to a sum of costs for encoding each partition using partition size transforms.

[0089] FIG. 7 is a diagram of an interpolation operation according to an implementation of this disclosure. In the example of FIG. 7, a 6-tap filter is used. This means that values for the sub-pixels or pixel locations 720, 722, 724 can be interpolated by applying an interpolation filter to the pixel locations 700-710. Pixel location 720 is a half-pixel location between the two pixel locations 704 and 706, while pixel locations 722 and 724 are quarterpixel locations between the two pixel locations 704 and 706. The pixel locations 722 and 724 may be referred to as a quarter-pixel and a three-quarter-pixel, respectively. Only sub-pixel locations between the two pixel locations 704 and 706 are shown in FIG. 7. However, subpixel values for other sub-pixel locations between the other full pixels of the line of pixels can be determined in a like manner. For example, a sub-pixel value between the two pixel locations 706 and 708 may be determined or generated by applying an interpolation filter to the pixels at pixel locations 702, 704, 706, 708, 710, and an integer pixel adjacent to the pixel location 710, if available.

[0090] To produce pixel values for the sub-pixel locations, an interpolation operation can be applied. In one example, the interpolation operation is performed using interpolation filters such as finite impulse response (FIR) filters. An interpolation filter may comprise a 4-tap filter, a 6-tap filter, an 8-tap filter, a 10-tap filter, a 12-tap, a 14-tap filter, or other size filter. An asymmetric interpolation filter may also be used with different number of taps on either side of the pixel being approximated. The taps of an interpolation filter weight spatially neighboring pixel values with coefficient values (i.e., weights of the interpolation filter) to generate a sub-pixel value. If an asymmetric interpolation filter is used, different weights maybe utilized on either side of the sub-pixel being approximated. For example, if there are two taps on a first side and four taps on a second side, and we have an 8-tap symmetric filter with weights (wO, wl, w2, w3, w4, w5, w6, w7), the first side 2-tap weights can be (w0+ wl+ w2, w3) while the second side 4-tap weights are (w4, w5, w6, w7). Alternatively, for the same example, weights from a 4-tap symmetric filter may be used on the first side and weights from an 8-tap symmetric filter may be used on the second side. Alternatively, asymmetric filters may be provided with their own tap weights based on the number of taps on either side. For example, tap weights for the first side may be different from tap weights for the second side. The neighboring pixel values can be values of integer pixels or values of intermediate pixels as further described below with respect to FIGS. 9 A and 9B. In general, the interpolation filter used to generate each sub-pixel value at different sub-pixel locations between two pixels is different (i.e., has different coefficient values).

[0091] The pixels at pixel locations 700-710 can be integer pixels in a reference frame of a reference block. For example, and referring to FIG. 8, the pixels at pixel locations 700-710 can be pixels of a reference frame 830 (for example, pixels of reference blocks 829, 831, 833). The pixels at pixel locations 720-724 can be intermediate pixels (such as pixel 908 of FIGS. 9A and 9B). Alternatively, the pixels at pixel locations 700-710 can be intermediate pixels (i.e., sub-pixel values) as described with respect to FIGS. 9A and 9B and the pixel locations 720-724 can be pixels of the prediction block (e.g., prediction pixels 958, 980, and 982 of FIG. 9B).

[0092] FIG. 8 is a diagram 800 of motion vectors representing full and sub-pixel motion according to implementations of this disclosure. In FIG. 8, several blocks 802, 804, 806, 808 of a current frame 810 are inter-predicted using pixels from the reference frame 830. In this example, the reference frame 830 is a reference frame in a video sequence including the current frame 810, such as the video stream 300 of FIG. 3.

[0093] The reference frame 830 is a reconstructed frame (i.e., one that has been encoded and decoded such as by the reconstruction path of FIG. 4 or output by the filtering unit 560 of FIG. 5) that has been stored in a so-called last reference frame buffer and is available for coding blocks of the current frame 810 in this example. Other (e.g., reconstructed) frames, or portions of such frames may also be available for inter-prediction. Other available reference frames may include a golden frame, which is another frame of the video sequence that may be selected (e.g., periodically) according to any number of techniques, and a constructed reference frame, which is a frame that is constructed from one or more other frames of thevideo sequence but is not shown as part of the decoded output, such as the output video stream 504 of FIG. 5.

[0094] The prediction block 832 for encoding the block 802 corresponds to a motion vector 812. A prediction block 834 for encoding the block 804 corresponds to a motion vector 814. A prediction block 836 for encoding the block 806 corresponds to a motion vector 816. Finally, a prediction block 838 for encoding the block 808 corresponds to a motion vector 818. Each of the blocks 802, 804, 806, 808 is inter-predicted using a single motion vector and hence a single reference frame in this example, but the teachings herein also apply to interprediction using more than one motion vector (such as bi-prediction using two different reference frames), where pixels from each prediction are combined in some manner to form a prediction block. The prediction blocks do not need to coincide with the blocks that may have been used to decode reference frame 830, such as reference block 829, 831, or 833.

[0095] FIGS. 9 A and 9B are diagrams of generating a prediction block using asymmetric interpolation according to implementations of this disclosure when a motion vector identifies a prediction block having pixels at sub-pixel locations in the reference frame. By contrast, if a motion vector points to an integer pixel location, the existing pixels from the reference frame may be used without interpolation.

[0096] FIGS. 9A and 9B illustrate generating a 4x4 prediction block 956 of FIG. 9B (including prediction pixels represented by the filled circles, such as prediction pixels 958, 980, and 982) based on reference pixels including, for example, reference pixels from a reference frame as depicted in FIG. 9A (represented by the empty circles, such as pixels 916, 918, 920, 922). The pixels depicted in FIG. 9A may be for example pixels from reference blocks 829, 831, 833, 835, 837, and 839 of FIG.8 and the prediction block 956 can be the prediction block 832 of FIG. 8. FIGS. 9A and 9B illustrate generating a 4x4 prediction block using one-dimensional 8-tap interpolation filters applied in the horizontal and the vertical direction. FIGS. 9A and 9B illustrate 4x4 blocks for illustration purposes only.Implementations of this disclosure may be utilized with other sized prediction blocks or other sized interpolation filters. For example, 16x16 blocks may be utilized and larger sized interpolation filters may be utilized (e.g., up to or exceeding 6 taps on either side of the subpixel being approximated).

[0097] FIG. 9A illustrates applying a first interpolation filter in a first direction (in this case, in the horizontal direction), to pixel values of the reference frame 905 (including the pixels of the reference area 907) to generate intermediate pixel values (at locations represented by the half-filled pixels, such as pixel 908). FIG. 9B illustrates applying a secondinterpolation filter in a second direction (in this case, in the vertical direction) to the intermediate pixel values to generate pixel values of the prediction block 956. However, the first direction can be a vertical direction and the second direction can be a horizontal direction. In other implementations directions other than vertical or horizontal may be used and / or more or less than two directions may be used.

[0098] In each of FIG. 9A and FIG. 9B, a reference area 907 is shown indicating what pixels are available to the decoder for interpolation. The reference area may, for example, be defined in a video decoding standard according to which the current video is being encoded or decoded. In the example shown in FIG. 9A and FIG. 9B, the reference area indicates that one integer pixel is available above and to the left of the prediction block and two integer pixels are available to the right and below the prediction block. The reference area depicted in FIGS. 9A and 9B is for illustrative purposes only and the actual reference area and / or number of pixels available in each direction outside of the prediction area may differ depending on the implementation. For example, the number of pixels that may be available may instead be 3 pixels above and to the left of the prediction block and 4 pixels below and to the right of the prediction block. The number of available pixels may vary depending on where exactly the prediction block boundaries are established. In some implementations according to this disclosure, a first video coding standard may establish a reference area providing 3 or 4 pixels adjacent to the prediction block, such as may be required for an 8-tap symmetric filter and a second video coding standard may establish a reference area that does not exceed the reference area of the first video coding standard while also supporting a 12-tap or 14-tap symmetric interpolation filter and asymmetric interpolation filters having up to 6-taps or 7- taps on either side of the pixel being interpolated.

[0099] Referring now to FIG. 9A, the reference pixels can be integer pixels within a reference frame 905 (shown as unfilled circles). The integer pixels are arranged along a first direction and a second direction (i.e., x- and y-axes or y- and x-axes). The first direction can be the horizontal or vertical direction. The second direction is the other direction (i.e., the vertical direction or the horizontal direction).

[0100] To generate the 4x4 prediction block 956 of FIG. 9B, intermediate pixel values (as shown in FIG. 9A) are used. For example, to generate the prediction pixel 958 using an asymmetric filter, two intermediate pixels above the prediction pixel 958 (namely, pixels 964 and 966) and four intermediate pixels below the prediction pixel 958 (namely, pixels 908, 970, 972, and 974) are used. Generating an intermediate pixel, such as the pixel 908 of FIG. 9A, using an asymmetric interpolation filter requires two integer pixels to the left of the pixel908 (namely, pixels 914, and 916) and four integer pixels to the right of the pixel 908 (namely, pixels 918, 920, 922, and 924). In the example shown in FIGS. 9 A and 9B, the number of taps to the left and above respectively are constrained by the number of pixels available within the reference area between the pixel being interpolated (e.g., pixel 908 or pixel 958) and the edge of the reference area. In other implementations according to this disclosure, a different number of taps may be utilized based on a different constraint, such as the block boundary or a reference area that allows for more pixels outside the prediction block to be utilized.

[0101] In the provided example, to generate an intermediate pixel value, six (6) multiplication operations are required. For example, given an asymmetric interpolation filter having two taps on one side and four taps on the other side (i.e., the filter used to generate the intermediate pixels of FIG. 9A) has the weights (yvl, w2, w3, w4, w5, w6), then pixel 908 can be calculated using equation (1): pixel 908 = (pixel 914)*m / + (pixel 916)*w2 + (pixel 918)*w3 + (1)(pixel 920) *w4 + (pixel 922)*w5 + (pixel 924) Avd.

[0102] FIG. 10 is a flow diagram of an example implementation 1000 of motion compensation using an asymmetric interpolation filter according to implementations of this disclosure.

[0103] At step 1010, a motion vector indicating a displacement to a prediction block in a reference frame is decoded, for example as further described with respect to FIGS. 4, 6, 8, 9 A, and / or 9B. The displacement indicated by the motion vector is to a sub-pixel location within the reference frame. For example, with respect to FIG. 5, the motion vector may be decoded by entropy decoding unit 510.

[0104] At step 1020, an intermediate value is interpolated at a first location using an asymmetric interpolation filter. The interpolation and the asymmetric interpolation filter may be as described previously including with respect to FIG. 9A. For example, with respect to FIG. 5, the interpolation may be performed by intra / inter prediction unit 540.

[0105] At step 1030, a sub-pixel value is interpolated at a second location using an asymmetric interpolation filter. The interpolation and the asymmetric interpolation filter may be as described previously including with respect to FIG. 9B. The asymmetric interpolation filter used in step 1030 may be the same or may be different than the asymmetric interpolation filter used in step 1020. For example, with respect to FIG. 5, the interpolation may be performed by intra / inter prediction unit 540.

[0106] At step 1040, a block is decoded using the interpolated sub-pixel value. For- l-example, with respect to FIG. 5, the sub-pixel value may be used by reconstruction unit 550.

[0107] At step 1050, a decoded video including the decoded block from step 1040 is displayed. For example, with respect to FIG. 5, the video is displayed using output video stream 504.

[0108] The steps of example implementation 1000 may vary depending on the implementation. For example, in an encoder implementation, steps 1010, 1040 and 1050 may be omitted. In an encoder implementation, step 1020 and 1030 may be performed, for example with respect to FIG. 4, by intra / inter prediction unit 410.

[0109] In some implementations, step 1020 may be omitted and interpolation may be performed along a single direction. In some implementations, asymmetric interpolation may be performed in a first direction and symmetric interpolation may be performed in a second direction.

[0110] In some implementations, the asymmetric interpolation filter used in step 1020 or step 1030 has a first number of taps on a first side of the first location and a second number of taps on a second side of the first location and a difference between the first number and the second number is two or greater. In some implementations, the first number of taps is determined based on a number of pixels between the first location and a block boundary. In some implementations, the first number of taps is determined based on a distance between the first location and the edge of a reference area. In some implementations, the tap weights for the first side are different from the tap weights for the second side. In some implementations, the first number of taps is determined based on a difference between a motion vector for a first block and a motion vector for a second block.

[0111] In some implementations, the asymmetric interpolation filter used in step 1020 or step 1030 is performed according to a requirement of a first video decoding standard and the reference area is determined based on a requirement of a second video decoding standard.

[0112] In some implementations, the asymmetric interpolation filter used in step 1020 or step 1030 is a linear filter that operates on a row or column of pixels.

[0113] FIG. 11 is a diagram of a block and a reference area according to implementations of this disclosure.

[0114] FIG. 11 demonstrates that a reference area for a block may vary according to dimensions a and b. Dimensions a and b may be set in certain implementations according to the maximum number of taps that may be utilized in an interpolation filter. For example, a = n_tap / 2 - 1, and b = n_tap / 2 where n_tap is the number of filter taps. The pixels in the reference area may be fetched, for example by a hardware decoder, to enable the interpolationof sub-pixels within the block. A hardware decoder may be implemented according to values of a and b that permit decoding of a certain set of video coding standards, which may include those finalized prior to the priority date of this disclosure. For example, such hardware decoder implementations may support a reference area based on a=3 and b=4.

[0115] If it is desirable for a decoder to utilize a larger number of filter taps but fetch fewer pixels (e.g., as supported by an existing hardware decoder implemented based on a reference area according to a=3 and b=4), one workaround is to pad needed pixels around the reference area to avoid fetching a larger area. But this would increase the decoder complexity and reduce the efficacy of the longer filter. Instead, an asymmetric interpolation filter may be used according to implementations of this disclosure to permit a smaller reference area than otherwise would be required. For example, a reference area based on an 8-tap filter may be used while permitting the use of a 12-tap or 14-tap filter at certain areas within the block and asymmetric interpolation filters in other areas within the block (for example, an asymmetric filter with 3-7 taps on one side and 7 taps on the other side).

[0116] FIG. 12 is a diagram of available pixels used to interpolate a sub-pixel value within a reference area according to implementations of this disclosure.

[0117] FIG. 12 is an example of a situation where an asymmetric interpolation filter may be utilized. A filter formula such as the below formula may be used:

[0118] In the forgoing formula, y is the interpolated sub-pixel value, p is the available nearby pixels, and f is the filter coefficient. The (L + R)-tap asymmetric interpolation filter consists of 2 parts: the first part is the L-tap filter on the left side, and the second part is the R-tap filter on the right side. In this example (for a filter with a maximum of 14 taps), R is 7, and L is 4 since there are only 4 pixels available on the left side. The filter coefficients for left and right filters are designed based on the available taps to achieve good frequency response for accurate interpolation results. The same boundary constraint may apply to all sides of the reference blocks, including left and right sides, and above and bottom sides.

[0119] In some implementations, the filter coefficient may change for the position closest to the reference area, when not all the filter coefficients are utilized. For example, a 14-tap filter may be provided having coefficients of { fO, fl, f2, f3, f4, f5, f6, f7, f8, f9, fl 0, fll, fl 2, fl3 }, where coefficients fO to f6 correspond to the left side and coefficients f7 to fl3correspond to the right side. In the event where only 4 taps are used for the left side (e.g., according to the example shown in FIG. 12), the filter coefficients actually utilized may, for example, be { (fO + fl + f2 + f3 ), f4, f5, f6, f7, f8, f9, flO, fll, fl2, fl 3 }, where the filter coefficient for the pixel position next to the reference area boundary is replaced with (fO + fl + f2 +f3 ) instead of / 5. To further generalize this example, in such an implementation, the unused filter coefficients may be combined with the filter coefficient for the position closest to the edge of the reference area.

[0120] In some implementations, an existing hardware decoder implementation may be implemented to support an 8-tap filter provided for by an existing video coding standard(e.g., a first video coding standard), such as the 8-tap sharp filter provided by AVI, which may be defined as follows:DECLARE_ALIGNED (256, static const intl6_t, avl_sub_pel_f ilters_8sharp [SUBPEL_SHIFTS] ){ 0, 0, 0, 128, 0, 0, 0, 0 },{ -2, 2, -6, 126, 8, -2, 2, 0 },{ -2, 6, -12, 124, 16, -6, 4, -2 },{ -2, 8, -18, 120, 26, -10, 6, -2 },{ -4, 10, -22, 116, 38, -14, 6, -2 },{ -4, 10, -22, 108, 48, -18, 8, -2 },{ -4, 10, -24, 100, 60, -20, 8, -2 },{ -4, 10, -24, 90, 70, -22, 10, -2 },{ -4, 12, -24, 80, 80, -24, 12, -4 },{ -2, 10, -22, 70, 90, -24, 10, -4 },{ -2, 8, -20, 60, 100, -24, 10, -4 },{ -2, 8, -18, 48, 108, -22, 10, -4 },{ -2, 6, -14, 38, 116, -22, 10, -4 },{ -2, 6, -10, 26, 120, -18, 8, -2 },{ -2, 4, -6, 16, 124, -12, 6, -2 },{ 0, 2, -2, 8, 126, -6, 2, -2 }

[0121] In some implementations, an improved 12-tap sharp filter, an improved 14-tap sharp filter (or both, or combinations thereof) may be provided by an improved video coding standard (e.g., a second video coding standard), which may be defined as follows:DECLARE_ALIGNED (256, static const intl6_t, avl_sub_pel_f ilters_12sharp [SUBPEL_SHIFTS]

[0012] ) = { { 0, 0, 0, 0, 0, 128, 0, 0, 0, 0, 0, 0, 0 }, { -1, 1, -2, 4, -7, 127, 9, -4, 2, -2, 1, 0 },{ -1, 2, -4, 7, -13, 124, 18, -8, 5, -3, 2, -1 },{ -1, 4, -6, 9, -18, 120, 28, -12, 7, -5, 3, -1 },{ -1, 4, -7, 11, -22, 115, 38, -16, 9, -6, 4, -1 },{ -2, 5, -8, 13, -25, 108, 49, -19, 11, -7, 5, -2 },{ -2, 5, -9, 14, -26, 100, 60, -22, 13, -8, 5, -2 },15, -27, 91, 71, -25, 14, -9, 5, -2 },14, -26, 81, 81, -26, 14, -9, 6, -2 },14, -25, 71, 91, -27, 15, -9, 6, -2 },13, -22, 60, 100, -26, 14, -9, 5, -2 }, 11, -19, 49, 108, -25, 13, -8, 5, -2 }, 9, -16, 38, 115, -22, 11, -7, 4, -1 },7, -12, 28, 120, -18, 9, -6, 4, -1 }, 5, -8, 18, 124, -13, 7, -4, 2, -1 }, , -4, 9, 127, -7, 4, -2, 1, -1 }DECLARE_ALIGNED (256, static const int 16_t avl_sub_pel_f ilters_14sh rp [SUBPEL_SHIFTS ]

[0014] ) { 0 0, 0, 0, 0 0 , 128 , 0, 0, 0, 0, 0, 0 { 0 -1 1 -2, 4, -7, 127, 9, -4 2, -2 1, 0, 0 }, { 0 -1 2 -4, 7, -13, 124, 18, -8, 5, -3, 2, -1, 0 { 1 -2 4 -6, 9, -18, 120, 28, -12, 7, -5, 3, -2, 1 }, { 1 -2 4 -7, 11 , -22 , 115 , 38, -16 , 9 -6 4 -2, 1 1, { 1 -3 5 -8, 13 , -25 , 108 , 49, -19 , 11 , -7 , 5 , -3 , 1 } { 1 -3 5 -9, 14 , -26 , 100 , 60, -22 , 13 , -8 , 5 , -3 , 1 } { 1 -3 6 -9, 15 , -27 , 91, 71, -25, 14, -9, 5, -3, 1 1, { 1 -3 6 -9, 14 , -26 , 81, 81, -26, 14, -9, 6, -3, 1 1, { 1 -3 5 -9, 14 , -25 , 7^, 91, -27, 15, -9, 6, -3, 1 1, { 1 -3 5 -8, 13 , -22 , 60, 100, -26 , 14 , -9 , 5 , -3 , 1 } { 1 -3 5 -7, 11 , -19 , 49, 108, -25 , 13 , -8 , 5 , -3 , 1 } { 1 -2 4 -6, 9, -16 38, 115, -22, 11 -7 4 -2, 1 1, { 1 -2 3 -5, 7, -12 28, 120, -18, 9, -6, 4 -2, 1 1, { 0 -1 2 -3, 5, -8, 18 , 124 -13, 7, -4 2, -1, 0 { 0 0, 1, -2, 2 -4 9, 127, -7, 4 -2 1 -1

[0122] The improved 14-tap sharp filter may be utilized asymmetrically, such as described in implementations above. In the frequency domain, the 14-tap filter is a closer approximation of an ideal low-pass filter as compared to the 8-tap filter, which can result in better performance in the pass band and the stop band.

[0123] An existing video coding standard may support the selection of one of multiple available filters up to a maximum of an 8-tap filter, such as the following filters supported by AVI:EIGHTTAP_REGULAR, / / 6-tap regular filter EIGHTTAP_SMOOTH, / / smooth filter MULTITAP_SHARP, / / 8-tap sharp filter

[0124] In some implementations according to this disclosure, an improved video coding standard may support the selection of one of multiple available filters up to a maximum of a 14-tap filter, such as the following filters (in some implementations, a 12-tap filter may be utilized instead for the MULTITAP_SHARP filter):EIGHTTAP_REGULAR, / / 8-tap sharp filter EIGHTTAP_SMOOTH, / / smooth filter MULTITAP_SHARP , / / 14-tap sharp filter

[0125] Such an implementation utilizing a 14-tap filter utilized asymmetrically such as described with respect to certain implementations of this disclosure may be able to achieve peak signal to noise ration (PSNR) for certain video sequences of 0.16%-.024% with a marginal increase in encoder time of 1% and decoder time of 2%. Deviations from these experimental results in coding effectiveness and efficiency are expected depending on the specific implementation utilized, the specific methodology utilized to measure performance, and the implementation(s) compared against.

[0126] According to an aspect of the disclosure, there is provided methods for motion compensation. The method includes interpolating a sub-pixel value at a first location using a first asymmetric interpolation filter. The filter has a first number of taps on a first side of the first location and a second number of taps on a second side of the first location. The difference between the first number and the second number is two or greater. This method improves motion compensation accuracy when a reference area is constrained by using an asymmetric filter that can adapt to spatial constraints near reference area boundaries.

[0127] In implementations, the first asymmetric interpolation filter can be a linear filter that operates on a row or column of pixels. This has the technical effect of simplifying computations while still providing effective interpolation.

[0128] In implementations, the first number of taps can be determined based on a number of pixels between the first location and a block boundary. This allows the filter to adapt to spatial constraints, improving interpolation accuracy near block edges.

[0129] In implementations, the first number of taps can be determined based on a distance between the first location and an edge of a reference area. This enables the filter to optimize interpolation based on an available reference area.

[0130] In implementations, interpolating the sub-pixel value can be performed according to a requirement of a first video decoding standard and the reference area can be determined based on a requirement of a second video decoding standard. This allows for re-use of components, such as hardware blocks, between different video standards while also allowing for an improvement in interpolation quality.

[0131] In implementations, tap weights for the first side can be different from tap weights for the second side. This allows for further optimization of the asymmetric filter.

[0132] In implementations, the first number of taps can be determined based on adifference between a motion vector for a first block and a motion vector for a second block. This enables the filter to adapt to local motion characteristics, improving interpolation accuracy.

[0133] In implementations, the method can include decoding a third block in a current frame. Decoding the third block can include decoding a motion vector for the third block, where the motion vector indicates a displacement to a prediction block in a reference frame. The method can also include determining a pixel value of the third block based on the subpixel value.

[0134] In implementations, the method can include displaying a decoded video including the decoded third block.

[0135] In implementations, the method can include interpolating an intermediate value at a second location using a second asymmetric interpolation filter. The second filter can have a third number of taps on a first side of the second location and a fourth number of taps on a second side of the second location. The difference between the third number and the fourth number can be two or greater. The sub-pixel value can be interpolated using the intermediate value. This allows for multi-stage interpolation.

[0136] According to another aspect of the disclosure, there is provided a method for motion compensation. The method includes interpolating a sub-pixel value at a first location using a first asymmetric interpolation filter. The filter has a first number of taps on a first side of the first location and a second number of taps on a second side of the first location. The first number of taps depends on a number of pixels between the first location and an edge of a reference area. This method allows for adaptive interpolation based on an available reference area, improving motion compensation accuracy.

[0137] In implementations, the first asymmetric interpolation filter can be a linear filter that operates on a row or column of pixels. This simplifies computations while maintaining effective interpolation.

[0138] In implementations, the difference between the first number and the second number can be two or greater. This allows for significant asymmetry in the filter, enabling better adaptation to reference area constraints.

[0139] In implementations, the edge of the reference area can be outside a block in which the first location is located. This allows the filter to consider a context greater than the block when performing interpolation.

[0140] In implementations, interpolating the sub-pixel value can be performed according to a requirement of a first video decoding standard and the reference area can be determinedbased on a requirement of a second video decoding standard. This allows for re-use of components, such as hardware blocks, between different video standards while also allowing for an improvement in interpolation quality.

[0141] In implementations, tap weights for the first side can be different from tap weights for the second side. This allows for further optimization of the asymmetric filter based on local image characteristics.

[0142] In implementations, the first number of taps can be based on a difference between a motion vector for a first block and a motion vector for a second block. This enables the filter to adapt to local motion characteristics, improving interpolation accuracy.

[0143] In implementations, the method can include decoding a third block in a current frame. Decoding the third block can include decoding a motion vector for the third block, where the motion vector indicates a displacement to a prediction block in a reference frame. The method can also include determining a pixel value of the third block based on the subpixel value.

[0144] In implementations, the method can include displaying a decoded video including the decoded third block.

[0145] In implementations, the method can include interpolating an intermediate value at a second location using a second asymmetric interpolation filter. The second filter can have a third number of taps on a first side of the second location and a fourth number of taps on a second side of the second location. The third number of taps can depend on a number of pixels between the first location and an edge of a reference area. This allows for multi-stage interpolation with adaptive filter sizes.

[0146] According to another aspect of the disclosure, a video decoding apparatus may implement aspects of one or more of the foregoing methods. According to another aspect of the disclosure, a video encoding apparatus may implement aspects of one or more of the foregoing methods. These apparatuses provide hardware implementations of encoding and decoding utilizing the foregoing methods.

[0147] According to another aspect of the disclosure, a non-transitory computer readable medium includes instructions which, when executed by a computer, causes the computer to carry out the steps of one or more of the foregoing methods. According to another aspect of the disclosure, a computer program product includes instructions which, when the program is executed by a computer, causes the computer to carry out the steps of one or more of the foregoing methods. The medium including instructions and the computer program product allows for distribution and installation of software implementing the foregoing methods.

[0148] According to another aspect of the disclosure, a non-transitory computer readable medium includes an encoded bitstream that was encoded using one or more of the foregoing methods or is decodable using one or more of the foregoing methods. According to another aspect of the disclosure, a computer media product includes an encoded bitstream encoded using one or more of the foregoing methods or that is decodable using one or more of the foregoing methods. The medium including the encoded bitstream and the computer media product provides efficient and compressed storage and distribution of video content utilizing the foregoing methods.

[0149] As used herein, the terms “optimal”, “optimized”, “optimization”, or other forms thereof, are relative to a respective context and are not indicative of absolute theoretic optimization unless expressly specified herein.

[0150] As used herein, the term “set” indicates a distinguishable collection or grouping of zero or more distinct elements or members that may be represented as a one-dimensional array or vector, except as expressly described herein or otherwise clear from context.

[0151] The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an embodiment” or “one embodiment” or “an implementation” or “one implementation” throughout is not intended to mean the same embodiment or implementation unless described as such. As used herein, the terms “determine” and “identify”, or any variations thereof, includes selecting, ascertaining, computing, looking up, receiving, determining, establishing, obtaining, or otherwise identifying or determining in any manner whatsoever using one or more of the devices shown in FIG. 1.

[0152] Further, for simplicity of explanation, although the figures and descriptions herein may include sequences or series of steps or stages, elements of the methods disclosed hereincan occur in various orders and / or concurrently. Additionally, elements of the methods disclosed herein may occur with other elements not explicitly presented and described herein. Furthermore, one or more elements of the methods described herein may be omitted from implementations of methods in accordance with the disclosed subject matter.

[0153] The implementations of the transmitting computing and communication device 100A and / or the receiving computing and communication device 100B (and the algorithms, methods, instructions, etc., stored thereon and / or executed thereby) can be realized in hardware, software, or any combination thereof. The hardware can include, for example, computers, intellectual property (IP) cores, application- specific integrated circuits (ASICs), programmable logic arrays, optical processors, programmable logic controllers, microcode, microcontrollers, servers, microprocessors, digital signal processors or any other suitable circuit. In the claims, the term “processor” should be understood as encompassing any of the foregoing hardware, either singly or in combination. The terms “signal” and “data” are used interchangeably. Further, portions of the transmitting computing and communication device 100A and the receiving computing and communication device 100B do not necessarily have to be implemented in the same manner.

[0154] Further, in one implementation, for example, the transmitting computing and communication device 100A or the receiving computing and communication device 100B can be implemented using a computer program that, when executed, carries out any of the respective methods, algorithms and / or instructions described herein. In addition, or alternatively, for example, a special purpose computer / processor can be utilized which can contain specialized hardware for carrying out any of the methods, algorithms, or instructions described herein.

[0155] The transmitting computing and communication device 100A and receiving computing and communication device 100B can, for example, be implemented on computers in a real-time video system. Alternatively, the transmitting computing and communication device 100A can be implemented on a server and the receiving computing and communication device 100B can be implemented on a device separate from the server, such as a hand-held communications device. In this instance, the transmitting computing and communication device 100A can encode content using an encoder 400 into an encoded video signal and transmit the encoded video signal to the communications device. In turn, the communications device can then decode the encoded video signal using a decoder 500. Alternatively, the communications device can decode content stored locally on the communications device, for example, content that was not transmitted by the transmittingcomputing and communication device 100A. Other suitable transmitting computing and communication device 100A and receiving computing and communication device 100B implementation schemes are available. For example, the receiving computing and communication device 100B can be a generally stationary personal computer rather than a portable communications device and / or a device including an encoder 400 may also include a decoder 500.

[0156] Further, all or a portion of implementations can take the form of a computer program product accessible from or embodied on, for example, a tangible (non-transitory) computer-usable or computer-readable medium. A computer-usable or computer-readable medium can be any device that can, for example, tangibly contain, store, communicate, or transport the program for use by or in connection with any processor. The medium can be, for example, an electronic, magnetic, optical, electromagnetic, or a semiconductor device. Other suitable mediums are also available.

[0157] For example, a processor may be configured to perform executed instructions stored in the memory (e.g., computer readable medium) to perform techniques embodied in the instructions. For example, a non-transitory computer-readable storage medium may include executable instructions that, when executed by a processor, facilitate performance of operations corresponding to techniques described in this disclosure.

[0158] Further, all or a portion of implementations described herein may be utilized to generate or consume an encoded bitstream product (e.g., such as the compressed bitstream 404). For example, a non-transitory computer-readable storage medium may store an encoded bitstream that was encoded by or is decodable using techniques described in this disclosure. For example, a computer media product in the form of an encoded bitstream may be accessible from or embodied on, for example, a tangible (non-transitory) computer-usable or computer-readable medium.

[0159] It will be appreciated that aspects can be implemented in any convenient form. For example, aspects may be implemented by appropriate computer programs which may be carried on appropriate carrier media which may be tangible carrier media (e.g., disks) or intangible carrier media (e.g. communications signals). Aspects may also be implemented using suitable apparatus which may take the form of programmable computers running computer programs arranged to implement the methods and / or techniques disclosed herein. Aspects can be combined such that features described in the context of one aspect may be implemented in another aspect.

[0160] The above-described implementations have been described to allow easyunderstanding of the application are not limiting. On the contrary, the application covers various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation to encompass all such modifications and equivalent structure as is permitted under the law.

Claims

CLAIMSWhat is claimed is:

1. A method for motion compensation, comprising: interpolating a sub-pixel value at a first location using a first asymmetric interpolation filter having a first number of taps on a first side of the first location and a second number of taps on a second side of the first location, wherein a difference between the first number and the second number is two or greater.

2. The method of claim 1, wherein the first asymmetric interpolation filter is a linear filter that operates on a row or column of pixels.

3. The method of claim 1 or 2, wherein the first number of taps is determined based on a number of pixels between the first location and a block boundary.

4. The method of one of claim 1 or claim 2, wherein the first number of taps is determined based on a distance between the first location and an edge of a reference area.

5. The method of claim 4, wherein interpolating the sub-pixel value is performed according to a requirement of a first video decoding standard and the reference area is determined based on a requirement of a second video decoding standard.

6. The method of any one of claims 1 to 5, wherein tap weights for the first side are different from tap weights for the second side.

7. The method of any one of claims 1 to 6, wherein the first number of taps is determined based on a difference between a motion vector for a first block and a motion vector for a second block.

8. The method of any one of claims 1 to 7, comprising: decoding a third block in a current frame, wherein decoding the third block includes: decoding a motion vector for the third block, the motion vector indicating a displacement to a prediction block in a reference frame; and determining a pixel value of the third block based on the sub-pixel value.

9. The method of claim 8, comprising: displaying a decoded video including the decoded third block.

10. The method of any one of claims 1 to 9, comprising: interpolating an intermediate value at a second location using a second asymmetric interpolation filter having a third number of taps on a first side of the second location and a fourth number of taps on a second side of the second location, wherein a difference between the third number and the fourth number is two or greater, wherein the sub-pixel value is interpolated using the intermediate value.

11. A method for motion compensation, comprising: interpolating a sub-pixel value at a first location using a first asymmetric interpolation filter having a first number of taps on a first side of the first location and a second number of taps on a second side of the first location, wherein the first number of taps depends on a number of pixels between the first location and an edge of a reference area.

12. The method of claim 11, wherein the first asymmetric interpolation filter is a linear filter that operates on a row or column of pixels.

13. The method of claim 11 or 12, wherein a difference between the first number and the second number is two or greater.

14. The method of any one of claims 11 to 13, wherein the edge of the reference area is outside a block in which the first location is located.

15. The method of any one of claims 11 to 14, wherein interpolating the sub-pixel value is performed according to a requirement of a first video decoding standard and the reference area is determined based on a requirement of a second video decoding standard.

16. The method of any one of claims 11 to 15, wherein tap weights for the first side are different from tap weights for the second side.

17. The method of any one of claims 11 to 16, wherein the first number of taps is based on a difference between a motion vector for a first block and a motion vector for a second block.

18. The method of any one of claims 11 to 17, comprising: decoding a third block in a current frame, wherein decoding the third block includes: decoding a motion vector for the third block, the motion vector indicating a displacement to a prediction block in a reference frame; and determining a pixel value of the third block based on the sub-pixel value.

19. The method of claim 18, comprising: displaying a decoded video including the decoded third block.

20. The method of any one of claims 11 to 19, comprising: interpolating an intermediate value at a second location using a second asymmetric interpolation filter having a third number of taps on a first side of the second location and a fourth number of taps on a second side of the second location, wherein the third number of taps depends on a number of pixels between the first location and an edge of a reference area.

21. A video decoding apparatus implementing the method of any one of claims 1 to 20.

22. A video encoding apparatus implementing the method of any one of claims 1 to 20.

23. A non-transitory computer readable medium comprising instructions which, when executed by a computer, cause the computer to carry out the method of any one of claims 1 to 20.

24. A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method of any one of claims 1 to 20.

25. A non-transitory computer readable medium comprising an encoded bitstream that was encoded using the method of any one of claims 1 to 20 or is decodable using the method of any one of claims 1 to 20.

26. A computer media product comprising an encoded bitstream encoded using the method of any one of claims 1 to 20 or that is decodable using the method of any one of claims 1 to 20.

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