Pixel circuit, driving method, display panel and display apparatus

Abstract

A pixel circuit, a driving method, a display panel and a display apparatus. The pixel circuit comprises: a light-emitting device (L), wherein a first electrode of the light-emitting device (L) is coupled to a first power supply end (VSS); and a driving circuit (100), which is coupled to a second electrode of the light-emitting device (L), is configured to drive, on the basis of a data voltage signal, the light-emitting device (L) to emit light, and is configured to control the voltage of the second electrode of the light-emitting device (L) to be less than the voltage of the first electrode of the light-emitting device (L), and output a detection signal on the basis of the light-emitting device (L) once having controlled the voltage of the second electrode of the light-emitting device (L) to be less than the voltage of the first electrode of the light-emitting device (L).

Description

Pixel circuit, driving method, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, a display panel, and a display device. Background Art

[0002] LED displays, as display devices, are ubiquitous in everyday applications. Their current and long-term application prospects can be categorized into three categories: large outdoor or indoor spliced ​​displays, TV products, and wearable products. For display scenarios such as large-scale outdoor or indoor displays, optical touch is more convenient for screen control. This involves illuminating the selected location with a laser pointer, similar to a mouse. Therefore, light intensity detection is required to locate the selected location for remote interaction, or optical interaction. This same optical touch function can also be used for interaction with large-scale TV products. Secondly, rising temperature causes changes in the brightness of LED displays, necessitating brightness attenuation detection to compensate for this. This is also crucial for wearable products, such as mobile phones and watches. Finally, fingerprint detection is required for display scenarios in wearable products such as mobile phones and watches.

[0003] Summary of the Invention

[0004] The pixel circuit provided by the embodiment of the present disclosure includes:

[0005] a light emitting device, wherein a first electrode of the light emitting device is coupled to a first power supply terminal;

[0006] The driving circuit is coupled to the second electrode of the light-emitting device and is configured to drive the light-emitting device to emit light according to a data voltage signal, and is configured to control the voltage of the second electrode of the light-emitting device to be lower than the voltage of the first electrode of the light-emitting device, and output a detection signal according to the light-emitting device when the voltage of the second electrode of the light-emitting device is controlled to be lower than the voltage of the first electrode of the light-emitting device.

[0007] In some possible implementations, the driving circuit includes: a driving transistor, an initialization circuit, a data transmission circuit, a first control circuit, a second control circuit, and a third control circuit;

[0008] The working process of the pixel circuit includes: a reset phase, a detection phase and a light emitting phase;

[0009] The initialization circuit is coupled to the second electrode of the light-emitting device and the gate of the driving transistor, and is configured to provide a signal from a first initialization signal terminal to the gate of the driving transistor in response to a signal from a first reset signal terminal during the reset phase, and provide a signal from a second initialization signal terminal to the second electrode of the light-emitting device in response to a signal from a second reset signal terminal;

[0010] The data transmission circuit is coupled to the first electrode of the driving transistor and is configured to connect the first electrode of the driving transistor to the data transmission signal terminal in response to the signal of the first scanning signal terminal during the detection phase;

[0011] The first control circuit is coupled to the driving transistor, the second electrode of the light-emitting device, and a first node, and is configured to provide a signal from the second power supply terminal to the first electrode of the driving transistor in response to a signal from the light-emitting control signal terminal during the light-emitting phase, and to conduct the second electrode of the driving transistor to the second electrode of the light-emitting device in response to a signal from the first node during the detection phase and the light-emitting phase;

[0012] The second control circuit is coupled to the second electrode and the gate of the driving transistor and is configured to connect the second electrode and the gate of the driving transistor in response to a signal at the second scanning signal terminal during the detection phase;

[0013] The third control circuit is coupled to the first node and is configured to provide a signal from the pulse control signal terminal or a signal from the light emitting control signal terminal to the first node during the reset phase, the detection phase, and the light emitting phase.

[0014] In some possible embodiments, the data transmission circuit includes: a first transistor; the gate of the first transistor is coupled to the first scanning signal end, the first electrode of the first transistor is coupled to the first electrode of the driving transistor, and the second electrode of the first transistor is coupled to the data transmission signal end.

[0015] In some possible implementations, the light-emitting control signal terminal is coupled to the first node.

[0016] In some possible implementations, the operation process of the pixel circuit further includes: a compensation stage;

[0017] The data transmission circuit includes: a data writing circuit and a detection circuit;

[0018] The data writing circuit is coupled to the first electrode of the driving transistor and is configured to provide the data voltage signal of the data transmission signal terminal to the first electrode of the driving transistor in response to the signal of the third scanning signal terminal during the compensation phase;

[0019] The detection circuit is coupled to the first electrode of the driving transistor and is configured to provide the signal of the second power supply terminal to the second node in response to the signal of the first electrode of the driving transistor during the detection phase, and to connect the second node to the detection signal terminal in response to the signal of the fourth scanning signal terminal, and output the detection signal through the detection signal terminal.

[0020] In some possible implementations, the detection circuit includes: a second transistor and a third transistor;

[0021] The gate of the second transistor is coupled to the first electrode of the driving transistor, the first electrode of the second transistor is coupled to the second power supply terminal, and the second electrode of the second transistor is coupled to the second node;

[0022] A gate of the third transistor is coupled to the fourth scan signal terminal, a first electrode of the third transistor is coupled to the second node, and a second electrode of the third transistor is coupled to the detection signal terminal.

[0023] In some possible embodiments, it further includes: a potential selection circuit, coupled to the driving circuit, configured to respond to the signal of the fifth scanning signal terminal in the reset phase and the detection phase to provide the signal of the third initialization signal terminal to the driving circuit, and respond to the signal of the sixth scanning signal terminal in the compensation phase and the light-emitting phase to provide the signal of the second power supply terminal to the driving circuit.

[0024] In some possible implementations, the potential selection circuit includes: a fourth transistor and a fifth transistor;

[0025] The gate of the fourth transistor is coupled to the fifth scan signal terminal, the first electrode of the fourth transistor is coupled to the driving circuit, and the second electrode of the fourth transistor is coupled to the third initialization signal terminal;

[0026] A gate of the fifth transistor is coupled to the sixth scan signal terminal, a first electrode of the fifth transistor is coupled to the second power supply terminal, and a second electrode of the fifth transistor is coupled to the driving circuit.

[0027] In some possible implementations, the operation process of the pixel circuit further includes: a compensation stage;

[0028] The data transmission circuit includes: a data writing circuit, a detection circuit and a conduction control circuit;

[0029] The data writing circuit is coupled to the first electrode of the driving transistor and is configured to provide the data voltage signal of the data transmission signal terminal to the first electrode of the driving transistor in response to the signal of the seventh scanning signal terminal during the detection phase and the compensation phase;

[0030] The detection circuit is coupled to the second electrode of the driving transistor and is configured to provide the signal of the second power terminal to the third node in response to the signal of the second electrode of the driving transistor during the detection phase, and to connect the third node to the detection signal terminal in response to the signal of the eighth scanning signal terminal, and output the detection signal through the detection signal terminal;

[0031] The conduction control circuit is coupled to the second electrode of the driving transistor and the second electrode of the light-emitting device, and is configured to conduct the second electrode of the driving transistor and the second electrode of the light-emitting device in response to the signal of the ninth scanning signal terminal during the detection phase.

[0032] In some possible implementations, the detection circuit includes: a sixth transistor and a seventh transistor;

[0033] The gate of the sixth transistor is coupled to the second electrode of the driving transistor, the first electrode of the sixth transistor is coupled to the second power supply terminal, and the second electrode of the sixth transistor is coupled to the third node;

[0034] A gate of the seventh transistor is coupled to the eighth scan signal terminal, a first electrode of the seventh transistor is coupled to the third node, and a second electrode of the seventh transistor is coupled to the detection signal terminal.

[0035] In some possible embodiments, the conduction control circuit includes: an eighth transistor; the gate of the eighth transistor is coupled to the ninth scanning signal terminal, the first electrode of the eighth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the eighth transistor is coupled to the second electrode of the light-emitting device.

[0036] In some possible implementations, the driving circuit includes: a driving transistor, an initialization circuit, a detection circuit, a potential selection circuit, a data writing circuit, a first control circuit, and a second control circuit;

[0037] The working process of the pixel circuit includes: a reset stage, a detection stage, a compensation stage and a light emitting stage;

[0038] The initialization circuit is coupled to the second electrode of the light emitting device and is configured to provide a signal from the first initialization signal terminal to the second electrode of the light emitting device in response to a signal from the first reset signal terminal during the reset phase;

[0039] The detection circuit is coupled to the second electrode of the driving transistor and is configured to provide a signal from the second power supply terminal to the first node in response to a signal from the second electrode of the driving transistor during the detection phase, connect the first node to the detection signal terminal in response to a signal from the first scanning signal terminal, and output a detection signal through the detection signal terminal;

[0040] The potential selection circuit is coupled to the first electrode of the driving transistor and is configured to respond to a signal from a second scanning signal terminal during the reset phase, the compensation phase, and the light-emitting phase to provide a signal from the second power supply terminal to the first electrode of the driving transistor, and respond to a signal from a second initialization signal terminal during the compensation phase and the light-emitting phase to provide a signal from the second initialization signal terminal to the first electrode of the driving transistor;

[0041] The data writing circuit is coupled to the second node and configured to provide a data voltage signal at the data signal terminal to the second node in response to a signal at the third scan signal terminal during the compensation phase;

[0042] The first control circuit is coupled to the gate and the second electrode of the driving transistor and is configured to turn on the gate and the second electrode of the driving transistor in response to a signal at the second reset signal terminal during the reset phase and the compensation phase;

[0043] The second control circuit is coupled to the second electrode of the driving transistor, the second node and the second electrode of the light-emitting device, and is configured to respond to the signal of the light-emitting control signal end in the reset stage, the detection stage and the light-emitting stage, provide the signal of the first power supply end to the second node, and connect the second electrode of the driving transistor and the second electrode of the light-emitting device.

[0044] In some possible implementations, the detection circuit includes: a ninth transistor and a tenth transistor;

[0045] The gate of the ninth transistor is coupled to the second electrode of the driving transistor, the first electrode of the ninth transistor is coupled to the second power supply terminal, and the second electrode of the ninth transistor is coupled to the first node;

[0046] A gate of the tenth transistor is coupled to the first scan signal terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the detection signal terminal.

[0047] In some possible implementations, the potential selection circuit includes: an eleventh transistor and a twelfth transistor;

[0048] The gate of the eleventh transistor is coupled to the second scanning signal terminal, the first electrode of the eleventh transistor is coupled to the second power supply terminal, and the second electrode of the eleventh transistor is coupled to the first electrode of the driving transistor;

[0049] A gate of the twelfth transistor is coupled to the second initialization signal terminal, a first electrode of the twelfth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the twelfth transistor is coupled to the second initialization signal terminal.

[0050] In some possible implementations, the driving circuit includes: a driving transistor, a detection circuit, a data writing circuit, and a potential selection circuit;

[0051] The working process of the pixel circuit includes: a reset phase, a detection phase, a data writing phase and a compensation phase;

[0052] The detection circuit is coupled to the first electrode and the second electrode of the driving transistor, and is configured to respond to the signal of the second electrode of the driving transistor and the signal of the first scanning signal terminal during the reset phase, the detection phase, and the data writing phase, provide the signal of the first electrode of the driving transistor to the detection signal terminal, output the detection signal through the detection signal terminal, and connect the second electrode of the driving transistor to the detection signal terminal in response to the signal of the second scanning signal terminal during the compensation phase;

[0053] The data writing circuit is coupled to the gate of the driving transistor and is configured to provide a data voltage signal from a data signal terminal to the gate of the driving transistor in response to a signal from a third scanning signal terminal during the reset phase, the detection phase, the data writing phase, and the compensation phase;

[0054] The potential selection circuit is coupled to the first electrode of the driving transistor and is configured to respond to the signal of the fourth scanning signal terminal in the reset phase, the detection phase and the data writing phase, and provide the signal of the initialization signal terminal to the first electrode of the driving transistor, and respond to the signal of the second power supply terminal in the compensation phase, and provide the signal of the second power supply terminal to the second electrode of the driving transistor.

[0055] In some possible implementations, the detection circuit includes: a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor;

[0056] The gate of the thirteenth transistor is coupled to the second electrode of the driving transistor, the first electrode of the thirteenth transistor is coupled to the first electrode of the driving transistor, and the second electrode of the thirteenth transistor is coupled to the first electrode of the fourteenth transistor;

[0057] The gate of the fourteenth transistor is coupled to the first scan signal terminal, and the second electrode of the fourteenth transistor is coupled to the detection signal terminal;

[0058] A gate of the fifteenth transistor is coupled to the second scanning signal terminal, a first electrode of the fifteenth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the fifteenth transistor is coupled to the detection signal terminal.

[0059] In some possible implementations, the detection circuit includes: a thirteenth transistor and a fourteenth transistor;

[0060] A first gate of the thirteenth transistor is coupled to the second electrode of the driving transistor, a second gate of the thirteenth transistor is coupled to the first scanning signal terminal, a first electrode of the thirteenth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the thirteenth transistor is coupled to the first electrode of the fourteenth transistor;

[0061] A gate of the fourteenth transistor is coupled to the second scanning signal terminal, and a second electrode of the fourteenth transistor is coupled to the detection signal terminal.

[0062] In some possible implementations, the potential selection circuit includes: a sixteenth transistor and a seventeenth transistor;

[0063] The gate of the sixteenth transistor is coupled to the fourth scan signal terminal, the first electrode of the sixteenth transistor is coupled to the initialization signal terminal, and the second electrode of the sixteenth transistor is coupled to the first electrode of the driving transistor;

[0064] A gate of the seventeenth transistor is coupled to the second power supply terminal, a first electrode of the seventeenth transistor is coupled to the second power supply terminal, and a second electrode of the seventeenth transistor is coupled to the first electrode of the driving transistor.

[0065] In some possible implementations, the driving circuit includes: a driving transistor, a data writing circuit, a light emitting control circuit, and a detection circuit;

[0066] The working process of the pixel circuit includes: a detection phase and a light emitting phase;

[0067] The data writing circuit is coupled to the gate of the driving transistor and the first node, and is configured to provide a data voltage signal at the data signal terminal to the first node in response to a signal at the first scanning signal terminal during the light emitting phase, and provide a signal at the first level signal terminal or a signal at the second level signal terminal to the gate of the driving transistor in response to the signal at the first node;

[0068] The light emitting control circuit is coupled to the second electrode of the driving transistor and the second electrode of the light emitting device, and is configured to connect the second electrode of the driving transistor and the second electrode of the light emitting device in response to the signal of the light emitting control signal terminal during the detection phase and the light emitting phase;

[0069] The detection circuit is coupled to the gate of the driving transistor and the second electrode of the light-emitting device, and is configured to provide a signal from the initialization signal terminal to the second electrode of the driving transistor in response to a signal from the gate of the driving transistor during the detection phase, provide a signal from the second power supply terminal to the second node in response to a signal from the second electrode of the light-emitting device, provide a signal from the second node to the detection signal terminal in response to a signal from the second scanning signal terminal, and output a detection signal through the detection signal terminal.

[0070] In some possible implementations, the detection circuit includes: an eighteenth transistor, a nineteenth transistor, and a twentieth transistor;

[0071] A gate of the eighteenth transistor is coupled to a gate of the driving transistor, a first electrode of the eighteenth transistor is coupled to the initialization signal terminal, and a second electrode of the eighteenth transistor is coupled to a second electrode of the driving transistor;

[0072] The gate of the nineteenth transistor is coupled to the second electrode of the light-emitting device, the first electrode of the nineteenth transistor is coupled to the second power supply terminal, and the second electrode of the nineteenth transistor is coupled to the second node;

[0073] A gate of the twentieth transistor is coupled to a signal of the second scanning signal terminal, a first electrode of the twentieth transistor is coupled to the second node, and a second electrode of the twentieth transistor is coupled to the detection signal terminal.

[0074] The pixel circuit provided by the embodiment of the present disclosure includes:

[0075] a first light emitting device;

[0076] a driving circuit, coupled to the first light emitting device, and configured to drive the first light emitting device to emit light according to a data voltage signal;

[0077] a second light emitting device;

[0078] The detection circuit is coupled to the second light-emitting device and is configured to control the voltage of the second electrode of the second light-emitting device to be lower than the voltage of the first electrode of the second light-emitting device, and when the voltage of the second electrode of the second light-emitting device is controlled to be lower than the voltage of the first electrode of the second light-emitting device, control the driving circuit to stop driving the first light-emitting device to emit light, and output a detection signal according to the second light-emitting device.

[0079] In some possible implementations, the driving circuit includes: a driving transistor, an initialization circuit, a data writing circuit, a first control circuit, a second control circuit, a third control circuit, and a conduction control circuit;

[0080] The initialization circuit is coupled to the second electrode of the first light-emitting device and the gate of the driving transistor, and is configured to provide a signal of a first initialization signal terminal to the gate of the driving transistor in response to a signal of a first reset signal terminal, and provide a signal of a second initialization signal terminal to the second electrode of the first light-emitting device in response to a signal of a second reset signal terminal;

[0081] The data writing circuit is coupled to the first electrode of the driving transistor and is configured to provide a data voltage signal from the data signal terminal to the first electrode of the driving transistor in response to a signal from the first scanning signal terminal;

[0082] The first control circuit is coupled to the first node, the second electrode of the driving transistor, the second electrode of the first light-emitting device, and the second node, and is configured to provide a signal from the second power supply terminal to the first node in response to a signal from the second node, thereby conducting the second electrode of the driving transistor and the second electrode of the first light-emitting device;

[0083] The second control circuit is coupled to the second electrode and the gate of the driving transistor and is configured to conduct the second electrode and the gate of the driving transistor in response to a signal at the second scanning signal terminal;

[0084] The third control circuit is coupled to the second node and is configured to provide the signal of the pulse control signal terminal or the signal of the light emitting control signal terminal to the second node;

[0085] a conduction control circuit coupled to the detection circuit and configured to conduct the first node with the first electrode of the driving transistor in response to a control signal output by the detection circuit;

[0086] The detection circuit is coupled to the conduction control circuit and controls the conduction control circuit to disconnect the first node from the first electrode of the driving transistor.

[0087] In some possible implementations, the detection circuit includes: a first transistor and a second transistor;

[0088] The gate of the first transistor is coupled to the second power supply terminal, the first electrode of the first transistor is coupled to the second power supply terminal, and the second electrode of the first transistor is coupled to the conduction control circuit;

[0089] A gate of the second transistor is coupled to the third scan signal terminal, a first electrode of the second transistor is coupled to the first electrode of the second light emitting device, and a second electrode of the second transistor is coupled to the detection signal terminal.

[0090] In some possible embodiments, the conduction control circuit includes: a third transistor; the gate of the third transistor is coupled to the detection circuit, the first electrode of the third transistor is coupled to the first node, and the second electrode of the third transistor is coupled to the first electrode of the driving transistor.

[0091] The display panel provided by the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0092] In some possible implementations, the display panel includes a plurality of sub-pixels, and each of the sub-pixels includes the aforementioned pixel circuit.

[0093] In some possible implementations, when the pixel circuit includes a potential selection circuit, the pixel circuits in a row of sub-pixels are connected to the same potential selection circuit.

[0094] In some possible implementations, in a pixel circuit of at least one sub-pixel in a row of sub-pixels, the first electrode of the light-emitting device serves as a cathode, and the second electrode serves as an anode.

[0095] In some possible implementations, a row of sub-pixels includes a first sub-pixel and a second sub-pixel;

[0096] In the pixel circuit of the first sub-pixel, the first electrode of the light-emitting device is a cathode, and the second electrode is an anode;

[0097] In the pixel circuit of the second sub-pixel, the first electrode of the light-emitting device serves as an anode, and the second electrode serves as a cathode.

[0098] In some possible implementations, in a row of sub-pixels, the first sub-pixels and the second sub-pixels are alternately arranged.

[0099] In some possible implementations, in a pixel circuit of at least one sub-pixel in a column of sub-pixels, the first electrode of the light-emitting device serves as a cathode, and the second electrode serves as an anode.

[0100] In some possible implementations, a column of sub-pixels includes a third sub-pixel and a fourth sub-pixel;

[0101] In the pixel circuit of the third sub-pixel, the first electrode of the light-emitting device is a cathode, and the second electrode is an anode;

[0102] In the pixel circuit of the fourth sub-pixel, the first electrode of the light-emitting device serves as an anode, and the second electrode serves as a cathode.

[0103] In some possible implementations, in a column of sub-pixels, the third sub-pixels and the fourth sub-pixels are alternately arranged.

[0104] In some possible embodiments, the display panel includes a plurality of sub-pixels, the plurality of sub-pixels include at least one first sub-pixel and at least one second sub-pixel, the first sub-pixel includes the first light-emitting device and the driving circuit, and the second sub-pixel includes the second light-emitting device and the detection circuit.

[0105] In some possible implementations, the driving circuits in a plurality of the first sub-pixels are connected to the same detection circuit.

[0106] In some possible implementations, the second sub-pixel where the detection circuit is located and the first sub-pixel connected to the same detection circuit are arranged in M*N order, where M is an integer greater than 0, and N is an integer greater than 0.

[0107] The display device provided by the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0108] The driving method of the pixel circuit provided by the embodiment of the present disclosure includes: the driving circuit drives the light-emitting device to emit light according to the data voltage signal, and controls the voltage of the second pole of the light-emitting device to be lower than the voltage of the first pole of the light-emitting device, and outputs a detection signal according to the light-emitting device when the voltage of the second pole of the light-emitting device is controlled to be lower than the voltage of the first pole of the light-emitting device.

[0109] The driving method of the pixel circuit provided by the embodiment of the present disclosure includes: the driving circuit driving the first light emitting device to emit light according to the data voltage signal;

[0110] The detection circuit controls the voltage of the second pole of the second light-emitting device to be lower than the voltage of the first pole of the second light-emitting device, and when the voltage of the second pole of the second light-emitting device is controlled to be lower than the voltage of the first pole of the second light-emitting device, controls the driving circuit to stop driving the first light-emitting device to emit light, and outputs a detection signal according to the second light-emitting device. BRIEF DESCRIPTION OF THE DRAWINGS

[0111] FIG1 is a schematic diagram of some simulations provided by an embodiment of the present disclosure;

[0112] FIG2 is a schematic diagram of some test circuit structures provided by an embodiment of the present disclosure;

[0113] FIG3 is a schematic structural diagram of some light emitting device arrangements provided by an embodiment of the present disclosure;

[0114] FIG4 is a schematic diagram of some structures of pixel circuits provided by an embodiment of the present disclosure;

[0115] FIG5 is another schematic diagram of the structure of the pixel circuit provided by the embodiment of the present disclosure;

[0116] FIG6 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0117] FIG7 is a schematic diagram of some further structures of pixel circuits provided by embodiments of the present disclosure;

[0118] FIG8 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0119] FIG9 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0120] FIG10 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0121] FIG11 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0122] FIG12 is a schematic diagram of the control structure inside a chip provided by an embodiment of the present disclosure;

[0123] FIG13 is a schematic diagram of some structures of a signal selection circuit provided by an embodiment of the present disclosure;

[0124] FIG14 is another signal timing diagram provided by an embodiment of the present disclosure;

[0125] FIG15 is another schematic diagram of the structure of the signal selection circuit provided by the embodiment of the present disclosure;

[0126] FIG16 is a schematic diagram of some further structures of the signal selection circuit provided by an embodiment of the present disclosure;

[0127] FIG17 is a schematic diagram of some further structures of the signal selection circuit provided by an embodiment of the present disclosure;

[0128] FIG18 is a schematic diagram of some further structures of the signal selection circuit provided by an embodiment of the present disclosure;

[0129] FIG19 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0130] FIG20 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0131] FIG21 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0132] FIG22 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0133] FIG23 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0134] FIG24 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0135] FIG25 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0136] FIG26 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0137] FIG27 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0138] FIG28 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0139] FIG29 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0140] FIG30 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0141] FIG31 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0142] FIG32 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0143] FIG33 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0144] FIG34 is a schematic diagram of some further structures of pixel circuits provided by embodiments of the present disclosure;

[0145] FIG35 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0146] FIG36 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0147] FIG37 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0148] FIG38 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0149] FIG39 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0150] FIG40 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0151] FIG41 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0152] FIG42 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0153] FIG43 is a schematic diagram of some structures of a gate driving circuit provided by an embodiment of the present disclosure;

[0154] FIG44 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0155] FIG45 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0156] FIG46 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0157] FIG47 is a schematic diagram of some further structures of pixel circuits provided by embodiments of the present disclosure;

[0158] FIG48 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0159] FIG49 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0160] FIG50 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0161] FIG51 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0162] FIG52 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0163] FIG53 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0164] FIG54 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0165] FIG55 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0166] FIG56 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0167] FIG57 is a schematic diagram of some further structures of pixel circuits provided by embodiments of the present disclosure;

[0168] FIG58 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0169] FIG59 is a schematic diagram of some structures of a display panel provided by an embodiment of the present disclosure;

[0170] FIG60 is a schematic diagram of another structure of a display panel provided by an embodiment of the present disclosure;

[0171] FIG61 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0172] FIG62 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0173] FIG63 is a schematic diagram of some further structures of a display panel provided by an embodiment of the present disclosure;

[0174] FIG64 is a schematic diagram of some further structures of the display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0175] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0176] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0177] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0178] The display device provided by the embodiment of the present disclosure includes: a display panel, the display area of ​​the display panel includes a plurality of pixel units arranged in an array, and the pixel unit includes a plurality of sub-pixels. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, so that red, green and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, so that red, green, blue and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0179] It should be noted that when the light-emitting device in the display panel is in a reverse bias state (i.e., the voltage of the anode of the light-emitting device is less than the voltage of the cathode of the light-emitting device), the light-emitting device in the reverse bias state has the characteristic of being sensitive to external light and generates leakage current. When the light-emitting device is in a reverse bias state, the magnitude of the leakage current of the light-emitting device is related to the light intensity received by the light-emitting device. For example, as shown in the simulation diagram of FIG1 , the value of the horizontal axis in FIG1 represents the reverse bias voltage value of the light-emitting device, and the value of the vertical axis in FIG1 represents the current value of the leakage current of the light-emitting device. It can be seen from FIG1 that when the reverse bias voltage value is -1.5V, the ratio of the leakage current of the light-emitting device in an environment of 100lx illumination to the leakage current of the light-emitting device in an environment of 0lx illumination is close to 1000; that is, the leakage current of the light-emitting device in an environment of 100lx illumination is much greater than the leakage current of the light-emitting device in an environment of 0lx illumination.

[0180] It should be noted that a light-emitting device in a reverse bias state responds faster to external light. For example, the test circuit diagram shown in Figure 2 includes: a photosensitive circuit 1 and a light source circuit 2; wherein the photosensitive circuit 1 includes: an oscilloscope, a resistor R, and a first light-emitting device L1 (a total of 20, the 20 first light-emitting devices L1 are arranged as shown in Figure 3); the light source circuit 2 includes: a power supply and a second light-emitting device L2. According to Table 1 below, under the condition of brightness 1 (that is, when the voltage value of the power supply in the light source circuit 2 is 3V), the photosensitivity time Tr of the 20 first light-emitting devices L1 is 7.187μ, and the voltage difference U across the first light-emitting device L1 is 312mV; under the condition of brightness 2 (that is, when the voltage value of the power supply in the light source circuit 2 is 4V), the photosensitivity time Tr of the 20 first light-emitting devices L1 is 8.233μs, and the voltage difference U across the first light-emitting device L1 is 720mV; under the condition of brightness 3 (that is, when the voltage value of the power supply in the light source circuit 2 is 5V), the photosensitivity time Tr of the 20 first light-emitting devices L1 is 7.76μs, and the voltage difference U across the first light-emitting device L1 is 864mV; therefore, it can be seen that the first light-emitting device L1 in the reverse bias state responds faster to external light, and within a certain range, the greater the brightness of the light received, the greater the voltage difference across the first light-emitting device L1 in the reverse bias state, and thus the greater the leakage current.

[0181] Table 1

[0182] Based on the above experimental conclusions, the pixel circuit provided by the embodiment of the present disclosure, as shown in FIG4 , includes:

[0183] a light emitting device L, wherein a first electrode of the light emitting device L is coupled to a first power supply terminal VSS;

[0184] The driving circuit 100 is coupled to the second electrode of the light-emitting device L, and is configured to drive the light-emitting device L to emit light according to the data voltage signal, and is configured to control the voltage of the second electrode of the light-emitting device L to be lower than the voltage of the first electrode of the light-emitting device L, and when the voltage of the second electrode of the light-emitting device L is controlled to be lower than the voltage of the first electrode of the light-emitting device L, a detection signal is output according to the light-emitting device L.

[0185] The pixel circuit provided by the embodiments of the present disclosure utilizes a light-emitting device and a driver circuit to cooperate with each other. Specifically, the driver circuit is configured to drive the light-emitting device to emit light according to a data voltage signal, control the voltage at the second electrode of the light-emitting device to be lower than the voltage at the first electrode of the light-emitting device, and output a detection signal based on the light-emitting device when the voltage at the second electrode of the light-emitting device is lower than the voltage at the first electrode of the light-emitting device. This detection signal can be used to determine the illumination conditions of the pixel circuit, thereby realizing functions such as optical touch control, brightness decay detection, and fingerprint detection.

[0186] In some embodiments of the present disclosure, as shown in FIG5 , the driving circuit 100 includes: a driving transistor M0 , an initialization circuit 101 , a data transmission circuit 102 , a first control circuit 103 , a second control circuit 104 , and a third control circuit 105 ;

[0187] The initialization circuit 101 is coupled to the second electrode of the light-emitting device L and the gate of the driving transistor M0, and is configured to provide a signal from a first initialization signal terminal VINIT1 to the gate of the driving transistor M0 in response to a signal from a first reset signal terminal RE1 during a reset phase, and provide a signal from a second initialization signal terminal VINIT2 to the second electrode of the light-emitting device L in response to a signal from a second reset signal terminal RE2;

[0188] The data transmission circuit 102 is coupled to the first electrode of the driving transistor M0 and is configured to connect the first electrode of the driving transistor M0 to the data transmission signal terminal DAS in response to the signal of the first scanning signal terminal SS1 during the detection phase;

[0189] The first control circuit 103 is coupled to the driving transistor M0, the second electrode of the light-emitting device L, and the first node N1, and is configured to provide a signal from the second power supply terminal VDD to the first electrode of the driving transistor M0 in response to a signal from the light-emitting control signal terminal EM during the light-emitting phase, and to conduct the second electrode of the driving transistor M0 to the second electrode of the light-emitting device L in response to a signal from the first node N1 during the detection phase and the light-emitting phase;

[0190] The second control circuit 104 is coupled to the second electrode and the gate of the driving transistor M0 and is configured to connect the second electrode and the gate of the driving transistor M0 in response to the signal of the second scanning signal terminal SS2 during the detection phase;

[0191] The third control circuit 105 is coupled to the first node N1 and is configured to provide the signal of the pulse control signal terminal HF or the signal of the light emitting control signal terminal EM to the first node N1 in the reset phase, the detection phase and the light emitting phase.

[0192] Exemplarily, the voltage of the signal at the first initialization signal terminal VINIT1 and the voltage of the signal at the second initialization signal terminal VINIT2 are both lower than the voltage of the signal at the first power supply terminal VSS.

[0193] Exemplarily, the first electrode of the light emitting device L is a cathode, and the second electrode of the light emitting device L is an anode.

[0194] In some embodiments of the present disclosure, as shown in Figure 6, the data transmission circuit 102 includes: a first transistor M1; wherein the gate of the first transistor M1 is coupled to the first scan signal terminal SS1, the first electrode of the first transistor M1 is coupled to the first electrode of the driving transistor M0, and the second electrode of the first transistor M1 is coupled to the data transmission signal terminal DAS.

[0195] Exemplarily, the first transistor M1 can be turned on under the control of the active level of the first scan signal transmitted on the first scan signal terminal SS1, and can be turned off under the control of the inactive level of the first scan signal. For example, the first transistor M1 can be set as an N-type transistor, in which case the active level of the first scan signal is a high level, and the inactive level of the first scan signal is a low level. Alternatively, the first transistor M1 can be set as a P-type transistor, in which case the active level of the first scan signal is a low level, and the inactive level of the first scan signal is a high level.

[0196] Exemplarily, as shown in Figure 6, the initialization circuit 101 includes: a second initialization transistor M2 and a third initialization transistor M3; wherein, the gate of the second initialization transistor M2 is coupled to the first reset signal terminal RE1, the first electrode of the second initialization transistor M2 is coupled to the gate of the driving transistor M0, and the second electrode of the second initialization transistor M2 is coupled to the first initialization signal terminal VINIT1; the gate of the third initialization transistor M3 is coupled to the second reset signal terminal RE2, the first electrode of the third initialization transistor M3 is coupled to the second electrode of the light-emitting device L, and the second electrode of the third initialization transistor M3 is coupled to the second initialization signal terminal VINIT2.

[0197] Exemplarily, the second initialization transistor M2 can be turned on under the control of the active level of the first reset signal transmitted on the first reset signal terminal RE1, and can be turned off under the control of the inactive level of the first reset signal. For example, the second initialization transistor M2 can be set as an N-type transistor, in which case the active level of the first reset signal is a high level, and the inactive level of the first reset signal is a low level. Alternatively, the second initialization transistor M2 can be set as a P-type transistor, in which case the active level of the first reset signal is a low level, and the inactive level of the first reset signal is a high level.

[0198] Exemplarily, the third initialization transistor M3 can be turned on under the control of the active level of the second reset signal transmitted on the second reset signal terminal RE2, and can be turned off under the control of the inactive level of the second reset signal. For example, the third initialization transistor M3 can be set as an N-type transistor, in which case the active level of the second reset signal is a high level, and the inactive level of the second reset signal is a low level. Alternatively, the third initialization transistor M3 can be set as a P-type transistor, in which case the active level of the second reset signal is a low level, and the inactive level of the second reset signal is a high level.

[0199] Exemplarily, as shown in Figure 6, the first control circuit 103 includes: a fourth control transistor M4 and a fifth control transistor M5; wherein, the gate of the fourth control transistor M4 is coupled to the light-emitting control signal terminal EM, the first electrode of the fourth control transistor M4 is coupled to the second power supply terminal VDD, and the second electrode of the fourth control transistor M4 is coupled to the first electrode of the driving transistor M0; the gate of the fifth control transistor M5 is coupled to the first node N1, the first electrode of the fifth control transistor M5 is coupled to the second electrode of the driving transistor M0, and the second electrode of the fifth control transistor M5 is coupled to the second electrode of the light-emitting device L.

[0200] Exemplarily, the fourth control transistor M4 can be turned on under the control of the active level of the light-emitting control signal transmitted on the light-emitting control signal terminal EM, and can be turned off under the control of the inactive level of the light-emitting control signal. For example, the fourth control transistor M4 can be configured as an N-type transistor, in which case the active level of the light-emitting control signal is a high level, and the inactive level of the light-emitting control signal is a low level. Alternatively, the fourth control transistor M4 can be configured as a P-type transistor, in which case the active level of the light-emitting control signal is a low level, and the inactive level of the light-emitting control signal is a high level.

[0201] Exemplarily, the fifth control transistor M5 can be turned on under the control of the active level of the signal at the first node N1, and can be turned off under the control of the inactive level of the signal at the first node N1. For example, the fifth control transistor M5 can be configured as an N-type transistor, in which case the active level of the signal at the first node N1 is a high level, and the inactive level of the signal at the first node N1 is a low level. Alternatively, the fifth control transistor M5 can be configured as a P-type transistor, in which case the active level of the signal at the first node N1 is a low level, and the inactive level of the signal at the first node N1 is a high level.

[0202] Exemplarily, as shown in FIG6 , the second control circuit 104 includes: a sixth control transistor M6 and a first capacitor C1; wherein, the gate of the sixth control transistor M6 is coupled to the second scan signal terminal SS2, the first electrode of the sixth control transistor M6 is coupled to the gate of the driving transistor M0, and the second electrode of the sixth control transistor M6 is coupled to the second electrode of the driving transistor M0; the first electrode of the first capacitor C1 is coupled to the second power supply terminal VDD, and the second electrode of the first capacitor C1 is coupled to the gate of the driving transistor M0.

[0203] Exemplarily, the sixth control transistor M6 can be turned on under the control of the active level of the second scan signal transmitted on the second scan signal terminal SS2, and can be turned off under the control of the inactive level of the second scan signal. For example, the sixth control transistor M6 can be configured as an N-type transistor, in which case the active level of the second scan signal is a high level, and the inactive level of the second scan signal is a low level. Alternatively, the sixth control transistor M6 can be configured as a P-type transistor, in which case the active level of the second scan signal is a low level, and the inactive level of the second scan signal is a high level.

[0204] Exemplarily, as shown in Figure 6, the third control circuit 105 includes: a seventh control transistor M7, an eighth control transistor M8, a ninth control transistor M9 and a second capacitor C2; wherein, the gate of the seventh control transistor M7 is coupled to the second control node N2, the first electrode of the seventh control transistor M7 is coupled to the pulse control signal terminal HF, and the second electrode of the seventh control transistor M7 is coupled to the first node N1; the gate of the eighth control transistor M8 is coupled to the second control node N2, the first electrode of the eighth control transistor M8 is coupled to the first node N1, and the second electrode of the eighth control transistor M8 is coupled to the light-emitting control signal terminal EM; the gate of the ninth control transistor M9 is coupled to the reset signal terminal Rst, the first electrode of the ninth control transistor M9 is coupled to the second control node N2, and the second electrode of the ninth control transistor M9 is coupled to the data signal terminal DA; the first electrode of the second capacitor C2 is coupled to the second control node N2, and the second electrode of the second capacitor C2 is coupled to the first power supply terminal VSS.

[0205] Exemplarily, the seventh control transistor M7 and the eighth control transistor M8 can be turned on under the control of the active level of the signal at the second control node N2, and can be turned off under the control of the inactive level of the signal at the second control node N2. For example, the seventh control transistor M7 and the eighth control transistor M8 can be configured as N-type transistors, in which case the active level of the signal at the second control node N2 is a high level, and the inactive level of the signal at the second control node N2 is a low level. Alternatively, the seventh control transistor M7 and the eighth control transistor M8 can be configured as P-type transistors, in which case the active level of the signal at the second control node N2 is a low level, and the inactive level of the signal at the second control node N2 is a high level.

[0206] Exemplarily, the ninth control transistor M9 can be turned on under the control of the active level of the reset signal transmitted on the reset signal terminal Rst, and can be turned off under the control of the inactive level of the reset signal. For example, the ninth control transistor M9 can be configured as an N-type transistor, in which case the active level of the reset signal is a high level, and the inactive level of the reset signal is a low level. Alternatively, the ninth control transistor M9 can be configured as a P-type transistor, in which case the active level of the reset signal is a low level, and the inactive level of the reset signal is a high level.

[0207] In some embodiments of the present disclosure, the first scan signal terminal SS1 and the second scan signal terminal SS2 can be loaded with the same signal; as shown in Figure 7, the gate of the sixth control transistor M6 can be coupled to the first scan signal terminal SS1; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0208] In some embodiments of the present disclosure, the first initialization signal terminal VINIT1 and the second initialization signal terminal VINIT2 can be loaded with the same signal; as shown in Figure 7, the second electrode of the second initialization transistor M2 and the second electrode of the third initialization transistor M3 are both coupled to the first initialization signal terminal VINIT1; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0209] In some embodiments of the present disclosure, the first reset signal terminal RE1, the second reset signal terminal RE2, and the reset signal terminal Rst can be loaded with the same signal; as shown in Figure 7, the gate of the second initialization transistor M2 and the gate of the third initialization transistor M3 can both be coupled to the reset signal terminal Rst; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0210] In some embodiments of the present disclosure, the data transmission signal terminal DAS and the data signal terminal DA can be loaded with the same signal; as shown in Figure 7, the second electrode of the first transistor M1 is coupled to the data signal terminal DA; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0211] For example, the first power supply terminal VSS can be loaded with a constant first power supply voltage Vss, which can generally be a ground voltage or a negative value. Furthermore, the second power supply terminal VDD can be configured to be loaded with a constant second power supply voltage Vdd, which can generally be a positive value. In actual applications, the specific values ​​of the first power supply voltage Vss and the second power supply voltage Vdd can be designed and determined based on the actual application environment and are not limited here.

[0212] The driving method of the pixel circuit provided by the embodiment of the present disclosure includes: the driving circuit drives the light-emitting device to emit light according to the data voltage signal, and controls the voltage of the second electrode of the light-emitting device to be lower than the voltage of the first electrode of the light-emitting device, and when the voltage of the second electrode of the light-emitting device is controlled to be lower than the voltage of the first electrode of the light-emitting device, outputs a detection signal according to the light-emitting device.

[0213] In some embodiments of the present disclosure, as shown in FIG8 , the operation process of the pixel circuit includes: a reset phase F1 , a detection phase F2 , and a light emitting phase F4 .

[0214] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG6 as an example in combination with the signal timing diagram shown in FIG8 .

[0215] As shown in Figure 8, re1 represents the first reset signal of the first reset signal terminal RE1, re2 represents the second reset signal of the second reset signal terminal RE2, rst represents the reset signal of the reset signal terminal Rst, ss1 represents the first scan signal of the first scan signal terminal SS1, ss2 represents the second scan signal of the second scan signal terminal SS2, em represents the light-emitting control signal of the light-emitting control signal terminal EM, da represents the data voltage signal of the data signal terminal DA, das represents the data transmission signal of the data transmission signal terminal DAS, and hf represents the pulse control signal of the pulse control signal terminal HF.

[0216] Furthermore, a reset phase F1 , a detection phase F2 , and a light-emitting phase F4 in one display frame are selected.

[0217] In the reset phase F1, as shown in Figure 9, the first transistor M1 is turned off under the control of the high level of the first scan signal ss1; the second initialization transistor M2 is turned on under the control of the high level of the first reset signal re1; the third initialization transistor M3 is turned on under the control of the high level of the second reset signal re2; the fourth control transistor M4 is turned off under the control of the high level of the light emitting control signal em; the fifth control transistor M5 is turned off under the control of the high level of the signal at the first node N1; the sixth control transistor M6 is turned off under the control of the high level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2; the eighth control transistor M8 is turned off under the control of the low level of the signal at the second control node N2; and the ninth control transistor M9 is turned on under the control of the high level of the reset signal rst. The turned-on ninth control transistor M9 provides the low-level data voltage signal da to the second control node N2; the second capacitor C2 stores the low-level data voltage signal da; the turned-on seventh control transistor M7 provides the high-level pulse control signal hf to the first node N1; the turned-on second initialization transistor M2 provides the signal of the first initialization signal terminal VINIT1 to the gate of the driving transistor M0; the turned-on third initialization transistor M3 provides the signal of the second initialization signal terminal VINIT2 to the second electrode of the light-emitting device L; since the voltage of the signal of the second initialization signal terminal VINIT2 is less than the voltage of the signal of the first power supply terminal VSS, the voltage of the signal of the second electrode of the light-emitting device L is less than the voltage of the signal of the first electrode of the light-emitting device L, and the light-emitting device L is in a reverse biased state.

[0218] In the detection stage F2, as shown in Figure 10, the first transistor M1 is turned on under the control of the low level of the first scan signal ss1; the second initialization transistor M2 is turned off under the control of the low level of the first reset signal re1; the third initialization transistor M3 is turned off under the control of the low level of the second reset signal re2; the fourth control transistor M4 is turned off under the control of the high level of the light emitting control signal em; the fifth control transistor M5 is turned on under the control of the low level of the signal at the first node N1; the sixth control transistor M6 is turned on under the control of the low level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2; the eighth control transistor M8 is turned off under the control of the low level of the signal at the second control node N2; and the ninth control transistor M9 is turned off under the control of the low level of the reset signal rst. The turned-on seventh control transistor M7 provides the low-level pulse control signal hf to the first node N1; the turned-on sixth control transistor M6 conducts the gate of the driving transistor M0 with the second electrode of the driving transistor M0; the turned-on fifth control transistor M5 conducts the second electrode of the driving transistor M0 with the second electrode of the light-emitting device L; the turned-on first transistor M1 conducts the first electrode of the driving transistor M0 with the data transmission signal terminal DAS; the light-emitting device L, the fifth control transistor M5, the driving transistor M0 and the first transistor M1 form a path, and the light-emitting device L is in a reverse bias state. If the signal at the second electrode of the light-emitting device L is When the voltage of the signal at the first electrode of the driving transistor M0 changes, the voltage of the signal at the first electrode of the driving transistor M0 also changes accordingly, and then the first transistor M1 can transmit the signal at the first electrode of the driving transistor M0 to the data input signal terminal DAS, thereby outputting the detection signal through the detection signal terminal RD; that is, the first transistor M1 can transmit the detection signal to the data input signal terminal DAS according to the voltage change of the signal at the second electrode of the light-emitting device L; wherein the voltage of the detection signal is proportional to the brightness received by the light-emitting device L, that is, the greater the brightness received by the light-emitting device L, the greater the voltage of the detection signal, and the smaller the brightness received by the light-emitting device L, the smaller the voltage of the detection signal.

[0219] In the light-emitting stage F4, as shown in Figure 11, the first transistor M1 is turned off under the control of the high level of the first scan signal ss1; the second initialization transistor M2 is turned off under the control of the low level of the first reset signal re1; the third initialization transistor M3 is turned off under the control of the low level of the second reset signal re2; the fourth control transistor M4 is turned on under the control of the low level of the light-emitting control signal em; the fifth control transistor M5 is turned on under the control of the low level of the signal at the first node N1; the sixth control transistor M6 is turned off under the control of the high level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2; the eighth control transistor M8 is turned off under the control of the low level of the signal at the second control node N2; and the ninth control transistor M9 is turned off under the control of the low level of the reset signal rst. The turned-on seventh control transistor M7 provides the pulse control signal hf to the first node N1; the turned-on fourth control transistor M4 provides the signal of the second power supply terminal VDD to the first electrode of the driving transistor M0; the turned-on fifth control transistor M5 connects the second electrode of the driving transistor M0 to the second electrode of the light-emitting device L; the driving transistor M0 generates a driving current for driving the light-emitting device L, driving the light-emitting device L to emit light, wherein the grayscale is displayed as a medium and low grayscale.

[0220] It should be noted that, as shown in Figure 6, with the brightness decay detection function as the basic application scenario, the W / L value of the driving transistor M0, the first transistor M1, and the fifth control transistor M5 in the pixel circuit is P, where W / L represents the channel width-to-length ratio of the driving transistor M0, the first transistor M1, and the fifth control transistor M5. The larger the W / L value, the smaller the on-resistance of the driving transistor M0, the first transistor M1, and the fifth control transistor M5. When implementing a remote interaction scenario (i.e., the pixel circuit implements a light touch function), the W / L value of the driving transistor M0, the first transistor M1, and the fifth control transistor M5 in the pixel circuit is P1. When the brightness of the laser pen is high (the resistance of the light-emitting device L is small during the detection phase), the smaller the resistance of the path formed by the driving transistor M0, the first transistor M1, and the fifth control transistor M5 during the detection phase, the more obvious the voltage change of the light-emitting device L in different states, and thus P1>P. When implementing the fingerprint recognition scenario (i.e., the pixel circuit implements the fingerprint detection function), the W / L value of the driving transistor M0, the first transistor M1, and the fifth control transistor M5 in the pixel circuit is P2. Since the brightness change is small when a finger touches, and the brightness is low, which is reflected light, the greater the resistance of the path formed by the driving transistor M0, the first transistor M1, and the fifth control transistor M5 in the pixel circuit, the more obvious the voltage change of the light-emitting device L in different states, and P2 <P。

[0221] It should be noted that if the brightness attenuation detection function needs to be implemented, a random reading of the detection signal is adopted (it should be noted that the detection signal will be read once for each row of sub-pixels in the end), and the pixel circuit in a row of sub-pixels in the display panel is selected to read the detection signal. For the sub-pixels whose detection signals are read, medium and low grayscales will be displayed (because the detection signal needs to be transmitted through the data transmission signal terminal, the data voltage signal cannot be transmitted through the data transmission signal terminal, so the pixel circuit cannot write the data voltage signal, and thus the threshold voltage compensation of the driving transistor cannot be achieved, resulting in display abnormality). The abnormal display time of the sub-pixel whose detection signal is read is 1 / 60 frame. If the fingerprint detection function needs to be implemented, the detection signal is only read for the sub-pixels in the rows near the detected fingerprint.

[0222] It should be noted that, as shown in Figures 6 to 12, the data transmission signal terminal DAS can transmit both detection signals and be multiplexed into a data voltage signal. For example, as shown in Figure 12, the chip's internal control includes: a first switch SW1, a second switch SW2, an analog-to-digital converter ADC, and a digital-to-analog converter DAC. During the reset phase F1, the chip internally controls the first switch SW1 to open, and during the detection phase F2, the chip internally controls the second switch SW2 to open.

[0223] The present disclosure provides some other structural diagrams, which are modifications of the implementation methods in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0224] In other embodiments of the present disclosure, as shown in Figures 13 to 18, the display panel may further include: multiple gate lines (for example, GA(N-1), GA(N), GA(N+1) in Figure 13) and a signal selection circuit 106; the pixel circuit in a row of sub-pixels is coupled to a gate line through a signal selection circuit; a row of sub-pixels shares a signal selection circuit 106; wherein the signal selection circuit 106 is coupled to the first scan signal terminal (for example, SS1(N-1), SS1(N), SS1(N+1) in Figure 13) in the pixel circuit, and is configured to provide a first scan signal to the first scan signal terminal (for example, SS1(N-1), SS1(N), SS1(N+1) in Figure 13).

[0225] Exemplarily, as shown in FIG13 , the signal selection circuit 106 includes: a first selection transistor T1, a second selection transistor T2, a third selection transistor T3, a fourth selection transistor T4, and a capacitor C; the gate of the first selection transistor T1 is coupled to a gate line (e.g., GA(N-1), GA(N), GA(N+1) in FIG13 ), a first electrode of the first selection transistor T1 is coupled to the selection signal terminal OE, and a second electrode of the first selection transistor T1 is coupled to the control node A; the gate of the second selection transistor T2 is coupled to the control node A, and a first electrode of the second selection transistor T2 is coupled to a second electrode of the third selection transistor T3. , the second electrode of the second selection transistor T2 is coupled to the first level signal terminal VGL; the gate of the third selection transistor T3 is coupled to the read signal terminal RL, and the first electrode of the third selection transistor T3 is coupled to the first scan signal terminal; the gate of the fourth selection transistor T4 is coupled to the read signal terminal RL, the first electrode of the fourth selection transistor T4 is coupled to the gate line, and the second electrode of the fourth selection transistor T4 is coupled to the first scan signal terminal (for example, SS1(N-1), SS1(N), SS1(N+1) in Figure 13); the first electrode of the capacitor C is coupled to the control node A, and the second electrode of the capacitor C is coupled to the first level signal terminal VGL.

[0226] The following will describe the working process of the signal selection circuit with the structure shown in Figure 13 in combination with the signal timing diagram shown in Figure 14; wherein, ga(N-1) represents the signal transmitted on the gate line GA(N-1) corresponding to the N-1th row of sub-pixels, ga(N) represents the signal transmitted on the gate line GA(N) corresponding to the Nth row of sub-pixels, ga(N+1) represents the signal transmitted on the gate line GA(N+1) corresponding to the N+1th row of sub-pixels, ss1(N-1) represents the signal of the first scanning signal terminal SS1(N-1) corresponding to the pixel circuit in the N-1th row of sub-pixels, ss1(N) represents the signal of the first scanning signal terminal SS1(N+1) corresponding to the pixel circuit in the Nth row of sub-pixels, ss1(N+1) represents the signal of the first scanning signal terminal SS1(N+1) corresponding to the pixel circuit in the N+1th row of sub-pixels, oe represents the signal of the selection signal terminal OE, and rl represents the signal of the reading signal terminal RL.

[0227] In the first stage S11 of the data writing stage S1, as shown in Figure 15, the signal ga(N-1) transmitted on the gate line GA(N-1) corresponding to the N-1th row of sub-pixels is a low-level signal. The first selection transistor T1 is turned on under the control of the low level of the signal ga(N-1). The turned-on first selection transistor T1 provides the selection signal oe to the control node A, and the selection signal oe is a high-level signal; the capacitor C stores the high-level selection signal oe; the second selection transistor T2 is turned off under the control of the high level of the signal at the control node A; the third selection transistor T3 is turned off under the control of the high level of the read signal rl; the fourth selection transistor T4 is turned on under the control of the high level of the read signal rl. The turned-on fourth selection transistor T4 provides the signal ga(N-1) transmitted on the gate line GA(N-1) to the first scan signal terminal SS1(N-1) corresponding to the pixel circuit in the N-1th row of sub-pixels. Then, the first scan signal ss1(N-1) of the first scan signal terminal SS1(N-1) corresponding to the pixel circuit in the N-1th row of sub-pixels is a low-level signal. The first transistor M1 in the pixel circuit of the N-1th row of sub-pixels is turned on under the control of the low level of the first scanning signal terminal, and the data voltage signal can be transmitted through the data transmission signal terminal, so that the pixel circuit in the N-1th row of sub-pixels can normally write the data voltage signal, and the pixel circuit in the N-1th row of sub-pixels can emit light normally.

[0228] In the second stage S12 in the data writing stage S1, as shown in Figure 16, the signal ga(N) transmitted on the gate line GA(N) corresponding to the sub-pixel in the Nth row is a low-level signal, and the first selection transistor T1 is turned on under the control of the low level of the signal ga(N). The turned-on first selection transistor T1 provides the selection signal oe to the control node A, and the selection signal oe is a low-level signal; the capacitor C stores the low-level selection signal oe; the second selection transistor T2 is turned on under the control of the low level of the signal at the control node A, and the turned-on second selection transistor T2 provides the low-level signal of the first-level signal terminal VGL to the second electrode of the third selection transistor T3; the third selection transistor T3 is turned off under the control of the high level of the read signal rl; the fourth selection transistor T4 is turned on under the control of the high level of the read signal rl, and the turned-on fourth selection transistor T4 provides the signal ga(N) transmitted on the gate line GA(N) to the first scanning signal terminal SS1(N) corresponding to the pixel circuit in the sub-pixel in the Nth row. Then, the first scanning signal ss1(N) at the first scanning signal terminal SS1(N) corresponding to the pixel circuit in the Nth row of sub-pixels is a low-level signal. The first transistor M1 in the pixel circuit in the Nth row of sub-pixels is turned on under the control of the low level of the first scanning signal terminal, and the data voltage signal can be transmitted through the data transmission signal terminal, so that the pixel circuit in the Nth row of sub-pixels can normally write the data voltage signal, and the pixel circuit in the Nth row of sub-pixels can normally emit light.

[0229] In the third stage S13 of the data writing stage S1, as shown in FIG17 , the signal ga(N+1) transmitted on the gate line GA(N+1) corresponding to the sub-pixels in the N+1th row is a low-level signal. The first selection transistor T1 is turned on under the control of the low-level signal ga(N+1). The turned-on first selection transistor T1 provides the selection signal oe to the control node A, and the selection signal oe is a high-level signal. The capacitor C stores the high-level selection signal oe. The second selection transistor T2 is turned off under the control of the high-level signal of the control node A. The third selection transistor T3 is turned off under the control of the high-level read signal rl. The fourth selection transistor T4 is turned on under the control of the high-level read signal rl. The turned-on fourth selection transistor T4 provides the signal ga(N+1) transmitted on the gate line GA(N+1) to the first scan signal terminal SS1(N+1) corresponding to the pixel circuit in the sub-pixels in the N+1th row. Then, the first scan signal ss1(N+1) of the first scan signal terminal SS1(N+1) corresponding to the pixel circuit in the sub-pixels in the N+1th row is a low-level signal. The first transistor M1 in the pixel circuit of the sub-pixel in the N+1th row is turned on under the control of the low level of the first scanning signal terminal, and the data voltage signal can be transmitted through the data transmission signal terminal, so that the pixel circuit in the sub-pixel in the N+1th row can normally write the data voltage signal, and the pixel circuit in the sub-pixel in the N+1th row can emit light normally.

[0230] During the blank phase B1, as shown in FIG18 , in the second phase S12 of the data write phase S1, the signal at the control node A in the signal selection circuit 106 corresponding to the Nth row of sub-pixels is at a low level, i.e., the capacitor C in the signal selection circuit 106 stores the low-level selection signal oe, which selects the pixel circuit corresponding to the Nth row of sub-pixels for reading the detection signal. The first selection transistor T1 is turned off under the control of the high-level signal. The second selection transistor T2 is turned on under the control of the low-level signal at the control node A. The third selection transistor T3 is turned on under the control of the low-level read signal rl. The fourth selection transistor T4 is turned off under the control of the low-level read signal rl. The turned-on second selection transistor T2 and third selection transistor T3 provide the low-level signal of the first level signal terminal VGL to the first scan signal terminal SS1(N) corresponding to the pixel circuit in the Nth row of sub-pixels. Consequently, the first scan signal ss1(N) at the first scan signal terminal SS1(N) corresponding to the pixel circuit in the Nth row of sub-pixels is a low-level signal. The first transistor M1 in the pixel circuit of the Nth row of sub-pixels is turned on under the control of the low level of the first scanning signal terminal, and the detection signal is transmitted through the data transmission signal terminal, so that the detection signal can be read from the pixel circuit of the Nth row of sub-pixels.

[0231] In summary, in other embodiments of the present disclosure, by setting a signal selection circuit, the pixel circuit can normally perform the process of writing the data voltage signal in the data writing stage, and select the pixel circuit to read the detection signal in the blank stage, so that it will not affect the display or the reading of the detection signal.

[0232] The present disclosure provides some further structural diagrams of pixel circuits, as shown in Figure 19, which are variations of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0233] In some other embodiments of the present disclosure, as shown in FIG. 19 , the light emitting control signal terminal EM is coupled to the first node N1 .

[0234] In some other embodiments of the present disclosure, as shown in Figure 19, the data transmission circuit 102 includes: a data writing circuit 1021 and a detection circuit 1022; the data writing circuit 1021 is coupled to the first electrode of the driving transistor M0, and is configured to respond to the signal of the third scanning signal terminal SS3 in the compensation stage, and provide the data voltage signal of the data transmission signal terminal DAS to the first electrode of the driving transistor M0; the detection circuit 1022 is coupled to the first electrode of the driving transistor M0, and is configured to respond to the signal of the first electrode of the driving transistor M0 in the detection stage, and provide the signal of the second power supply terminal VDD to the second node N02, and in response to the signal of the fourth scanning signal terminal SS4, connect the second node N02 with the detection signal terminal RD, and output the detection signal through the detection signal terminal RD.

[0235] Exemplarily, the voltage of the signal at the third initialization signal terminal VINIT3 is less than the voltage of the signal at the first initialization signal terminal VINIT1 and the voltage of the signal at the second initialization signal terminal VINIT2, and the voltage of the signal at the first initialization signal terminal VINIT1 and the voltage of the signal at the second initialization signal terminal VINIT2 are both less than the voltage of the signal at the first power supply terminal VSS.

[0236] In some other embodiments of the present disclosure, as shown in Figure 19, the detection circuit 1022 includes: a second transistor M02 and a third transistor M03; wherein, the gate of the second transistor M02 is coupled to the first electrode of the driving transistor M0, the first electrode of the second transistor M02 is coupled to the second power supply terminal VDD, and the second electrode of the second transistor M02 is coupled to the second node N02; the gate of the third transistor M03 is coupled to the fourth scanning signal terminal SS4, the first electrode of the third transistor M03 is coupled to the second node N02, and the second electrode of the third transistor M03 is coupled to the detection signal terminal RD.

[0237] Exemplarily, the second transistor M02 can be turned on under the control of the effective level of the signal of the first electrode of the driving transistor M0, and can be turned off under the control of the ineffective level of the signal of the first electrode of the driving transistor M0. For example, the second transistor M02 can be set as an N-type transistor, then the effective level of the signal of the first electrode of the driving transistor M0 is a high level, and the ineffective level of the signal of the first electrode of the driving transistor M0 is a low level. Alternatively, the second transistor M02 can be set as a P-type transistor, then the effective level of the signal of the first electrode of the driving transistor M0 is a low level, and the ineffective level of the signal of the first electrode of the driving transistor M0 is a high level.

[0238] Exemplarily, the third transistor M03 can be turned on under the control of the active level of the fourth scan signal transmitted on the fourth scan signal terminal SS4, and can be turned off under the control of the inactive level of the fourth scan signal. For example, the third transistor M03 can be set as an N-type transistor, in which case the active level of the fourth scan signal is a high level, and the inactive level of the fourth scan signal is a low level. Alternatively, the third transistor M03 can be set as a P-type transistor, in which case the active level of the fourth scan signal is a low level, and the inactive level of the fourth scan signal is a high level.

[0239] In some other embodiments of the present disclosure, as shown in Figure 19, the data write circuit 1021 includes: a first data transistor M01; wherein, the gate of the first data transistor M01 is coupled to the third scan signal terminal SS3, the first electrode of the first data transistor M01 is coupled to the first electrode of the driving transistor M0, and the second electrode of the first data transistor M01 is coupled to the data transmission signal terminal DAS.

[0240] Exemplarily, the first data transistor M01 can be turned on under the control of the active level of the third scan signal transmitted on the third scan signal terminal SS3, and can be turned off under the control of the inactive level of the third scan signal. For example, the first data transistor M01 can be set as an N-type transistor, in which case the active level of the third scan signal is a high level, and the inactive level of the third scan signal is a low level. Alternatively, the first data transistor M01 can be set as a P-type transistor, in which case the active level of the third scan signal is a low level, and the inactive level of the third scan signal is a high level.

[0241] In some other embodiments of the present disclosure, as shown in Figure 19, it also includes: a potential selection circuit 110, coupled to the driving circuit 100, and configured to respond to the signal of the fifth scan signal terminal SS5 in the reset stage and the detection stage to provide the signal of the third initialization signal terminal VINIT3 to the driving circuit 100, and respond to the signal of the sixth scan signal terminal SS6 in the compensation stage and the light-emitting stage to provide the signal of the second power supply terminal VDD to the driving circuit 100.

[0242] Exemplarily, the pixel circuits in each row of sub-pixels share the same potential selection circuit.

[0243] In some other embodiments of the present disclosure, as shown in Figure 19, the potential selection circuit 110 includes: a fourth transistor M04 and a fifth transistor M05; wherein, the gate of the fourth transistor M04 is coupled to the fifth scan signal terminal SS5, the first electrode of the fourth transistor M04 is coupled to the first electrode of the fourth control transistor M4 in the driving circuit 100, and the second electrode of the fourth transistor M04 is coupled to the third initialization signal terminal VINIT3; the gate of the fifth transistor M05 is coupled to the sixth scan signal terminal SS6, the first electrode of the fifth transistor M05 is coupled to the second power supply terminal VDD, and the second electrode of the fifth transistor M05 is coupled to the first electrode of the fourth control transistor M4 in the driving circuit 100.

[0244] Exemplarily, the fourth transistor M04 can be turned on under the control of the active level of the fifth scan signal transmitted on the fifth scan signal terminal SS5, and can be turned off under the control of the inactive level of the fifth scan signal. For example, the fourth transistor M04 can be set as an N-type transistor, in which case the active level of the fifth scan signal is a high level, and the inactive level of the fifth scan signal is a low level. Alternatively, the fourth transistor M04 can be set as a P-type transistor, in which case the active level of the fifth scan signal is a low level, and the inactive level of the fifth scan signal is a high level.

[0245] Exemplarily, the fifth transistor M05 can be turned on under the control of the effective level of the sixth scan signal transmitted on the sixth scan signal terminal SS6, and can be turned off under the control of the inactive level of the sixth scan signal. For example, the fifth transistor M05 can be set as an N-type transistor, then the effective level of the sixth scan signal is a high level, and the inactive level of the sixth scan signal is a low level. Alternatively, the fifth transistor M05 can be set as a P-type transistor, then the effective level of the sixth scan signal is a low level, and the inactive level of the sixth scan signal is a high level.

[0246] For example, the second scan signal terminal SS2 and the third scan signal terminal SS3 can be loaded with the same signal; as shown in FIG20 , the gate of the sixth control transistor M5 is coupled to the third scan signal terminal SS3. This can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0247] For example, the first reset signal terminal RE1, the fourth scan signal terminal SS4, the fifth scan signal terminal SS5, the sixth scan signal terminal SS6, and the reset signal terminal Rst can be loaded with the same signal. As shown in FIG20 , the gate of the second control transistor M2 is coupled to the fourth scan signal terminal SS4; the gate of the ninth control transistor M9 is coupled to the fourth scan signal terminal SS4; the gate of the fourth transistor M04 is coupled to the fourth scan signal terminal SS4; and the gate of the fifth transistor M05 is coupled to the fourth scan signal terminal SS4. This can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0248] For example, the first initialization signal terminal VINIT1 and the second initialization signal terminal VINIT2 can be loaded with the same signal. As shown in FIG20 , the first electrode of the third initialization transistor M3 is coupled to the first initialization signal terminal VINIT1. This can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0249] In some embodiments of the present disclosure, as shown in FIG. 21 , the operation process of the pixel circuit includes: a reset stage F1 , a detection stage F2 , a compensation stage F3 , and a light emitting stage F4 .

[0250] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG19 as an example in combination with the signal timing diagram shown in FIG21 .

[0251] As shown in Figure 21, re1 represents the first reset signal of the first reset signal terminal RE1, re2 represents the second reset signal of the second reset signal terminal RE2, rst represents the reset signal of the reset signal terminal Rst, ss2 represents the second scan signal of the second scan signal terminal SS2, ss3 represents the third scan signal of the third scan signal terminal SS3, ss4 represents the fourth scan signal of the fourth scan signal terminal SS4, ss5 represents the fifth scan signal of the fifth scan signal terminal SS5, ss6 represents the sixth scan signal of the sixth scan signal terminal SS6, em represents the light-emitting control signal of the light-emitting control signal terminal EM, da represents the data voltage signal of the data signal terminal DA, das represents the data voltage signal of the data transmission signal terminal DAS, and hf represents the pulse control signal of the pulse control signal terminal HF.

[0252] Furthermore, a reset phase F1 , a detection phase F2 , a compensation phase F3 and a light emitting phase F4 in one display frame are selected.

[0253] In the reset phase F1, as shown in FIG22 , the first data transistor M01 is turned off under the control of the high level of the third scan signal ss3; the second transistor M02 is turned on under the control of the low level of the signal at the first electrode of the driving transistor M0; the third transistor M03 is turned on under the control of the high level of the fourth scan signal ss4; the fourth transistor M04 is turned on under the control of the high level of the fifth scan signal ss5; the fifth transistor M05 is turned off under the control of the high level of the sixth scan signal ss6; the second initialization transistor M2 is turned on under the control of the high level of the first reset signal re1; the third initialization transistor M3 is turned on under the control of the high level of the second reset signal re2; the fourth control transistor M4 and the fifth control transistor M5 are turned off under the control of the high level of the first node N1; the sixth control transistor M6 is turned off under the control of the high level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2; the eighth control transistor M8 is turned off under the control of the low level of the signal at the second control node N2; and the ninth control transistor M9 is turned on under the control of the high level of the reset signal rst. The conductive ninth control transistor M9 provides the low-level data voltage signal da to the second control node N2; the second capacitor C2 stores the low-level data voltage signal da; the conductive seventh control transistor M7 provides the high-level pulse control signal hf to the first node N1; the conductive fourth transistor M04 provides the signal of the third initialization signal terminal VINIT3 to the first electrode of the fourth control transistor M4 in the driving circuit 100; the conductive second transistor M02 provides the signal of the second power supply terminal VDD to the second node N02, and the conductive third transistor M03 provides the signal of the second node N02 to the detection signal terminal RD; the conductive second initialization transistor M2 provides the signal of the first initialization signal terminal VINIT1 to the gate of the driving transistor M0; the conductive third initialization transistor M3 provides the signal of the second initialization signal terminal VINIT2 to the second electrode of the light-emitting device L; since the voltage of the signal of the second initialization signal terminal VINIT2 is lower than the voltage of the signal of the first power supply terminal VSS, the voltage of the signal of the second electrode of the light-emitting device L is lower than the voltage of the signal of the first electrode of the light-emitting device L, and the light-emitting device L is in a reverse biased state.

[0254] In the detection stage F2, as shown in Figure 23, the first data transistor M01 is turned off under the control of the high level of the third scan signal ss3; the second transistor M02 is turned on under the control of the low level of the signal at the first electrode of the driving transistor M0; the third transistor M03 is turned on under the control of the high level of the fourth scan signal ss4; the fourth transistor M04 is turned on under the control of the high level of the fifth scan signal ss5; the fifth transistor M05 is turned off under the control of the high level of the sixth scan signal ss6; the second initialization transistor M2 is turned on under the control of the high level of the first reset signal re1; the third initialization transistor M3 is turned off under the control of the low level of the second reset signal re2; the fourth control transistor M4 and the fifth control transistor M5 are turned on under the control of the low level of the first node N1; the sixth control transistor M6 is turned off under the control of the high level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2 or the eighth control transistor M8 is turned on under the control of the high level of the signal at the second control node N2; and the ninth control transistor M9 is turned on under the control of the high level of the reset signal rst.The turned-on second initialization transistor M2 provides the signal of the first initialization signal terminal VINIT1 to the gate of the driving transistor M0; the turned-on ninth control transistor M9 provides the data voltage signal da to the second control node N2; the second capacitor C2 stores the data voltage signal da; the turned-on seventh control transistor M7 provides the low-level pulse control signal hf to the first node N1; the turned-on eighth control transistor provides the low-level light-emitting control signal em to the first node N1; the turned-on fourth transistor M04 provides the signal of the third initialization signal terminal VINIT3 to the driving circuit 100; the turned-on fourth control transistor M4 connects the first electrode of the fourth transistor M04 to the first electrode of the driving transistor M0; the turned-on fifth control transistor M5 connects the second electrode of the light-emitting device L to the second electrode of the driving transistor M0; then the light-emitting device L, the fifth control transistor M5, the fourth control transistor M4 and the fourth transistor M04 are connected. A path is formed. Since the voltage of the signal at the third initialization signal terminal VINIT3 is less than the voltage of the signal at the first power supply terminal VSS, the light-emitting device L is in a reverse biased state. Since the gate of the second transistor M02 is coupled to the first electrode of the driving transistor M0, if the voltage of the signal at the second electrode of the light-emitting device L changes, the voltage of the signal at the first electrode of the driving transistor M0 also changes accordingly. The second transistor M02 adjusts the voltage of the signal input to the second node N02 according to the change in the voltage of the signal at the first electrode of the driving transistor M0. The turned-on third transistor M03 provides a detection signal to the detection signal terminal RD according to the signal at the second node N02, that is, the detection signal is output through the detection signal terminal RD. The voltage of the detection signal is inversely proportional to the brightness received by the light-emitting device L, that is, the greater the brightness received by the light-emitting device L, the smaller the voltage of the detection signal; and the smaller the brightness received by the light-emitting device L, the larger the voltage of the detection signal.

[0255] In the compensation stage F3, as shown in FIG24 , the first data transistor M01 is turned on under the control of the low level of the third scan signal ss3; the second transistor M02 is turned on under the control of the low level of the signal of the first electrode of the driving transistor M0; the third transistor M03 is turned off under the control of the low level of the fourth scan signal ss4; the fourth transistor M04 is turned off under the control of the low level of the fifth scan signal ss5; the fifth transistor M05 is turned on under the control of the low level of the sixth scan signal ss6; the second initialization transistor M2 is turned off under the control of the low level of the first reset signal re1; the third initialization transistor M3 is turned off under the control of the low level of the second reset signal re2; the fourth control transistor M4 and the fifth control transistor M5 are turned off under the control of the high level of the first node N1; the sixth control transistor M6 is turned on under the control of the low level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal of the second control node N2 or the eighth control transistor M8 is turned on under the control of the high level of the signal of the second control node N2; and the ninth control transistor M9 is turned off under the control of the low level of the reset signal rst. The turned-on seventh control transistor M7 provides a high-level pulse control signal hf to the first node N1; the turned-on eighth control transistor M8 provides a high-level light-emitting control signal em to the first node N1; the turned-on second transistor M02 provides a signal from the second power supply terminal VDD to the second node N02; the turned-on fifth transistor M05 provides a signal from the second power supply terminal VDD to the driving circuit 100; the turned-on first data transistor M01 provides a data voltage signal das to the first electrode of the driving transistor M0; the turned-on sixth control transistor M6 connects the second electrode of the driving transistor M0 to the gate of the driving transistor M0.

[0256] In the light-emitting stage F4, as shown in Figure 25, the first data transistor M01 is turned off under the control of the high level of the third scan signal ss3; the second transistor M02 is turned off under the control of the high level of the signal of the first electrode of the driving transistor M0; the third transistor M03 is turned off under the control of the low level of the fourth scan signal ss4; the fourth transistor M04 is turned off under the control of the low level of the fifth scan signal ss5; the fifth transistor M05 is turned on under the control of the low level of the sixth scan signal ss6; the second initialization transistor M2 is turned off under the control of the low level of the first reset signal re1; the third initialization transistor M3 is turned off under the control of the low level of the second reset signal re2; the fourth control transistor M4 and the fifth control transistor M5 are turned on under the control of the low level of the first node N1; the sixth control transistor M6 is turned off under the control of the high level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2 or the eighth control transistor M8 is turned on under the control of the high level of the signal at the second control node N2; and the ninth control transistor M9 is turned off under the control of the low level of the reset signal rst. The turned-on seventh control transistor M7 provides the pulse control signal hf to the first node N1; the turned-on eighth control transistor M8 provides the low-level light-emitting control signal em to the first node N1; the turned-on fifth transistor M05 provides the signal of the second power supply terminal VDD to the driving circuit 100; the turned-on fourth control transistor M4 connects the first electrode of the fourth transistor M04 with the first electrode of the driving transistor M0; the turned-on fifth control transistor M5 connects the second electrode of the light-emitting device L with the second electrode of the driving transistor M0; the driving transistor M0 generates a driving current for driving the light-emitting device L, driving the light-emitting device L to emit light.

[0257] It should be noted that, taking the brightness decay detection function as the basic application scenario, the W / L value of the fourth transistor M04, the fourth control transistor M4, the driving transistor M0, and the fifth control transistor M5 in the pixel circuit is P, where W / L represents the channel width-to-length ratio of the driving transistor M0, the first transistor M1, and the fifth control transistor M5. The larger the W / L value, the smaller the on-resistance of the fourth transistor M04, the fourth control transistor M4, the driving transistor M0, and the fifth control transistor M5. When implementing a remote interaction scenario (i.e., the pixel circuit implements a light touch function), the W / L value of the fourth transistor M04, the fourth control transistor M4, the driving transistor M0, and the fifth control transistor M5 in the pixel circuit is P1. When the brightness of the laser pen is high (the resistance of the light-emitting device L is small during the detection phase), the resistance of the path formed by the fourth transistor M04, the fourth control transistor M4, the driving transistor M0, and the fifth control transistor M5 is smaller during the detection phase, and the voltage change of the light-emitting device L in different states is more obvious, so P1>P. When implementing the fingerprint recognition scenario (i.e., the pixel circuit implements the fingerprint detection function), the W / L value of the driving transistor M0, the first transistor M1, and the fifth control transistor M5 in the pixel circuit is P2. Since the brightness change is small when a finger touches (in the detection stage, the resistance of the light-emitting device L is large), and the brightness is low, it is reflected light. Therefore, the greater the resistance of the path formed by the driving transistor M0, the first transistor M1, and the fifth control transistor M5 in the pixel circuit, the more obvious the voltage change of the light-emitting device L in different states, and P2 <P。

[0258] The present disclosure provides some structural diagrams of pixel circuits, as shown in Figure 26, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0259] In some further embodiments of the present disclosure, as shown in FIG26 , the data transmission circuit 102 includes: a data writing circuit 1021 , a detection circuit 1022 , and a conduction control circuit 1023 ;

[0260] The data writing circuit 1021 is coupled to the first electrode of the driving transistor M0 and is configured to provide the data voltage signal of the data transmission signal terminal DAS to the first electrode of the driving transistor M0 in response to the signal of the seventh scanning signal terminal SS7 during the detection phase and the compensation phase;

[0261] The detection circuit 1022 is coupled to the second electrode of the driving transistor M0 and is configured to provide a signal from the second power supply terminal VDD to the third node N03 in response to a signal from the second electrode of the driving transistor M0 during a detection phase, and to conduct electricity between the third node N03 and the detection signal terminal RD in response to a signal from the eighth scan signal terminal SS8, thereby outputting a detection signal through the detection signal terminal.

[0262] The conduction control circuit 1023 is coupled to the second electrode of the driving transistor M0 and the second electrode of the light emitting device L, and is configured to conduct the second electrode of the driving transistor M0 and the second electrode of the light emitting device L in response to the signal of the ninth scanning signal terminal SS9 during the detection phase.

[0263] Exemplarily, the voltage of the signal at the first initialization signal terminal VINIT1 and the voltage of the signal at the second initialization signal terminal VINIT2 are both lower than the voltage of the signal at the first power supply terminal VSS.

[0264] In some other embodiments of the present disclosure, as shown in Figure 26, the detection circuit includes: a sixth transistor M06 and a seventh transistor M07; wherein, the gate of the sixth transistor M06 is coupled to the second electrode of the driving transistor M0, the first electrode of the sixth transistor M06 is coupled to the second power supply terminal VDD, and the second electrode of the sixth transistor M06 is coupled to the third node N03; the gate of the seventh transistor M07 is coupled to the eighth scan signal terminal SS8, the first electrode of the seventh transistor M07 is coupled to the third node N03, and the second electrode of the seventh transistor M07 is coupled to the detection signal terminal RD.

[0265] Exemplarily, the sixth transistor M06 can be turned on under the control of the effective level of the signal at the second pole of the driving transistor M0, and can be turned off under the control of the inactive level of the signal at the second pole of the driving transistor M0. For example, the sixth transistor M06 can be set as an N-type transistor, then the effective level of the signal at the second pole of the driving transistor M0 is a high level, and the inactive level of the signal at the second pole of the driving transistor M0 is a low level. Alternatively, the sixth transistor M06 can be set as a P-type transistor, then the effective level of the signal at the second pole of the driving transistor M0 is a low level, and the inactive level of the signal at the second pole of the driving transistor M0 is a high level.

[0266] Exemplarily, the seventh transistor M07 can be turned on under the control of the active level of the eighth scan signal transmitted on the eighth scan signal terminal SS8, and can be turned off under the control of the inactive level of the eighth scan signal. For example, the seventh transistor M07 can be set as an N-type transistor, in which case the active level of the eighth scan signal is a high level, and the inactive level of the eighth scan signal is a low level. Alternatively, the seventh transistor M07 can be set as a P-type transistor, in which case the active level of the eighth scan signal is a low level, and the inactive level of the eighth scan signal is a high level.

[0267] In some other embodiments of the present disclosure, as shown in Figure 26, the data write circuit 1021 includes: a first data transistor M01; wherein, the gate of the first data transistor M01 is coupled to the seventh scan signal terminal SS7, the first electrode of the first data transistor M01 is coupled to the first electrode of the driving transistor M0, and the second electrode of the first data transistor M01 is coupled to the data transmission signal terminal DAS.

[0268] Exemplarily, the first data transistor M01 can be turned on under the control of the active level of the seventh scan signal transmitted on the seventh scan signal terminal SS7, and can be turned off under the control of the inactive level of the seventh scan signal. For example, the first data transistor M01 can be set as an N-type transistor, in which case the active level of the seventh scan signal is a high level, and the inactive level of the seventh scan signal is a low level. Alternatively, the first data transistor M01 can be set as a P-type transistor, in which case the active level of the seventh scan signal is a low level, and the inactive level of the seventh scan signal is a high level.

[0269] In some other embodiments of the present disclosure, as shown in Figure 26, the conduction control circuit 1023 includes: an eighth transistor M08; wherein the gate of the eighth transistor M08 is coupled to the ninth scan signal terminal SS9, the first electrode of the eighth transistor M08 is coupled to the second electrode of the driving transistor M0, and the second electrode of the eighth transistor M08 is coupled to the second electrode of the light-emitting device L.

[0270] Exemplarily, the eighth transistor M08 can be turned on under the control of the active level of the ninth scan signal transmitted on the ninth scan signal terminal SS9, and can be turned off under the control of the inactive level of the ninth scan signal. For example, the eighth transistor M08 can be set as an N-type transistor, in which case the active level of the ninth scan signal is a high level, and the inactive level of the ninth scan signal is a low level. Alternatively, the eighth transistor M08 can be set as a P-type transistor, in which case the active level of the ninth scan signal is a low level, and the inactive level of the ninth scan signal is a high level.

[0271] Illustratively, the eighth scan signal terminal SS8 and the ninth scan signal terminal SS9 can be loaded with the same signal; as shown in FIG27 , the gate of the eighth transistor M08 is coupled to the eighth scan signal terminal SS8; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0272] Illustratively, the first initialization signal terminal VINIT1 and the second initialization signal terminal VINIT2 can be loaded with the same signal; as shown in FIG27 , the second electrode of the second initialization transistor M2 and the second electrode of the third initialization transistor M3 can both be coupled to the first initialization signal terminal VINIT1; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0273] Illustratively, the first reset signal terminal RE1, the second reset signal terminal RE2, and the reset signal terminal Rst can be loaded with the same signal; as shown in FIG27 , the gate of the second initialization transistor M2 and the gate of the third initialization transistor M3 can both be coupled to the reset signal terminal Rst; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0274] For example, the data transmission signal terminal DAS and the data signal terminal DA can be loaded with the same signal; as shown in FIG27 , the second electrode of the first transistor M1 can be coupled to the data signal terminal DA; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0275] In some embodiments of the present disclosure, as shown in FIG. 28 , the operation process of the pixel circuit includes: a reset stage F1 , a detection stage F2 , a compensation stage F3 , and a light emitting stage F4 .

[0276] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG26 as an example in combination with the signal timing diagram shown in FIG28 .

[0277] As shown in Figure 28, re1 represents the first reset signal of the first reset signal terminal RE1, re2 represents the second reset signal of the second reset signal terminal RE2, rst represents the reset signal of the reset signal terminal Rst, ss2 represents the second scan signal of the second scan signal terminal SS2, ss7 represents the seventh scan signal of the seventh scan signal terminal SS7, ss8 represents the eighth scan signal of the eighth scan signal terminal SS8, ss9 represents the ninth scan signal of the ninth scan signal terminal SS9, em represents the light-emitting control signal of the light-emitting control signal terminal EM, hf represents the pulse control signal of the pulse control signal terminal HF, da represents the data voltage signal of the data signal terminal DA, and das represents the data voltage signal of the data transmission signal terminal DAS.

[0278] Furthermore, a reset phase F1 , a detection phase F2 , a compensation phase F3 and a light emitting phase F4 in one display frame are selected.

[0279] In the reset phase F1, as shown in FIG29 , the first data transistor M01 is turned off under the control of the high level of the seventh scan signal ss7; the sixth transistor M06 is turned on under the control of the low level of the signal at the second electrode of the driving transistor M0; the seventh transistor M07 is turned off under the control of the high level of the eighth scan signal ss8; the eighth transistor M08 is turned off under the control of the high level of the ninth scan signal ss9; the second initialization transistor M2 is turned on under the control of the high level of the first reset signal re1; the third initialization transistor M3 is turned on under the control of the high level of the second reset signal re2; the fourth control transistor M4 is turned off under the control of the high level of the light emitting control signal em; the fifth control transistor M5 is turned off under the control of the high level of the first node N1; the sixth control transistor M6 is turned off under the control of the high level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2 or the eighth control transistor M8 is turned on under the control of the high level of the signal at the second control node N2; and the ninth control transistor M9 is turned on under the control of the high level of the reset signal rst. The turned-on ninth control transistor M9 provides the low-level data voltage signal da to the second control node N2; the turned-on seventh control transistor M7 provides the high-level pulse control signal hf to the first node N1; the turned-on eighth control transistor M8 provides the high-level light-emitting control signal em to the first node N1; the turned-on sixth transistor M06 provides the signal of the second power supply terminal VDD to the third node N03; the turned-on second initialization transistor M2 provides the signal of the first initialization signal terminal VINIT1 to the gate of the driving transistor M0; the turned-on third initialization transistor M3 provides the signal of the second initialization signal terminal VINIT2 to the second electrode of the light-emitting device L, then the voltage of the second electrode of the light-emitting device L is less than the voltage of the first electrode, and is in a reverse biased state.

[0280] In the detection stage F2, as shown in Figure 30, the first data transistor M01 is turned on under the control of the low level of the seventh scan signal ss7; the sixth transistor M06 is turned on under the control of the low level of the signal at the second electrode of the driving transistor M0; the seventh transistor M07 is turned on under the control of the low level of the eighth scan signal ss8; the eighth transistor M08 is turned on under the control of the low level of the ninth scan signal ss9; the second initialization transistor M2 is turned off under the control of the low level of the first reset signal re1; the third initialization transistor M3 is turned off under the control of the low level of the second reset signal re2; the fourth control transistor M4 is turned off under the control of the high level of the emission control signal em; the fifth control transistor M5 is turned off under the control of the high level of the first node N1; the sixth control transistor M6 is turned off under the control of the high level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2 or the eighth control transistor M8 is turned on under the control of the high level of the signal at the second control node N2; and the ninth control transistor M9 is turned off under the control of the low level of the reset signal rst. The turned-on seventh control transistor M7 provides a high-level pulse control signal hf to the first node N1; the turned-on eighth control transistor M8 provides a high-level light-emitting control signal em to the first node N1; the turned-on first data transistor M01 provides the signal das of the data transmission signal terminal DAS to the first electrode of the driving transistor M0, wherein, at this stage, the voltage of the signal of the data transmission signal terminal DAS is the same as the voltage of the signal of the second initialization signal terminal VINIT2; the turned-on eighth transistor M08 conducts the second electrode of the driving transistor M0 with the second electrode of the light-emitting device L; then the data voltage signal das is provided to the second electrode of the light-emitting device L through the first data transistor M01, the driving transistor M0 and the eighth transistor M08, so that the voltage of the signal of the second electrode of the light-emitting device L is less than the voltage of the signal of the first electrode of the light-emitting device L, and the light-emitting device is in reverse bias. The light-emitting device L, the eighth transistor M08, the sixth transistor M06, and the seventh transistor M07 form a path. Since the gate of the sixth transistor M06 is coupled to the second electrode of the driving transistor M0, if the voltage of the signal at the second electrode of the light-emitting device L changes, the voltage of the signal at the second electrode of the driving transistor M0 also changes accordingly. The sixth transistor M06 adjusts the voltage value of the signal input to the third node N03 according to the change in the voltage of the signal at the second electrode of the driving transistor M0. The turned-on seventh transistor M07 provides a detection signal to the detection signal terminal RD according to the signal at the third node N03, that is, the detection signal is output through the detection signal terminal RD. The voltage of the detection signal is inversely proportional to the brightness received by the light-emitting device L, that is, the greater the brightness received by the light-emitting device L, the smaller the voltage of the detection signal, and the smaller the brightness received by the light-emitting device L, the larger the voltage of the detection signal.

[0281] In the compensation stage F3, as shown in Figure 31, the first data transistor M01 is turned on under the control of the low level of the seventh scan signal ss7; the sixth transistor M06 is turned on under the control of the low level of the signal at the second electrode of the driving transistor M0; the seventh transistor M07 is turned off under the control of the high level of the eighth scan signal ss8; the eighth transistor M08 is turned off under the control of the high level of the ninth scan signal ss9; the second initialization transistor M2 is turned off under the control of the low level of the first reset signal re1; the third initialization transistor M3 is turned off under the control of the low level of the second reset signal re2; the fourth control transistor M4 is turned off under the control of the high level of the emission control signal em; the fifth control transistor M5 is turned off under the control of the high level of the first node N1; the sixth control transistor M6 is turned on under the control of the low level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2 or the eighth control transistor M8 is turned on under the control of the high level of the signal at the second control node N2; and the ninth control transistor M9 is turned off under the control of the low level of the reset signal rst. The turned-on seventh control transistor M7 provides the high-level pulse control signal hf to the first node N1; the turned-on eighth control transistor M8 provides the high-level light-emitting control signal em to the first node N1; the turned-on sixth transistor M06 provides the signal of the second power supply terminal VDD to the third node N03; the turned-on first data transistor M01 provides the data voltage signal das to the first electrode of the driving transistor M0; the turned-on sixth control transistor M6 connects the second electrode of the driving transistor M0 with the gate of the driving transistor M0.

[0282] In the light-emitting stage F4, as shown in Figure 32, the first data transistor M01 is turned off under the control of the high level of the seventh scan signal ss7; the sixth transistor M06 is turned off under the control of the high level of the signal at the second electrode of the driving transistor M0; the seventh transistor M07 is turned off under the control of the high level of the eighth scan signal ss8; the eighth transistor M08 is turned off under the control of the high level of the ninth scan signal ss9; the second initialization transistor M2 is turned off under the control of the low level of the first reset signal re1; the third initialization transistor M3 is turned off under the control of the low level of the second reset signal re2; the fourth control transistor M4 is turned on under the control of the low level of the light-emitting control signal em; the fifth control transistor M5 is turned off under the control of the low level of the first node N1; the sixth control transistor M6 is turned off under the control of the high level of the second scan signal ss2; the seventh control transistor M7 is turned on under the control of the low level of the signal at the second control node N2; the eighth control transistor M8 is turned on under the control of the high level of the signal at the second control node N2; and the ninth control transistor M9 is turned off under the control of the low level of the reset signal rst. The turned-on seventh control transistor M7 provides the pulse control signal hf to the first node N1; the turned-on eighth control transistor M8 provides the low-level light-emitting control signal em to the first node N1; the turned-on fourth control transistor M4 provides the signal of the second power supply terminal VDD to the first electrode of the driving transistor M0; the turned-on fifth control transistor M5 connects the second electrode of the light-emitting device L with the second electrode of the driving transistor M0; the driving transistor M0 generates a driving current for driving the light-emitting device L, driving the light-emitting device L to emit light.

[0283] It should be noted that, taking the brightness decay detection function as the basic application scenario, the W / L value of the first data transistor M01, the eighth transistor M08, and the driving transistor M0 in the pixel circuit is P, where W / L represents the channel width-to-length ratio of the first data transistor M01, the eighth transistor M08, and the driving transistor M0. The larger the W / L value, the smaller the on-resistance of the first data transistor M01, the eighth transistor M08, and the driving transistor M0. When implementing a remote interaction scenario (i.e., the pixel circuit implements a light touch function), the W / L value of the first data transistor M01, the eighth transistor M08, and the driving transistor M0 in the pixel circuit is P1. When the brightness of the laser pen is high (the resistance of the light-emitting device L is small during the detection phase), the resistance of the path formed by the first data transistor M01, the eighth transistor M08, and the driving transistor M0 is smaller during the detection phase, and the voltage change of the light-emitting device L in different states is more obvious, then P1>P. When implementing the fingerprint recognition scenario (i.e., the pixel circuit implements the fingerprint detection function), the W / L value of the first data transistor M01, the eighth transistor M08, and the driving transistor M0 in the pixel circuit is P2. Since the brightness change is small when a finger touches (in the detection stage, the resistance of the light-emitting device L is large), and the brightness is low, it is reflected light. Therefore, the greater the resistance of the path formed by the first data transistor M01, the eighth transistor M08, and the driving transistor M0 in the pixel circuit, the more obvious the voltage change of the light-emitting device L in different states, and P2 <P。

[0284] The present disclosure provides some structural diagrams of pixel circuits, as shown in Figure 33, which are modified from the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0285] In some other embodiments of the present disclosure, as shown in FIG33 , the driving circuit 100 includes: a driving transistor M0, an initialization circuit 111, a detection circuit 112, a potential selection circuit 113, a data writing circuit 114, a first control circuit 115, and a second control circuit 116;

[0286] The initialization circuit 111 is coupled to the second electrode of the light emitting device L and is configured to provide a signal from the first initialization signal terminal VINIT1 to the second electrode of the light emitting device L in response to a signal from the first reset signal terminal RE1 during a reset phase.

[0287] The detection circuit 112 is coupled to the second electrode of the driving transistor M0 and is configured to provide a signal from the second power supply terminal VDD to the first node N1 in response to a signal from the second electrode of the driving transistor M0 during a detection phase, and to conduct electricity between the first node N1 and the detection signal terminal RD in response to a signal from the first scan signal terminal SS1, thereby outputting a detection signal through the detection signal terminal RD.

[0288] The potential selection circuit 113 is coupled to the first electrode of the driving transistor M0 and is configured to respond to the signal of the second scanning signal terminal SS2 during the reset phase, the compensation phase, and the light-emitting phase to provide the signal of the second power supply terminal VDD to the first electrode of the driving transistor M0, and respond to the signal of the second initialization signal terminal VINIT2 during the compensation phase and the light-emitting phase to provide the signal of the second initialization signal terminal VINIT2 to the first electrode of the driving transistor M0;

[0289] The data writing circuit 114 is coupled to the second node N2 and is configured to provide a data voltage signal of the data signal terminal DA to the second node N2 in response to a signal of the third scan signal terminal SS3 during the compensation phase.

[0290] The first control circuit 115 is coupled to the gate and the second electrode of the driving transistor M0 and is configured to turn on the gate and the second electrode of the driving transistor M0 in response to the signal of the second reset signal terminal RE2 during the reset phase and the compensation phase;

[0291] The second control circuit 116 is coupled to the second electrode of the driving transistor M0, the second node N2 and the second electrode of the light-emitting device L, and is configured to respond to the signal of the light-emitting control signal terminal EM in the reset stage, the detection stage and the light-emitting stage, and provide the signal of the first power supply terminal VSS to the second node N2 to turn on the second electrode of the driving transistor M0 and the second electrode of the light-emitting device L.

[0292] Exemplarily, the pixel circuits in each row of sub-pixels share the same potential selection circuit.

[0293] For example, the first scan signal terminal SS1 and the second scan signal terminal SS2 may be loaded with the same signal, which can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0294] For example, the first reset signal terminal RE1 and the second reset signal terminal RE2 can be loaded with the same signal, which can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0295] In some other embodiments of the present disclosure, as shown in Figure 34, the detection circuit 112 includes: a ninth transistor M9 and a tenth transistor M10; wherein, the gate of the ninth transistor M9 is coupled to the second electrode of the driving transistor M0, the first electrode of the ninth transistor M9 is coupled to the second power supply terminal VDD, and the second electrode of the ninth transistor M9 is coupled to the first node N1; the gate of the tenth transistor M10 is coupled to the first scanning signal terminal SS1, the first electrode of the tenth transistor M10 is coupled to the first node N1, and the second electrode of the tenth transistor M10 is coupled to the detection signal terminal RD.

[0296] Exemplarily, the ninth transistor M9 can be turned on under the control of the effective level of the signal at the second electrode of the driving transistor M0, and can be turned off under the control of the inactive level of the signal at the second electrode of the driving transistor M0. For example, the ninth transistor M9 can be set as an N-type transistor, then the effective level of the signal at the second electrode of the driving transistor M0 is a high level, and the inactive level of the signal at the second electrode of the driving transistor M0 is a low level. Alternatively, the ninth transistor M9 can be set as a P-type transistor, then the effective level of the signal at the second electrode of the driving transistor M0 is a low level, and the inactive level of the signal at the second electrode of the driving transistor M0 is a high level.

[0297] Exemplarily, the tenth transistor M10 can be turned on under the control of the active level of the first scan signal transmitted on the first scan signal terminal SS1, and can be turned off under the control of the inactive level of the first scan signal. For example, the tenth transistor M10 can be configured as an N-type transistor, in which case the active level of the first scan signal is a high level, and the inactive level of the first scan signal is a low level. Alternatively, the tenth transistor M10 can be configured as a P-type transistor, in which case the active level of the first scan signal is a low level, and the inactive level of the first scan signal is a high level.

[0298] In some other embodiments of the present disclosure, as shown in Figure 34, the potential selection circuit 113 includes: an eleventh transistor M11 and a twelfth transistor M12; wherein, the gate of the eleventh transistor M11 is coupled to the second scan signal terminal SS2, the first electrode of the eleventh transistor M11 is coupled to the second power supply terminal VDD, and the second electrode of the eleventh transistor M11 is coupled to the first electrode of the driving transistor M0; the gate of the twelfth transistor M12 is coupled to the second initialization signal terminal VINIT2, the first electrode of the twelfth transistor M12 is coupled to the first electrode of the driving transistor M0, and the second electrode of the twelfth transistor M12 is coupled to the second initialization signal terminal VINIT2.

[0299] Exemplarily, the voltage of the signal at the second initialization signal terminal VINIT2 is lower than the voltage of the signal at the first initialization signal terminal VINIT1 , and the voltage of the signal at the first initialization signal terminal VINIT1 is lower than the voltage of the signal at the first power supply terminal VSS.

[0300] Exemplarily, the eleventh transistor M11 can be turned on under the control of the active level of the second scan signal transmitted on the second scan signal terminal SS1, and can be turned off under the control of the inactive level of the second scan signal. For example, the eleventh transistor M11 can be set as an N-type transistor, in which case the active level of the second scan signal is a high level, and the inactive level of the second scan signal is a low level. Alternatively, the eleventh transistor M11 can be set as a P-type transistor, in which case the active level of the second scan signal is a low level, and the inactive level of the second scan signal is a high level.

[0301] Exemplarily, as shown in Figure 34, the initialization circuit 111 includes: a first transistor T1; wherein, the gate of the first transistor T1 is coupled to the first reset signal terminal RE1, the first electrode of the first transistor T1 is coupled to the second electrode of the light-emitting device L, and the second electrode of the first transistor T1 is coupled to the first initialization signal terminal VINIT1.

[0302] Exemplarily, the first transistor T1 can be turned on under the control of the active level of the first reset signal transmitted on the first reset signal terminal RE1, and can be turned off under the control of the inactive level of the first reset signal. For example, the first transistor T1 can be configured as an N-type transistor, in which case the active level of the first reset signal is a high level, and the inactive level of the first reset signal is a low level. Alternatively, the first transistor T1 can be configured as a P-type transistor, in which case the active level of the first reset signal is a low level, and the inactive level of the first reset signal is a high level.

[0303] Exemplarily, as shown in Figure 34, the data write circuit 114 includes: a second transistor T2; wherein the gate of the second transistor T2 is coupled to the third scan signal terminal SS3, the first electrode of the second transistor T2 is coupled to the second node N2, and the second electrode of the second transistor T2 is coupled to the data signal terminal DA.

[0304] Exemplarily, the second transistor T2 can be turned on under the control of the active level of the third scan signal transmitted on the third scan signal terminal SS3, and can be turned off under the control of the inactive level of the third scan signal. For example, the second transistor T2 can be set as an N-type transistor, in which case the active level of the third scan signal is a high level, and the inactive level of the third scan signal is a low level. Alternatively, the second transistor T2 can be set as a P-type transistor, in which case the active level of the third scan signal is a low level, and the inactive level of the third scan signal is a high level.

[0305] Exemplarily, as shown in Figure 34, the first control circuit 115 includes: a third transistor T3 and a first capacitor C1; the gate of the third transistor T3 is coupled to the second reset signal terminal RE2, the first electrode of the third transistor T3 is coupled to the second electrode of the driving transistor M0, and the second electrode of the third transistor T3 is coupled to the gate of the driving transistor M0; the first electrode of the first capacitor C1 is coupled to the gate of the driving transistor M0, and the second electrode of the first capacitor C1 is coupled to the second node N2.

[0306] Exemplarily, the third transistor T3 can be turned on under the control of the active level of the second reset signal transmitted on the second reset signal terminal RE2, and can be turned off under the control of the inactive level of the second reset signal. For example, the third transistor T3 can be configured as an N-type transistor, in which case the active level of the second reset signal is a high level, and the inactive level of the second reset signal is a low level. Alternatively, the third transistor T3 can be configured as a P-type transistor, in which case the active level of the second reset signal is a low level, and the inactive level of the second reset signal is a high level.

[0307] Exemplarily, as shown in Figure 34, the second control circuit 116 includes: a fourth transistor T4 and a fifth transistor T5; wherein, the gate of the fourth transistor T4 is coupled to the light-emitting control signal terminal EM, the first electrode of the fourth transistor T4 is coupled to the first power supply terminal VSS, and the second electrode of the fourth transistor T4 is coupled to the second node N2; the gate of the fifth transistor T5 is coupled to the light-emitting control signal terminal EM, the first electrode of the fifth transistor T5 is coupled to the second electrode of the driving transistor M0, and the second electrode of the fifth transistor T5 is coupled to the second electrode of the light-emitting device L.

[0308] Exemplarily, the fourth transistor T4 and the fifth transistor T5 can be turned on under the control of the active level of the light-emitting control signal transmitted on the light-emitting control signal terminal EM, and can be turned off under the control of the inactive level of the light-emitting control signal. For example, the fourth transistor T4 and the fifth transistor T5 can be configured as N-type transistors, in which case the active level of the light-emitting control signal is a high level, and the inactive level of the light-emitting control signal is a low level. Alternatively, the fourth transistor T4 and the fifth transistor T5 can be configured as P-type transistors, in which case the active level of the light-emitting control signal is a low level, and the inactive level of the light-emitting control signal is a high level.

[0309] In some other embodiments of the present disclosure, as shown in FIG35 , the operation process of the pixel circuit includes: a reset stage F1 , a detection stage F2 , a compensation stage F3 and a light emitting stage F4 .

[0310] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG34 as an example and combining it with the signal timing diagram shown in FIG35 .

[0311] As shown in Figure 35, re1 represents the first reset signal of the first reset signal terminal RE1, re2 represents the second reset signal of the second reset signal terminal RE2, ss1 represents the first scanning signal of the first scanning signal terminal SS1, ss2 represents the second scanning signal of the second scanning signal terminal SS2, ss3 represents the third scanning signal of the third scanning signal terminal SS3, and em represents the light-emitting control signal of the light-emitting control signal terminal EM.

[0312] Furthermore, a reset phase F1 , a detection phase F2 , a compensation phase F3 and a light emitting phase F4 in one display frame are selected.

[0313] In the reset stage F1, as shown in Figure 36, the ninth transistor M9 is turned on under the control of the low level of the signal at the second electrode of the driving transistor M0; the tenth transistor M10 is turned off under the control of the high level of the first scanning signal ss1; the eleventh transistor M11 is turned on under the control of the high level of the second scanning signal ss2; the first transistor T1 is turned on under the control of the low level of the first repeat signal re1; the second transistor T2 is turned off under the control of the high level of the third scanning signal ss3; the third transistor T3 is turned on under the control of the low level of the second repeat signal re2; the fourth transistor T4 is turned on under the control of the low level of the light-emitting control signal em; and the fifth transistor T5 is turned on under the control of the low level of the light-emitting control signal em. The eleventh transistor M11 is turned on and provides the signal of the second power supply terminal VDD to the first electrode of the driving transistor M0; the ninth transistor M9 is turned on and provides the signal of the second power supply terminal VDD to the first node N1; the first transistor T1 is turned on and provides the signal of the first initialization signal terminal VINIT1 to the second electrode of the light-emitting device L; the fifth transistor T5 is turned on and connects the second electrode of the driving transistor M0 with the second electrode of the light-emitting device L; the third transistor T3 is turned on and connects the second electrode of the driving transistor M0 with the gate of the driving transistor M0, then the voltage value Vg of the gate of the driving transistor M0 is Vinit1, where Vinit1 represents the voltage value of the signal of the first initialization signal terminal VINIT1; the fourth transistor T4 is turned on and provides the signal of the first power supply terminal VSS to the second node N2, then the voltage value VN2 of the second node N2 is Vss, where Vss represents the voltage value of the signal of the first power supply terminal VSS.

[0314] In the detection stage F2, as shown in Figure 37, the ninth transistor M9 is turned on under the control of the low level of the signal at the second electrode of the driving transistor M0; the tenth transistor M10 is turned on under the control of the low level of the first scanning signal ss1; the eleventh transistor M11 is turned off under the control of the low level of the second scanning signal ss2; the twelfth transistor M12 is turned on under the control of the low level of the signal at the second initialization signal end; the first transistor T1 is turned off under the control of the high level of the first repeat signal re1; the second transistor T2 is turned off under the control of the high level of the third scanning signal ss3; the third transistor T3 is turned off under the control of the high level of the second repeat signal re2; the fourth transistor T4 is turned on under the control of the low level of the light-emitting control signal em; and the fifth transistor T5 is turned on under the control of the low level of the light-emitting control signal em. The conductive fourth transistor T4 provides the signal of the first power supply terminal VSS to the second node N2; the conductive twelfth transistor M12 provides the signal of the second initialization signal terminal VINIT2 to the first electrode of the driving transistor M0, then the voltage value Vx of the first electrode of the driving transistor M0 is Vinit2, wherein Vinit2 represents the voltage value of the signal of the second initialization signal terminal VINIT2; the conductive fifth transistor T5 connects the second electrode of the driving transistor M0 to the second electrode of the light-emitting device L, then the voltage value of the second electrode of the light-emitting device L is Vinit2, and the voltage value of the first electrode of the light-emitting device L is Vss, wherein Vss>Vinit2, then the light-emitting device L is in a reverse bias state; the light-emitting device L, the fifth transistor T5, the ninth transistor M9 and The tenth transistor M10 forms a path. Since the gate of the ninth transistor M9 is coupled to the second electrode of the driving transistor M0, if the voltage of the signal of the second electrode of the light-emitting device L changes, the voltage of the second electrode signal of the driving transistor M0 also changes accordingly. The ninth transistor M9 adjusts the voltage value of the signal input to the first node N1 according to the change in the voltage of the second electrode signal of the driving transistor M0. The turned-on tenth transistor M10 provides a detection signal to the detection signal terminal RD according to the signal of the first node N1, that is, the detection signal is output through the detection signal terminal RD; wherein the voltage of the detection signal is inversely proportional to the brightness received by the light-emitting device L, that is, the greater the brightness received by the light-emitting device L, the smaller the voltage of the detection signal; and the smaller the brightness received by the light-emitting device L, the larger the voltage of the detection signal.

[0315] In the compensation stage F3, as shown in Figure 38, the ninth transistor M9 is turned off under the control of the high level of the signal at the second electrode of the driving transistor M0; the tenth transistor M10 is turned off under the control of the high level of the first scanning signal ss1; the eleventh transistor M11 is turned on under the control of the high level of the second scanning signal ss2; the first transistor T1 is turned on under the control of the low level of the first repeat signal re1; the second transistor T2 is turned on under the control of the low level of the third scanning signal ss3; the third transistor T3 is turned on under the control of the low level of the second repeat signal re2; the fourth transistor T4 is turned off under the control of the high level of the light-emitting control signal em; and the fifth transistor T5 is turned off under the control of the high level of the light-emitting control signal em. The eleventh transistor M11 is turned on and provides the signal of the second power supply terminal VDD to the first electrode of the driving transistor M0; the first transistor T1 is turned on and provides the signal of the first initialization signal terminal VINIT1 to the second electrode of the light-emitting device L; the second transistor T2 is turned on and provides the data voltage signal of the data signal terminal DA to the second node N2, then the voltage value VN2 of the second node N2 is Vda, where Vda represents the voltage value of the data voltage signal; the third transistor T3 is turned on and connects the gate of the driving transistor M0 and the second electrode of the driving transistor M0; the data voltage signal of the second node N2 is coupled to the gate of the driving transistor M0 through the first capacitor C1 to compensate for the threshold voltage Vth of the driving transistor M0, then the voltage value Vg of the gate of the driving transistor M0 is Vda+Vth, where Vth represents the threshold voltage of the driving transistor M0.

[0316] In the light-emitting stage F4, as shown in Figure 39, the ninth transistor M9 is turned off under the control of the high level of the signal at the second electrode of the driving transistor M0; the tenth transistor M10 is turned off under the control of the high level of the first scanning signal ss1; the eleventh transistor M11 is turned on under the control of the high level of the second scanning signal ss2; the first transistor T1 is turned off under the control of the high level of the first repeat signal re1; the second transistor T2 is turned off under the control of the high level of the third scanning signal ss3; the third transistor T3 is turned off under the control of the high level of the second repeat signal re2; the fourth transistor T4 is turned on under the control of the low level of the light-emitting control signal em; and the fifth transistor T5 is turned on under the control of the low level of the light-emitting control signal em. The eleventh transistor M11 is turned on, providing the signal of the second power supply terminal VDD to the first electrode of the driving transistor M0; the fifth transistor T5 is turned on, connecting the second electrode of the driving transistor M0 to the second electrode of the light-emitting device L; the fourth transistor T4 is turned on, providing the signal of the first power supply terminal VSS to the second node N2, then the voltage value VN2 of the second node N2 is Vss, the voltage value of the second node N2 jumps from Vda to Vss, the data voltage signal is written to the gate of the driving transistor M0, then the voltage difference between the gate and source of the driving transistor M0 is Vgs=Vdd+Vth+Vss-Vda-Vdd=Vss-Vda+Vth, and the threshold voltage Vth of the driving transistor M0 is compensated.

[0317] It should be noted that, with the realization of brightness attenuation detection function as the basic application scenario, the W / L value of the driving transistor M0, the twelfth transistor M12, and the fifth transistor T5 in the pixel circuit is P, where W / L represents the channel width-to-length ratio of the driving transistor M0, the twelfth transistor M12, and the fifth transistor T5. The larger the W / L value, the smaller the on-resistance of the driving transistor M0, the twelfth transistor M12, and the fifth transistor T5. When realizing the remote interaction scenario (i.e., the pixel circuit realizes the light touch function), the W / L value of the driving transistor M0, the twelfth transistor M12, and the fifth transistor T5 in the pixel circuit is P1. When the brightness of the laser pen is high (in the detection phase, the resistance of the light-emitting device L is small), therefore, in the detection phase, the smaller the resistance of the path formed by the driving transistor M0, the twelfth transistor M12, and the fifth transistor T5, the more obvious the voltage change of the light-emitting device L in different states, then P1>P. When implementing the fingerprint recognition scenario (i.e., the pixel circuit implements the fingerprint detection function), the W / L value of the driving transistor M0, the twelfth transistor M12, and the fifth transistor T5 in the pixel circuit is P2. Since the brightness change is small when a finger touches (in the detection stage, the resistance of the light-emitting device L is large), and the brightness is low, it is reflected light. Therefore, the greater the resistance of the path formed by the driving transistor M0, the twelfth transistor M12, and the fifth transistor T5 in the pixel circuit, the more obvious the voltage change of the light-emitting device L in different states, and P2 <P。

[0318] The present disclosure provides some further structural diagrams of pixel circuits, as shown in Figure 40, which are variations of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0319] In some other embodiments of the present disclosure, as shown in FIG40 , the driving circuit 100 includes: a driving transistor M0 , a detection circuit 121 , a data writing circuit 122 , and a potential selection circuit 123 ;

[0320] The detection circuit 121 is coupled to the first electrode and the second electrode of the driving transistor M0 and is configured to respond to the signal of the second electrode of the driving transistor M0 and the signal of the first scanning signal terminal SS1 during the reset phase, the detection phase, and the data writing phase, provide the signal of the first electrode of the driving transistor M0 to the detection signal terminal RD, output the detection signal through the detection signal terminal RD, and connect the second electrode of the driving transistor M0 to the detection signal terminal RD in response to the signal of the second scanning signal terminal SS2 during the compensation phase;

[0321] The data writing circuit 122 is coupled to the gate of the driving transistor M0 and is configured to provide a data voltage signal of the data signal terminal DA to the gate of the driving transistor M0 in response to the signal of the third scanning signal terminal SS3 during the reset phase, the detection phase, the data writing phase, and the compensation phase;

[0322] The potential selection circuit 123 is coupled to the first electrode of the driving transistor M0 and is configured to respond to the signal of the fourth scanning signal terminal SS4 in the reset phase, the detection phase and the data writing phase to provide the signal of the initialization signal terminal VINIT to the first electrode of the driving transistor M0, and respond to the signal of the second power supply terminal VDD in the compensation phase to provide the signal of the second power supply terminal VDD to the second electrode of the driving transistor M0.

[0323] For example, the first scan signal terminal SS1 and the fourth scan signal terminal SS4 may be loaded with the same signal; this can reduce the number of signal lines, reduce the space occupied by wiring, and simplify circuit design.

[0324] Exemplarily, the voltage value of the signal at the initialization signal terminal VINIT is smaller than the voltage value of the signal at the first power terminal VSS, and the voltage value of the signal at the first power terminal VSS is smaller than the voltage value of the signal at the second power terminal VDD.

[0325] Exemplarily, the pixel circuits in each row of sub-pixels share the same potential selection circuit.

[0326] In some other embodiments of the present disclosure, as shown in Figure 41, the detection circuit 121 includes: a thirteenth transistor M13, a fourteenth transistor M14 and a fifteenth transistor M15; wherein, the gate of the thirteenth transistor M13 is coupled to the second electrode of the driving transistor M0, the first electrode of the thirteenth transistor M13 is coupled to the first electrode of the driving transistor M0, and the second electrode of the thirteenth transistor M13 is coupled to the first electrode of the fourteenth transistor M14; the gate of the fourteenth transistor M14 is coupled to the first scan signal terminal SS1, and the second electrode of the fourteenth transistor M14 is coupled to the detection signal terminal RD; the gate of the fifteenth transistor M14 is coupled to the second scan signal terminal SS2, the first electrode of the fifteenth transistor M15 is coupled to the second electrode of the driving transistor M0, and the second electrode of the fifteenth transistor M15 is coupled to the detection signal terminal RD.

[0327] Exemplarily, the thirteenth transistor M13 can be turned on under the control of the effective level of the signal at the second electrode of the driving transistor M0, and can be turned off under the control of the inactive level of the signal at the second electrode of the driving transistor M0. For example, the thirteenth transistor M13 can be set as an N-type transistor, then the effective level of the signal at the second electrode of the driving transistor M0 is a high level, and the inactive level of the signal at the second electrode of the driving transistor M0 is a low level. Alternatively, the thirteenth transistor M13 can be set as a P-type transistor, then the effective level of the signal at the second electrode of the driving transistor M0 is a low level, and the inactive level of the signal at the second electrode of the driving transistor M0 is a high level.

[0328] Exemplarily, the fourteenth transistor M14 can be turned on under the control of the active level of the first scan signal transmitted on the first scan signal terminal SS1, and can be turned off under the control of the inactive level of the first scan signal. For example, the fourteenth transistor M14 can be set as an N-type transistor, in which case the active level of the first scan signal is a high level, and the inactive level of the first scan signal is a low level. Alternatively, the fourteenth transistor M14 can be set as a P-type transistor, in which case the active level of the first scan signal is a low level, and the inactive level of the first scan signal is a high level.

[0329] Exemplarily, the fifteenth transistor M15 can be turned on under the control of the active level of the second scan signal transmitted on the second scan signal terminal SS2, and can be turned off under the control of the inactive level of the second scan signal. For example, the fifteenth transistor M15 can be set as an N-type transistor, in which case the active level of the second scan signal is a high level, and the inactive level of the second scan signal is a low level. Alternatively, the fifteenth transistor M15 can be set as a P-type transistor, in which case the active level of the second scan signal is a low level, and the inactive level of the second scan signal is a high level.

[0330] In some other embodiments of the present disclosure, as shown in Figure 41, the potential selection circuit 123 includes: a sixteenth transistor M16 and a seventeenth transistor M17; wherein, the gate of the sixteenth transistor M16 is coupled to the fourth scan signal terminal SS4, the first electrode of the sixteenth transistor M16 is coupled to the initialization signal terminal VINIT, and the second electrode of the sixteenth transistor M16 is coupled to the first electrode of the driving transistor M0; the gate of the seventeenth transistor M17 is coupled to the second power supply terminal VDD, the first electrode of the seventeenth transistor M17 is coupled to the second power supply terminal VDD, and the second electrode of the seventeenth transistor M17 is coupled to the first electrode of the driving transistor M0.

[0331] Exemplarily, the sixteenth transistor M16 can be turned on under the control of the active level of the fourth scan signal transmitted on the fourth scan signal terminal SS4, and can be turned off under the control of the inactive level of the fourth scan signal. For example, the sixteenth transistor M16 can be set as an N-type transistor, in which case the active level of the fourth scan signal is a high level, and the inactive level of the fourth scan signal is a low level. Alternatively, the sixteenth transistor M16 can be set as a P-type transistor, in which case the active level of the fourth scan signal is a low level, and the inactive level of the fourth scan signal is a high level.

[0332] Exemplarily, as shown in Figure 41, the data writing circuit 122 includes: a first transistor T1 and a first capacitor C1; wherein, the gate of the first transistor T1 is coupled to the third scan signal terminal SS3, the first electrode of the first transistor T1 is coupled to the data signal terminal DA, and the second electrode of the first transistor T1 is coupled to the gate of the driving transistor M0; the first electrode of the first capacitor C1 is coupled to the gate of the driving transistor M0, and the second electrode of the first capacitor C1 is coupled to the second electrode of the light-emitting device L.

[0333] Exemplarily, the first transistor T1 can be turned on under the control of the active level of the third scan signal transmitted on the third scan signal terminal SS3, and can be turned off under the control of the inactive level of the third scan signal. For example, the first transistor T1 can be set as an N-type transistor, in which case the active level of the third scan signal is a high level, and the inactive level of the third scan signal is a low level. Alternatively, the first transistor T1 can be set as a P-type transistor, in which case the active level of the third scan signal is a low level, and the inactive level of the third scan signal is a high level.

[0334] Exemplarily, as shown in FIG42 , the operation process of the pixel circuit includes: a reset phase F1 , a detection phase F2 , a data writing phase F5 , and a compensation phase F3 .

[0335] Illustratively, as shown in FIG43 , an embodiment of the present disclosure further provides a gate drive circuit 300, which is coupled to the first scan signal terminal SS1, the second scan signal terminal SS2, the third scan signal terminal SS3, and the fourth scan signal terminal SS4 in the pixel circuit, and is configured to respond to the signal of the second switching signal terminal SW2 in the detection phase or the data writing phase, and provide the signal of the first potential signal terminal VGL to the second scan signal terminal SS2, and respond to the signal of the first switching signal terminal SW1 in the compensation phase F3, and provide the signal of the first potential signal terminal VGL to the first scan signal terminal SS1 and the fourth scan signal terminal SS4. The gate drive circuit 300 includes: a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3 and a fourth thin film transistor M4; the gate of the first thin film transistor M1 is coupled to the second switch signal terminal SW2, the first electrode of the first thin film transistor M1 is coupled to the first potential signal terminal VGL, and the second electrode of the first thin film transistor M1 is coupled to the second scan signal terminal SS2; the gate of the second thin film transistor M2 is coupled to the first switch signal terminal SW1, the first electrode of the second thin film transistor M2 is coupled to the third scan signal terminal SS3, and the gate of the second thin film transistor M2 is coupled to the first switch signal terminal SW1. The second electrode of the third thin film transistor M3 is coupled to the second scan signal terminal SS2; the gate of the third thin film transistor M3 is coupled to the second switching signal terminal SW2, the first electrode of the third thin film transistor M3 is coupled to the third scan signal terminal SS3, and the second electrode of the third thin film transistor M3 is coupled to the first scan signal terminal SS1 and the fourth scan signal terminal SS4; the gate of the fourth thin film transistor M4 is coupled to the first switching signal terminal SW1, the first electrode of the fourth thin film transistor M4 is coupled to the first potential signal terminal VGL, and the second electrode of the fourth thin film transistor M4 is coupled to the first scan signal terminal SS1 and the fourth scan signal terminal SS4.

[0336] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG41 as an example and combining it with the signal timing diagram shown in FIG42 .

[0337] As shown in Figure 42, ss1 represents the first scanning signal of the first scanning signal terminal SS1, ss2 represents the second scanning signal of the second scanning signal terminal SS2, ss3 represents the third scanning signal of the third scanning signal terminal SS3, ss4 represents the fourth scanning signal of the fourth scanning signal terminal SS4, and da represents the data voltage signal of the data signal terminal DA.

[0338] Furthermore, a reset phase F1 , a detection phase F2 , a data writing phase F5 and a compensation phase F3 in one display frame are selected.

[0339] In the reset stage F1, as shown in Figure 44, the first transistor T1 is turned on under the control of the high level of the third scan signal ss3, the fourteenth transistor M14 is turned on under the control of the high level of the first scan signal ss1, the fifteenth transistor M15 is turned off under the control of the low level of the second scan signal ss2, and the sixteenth transistor M16 is turned on under the control of the high level of the fourth scan signal ss4. The turned-on first transistor T1 provides the high-level data voltage signal da to the gate of the driving transistor M0, and the driving transistor M0 is turned on under the control of the high-level data voltage signal da; the turned-on sixteenth transistor M16 provides the signal of the initialization signal terminal VINIT to the first electrode of the driving transistor M0, and the turned-on driving transistor M0 connects the second electrode of the sixteenth transistor M16 to the second electrode of the light-emitting device L, and the voltage of the signal at the second electrode of the light-emitting device L is close to Vinit, where Vinit represents the voltage value of the signal at the initialization signal terminal VINIT; since the voltage value of the signal at the initialization signal terminal VINIT is less than the voltage value of the signal at the first power supply terminal VSS, the voltage of the signal at the second electrode of the light-emitting device L is less than the voltage of the signal at the first electrode of the light-emitting device L, so that the light-emitting device L is in a reverse biased state.

[0340] In the detection stage F2, as shown in Figure 45, the first transistor T1 is turned on under the control of the high level of the third scanning signal ss3, the fourteenth transistor M14 is turned on under the control of the high level of the first scanning signal ss1, the fifteenth transistor M15 is turned off under the control of the low level of the second scanning signal ss2, and the sixteenth transistor M16 is turned on under the control of the high level of the fourth scanning signal ss4. The turned-on first transistor T1 provides the low-level data voltage signal da to the gate of the driving transistor M0, and the driving transistor M0 is turned off under the control of the low-level data voltage signal da; the light-emitting device L is in a reverse biased state; since the gate of the thirteenth transistor M13 is coupled to the signal of the second electrode of the light-emitting device L, if the voltage of the signal of the second electrode of the light-emitting device L changes, the voltage of the signal of the gate of the thirteenth transistor M13 also changes accordingly, and the thirteenth transistor M13 adjusts the voltage of the signal input to the fourteenth transistor M14 according to the voltage of the signal of the second electrode of the light-emitting device L; the turned-on fourteenth transistor M14 provides a detection signal to the detection signal terminal RD according to the signal input by the thirteenth transistor M13, that is, outputs the detection signal through the detection signal terminal RD; wherein the voltage of the detection signal is proportional to the brightness received by the light-emitting device L, that is, the greater the brightness received by the light-emitting device L, the greater the voltage of the detection signal, and the smaller the brightness received by the light-emitting device L, the smaller the voltage of the detection signal.

[0341] In the data writing phase F5, as shown in FIG44 , the first transistor T1 is turned on by the high level of the third scan signal ss3, the fourteenth transistor M14 is turned on by the high level of the first scan signal ss1, the fifteenth transistor M15 is turned off by the low level of the second scan signal ss2, and the sixteenth transistor M16 is turned on by the high level of the fourth scan signal ss4. The turned-on sixteenth transistor M16 provides the signal of the initialization signal terminal VINIT to the first electrode of the driving transistor M0; the turned-on first transistor T1 provides the data voltage signal da to the gate of the driving transistor M0; the driving transistor M0 generates a driving current that drives the light-emitting device L to emit light based on the data voltage signal da, thereby driving the light-emitting device L to emit light; the turned-on thirteenth transistor M13 and the turned-on fourteenth transistor M14 connect the second electrode of the sixteenth transistor M16 to the detection signal terminal RD.

[0342] In compensation phase F3, as shown in FIG46 , the first transistor T1 is turned on by the high level of the third scan signal ss3, the fourteenth transistor M14 is turned off by the low level of the first scan signal ss1, the fifteenth transistor M15 is turned on by the high level of the second scan signal ss2, and the sixteenth transistor M16 is turned off by the low level of the fourth scan signal ss4. The turned-on first transistor T1 provides the signal from the data signal terminal DA to the gate of the drive transistor M0; the turned-on seventeenth transistor M17 provides the signal from the second power supply terminal VDD to the first electrode of the drive transistor M0; and the turned-on fifteenth transistor M15 connects the second electrode of the drive transistor M0 to the detection signal terminal RD.

[0343] It should be noted that, with the realization of brightness attenuation detection function as the basic application scenario, the W / L value of the driving transistor M0 and the sixteenth transistor M16 in the pixel circuit is P, where W / L represents the channel width-to-length ratio of the driving transistor M0 and the sixteenth transistor M16. The larger the value of W / L, the smaller the on-resistance of the driving transistor M0 and the sixteenth transistor M16. When realizing the remote interaction scenario (that is, the pixel circuit realizes the light touch function), the W / L value of the driving transistor M0 and the sixteenth transistor M16 in the pixel circuit is P1. When the brightness of the laser pen is high (in the detection stage, the resistance of the light-emitting device L is small), therefore, in the detection stage, the smaller the resistance of the path formed by the driving transistor M0 and the sixteenth transistor M16, the more obvious the voltage change of the light-emitting device L in different states, then P1>P. When implementing the fingerprint recognition scenario (i.e., the pixel circuit implements the fingerprint detection function), the W / L value of the driving transistor M0 and the sixteenth transistor M16 in the pixel circuit is P2. Since the brightness change is small when a finger touches (in the detection stage, the resistance of the light-emitting device L is large), and the brightness is low, it is reflected light. Therefore, the greater the resistance of the path formed by the driving transistor M0 and the sixteenth transistor M16 in the pixel circuit, the more obvious the voltage change of the light-emitting device L in different states, and P2 <P。

[0344] The present disclosure provides some further structural diagrams of pixel circuits, as shown in Figure 47, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0345] In some other embodiments of the present disclosure, as shown in Figure 47, the detection circuit 121 includes: a thirteenth transistor M13 and a fourteenth transistor M14; wherein, the first gate of the thirteenth transistor M13 is coupled to the second electrode of the driving transistor M0, the second gate of the thirteenth transistor M13 is coupled to the first scan signal terminal SS1, the first electrode of the thirteenth transistor M13 is coupled to the first electrode of the driving transistor M0, and the second electrode of the thirteenth transistor M13 is coupled to the first electrode of the fourteenth transistor M14; the gate of the fourteenth transistor M14 is coupled to the second scan signal terminal SS2, and the second electrode of the fourteenth transistor M14 is coupled to the detection signal terminal RD.

[0346] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG47 as an example and combining it with the signal timing diagram shown in FIG42 .

[0347] As shown in Figure 42, ss1 represents the first scanning signal of the first scanning signal terminal SS1, ss2 represents the second scanning signal of the second scanning signal terminal SS2, ss3 represents the third scanning signal of the third scanning signal terminal SS3, ss4 represents the fourth scanning signal of the fourth scanning signal terminal SS4, and da represents the data voltage signal of the data signal terminal DA.

[0348] Furthermore, a reset phase F1 , a detection phase F2 , a data writing phase F5 and a compensation phase F3 in one display frame are selected.

[0349] In the reset phase F1, as shown in FIG48 , the first transistor T1 is turned on by the high level of the third scan signal ss3, the fourteenth transistor M14 is turned off by the low level of the second scan signal ss2, and the sixteenth transistor M16 is turned on by the high level of the fourth scan signal ss4. The turned-on first transistor T1 provides the high level data voltage signal da to the gate of the driving transistor M0, turning the driving transistor M0 on by the high level data voltage signal da. The turned-on sixteenth transistor M16 provides the signal of the initialization signal terminal VINIT to the first electrode of the driving transistor M0. The turned-on driving transistor M0 connects the second electrode of the sixteenth transistor M16 to the second electrode of the light-emitting device L, and the voltage of the signal at the second electrode of the light-emitting device L approaches Vinit, where Vinit represents the voltage value of the signal at the initialization signal terminal VINIT. Since the voltage value of the signal at the initialization signal terminal VINIT is lower than the voltage value of the signal at the first power supply terminal VSS, the voltage of the signal at the second electrode of the light-emitting device L is lower than the voltage of the signal at the first electrode of the light-emitting device L, thereby placing the light-emitting device L in a reverse biased state.

[0350] In the detection stage F2, as shown in Figure 49, the first transistor T1 is turned on under the control of the high level of the third scanning signal ss3, the fourteenth transistor M14 is turned off under the control of the low level of the second scanning signal ss2, and the sixteenth transistor M16 is turned on under the control of the high level of the fourth scanning signal ss4. The turned-on first transistor T1 provides the low-level data voltage signal da to the gate of the driving transistor M0, and the driving transistor M0 is turned off under the control of the low-level data voltage signal da; the light-emitting device L is in a reverse biased state; since the gate of the thirteenth transistor M13 is coupled to the signal of the second electrode of the light-emitting device L, if the voltage of the signal of the second electrode of the light-emitting device L changes, the voltage of the signal of the first gate of the thirteenth transistor M13 also changes accordingly, and the thirteenth transistor M13 adjusts the voltage of the detection signal input to the detection signal terminal RD according to the voltage of the signal of the second electrode of the light-emitting device L, that is, the voltage of the detection signal output through the detection signal terminal RD will change; wherein, the voltage of the detection signal is proportional to the brightness received by the light-emitting device L, that is, the greater the brightness received by the light-emitting device L, the greater the voltage of the detection signal, and the smaller the brightness received by the light-emitting device L, the smaller the voltage of the detection signal.

[0351] In the data writing phase F5, as shown in FIG48 , the first transistor T1 is turned on by the high level of the third scan signal ss3, the fourteenth transistor M14 is turned off by the low level of the second scan signal ss2, and the sixteenth transistor M16 is turned on by the high level of the fourth scan signal ss4. The turned-on sixteenth transistor M16 provides the signal of the initialization signal terminal VINIT to the first electrode of the driving transistor M0; the turned-on first transistor T1 provides the data voltage signal da to the gate of the driving transistor M0; the driving transistor M0 generates a driving current that drives the light-emitting device L to emit light based on the data voltage signal da, thereby driving the light-emitting device L to emit light; the turned-on thirteenth transistor M13 connects the second electrode of the sixteenth transistor M16 to the detection signal terminal RD.

[0352] In compensation phase F3, as shown in FIG50 , the first transistor T1 is turned on by the high level of the third scan signal ss3, the fourteenth transistor M14 is turned on by the high level of the second scan signal ss2, and the sixteenth transistor M16 is turned off by the low level of the fourth scan signal ss4. The turned-on first transistor T1 provides the data voltage signal da to the gate of the drive transistor M0; the turned-on seventeenth transistor M17 provides the signal from the second power supply terminal VDD to the first electrode of the drive transistor M0; and the turned-on fourteenth transistor M14 connects the second electrode of the drive transistor M0 to the detection signal terminal RD.

[0353] It should be noted that, with the realization of brightness attenuation detection function as the basic application scenario, the W / L value of the driving transistor M0 and the sixteenth transistor M16 in the pixel circuit is P, where W / L represents the channel width-to-length ratio of the driving transistor M0 and the sixteenth transistor M16. The larger the value of W / L, the smaller the on-resistance of the driving transistor M0 and the sixteenth transistor M16. When realizing the remote interaction scenario (that is, the pixel circuit realizes the light touch function), the W / L value of the driving transistor M0 and the sixteenth transistor M16 in the pixel circuit is P1. When the brightness of the laser pen is high (in the detection stage, the resistance of the light-emitting device L is small), therefore, in the detection stage, the smaller the resistance of the path formed by the driving transistor M0 and the sixteenth transistor M16, the more obvious the voltage change of the light-emitting device L in different states, then P1>P. When implementing the fingerprint recognition scenario (i.e., the pixel circuit implements the fingerprint detection function), the W / L value of the driving transistor M0 and the sixteenth transistor M16 in the pixel circuit is P2. Since the brightness change is small when a finger touches (in the detection stage, the resistance of the light-emitting device L is large), and the brightness is low, it is reflected light. Therefore, the greater the resistance of the path formed by the driving transistor M0 and the sixteenth transistor M16 in the pixel circuit, the more obvious the voltage change of the light-emitting device L in different states, and P2 <P。

[0354] The present disclosure provides some further structural diagrams of pixel circuits, as shown in Figure 51, which are variations of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0355] In some other embodiments of the present disclosure, as shown in FIG51 , the driving circuit includes: a driving transistor M0, a data writing circuit 131, a light emitting control circuit 132, and a detection circuit 133;

[0356] The data writing circuit 131 is coupled to the gate of the driving transistor M0 and the first node N1, and is configured to respond to the signal of the first scanning signal terminal SS1 during the light emitting phase to provide the data voltage signal of the data signal terminal DA to the first node N1, and respond to the signal of the first node N1 to provide the signal of the first level signal terminal VGL or the signal of the second level signal terminal VGH to the gate of the driving transistor M0;

[0357] The light emitting control circuit 132 is coupled to the second electrode of the driving transistor M0 and the second electrode of the light emitting device L, and is configured to connect the second electrode of the driving transistor M0 and the second electrode of the light emitting device L in response to the signal of the light emitting control signal terminal EM during the detection phase and the light emitting phase;

[0358] The detection circuit 133 is coupled to the gate and the second electrode of the driving transistor M0, and is configured to respond to the signal of the gate of the driving transistor M0 in the detection phase, provide the signal of the initialization signal terminal VINIT to the second electrode of the driving transistor M0, respond to the signal of the second electrode of the light-emitting device L, provide the signal of the second power supply terminal VDD to the second node N2, respond to the signal of the second scan signal terminal SS2, provide the signal of the second node N2 to the detection signal terminal RD, and output the detection signal through the detection signal terminal RD.

[0359] Exemplarily, the voltage value of the signal at the initialization signal terminal VINIT is smaller than the voltage value of the signal at the first power supply terminal VSS.

[0360] Exemplarily, the first level signal terminal VGL is loaded with a low level signal; and the second level signal terminal VGH simulates a high level signal.

[0361] In some other embodiments of the present disclosure, as shown in Figure 52, the detection circuit 133 includes: an eighteenth transistor M18, a nineteenth transistor M19 and a twentieth transistor M20; wherein, the gate of the eighteenth transistor M18 is coupled to the gate of the driving transistor M0, the first electrode of the eighteenth transistor M18 is coupled to the initialization signal terminal VINIT, and the second electrode of the eighteenth transistor M18 is coupled to the second electrode of the driving transistor M0; the gate of the nineteenth transistor M19 is coupled to the second electrode of the light-emitting device L, the first electrode of the nineteenth transistor M19 is coupled to the second power supply terminal VDD, and the second electrode of the nineteenth transistor M19 is coupled to the second node N2; the gate of the twentieth transistor M20 is coupled to the signal of the second scan signal terminal SS2, the first electrode of the twentieth transistor M20 is coupled to the second node N2, and the second electrode of the twentieth transistor M20 is coupled to the detection signal terminal RD.

[0362] Exemplarily, as shown in FIG52, the data writing circuit 131 includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5; wherein the gate of the first transistor T1 is coupled to the first scan signal terminal SS1, the first electrode of the first transistor T1 is coupled to the data signal terminal DA, and the second electrode of the first transistor T1 is coupled to the first node N1; the gate of the second transistor T2 is coupled to the first node N1, the first electrode of the second transistor T2 is coupled to the second level signal terminal VGH, and the second electrode of the second transistor T2 is coupled to the gate of the third transistor T3. The gate is coupled; the first electrode of the third transistor T3 is coupled to the first node N1, and the second electrode of the third transistor T3 is coupled to the second level signal terminal VGH; the gate of the fourth transistor T4 is coupled to the gate of the driving transistor M0, the first electrode of the fourth transistor T4 is coupled to the gate of the fifth transistor T5, and the second electrode of the fourth transistor T4 is coupled to the first level signal terminal VGL; the gate of the fifth transistor T5 is coupled to the second electrode of the second transistor T2, the first electrode of the fifth transistor T5 is coupled to the first level signal terminal VGL, and the second electrode of the fifth transistor T5 is coupled to the gate of the driving transistor M0.

[0363] Exemplarily, as shown in Figure 52, the light-emitting control circuit 132 includes: a sixth transistor T6; wherein the gate of the sixth transistor T6 is coupled to the light-emitting control signal terminal EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor M0, and the second electrode of the sixth transistor T6 is coupled to the second electrode of the light-emitting device L.

[0364] In some other embodiments of the present disclosure, as shown in FIG53 , the operation process of the pixel circuit includes: a light emitting stage F1 and a detection stage F2.

[0365] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in Figure 52 as an example and combining it with the signal timing diagram shown in Figure 53.

[0366] As shown in FIG53 , ss1 represents the first scanning signal of the first scanning signal terminal SS1 , ss2 represents the second scanning signal of the second scanning signal terminal SS2 , and em represents the light emitting control signal of the light emitting control signal terminal EM.

[0367] In the light-emitting stage F1, as shown in FIG54, the first transistor T1 is turned on under the control of the low level of the first scanning signal ss1, and the turned-on first transistor T1 provides the low-level data voltage signal to the first node N1 and the gate of the driving transistor M0; the second transistor T2 is turned on under the control of the low level of the first node N1, and the turned-on second transistor T2 provides the high-level signal of the second-level signal terminal VGH to the gate of the fifth transistor T5; the fifth transistor T5 is turned on under the control of the high-level signal, and the turned-on fifth transistor T5 provides the low-level signal of the first-level signal terminal VGL to the first node N1. The third transistor T3 is turned off under the control of a high-level signal; the fourth transistor T4 is turned off under the control of a low-level signal; the eighteenth transistor M18 is turned off under the control of a low-level signal; the driving transistor M0 is turned on under the control of a low-level signal, and the turned-on driving transistor M0 provides the signal of the second power supply terminal VDD to the first electrode of the sixth transistor T6; the sixth transistor T6 is turned on under the control of a low-level light-emitting control signal em, and the turned-on sixth transistor T6 connects the second electrode of the driving transistor M0 to the second electrode of the light-emitting device L, thereby driving the light-emitting device L to emit light. The nineteenth transistor M19 is turned off under the control of a high-level signal at the second electrode of the light-emitting device L; the twentieth transistor M20 is turned on under the control of a low-level second scanning signal ss2, and the turned-on twentieth transistor M20 connects the second node N2 to the detection signal terminal RD.

[0368] In the detection phase F2, as shown in FIG55 , the first transistor T1 is turned on under the control of the low level of the first scan signal ss1, and the turned-on first transistor T1 provides the high level data voltage signal to the first node N1 and the gate of the driving transistor M0; the fourth transistor T4 is turned on under the control of the high level of the first node N1, and the turned-on fourth transistor T4 provides the low level signal of the first level signal terminal VGL to the gate of the third transistor T3; the third transistor T3 is turned on under the control of the low level signal, and the turned-on third transistor T3 provides the high level signal of the second level signal terminal VGH to the first node N1 and the gate of the driving transistor M0; the second transistor T2 is turned on under the control of the high level of the first node N1, and the turned-on fourth transistor T4 provides the low level signal of the first level signal terminal VGL to the gate of the third transistor T3; the third transistor T3 is turned on under the control of the low level signal, and the turned-on third transistor T3 provides the high level signal of the second level signal terminal VGH to the first node N1 and the gate of the driving transistor M0; It is turned off under the control of a high-level signal; the fifth transistor T5 is turned off under the control of a low-level signal; the driving transistor M0 is turned off under the control of a high-level signal; the eighteenth transistor M18 is turned on under the control of a high level, and the turned-on eighteenth transistor M18 provides the signal of the initialization signal terminal VINIT to the first electrode of the sixth transistor T6; the sixth transistor T6 is turned on under the control of a low-level light-emitting control signal em, and the turned-on sixth transistor T6 turns the second electrode of the eighteenth transistor M18 on the second electrode of the light-emitting device L, then the voltage of the signal at the second electrode of the light-emitting device L is less than the voltage of the signal at the first electrode of the light-emitting device L, and the light-emitting device L is in a reverse biased state. The sixth transistor T6, the light-emitting device L, the nineteenth transistor M19 and the twentieth transistor M20 form a path. Since the gate of the nineteenth transistor M19 is coupled to the second electrode of the light-emitting device L, if the voltage of the signal at the second electrode of the light-emitting device L changes, the voltage of the signal at the gate of the nineteenth transistor M19 also changes accordingly; therefore, the nineteenth transistor M19 adjusts the voltage of the signal input to the second node N2 according to the voltage of the signal at the second electrode of the light-emitting device L; the twentieth transistor M20 is turned on under the control of the low level of the second scanning signal ss2, and the turned-on twentieth transistor M20 will provide a detection signal to the detection signal terminal RD according to the voltage of the signal at the second node N2, that is, output the detection signal through the detection signal terminal RD; wherein the voltage of the detection signal is inversely proportional to the brightness received by the light-emitting device L, that is, the greater the brightness received by the light-emitting device L, the smaller the voltage of the detection signal, and the smaller the brightness received by the light-emitting device L, the larger the voltage of the detection signal.

[0369] It should be noted that, with the realization of brightness attenuation detection function as the basic application scenario, the W / L value of the sixth transistor T6 and the eighteenth transistor M18 in the pixel circuit is P, where W / L represents the channel width-to-length ratio of the sixth transistor T6 and the eighteenth transistor M18. The larger the value of W / L, the smaller the on-resistance of the sixth transistor T6 and the eighteenth transistor M18. When realizing the remote interaction scenario (that is, the pixel circuit realizes the light touch function), the W / L value of the sixth transistor T6 and the eighteenth transistor M18 in the pixel circuit is P1. When the brightness of the laser pen is high (in the detection stage, the resistance of the light-emitting device L is small), therefore, in the detection stage, the smaller the resistance of the path formed by the sixth transistor T6 and the eighteenth transistor M18, the more obvious the voltage change of the light-emitting device L in different states, then P1>P. When implementing the fingerprint recognition scenario (i.e., the pixel circuit implements the fingerprint detection function), the W / L value of the sixth transistor T6 and the eighteenth transistor M18 in the pixel circuit is P2. Since the brightness change is small when a finger touches (in the detection stage, the resistance of the light-emitting device L is large), and the brightness is low, it is reflected light. Therefore, the greater the resistance of the path formed by the sixth transistor T6 and the eighteenth transistor M18 in the pixel circuit, the more obvious the voltage change of the light-emitting device L in different states, and P2 <P。

[0370] In some other embodiments of the present disclosure, the pixel circuit, as shown in FIG56 , includes:

[0371] a first light emitting device L1;

[0372] The driving circuit 100 is coupled to the first light emitting device L1 and is configured to drive the first light emitting device L1 to emit light according to the data voltage signal;

[0373] a second light emitting device L2;

[0374] The detection circuit 400 is coupled to the second light-emitting device L2 and is configured to control the voltage of the second electrode of the second light-emitting device L2 to be lower than the voltage of the first electrode of the second light-emitting device L2, and when the voltage of the second electrode of the second light-emitting device L2 is controlled to be lower than the voltage of the first electrode of the second light-emitting device L2, the driving circuit 100 is controlled to stop driving the first light-emitting device L1 to emit light, and output a detection signal according to the second light-emitting device L2.

[0375] The pixel circuit provided in the embodiment of the present disclosure cooperates with the detection circuit and the driving circuit, that is, the driving circuit drives the light-emitting device to emit light according to the data voltage signal, and the detection circuit controls the voltage of the second electrode of the second light-emitting device to be lower than the voltage of the first electrode of the second light-emitting device, and when the voltage of the second electrode of the second light-emitting device is controlled to be lower than the voltage of the first electrode of the second light-emitting device, the driving circuit is controlled to stop driving the first light-emitting device to emit light, and outputs a detection signal based on the second light-emitting device, so that the illumination condition of the pixel circuit can be judged based on the detection signal, thereby realizing functions such as light touch function, brightness attenuation detection function and fingerprint detection function.

[0376] Exemplarily, the first electrodes of the first light emitting device L1 and the second light emitting device L2 serve as cathodes, and the second electrodes of the first light emitting device L1 and the second light emitting device L2 serve as anodes.

[0377] In some other embodiments of the present disclosure, as shown in FIG57 , the driving circuit 100 includes: a driving transistor M0, an initialization circuit 141, a data writing circuit 142, a first control circuit 143, a second control circuit 144, a third control circuit 145, and a conduction control circuit 146;

[0378] The initialization circuit 141 is coupled to the second electrode of the first light-emitting device L1 and the gate of the driving transistor M0, and is configured to provide a signal from the first initialization signal terminal VINIT1 to the gate of the driving transistor M0 in response to a signal from the first reset signal terminal RE1, and provide a signal from the second initialization signal terminal VINIT2 to the second electrode of the first light-emitting device L1 in response to a signal from the second reset signal terminal RE2;

[0379] The data writing circuit 142 is coupled to the first electrode of the driving transistor M0 and is configured to provide a data voltage signal of the data signal terminal DA to the first electrode of the driving transistor M0 in response to a signal of the first scanning signal terminal SS1;

[0380] The first control circuit 143 is coupled to the first node N1, the second electrode of the driving transistor M0, the second electrode of the first light-emitting device L1, and the second node N2, and is configured to provide a signal from the second power supply terminal VDD to the first node N1 in response to a signal from the second node N2, thereby conducting the second electrode of the driving transistor M0 and the second electrode of the first light-emitting device L1;

[0381] The second control circuit 144 is coupled to the second electrode and the gate of the driving transistor M0 and is configured to conduct the second electrode and the gate of the driving transistor M0 in response to the signal of the second scanning signal terminal SS2;

[0382] The third control circuit 145 is coupled to the second node N2 and is configured to provide the signal of the pulse control signal terminal HF or the signal of the light emitting control signal terminal EM to the second node N2;

[0383] The conduction control circuit 146 is coupled to the detection circuit 400 and is configured to conduct the first node N1 and the first electrode of the driving transistor M0 in response to the control signal output by the detection circuit 400 during the detection phase;

[0384] The detection circuit 400 is coupled to the conduction control circuit 146 and controls the conduction control circuit 146 to disconnect the first node N1 from the first electrode of the driving transistor M0 .

[0385] Exemplarily, the voltage of the signal at the first initialization signal terminal VINIT1 and the voltage of the signal at the second initialization signal terminal VINIT2 are both lower than the voltage of the signal at the first power supply terminal VSS.

[0386] In some other embodiments of the present disclosure, as shown in Figure 58, the detection circuit 400 includes: a first transistor M1 and a second transistor M2; wherein, the gate of the first transistor M1 is coupled to the second power supply terminal VDD, the first electrode of the first transistor M1 is coupled to the second power supply terminal VDD, and the second electrode of the first transistor M1 is coupled to the conduction control circuit 146; the gate of the second transistor M2 is coupled to the third scan signal terminal SS3, the first electrode of the second transistor M2 is coupled to the first electrode of the second light-emitting device L2, and the second electrode of the second transistor M2 is coupled to the detection signal terminal RD.

[0387] In some other embodiments of the present disclosure, as shown in Figure 58, the conduction control circuit 146 includes: a third transistor M3; wherein the gate of the third transistor M3 is coupled to the detection circuit 400, the first electrode of the third transistor M3 is coupled to the first node N1, and the second electrode of the third transistor M3 is coupled to the first electrode of the driving transistor M0.

[0388] Illustratively, as shown in FIG58 , the initialization circuit 141 includes: a fourth transistor M4 and a fifth transistor M5; wherein, the gate of the fourth transistor M4 is coupled to the first reset signal terminal RE1, the first electrode of the fourth transistor M4 is coupled to the gate of the driving transistor M0, and the second electrode of the fourth transistor M4 is coupled to the first initialization signal terminal VINIT1; the gate of the fifth transistor M5 is coupled to the second reset signal terminal RE2, the first electrode of the fifth transistor M5 is coupled to the second electrode of the first light-emitting device L1, and the second electrode of the fifth transistor M5 is coupled to the second initialization signal terminal VINIT2.

[0389] Exemplarily, as shown in FIG58 , the data writing circuit 142 includes: a sixth transistor M6; wherein the gate of the sixth transistor M6 is coupled to the first scan signal terminal SS1, the first electrode of the sixth transistor M6 is coupled to the first electrode of the driving transistor M0, and the second electrode of the sixth transistor M6 is coupled to the data signal terminal DA.

[0390] Illustratively, as shown in FIG58 , the first control circuit 143 includes: a seventh transistor M7 and an eighth transistor M8; wherein, the gate of the seventh transistor M7 is coupled to the second node N2, the first electrode of the seventh transistor M7 is coupled to the second power supply terminal VDD, and the second electrode of the seventh transistor M7 is coupled to the first node N1; the gate of the eighth transistor M8 is coupled to the second node N2, the first electrode of the eighth transistor M8 is coupled to the second electrode of the driving transistor M0, and the second electrode of the eighth transistor M8 is coupled to the second electrode of the first light-emitting device L1.

[0391] Exemplarily, as shown in Figure 58, the second control circuit 144 includes: a ninth transistor M9 and a first capacitor; wherein, the gate of the ninth transistor M9 is coupled to the second scan signal terminal SS2, the first electrode of the ninth transistor M9 is coupled to the gate of the driving transistor M0, and the second electrode of the ninth transistor M9 is coupled to the second electrode of the driving transistor M0; the first electrode of the first capacitor C1 is coupled to the second power supply terminal VDD, and the second electrode of the first capacitor C1 is coupled to the second electrode of the driving transistor M0.

[0392] Exemplarily, as shown in Figure 58, the third control circuit 145 includes: a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12 and a second capacitor C2; wherein, the gate of the tenth transistor M10 is coupled to the third node N3, the first electrode of the tenth transistor M10 is coupled to the pulse control signal terminal HF, and the second electrode of the tenth transistor M10 is coupled to the second node N2; the gate of the eleventh transistor M11 is coupled to the third node N3, the first electrode of the eleventh transistor M11 is coupled to the second node N2, and the second electrode of the eleventh transistor M11 is coupled to the light-emitting control signal terminal EM; the gate of the twelfth transistor M12 is coupled to the reset signal terminal Rst, the first electrode of the twelfth transistor M12 is coupled to the third node N3, and the second electrode of the twelfth transistor M12 is coupled to the data signal terminal DA; the first electrode of the second capacitor C2 is coupled to the third node N3, and the second electrode of the second capacitor C2 is coupled to the first power supply terminal VSS.

[0393] The driving method of the pixel circuit provided by the embodiment of the present disclosure includes: a driving circuit driving a first light-emitting device to emit light according to a data voltage signal;

[0394] The detection circuit controls the voltage of the second electrode of the second light-emitting device to be lower than the voltage of the first electrode of the second light-emitting device, and when the voltage of the second electrode of the second light-emitting device is controlled to be lower than the voltage of the first electrode of the second light-emitting device, the detection circuit controls the driving circuit to stop driving the first light-emitting device to emit light, and outputs a detection signal according to the second light-emitting device.

[0395] The following takes the pixel circuit shown in Figure 58 as an example, and describes the working process of the pixel circuit provided by the embodiment of the present disclosure in combination with whether there is a finger touching it.

[0396] When a finger touches the second light emitting device L2, since the voltage of the signal at the first electrode of the second light emitting device L2 is greater than the voltage of the signal at the second electrode of the second light emitting device L2, the second light emitting device L2 is in a reverse biased state; the second light emitting device L2 in the reverse biased state receives weak external brightness, and the second light emitting device L2 is in a closed state (i.e., the leakage current is small); the first transistor M1 is turned on under the control of the high level signal of the second power supply terminal VDD, and the turned-on first transistor M1 provides the high level signal of the second power supply terminal VDD to the gate of the third transistor M3 and the first electrode of the second transistor M2; the third transistor M3 is turned on under the control of the high level signal When the control is turned off, the third transistor M3 disconnects the first node N1 from the first electrode of the driving transistor M0, so that the driving circuit 100 stops driving the first light-emitting device L1 to emit light; the second transistor M2 is turned on under the control of the low-level signal of the third scanning signal terminal SS3, and the turned-on second transistor M2 provides a high-level signal to the detection signal terminal, that is, the detection signal is output through the detection signal terminal; thereby, it can be determined that there is a finger touch based on the detection signal; and when there is a finger touch, the driving circuits 100 around the detection circuit 400 (for example, as shown in Figure 59) all stop driving the first light-emitting device L1 to emit light, which can save power consumption and cost.

[0397] When there is no finger touch, since the voltage of the signal at the first electrode of the second light-emitting device L2 is greater than the voltage of the signal at the second electrode of the second light-emitting device L2, the second light-emitting device L2 is in a reverse biased state; the second light-emitting device L2 in the reverse biased state receives strong external brightness, and the second light-emitting device L2 is in a conductive state (i.e., the leakage current is large); the conductive second light-emitting device L2 provides a low-level signal of the first power supply terminal VSS to the gate of the third transistor M3 and the first electrode of the second transistor M2; the third transistor M3 is turned on under the control of the low-level signal, and the conductive third transistor M3 connects the first node N1 to the first electrode of the driving transistor M0, so that the driving circuit 100 can drive the first light-emitting device L1 to emit light; the second transistor M2 is turned on under the control of the low-level signal of the third scan signal terminal SS3, and the conductive second transistor M2 provides a low-level signal to the detection signal terminal, that is, outputs a detection signal through the detection signal terminal; thus, it can be determined that there is no finger touch based on the detection signal. And when there is no finger touching, the driving circuit 100 around the detection circuit 400 (for example, as shown in Figure 59) can normally drive the first light-emitting device L1 to emit light, that is, the driving circuit can work normally while obtaining the detection signal.

[0398] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0399] Generally, transistors using low-temperature polysilicon (LTPS) as active layers have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, thereby achieving high mobility in the pixel circuit, and allowing it to be made thinner and smaller, with lower power consumption.

[0400] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, to reduce leakage current, in some embodiments of the present disclosure, the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0401] For example, all transistors may be configured as LTPS transistors, or all transistors may be configured as oxide transistors, or some transistors may be configured as oxide transistors and the remaining transistors may be configured as LTPS transistors.

[0402] The display panel provided by the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0403] In the embodiment of the present disclosure, the display panel includes a plurality of sub-pixels, and each sub-pixel includes the aforementioned pixel circuit.

[0404] In an embodiment of the present disclosure, as shown in FIG60 , when the pixel circuit includes a potential selection circuit, the pixel circuits in a row of sub-pixels are connected to the same potential selection circuit.

[0405] In some embodiments of the present disclosure, in a pixel circuit of at least one sub-pixel in a row of sub-pixels, the first pole of the light-emitting device is a cathode, and the second pole is an anode.

[0406] In some embodiments of the present disclosure, as shown in FIG61 , a row of sub-pixels includes a first sub-pixel spx1 and a second sub-pixel spx2 ;

[0407] In the pixel circuit of the first sub-pixel spx1 (for example, the pixel circuit shown in FIG6 ), the first electrode of the light-emitting device is a cathode, and the second electrode is an anode;

[0408] In the pixel circuit of the second sub-pixel spx2 (for example, the pixel circuit shown in FIG6 ), the first electrode of the light-emitting device serves as an anode, and the second electrode serves as a cathode.

[0409] In some embodiments of the present disclosure, as shown in FIG61 , in a row of sub-pixels, first sub-pixels spx1 and second sub-pixels spx2 are alternately arranged.

[0410] Exemplarily, the arrangement may be made directly on the anode and cathode of the light-emitting device in the sub-pixel of the display panel, or on the anode and cathode of the light-emitting device in the array substrate.

[0411] In some other embodiments of the present disclosure, as shown in FIG62 , in the pixel circuit of at least one sub-pixel in a column of sub-pixels, the first pole of the light-emitting device is a cathode, and the second pole is an anode.

[0412] In some other embodiments of the present disclosure, as shown in FIG62 , a column of sub-pixels includes a third sub-pixel spx3 and a fourth sub-pixel spx4 ;

[0413] In the pixel circuit of the third sub-pixel spx3 (for example, the pixel circuit shown in FIG6 ), the first electrode of the light-emitting device is a cathode, and the second electrode is an anode;

[0414] In the pixel circuit of the fourth sub-pixel spx4 (for example, the pixel circuit shown in FIG6 ), the first electrode of the light-emitting device serves as an anode, and the second electrode serves as a cathode.

[0415] In some other embodiments of the present disclosure, as shown in FIG62 , in a column of sub-pixels, the third sub-pixel spx3 and the fourth sub-pixel spx4 are alternately arranged.

[0416] Exemplarily, the arrangement may be made directly on the anode and cathode of the light-emitting device in the sub-pixel of the display panel, or on the anode and cathode of the light-emitting device in the array substrate.

[0417] In some further embodiments of the present disclosure, as shown in FIG63 , the display panel includes a plurality of sub-pixels, the plurality of sub-pixels include at least one first sub-pixel spx1 and at least one second sub-pixel spx2, the first sub-pixel spx1 includes a first light-emitting device L1 and a driving circuit 100 as shown in FIG58 , and the second sub-pixel includes a second light-emitting device L2 and a detection circuit 400 as shown in FIG58 .

[0418] In some other embodiments of the present disclosure, as shown in FIG59 , the driving circuits in a plurality of first sub-pixels are connected to the same detection circuit.

[0419] In some other embodiments of the present disclosure, the second sub-pixel where the detection circuit is located and the first sub-pixel connected to the same detection circuit are arranged according to M*N, where M is an integer greater than 0, and N is an integer greater than 0.

[0420] For example, as shown in FIG64 , the second light emitting device L2 and the detection circuit 400 may be arranged in a Δ arrangement.

[0421] Based on the same disclosed concept, the present disclosure also provides a display device including the aforementioned pixel circuit provided in the present disclosure. The principles of this display device are similar to those of the aforementioned pixel circuit, so the implementation of this display device can refer to the implementation of the aforementioned pixel circuit, and the repeated parts will not be repeated here.

[0422] In specific implementations, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, an electronic watch, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0423] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0424] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A pixel circuit, wherein: include: a light emitting device, wherein a first electrode of the light emitting device is coupled to a first power supply terminal; The driving circuit is coupled to the second electrode of the light-emitting device and is configured to drive the light-emitting device to emit light according to a data voltage signal, and is configured to control the voltage of the second electrode of the light-emitting device to be lower than the voltage of the first electrode of the light-emitting device, and output a detection signal according to the light-emitting device when the voltage of the second electrode of the light-emitting device is controlled to be lower than the voltage of the first electrode of the light-emitting device.

2. The pixel circuit according to claim 1, wherein: The driving circuit includes: a driving transistor, an initialization circuit, a data transmission circuit, a first control circuit, a second control circuit and a third control circuit; The working process of the pixel circuit includes: a reset phase, a detection phase and a light emitting phase; The initialization circuit is coupled to the second electrode of the light-emitting device and the gate of the driving transistor, and is configured to provide a signal from a first initialization signal terminal to the gate of the driving transistor in response to a signal from a first reset signal terminal during the reset phase, and provide a signal from a second initialization signal terminal to the second electrode of the light-emitting device in response to a signal from a second reset signal terminal; The data transmission circuit is coupled to the first electrode of the driving transistor and is configured to connect the first electrode of the driving transistor to the data transmission signal terminal in response to the signal of the first scanning signal terminal during the detection phase; The first control circuit is coupled to the driving transistor, the second electrode of the light-emitting device, and a first node, and is configured to provide a signal from the second power supply terminal to the first electrode of the driving transistor in response to a signal from the light-emitting control signal terminal during the light-emitting phase, and to conduct the second electrode of the driving transistor to the second electrode of the light-emitting device in response to a signal from the first node during the detection phase and the light-emitting phase; The second control circuit is coupled to the second electrode and the gate of the driving transistor and is configured to connect the second electrode and the gate of the driving transistor in response to a signal at the second scanning signal terminal during the detection phase; The third control circuit is coupled to the first node and is configured to provide a signal from the pulse control signal terminal or a signal from the light emitting control signal terminal to the first node during the reset phase, the detection phase, and the light emitting phase.

3. The pixel circuit according to claim 2, wherein: The data transmission circuit includes: a first transistor; a gate of the first transistor is coupled to the first scanning signal end, a first electrode of the first transistor is coupled to the first electrode of the driving transistor, and a second electrode of the first transistor is coupled to the data transmission signal end.

4. The pixel circuit according to claim 2, wherein: The light emitting control signal terminal is coupled to the first node.

5. The pixel circuit according to claim 2, wherein: The working process of the pixel circuit further includes: a compensation stage; The data transmission circuit includes: a data writing circuit and a detection circuit; The data writing circuit is coupled to the first electrode of the driving transistor and is configured to provide the data voltage signal of the data transmission signal terminal to the first electrode of the driving transistor in response to the signal of the third scanning signal terminal during the compensation phase; The detection circuit is coupled to the first electrode of the driving transistor and is configured to provide the signal of the second power supply terminal to the second node in response to the signal of the first electrode of the driving transistor during the detection phase, and to connect the second node to the detection signal terminal in response to the signal of the fourth scanning signal terminal, and output the detection signal through the detection signal terminal.

6. The pixel circuit according to claim 5, wherein: The detection circuit includes: a second transistor and a third transistor; The gate of the second transistor is coupled to the first electrode of the driving transistor, the first electrode of the second transistor is coupled to the second power supply terminal, and the second electrode of the second transistor is coupled to the second node; A gate of the third transistor is coupled to the fourth scan signal terminal, a first electrode of the third transistor is coupled to the second node, and a second electrode of the third transistor is coupled to the detection signal terminal.

7. The pixel circuit according to claim 5, wherein: It also includes: a potential selection circuit, coupled to the driving circuit, and configured to respond to the signal of the fifth scanning signal terminal in the reset phase and the detection phase to provide the signal of the third initialization signal terminal to the driving circuit, and respond to the signal of the sixth scanning signal terminal in the compensation phase and the light-emitting phase to provide the signal of the second power supply terminal to the driving circuit.

8. The pixel circuit according to claim 7, wherein: The potential selection circuit includes: a fourth transistor and a fifth transistor; The gate of the fourth transistor is coupled to the fifth scan signal terminal, the first electrode of the fourth transistor is coupled to the driving circuit, and the second electrode of the fourth transistor is coupled to the third initialization signal terminal; A gate of the fifth transistor is coupled to the sixth scan signal terminal, a first electrode of the fifth transistor is coupled to the second power supply terminal, and a second electrode of the fifth transistor is coupled to the driving circuit.

9. The pixel circuit according to claim 2, wherein: The working process of the pixel circuit further includes: a compensation stage; The data transmission circuit includes: a data writing circuit, a detection circuit and a conduction control circuit; The data writing circuit is coupled to the first electrode of the driving transistor and is configured to provide the data voltage signal of the data transmission signal terminal to the first electrode of the driving transistor in response to the signal of the seventh scanning signal terminal during the detection phase and the compensation phase; The detection circuit is coupled to the second electrode of the driving transistor and is configured to provide the signal of the second power terminal to the third node in response to the signal of the second electrode of the driving transistor during the detection phase, and to connect the third node to the detection signal terminal in response to the signal of the eighth scanning signal terminal, and output the detection signal through the detection signal terminal; The conduction control circuit is coupled to the second electrode of the driving transistor and the second electrode of the light-emitting device, and is configured to conduct the second electrode of the driving transistor and the second electrode of the light-emitting device in response to the signal of the ninth scanning signal terminal during the detection phase.

10. The pixel circuit according to claim 9, wherein: The detection circuit includes: a sixth transistor and a seventh transistor; The gate of the sixth transistor is coupled to the second electrode of the driving transistor, the first electrode of the sixth transistor is coupled to the second power supply terminal, and the second electrode of the sixth transistor is coupled to the third node; A gate of the seventh transistor is coupled to the eighth scan signal terminal, a first electrode of the seventh transistor is coupled to the third node, and a second electrode of the seventh transistor is coupled to the detection signal terminal.

11. The pixel circuit according to claim 9, wherein: The conduction control circuit includes: an eighth transistor; the gate of the eighth transistor is coupled to the ninth scanning signal terminal, the first electrode of the eighth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the eighth transistor is coupled to the second electrode of the light-emitting device.

12. The pixel circuit according to claim 1, wherein: The driving circuit includes: a driving transistor, an initialization circuit, a detection circuit, a potential selection circuit, a data writing circuit, a first control circuit and a second control circuit; The working process of the pixel circuit includes: a reset stage, a detection stage, a compensation stage and a light emitting stage; The initialization circuit is coupled to the second electrode of the light emitting device and is configured to provide a signal from the first initialization signal terminal to the second electrode of the light emitting device in response to a signal from the first reset signal terminal during the reset phase; The detection circuit is coupled to the second electrode of the driving transistor and is configured to provide a signal from the second power supply terminal to the first node in response to a signal from the second electrode of the driving transistor during the detection phase, connect the first node to the detection signal terminal in response to a signal from the first scanning signal terminal, and output a detection signal through the detection signal terminal; The potential selection circuit is coupled to the first electrode of the driving transistor and is configured to respond to a signal from a second scanning signal terminal during the reset phase, the compensation phase, and the light-emitting phase to provide a signal from the second power supply terminal to the first electrode of the driving transistor, and respond to a signal from a second initialization signal terminal during the compensation phase and the light-emitting phase to provide a signal from the second initialization signal terminal to the first electrode of the driving transistor; The data writing circuit is coupled to the second node and configured to provide a data voltage signal at the data signal terminal to the second node in response to a signal at the third scan signal terminal during the compensation phase; The first control circuit is coupled to the gate and the second electrode of the driving transistor and is configured to turn on the gate and the second electrode of the driving transistor in response to a signal at the second reset signal terminal during the reset phase and the compensation phase; The second control circuit is coupled to the second electrode of the driving transistor, the second node and the second electrode of the light-emitting device, and is configured to respond to the signal of the light-emitting control signal end in the reset stage, the detection stage and the light-emitting stage, provide the signal of the first power supply end to the second node, and connect the second electrode of the driving transistor and the second electrode of the light-emitting device.

13. The pixel circuit according to claim 12, wherein: The detection circuit includes: a ninth transistor and a tenth transistor; The gate of the ninth transistor is coupled to the second electrode of the driving transistor, the first electrode of the ninth transistor is coupled to the second power supply terminal, and the second electrode of the ninth transistor is coupled to the first node; A gate of the tenth transistor is coupled to the first scan signal terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the detection signal terminal.

14. The pixel circuit according to claim 12, wherein: The potential selection circuit includes: an eleventh transistor and a twelfth transistor; The gate of the eleventh transistor is coupled to the second scanning signal terminal, the first electrode of the eleventh transistor is coupled to the second power supply terminal, and the second electrode of the eleventh transistor is coupled to the first electrode of the driving transistor; A gate of the twelfth transistor is coupled to the second initialization signal terminal, a first electrode of the twelfth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the twelfth transistor is coupled to the second initialization signal terminal.

15. The pixel circuit according to claim 1, wherein: The driving circuit includes: a driving transistor, a detection circuit, a data writing circuit, and a potential selection circuit; The working process of the pixel circuit includes: a reset phase, a detection phase, a data writing phase and a compensation phase; The detection circuit is coupled to the first electrode and the second electrode of the driving transistor, and is configured to respond to the signal of the second electrode of the driving transistor and the signal of the first scanning signal terminal during the reset phase, the detection phase, and the data writing phase, provide the signal of the first electrode of the driving transistor to the detection signal terminal, output the detection signal through the detection signal terminal, and connect the second electrode of the driving transistor to the detection signal terminal in response to the signal of the second scanning signal terminal during the compensation phase; The data writing circuit is coupled to the gate of the driving transistor and is configured to provide a data voltage signal from a data signal terminal to the gate of the driving transistor in response to a signal from a third scanning signal terminal during the reset phase, the detection phase, the data writing phase, and the compensation phase; The potential selection circuit is coupled to the first electrode of the driving transistor and is configured to respond to the signal of the fourth scanning signal terminal in the reset phase, the detection phase and the data writing phase, and provide the signal of the initialization signal terminal to the first electrode of the driving transistor, and respond to the signal of the second power supply terminal in the compensation phase, and provide the signal of the second power supply terminal to the second electrode of the driving transistor.

16. The pixel circuit according to claim 15, wherein: The detection circuit includes: a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; The gate of the thirteenth transistor is coupled to the second electrode of the driving transistor, the first electrode of the thirteenth transistor is coupled to the first electrode of the driving transistor, and the second electrode of the thirteenth transistor is coupled to the first electrode of the fourteenth transistor; The gate of the fourteenth transistor is coupled to the first scan signal terminal, and the second electrode of the fourteenth transistor is coupled to the detection signal terminal; A gate of the fifteenth transistor is coupled to the second scanning signal terminal, a first electrode of the fifteenth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the fifteenth transistor is coupled to the detection signal terminal.

17. The pixel circuit according to claim 15, wherein: The detection circuit includes: a thirteenth transistor and a fourteenth transistor; A first gate of the thirteenth transistor is coupled to the second electrode of the driving transistor, a second gate of the thirteenth transistor is coupled to the first scanning signal terminal, a first electrode of the thirteenth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the thirteenth transistor is coupled to the first electrode of the fourteenth transistor; A gate of the fourteenth transistor is coupled to the second scanning signal terminal, and a second electrode of the fourteenth transistor is coupled to the detection signal terminal.

18. The pixel circuit according to claim 15, wherein: The potential selection circuit includes: a sixteenth transistor and a seventeenth transistor; The gate of the sixteenth transistor is coupled to the fourth scan signal terminal, the first electrode of the sixteenth transistor is coupled to the initialization signal terminal, and the second electrode of the sixteenth transistor is coupled to the first electrode of the driving transistor; The gate of the seventeenth transistor is coupled to the second power supply terminal, and the first electrode of the seventeenth transistor is coupled to the The second power supply terminal is coupled to the second electrode of the seventeenth transistor and the first electrode of the driving transistor.

19. The pixel circuit according to claim 1, wherein: The driving circuit includes: a driving transistor, a data writing circuit, a light emitting control circuit and a detection circuit; The working process of the pixel circuit includes: a detection phase and a light emitting phase; The data writing circuit is coupled to the gate of the driving transistor and the first node, and is configured to provide a data voltage signal at the data signal terminal to the first node in response to a signal at the first scanning signal terminal during the light emitting phase, and provide a signal at the first level signal terminal or a signal at the second level signal terminal to the gate of the driving transistor in response to the signal at the first node; The light emitting control circuit is coupled to the second electrode of the driving transistor and the second electrode of the light emitting device, and is configured to connect the second electrode of the driving transistor and the second electrode of the light emitting device in response to the signal of the light emitting control signal terminal during the detection phase and the light emitting phase; The detection circuit is coupled to the gate of the driving transistor and the second electrode of the light-emitting device, and is configured to provide the signal of the initialization signal terminal to the second electrode of the driving transistor in response to the signal of the gate of the driving transistor during the detection phase, provide the signal of the second power supply terminal to the second node in response to the signal of the second electrode of the light-emitting device, provide the signal of the second node to the detection signal terminal in response to the signal of the second scanning signal terminal, and output the detection signal through the detection signal terminal.

20. The pixel circuit according to claim 19, wherein: The detection circuit includes: an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; A gate of the eighteenth transistor is coupled to a gate of the driving transistor, a first electrode of the eighteenth transistor is coupled to the initialization signal terminal, and a second electrode of the eighteenth transistor is coupled to a second electrode of the driving transistor; The gate of the nineteenth transistor is coupled to the second electrode of the light-emitting device, the first electrode of the nineteenth transistor is coupled to the second power supply terminal, and the second electrode of the nineteenth transistor is coupled to the second node; A gate of the twentieth transistor is coupled to a signal of the second scanning signal terminal, a first electrode of the twentieth transistor is coupled to the second node, and a second electrode of the twentieth transistor is coupled to the detection signal terminal.

21. A pixel circuit, wherein: include: a first light emitting device; a driving circuit, coupled to the first light emitting device, and configured to drive the first light emitting device to emit light according to a data voltage signal; a second light emitting device; The detection circuit is coupled to the second light-emitting device and is configured to control the voltage of the second electrode of the second light-emitting device to be lower than the voltage of the first electrode of the second light-emitting device, and when the voltage of the second electrode of the second light-emitting device is controlled to be lower than the voltage of the first electrode of the second light-emitting device, control the driving circuit to stop driving the first light-emitting device to emit light, and output a detection signal according to the second light-emitting device.

22. The pixel circuit according to claim 21, wherein: The driving circuit includes: a driving transistor, an initialization circuit, a data writing circuit, a first control circuit, a second control circuit, a third control circuit and a conduction control circuit; The initialization circuit is coupled to the second electrode of the first light-emitting device and the gate of the driving transistor, and is configured to provide a signal of a first initialization signal terminal to the gate of the driving transistor in response to a signal of a first reset signal terminal, and provide a signal of a second initialization signal terminal to the second electrode of the first light-emitting device in response to a signal of a second reset signal terminal; The data writing circuit is coupled to the first electrode of the driving transistor and is configured to provide a data voltage signal from the data signal terminal to the first electrode of the driving transistor in response to a signal from the first scanning signal terminal; The first control circuit is coupled to the first node, the second electrode of the driving transistor, the second electrode of the first light-emitting device, and the second node, and is configured to provide a signal from the second power supply terminal to the first node in response to a signal from the second node, thereby conducting the second electrode of the driving transistor and the second electrode of the first light-emitting device; The second control circuit is coupled to the second electrode and the gate of the driving transistor and is configured to conduct the second electrode and the gate of the driving transistor in response to a signal at the second scanning signal terminal; The third control circuit is coupled to the second node and is configured to provide the signal of the pulse control signal terminal or the signal of the light emitting control signal terminal to the second node; a conduction control circuit coupled to the detection circuit and configured to conduct the first node with the first electrode of the driving transistor in response to a control signal output by the detection circuit; The detection circuit is coupled to the conduction control circuit and controls the conduction control circuit to disconnect the first node from the first electrode of the driving transistor.

23. The pixel circuit according to claim 22, wherein: The detection circuit includes: a first transistor and a second transistor; The gate of the first transistor is coupled to the second power supply terminal, the first electrode of the first transistor is coupled to the second power supply terminal, and the second electrode of the first transistor is coupled to the conduction control circuit; A gate of the second transistor is coupled to the third scan signal terminal, a first electrode of the second transistor is coupled to the first electrode of the second light emitting device, and a second electrode of the second transistor is coupled to the detection signal terminal.

24. The pixel circuit according to claim 22, wherein: The conduction control circuit includes: a third transistor; a gate of the third transistor is coupled to the detection circuit, a first electrode of the third transistor is coupled to the first node, and a second electrode of the third transistor is coupled to the first electrode of the driving transistor.

25. A display panel, wherein: Comprising the pixel circuit according to any one of claims 1-24.

26. The display panel according to claim 25, wherein: The display panel includes a plurality of sub-pixels, and each of the sub-pixels includes the pixel circuit according to any one of claims 1 to 20.

27. The display panel according to claim 26, wherein: When the pixel circuit includes a potential selection circuit, the pixel circuits in a row of sub-pixels are connected to the same potential selection circuit.

28. The display panel according to claim 26 or 27, wherein: In the pixel circuit of at least one sub-pixel in a row of sub-pixels, the first electrode of the light-emitting device serves as a cathode, and the second electrode serves as an anode.

29. The display panel according to claim 28, wherein: A row of sub-pixels includes a first sub-pixel and a second sub-pixel; In the pixel circuit of the first sub-pixel, the first electrode of the light-emitting device is a cathode, and the second electrode is an anode; In the pixel circuit of the second sub-pixel, the first electrode of the light-emitting device serves as an anode, and the second electrode serves as a cathode.

30. The display panel according to claim 29, wherein: In a row of sub-pixels, the first sub-pixels and the second sub-pixels are alternately arranged.

31. The display panel according to any one of claims 26 to 30, wherein: In the pixel circuit of at least one sub-pixel in a column of sub-pixels, the first electrode of the light-emitting device serves as a cathode, and the second electrode serves as an anode.

32. The display panel according to claim 31, wherein: A column of sub-pixels includes a third sub-pixel and a fourth sub-pixel; In the pixel circuit of the third sub-pixel, the first electrode of the light-emitting device is a cathode, and the second electrode is an anode; In the pixel circuit of the fourth sub-pixel, the first electrode of the light-emitting device serves as an anode, and the second electrode serves as a cathode.

33. The display panel according to claim 32, wherein: In a column of sub-pixels, the third sub-pixels and the fourth sub-pixels are alternately arranged.

34. The display panel according to claim 25, wherein: The display panel includes a plurality of sub-pixels, and the plurality of sub-pixels include at least one first sub-pixel and at least one second sub-pixel, the first sub-pixel includes the first light-emitting device and the driving circuit as described in any one of claims 21-24, and the second sub-pixel includes the second light-emitting device and the detection circuit as described in any one of claims 21-24.

35. The display panel according to claim 34, wherein: The driving circuits in the plurality of first sub-pixels are connected to the same detection circuit.

36. The display panel according to claim 35, wherein: The second sub-pixel where the detection circuit is located and the first sub-pixel connected to the same detection circuit are arranged in M*N order, where M is an integer greater than 0 and N is an integer greater than 0.

37. A display device, wherein: Comprising the pixel circuit according to any one of claims 1-24.

38. A method for driving a pixel circuit according to any one of claims 1 to 20, wherein: include: The driving circuit drives the light-emitting device to emit light according to the data voltage signal, and controls the voltage of the second pole of the light-emitting device to be lower than the voltage of the first pole of the light-emitting device, and outputs a detection signal according to the light-emitting device when the voltage of the second pole of the light-emitting device is controlled to be lower than the voltage of the first pole of the light-emitting device.

39. A method for driving a pixel circuit according to any one of claims 21 to 24, wherein: include: The driving circuit drives the first light emitting device to emit light according to the data voltage signal; The detection circuit controls the voltage of the second pole of the second light-emitting device to be lower than the voltage of the first pole of the second light-emitting device, and when the voltage of the second pole of the second light-emitting device is controlled to be lower than the voltage of the first pole of the second light-emitting device, controls the driving circuit to stop driving the first light-emitting device to emit light, and outputs a detection signal according to the second light-emitting device.