Semiconductor device and electronic apparatus

Abstract

Provided in the present application are a semiconductor device and an electronic apparatus. In the semiconductor device, a first electrode and a second electrode are arranged on different layers to form a thin film transistor with a vertical structure, so that the space occupied by the thin film transistor is reduced, and thus the pixel density and the aperture ratio can be improved; moreover, a first gate and a second gate are respectively arranged on two sides of a channel portion, so that the mobility of the thin film transistor can be improved, the gate control capability of the semiconductor device is improved, and a short-channel effect is reduced.

Description

Semiconductor devices and electronic devices Technical Field

[0001] The present application relates to the field of display technology, and in particular to a semiconductor device and an electronic apparatus. Background Art

[0002] Virtual reality (VR) technology uses computers and other devices to create an immersive experience in a virtual world. However, VR products have been found to experience dizziness due to insufficient screen clarity and refresh rates. To address these issues, VR products need to increase pixel density and aperture ratio, while also achieving high frequency and low power consumption. To achieve this, existing display devices employ vertical thin-film transistors (TFTs) to reduce their footprint, lower power consumption, and increase aperture ratio and pixel density. However, these TFTs often utilize a single-gate driver, resulting in gate control capabilities that fall short of product requirements.

[0003] Therefore, the existing vertical structure thin film transistor has a technical problem of insufficient gate control capability when driven by a single gate. SUMMARY OF THE INVENTION

[0004] Embodiments of the present application provide a semiconductor device and an electronic apparatus to solve the technical problem of insufficient gate control capability of existing vertically structured thin-film transistors through single-gate driving.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] An embodiment of the present application provides a semiconductor device, comprising:

[0007] substrate;

[0008] A first electrode is provided on one side of the substrate;

[0009] a first gate, disposed on a side of the first electrode away from the substrate;

[0010] a first gate insulating layer, disposed on a side of the first gate away from the first electrode;

[0011] a second electrode, disposed on a side of the first gate insulating layer away from the first gate;

[0012] an active pattern comprising a channel portion and a first doped portion and a second doped portion located at both ends of the channel portion, wherein the first doped portion is connected to the first electrode, and the second doped portion is connected to the second electrode; and

[0013] a second gate, disposed on a side of the active pattern away from the second electrode;

[0014] The first gate insulating layer is disposed between the first gate and the channel portion, the channel portion overlaps the sidewall of the first gate insulating layer, and the first gate and the second gate are respectively disposed on both sides of the channel portion.

[0015] Meanwhile, an embodiment of the present application provides an electronic device, which includes a semiconductor device, wherein the semiconductor device includes:

[0016] substrate;

[0017] A first electrode is provided on one side of the substrate;

[0018] a first gate, disposed on a side of the first electrode away from the substrate;

[0019] a first gate insulating layer, disposed on a side of the first gate away from the first electrode;

[0020] a second electrode, disposed on a side of the first gate insulating layer away from the first gate;

[0021] an active pattern comprising a channel portion and a first doped portion and a second doped portion located at both ends of the channel portion, wherein the first doped portion is connected to the first electrode, and the second doped portion is connected to the second electrode; and

[0022] a second gate, disposed on a side of the active pattern away from the second electrode;

[0023] The first gate insulating layer is disposed between the first gate and the channel portion, the channel portion overlaps the sidewall of the first gate insulating layer, and the first gate and the second gate are respectively disposed on both sides of the channel portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0025] FIG1 is a schematic diagram of an array layer of a virtual reality product provided in an embodiment of the present application.

[0026] FIG2 is a first schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0027] FIG3 is a second schematic diagram of a semiconductor device provided in an embodiment of the present application.

[0028] FIG4 is a schematic diagram of the three-dimensional structure of a semiconductor device provided in an embodiment of the present application.

[0029] FIG5 is a schematic diagram of a first structure of a semiconductor device corresponding to each step of the method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0030] FIG6 is a second structural schematic diagram of a semiconductor device corresponding to each step of the method for manufacturing a semiconductor device provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0032] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0034] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0035] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0036] As shown in FIG1 , FIG1 (a) is a top view of the array layer of the virtual reality product, and FIG1 (b) is a cross-sectional view of the array layer of the virtual reality product. As shown in (b) of Figure 1, the array layer includes a substrate 101, a first insulating layer 102, a first light-shielding layer 103, a second insulating layer 104, a second light-shielding layer 105, a third insulating layer 106, a semiconductor layer 107, a fourth insulating layer 108, a gate layer 109, a fifth insulating layer 110, a first source-drain electrode layer 111, a sixth insulating layer 112, a second source-drain electrode layer 113, a seventh insulating layer 114, a first electrode layer 115, an eighth insulating layer 116, a ninth insulating layer 117, and a second electrode layer 118. As shown in Figure 1, the first source-drain electrode layer 111 includes a source electrode 121, and the second source-drain electrode layer 113 includes a drain electrode 122. The contact positions of the source electrode 121 and the drain electrode 122 with the semiconductor layer 107 are indicated by reference numeral 123. As can be seen from Figure 1, the thin film transistor adopts a horizontal structure, resulting in a larger space occupied by the thin film transistor and higher power consumption of the thin film transistor, which in turn leads to lower pixel density and aperture ratio, and lower refresh rate of the virtual reality product. To address these issues, existing VR products use vertical thin-film transistors (TFTs). However, these TFTs often utilize a single-gate driver, resulting in gate control capabilities that fall short of product requirements. Therefore, existing TFTs with vertical structures, driven by a single gate, suffer from insufficient gate control capabilities.

[0037] Figure 2 is a first schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 2 (a) is a top view schematic diagram of the semiconductor device provided in an embodiment of the present application. Figure 2 (b) is a cross-sectional schematic diagram of the semiconductor device provided in an embodiment of the present application. Figure 3 is a second schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 4 is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of the present application. Figure 5 is a first structural schematic diagram of a semiconductor device corresponding to each step of the method for preparing a semiconductor device provided in an embodiment of the present application. Figure 6 is a second structural schematic diagram of a semiconductor device corresponding to each step of the method for preparing a semiconductor device provided in an embodiment of the present application.

[0038] As shown in FIG2 , an embodiment of the present application provides a semiconductor device, which includes a substrate 201, a first electrode 203, a first gate 205, a first gate insulating layer 206, a second electrode 207, an active pattern 208, and a second gate 210. The first electrode 203 is disposed on one side of the substrate 201; the first gate 205 is disposed on a side of the first electrode 203 away from the substrate 201; the first gate insulating layer 206 is disposed on a side of the first gate 205 away from the first electrode 203; the second electrode 207 is disposed on a side of the first gate insulating layer 206 away from the first gate 205; the active pattern 208 includes a channel portion 208c and a first doped portion 208a and a second doped portion 208b located at both ends of the channel portion 208c, the first doped portion 208a being connected to the first electrode 203, and the second doped portion 208b being connected to the second electrode 207; and the second gate 210 is disposed on a side of the active pattern 208 away from the second electrode 207.

[0039] The first gate insulating layer 206 is disposed between the first gate 205 and the channel portion 208 c , the channel portion 208 c overlaps the sidewall of the first gate insulating layer 206 , and the first gate 205 and the second gate 210 are respectively disposed on both sides of the channel portion 208 c .

[0040] An embodiment of the present application provides a semiconductor device, which reduces the occupied space of the thin film transistor by arranging the first electrode and the second electrode in different layers to form a vertically structured thin film transistor, thereby improving the pixel density and aperture ratio; at the same time, by arranging the first gate and the second gate respectively, the first gate and the second gate are arranged on both sides of the channel portion, the thin film transistor can be controlled by the first gate and the second gate, thereby improving the mobility of the thin film transistor, improving the gate control capability of the semiconductor device, and reducing the short channel effect.

[0041] Specifically, the semiconductor device includes a thin film transistor.

[0042] Specifically, in the embodiment of the present application, since the thin film transistor in the semiconductor device has a vertical structure, the channel length of the thin film transistor can be in the thickness direction. The channel length can be controlled by controlling the thickness and angle of the first gate, the first interlayer insulating layer and the first gate insulating layer, thereby reducing the channel length and improving the mobility. The first gate and the second gate are arranged on both sides of the channel portion, which can increase the channel width, thereby increasing the aspect ratio of the thin film transistor and improving the mobility of the thin film transistor.

[0043] Specifically, FIG2 illustrates an example in which the first gate 205 is disposed on the left side of the channel portion 208 c and the second gate 210 is disposed on the right side of the channel portion 208 c. However, the embodiments of the present application are not limited thereto. The first gate 205 may be disposed on the right side of the channel portion 208 c and the second gate 210 may be disposed on the left side of the channel portion 208 c.

[0044] In some embodiments, as shown in FIG2 , the active pattern 208 is non-annular, with one end of the active pattern 208 in contact with the first electrode 203, and the other end of the active pattern 208 in contact with the second electrode 207. The first gate 205 is disposed on one side of the channel portion 208c, and the second gate 210 is disposed on the other side of the channel portion 208c. By making the active pattern non-annular, the embodiment of the present application can reduce the space occupied by the active pattern, and accordingly reduce the space occupied by the first gate and the second gate, thereby reducing the size of the thin film transistor. Furthermore, by disposing the first gate and the second gate on one side of the channel portion, the gate control capability of the thin film transistor can be improved and the short channel effect can be reduced.

[0045] Specifically, as shown in Figure 2, Figure 2 takes the example of the first gate 205 and the second gate 210 being respectively arranged on the left and right sides of the channel portion 208c, but the embodiments of the present application are not limited to this. The first gate 205 can be arranged on both sides of the channel portion 208c, and the second gate 210 can be arranged on the other two sides of the channel portion 208c, thereby further improving the gate control capability of the thin film transistor.

[0046] In some embodiments, as shown in Figures 3 and 4, the active pattern 208 is annular, the second gate 210 is disposed within the annular channel portion 208c, and the first gate 205 is disposed on a side of the channel portion 208c away from the second gate 210. By making the active pattern annular, the corresponding channel portion annular, and the second gate disposed within the channel portion and the first gate disposed on a side of the channel portion away from the second gate, the channel width can be increased, thereby improving the mobility of the device.

[0047] Specifically, as shown in Figures 3 and 4, the active pattern is annular, and accordingly, the channel portion and the second doped portion are both annular, and the first doped portion can be circular, so that the area of ​​the channel portion is increased. At the same time, by arranging the second gate in the annular space formed by the channel portion and arranging the first gate outside the channel portion, the first gate and the second gate correspond to at least multiple parts of the annular channel portion, so that the channel width of the thin film transistor is increased, thereby improving the gate control ability of the thin film transistor and improving the mobility of the thin film transistor.

[0048] In some embodiments, either the first gate or the second gate is non-annular, the first gate is disposed on at least two sides of the active pattern, and the second gate is disposed on at least two sides of the channel portion, and the first gate and the second gate are disposed opposite each other. By disposing the first gate on at least two sides of the active pattern and the second gate on at least two sides of the channel portion, the first gate and the second gate can control portions of the channel portion in multiple directions, thereby improving the gate control capability of the thin film transistor, increasing the channel width of the thin film transistor, and improving the mobility of the thin film transistor.

[0049] Specifically, if the channel portion is annular, a second gate can be set in the four directions of the internal annular space of the channel portion to control the channel portion, and a first gate can be set on all four sides of the outside of the channel portion to control the channel portion. In this embodiment of the present application, a first gate and a second gate can be set in at least one direction to improve the gate control capability of the thin film transistor.

[0050] Specifically, for example, the annular channel portion can be divided into a left portion, a right portion, a front portion, and a rear portion. A second gate and a first gate can be respectively disposed on the inner and outer sides of the left portion of the channel portion, and a second gate and a first gate can be respectively disposed on the inner and outer sides of the right portion of the channel portion. This allows control of multiple portions of the channel portion, improving the gate control capability of the thin film transistor, increasing the channel width of the thin film transistor, and improving the mobility of the thin film transistor. The embodiments of the present application are not limited to this. For example, the second gate and the first gate can be disposed on both sides of multiple other portions of the channel portion to further improve the gate control capability of the thin film transistor and improve the mobility of the thin film transistor.

[0051] In some embodiments, as shown in Figures 3 and 4, at least one of the first gate 205 and the second gate 210 is annular, and the annular one of the first gate 205 and the second gate 210 is disposed corresponding to the annular channel portion 208c. By making at least one of the first gate and the second gate annular, the annular one of the first gate and the second gate can be disposed corresponding to the annular channel portion, further improving the gate control capability of the thin film transistor. Moreover, the annular one of the first gate and the second gate can make the channel width of the thin film transistor equal to the circumference of the annular channel portion, further increasing the channel width, thereby increasing the mobility of the thin film transistor.

[0052] Specifically, the first gate can be annular, so that the first gate is disposed around the channel portion, thereby increasing the gate control capability of the channel portion and improving the mobility of the thin film transistor. Alternatively, the second gate can be annular, so that the annular second gate is disposed corresponding to the annular channel portion, thereby increasing the gate control capability of the channel portion and improving the mobility of the thin film transistor.

[0053] In some embodiments, as shown in Figures 3 and 4, the first gate 205 is annular, and the second gate 210 is annular. The first gate 205 is disposed around the channel portion 208c, and the channel portion 208c is disposed around the second gate 210. By making the first and second gates both annular, with the first gate disposed around the channel portion, and the channel portion disposed around the second gate, each channel portion is provided with a first gate and a second gate on both sides. The thin film transistor can be controlled by the first and second gates, thereby improving the gate control capability of the thin film transistor. The channel width of the thin film transistor is equal to the circumference of the annular hole formed by the channel portion, making the channel width larger and improving the mobility of the thin film transistor.

[0054] In some embodiments, as shown in FIG3 and FIG4 , the semiconductor device 2 further includes:

[0055] A first interlayer insulating layer 204 is disposed between the first electrode 203 and the first gate 205 , and the first interlayer insulating layer 204 is disposed around the active pattern 208 ;

[0056] a second gate insulating layer 209 disposed between the active pattern 208 and the second gate 210;

[0057] A second interlayer insulating layer 211 is provided on a side of the second gate 210 away from the second gate insulating layer 209;

[0058] The first gate insulating layer 206 is disposed around the channel portion 208c, the second gate insulating layer 209 is disposed around the second gate 210, and the second gate 210 is disposed around the second interlayer insulating layer 211. Disposing the first gate insulating layer between the first gate and the channel portion prevents direct contact between the first gate and the channel portion, and the first gate insulating layer can be disposed around the channel portion to separate the first gate and the channel portion. Disposing the second gate insulating layer between the channel portion and the second gate, and surrounding the second gate, can separate the channel portion and the second gate, thereby preventing short circuits between the electrodes and improving the yield of the thin film transistor.

[0059] In some embodiments, the first gate is connected to the second gate, or when the semiconductor device is in an operating state, the potential on the first gate is equal to the potential on the second gate. By connecting the first gate and the second gate so that the potentials of the first gate and the second gate are equal, inputting a voltage to the first gate or the second gate can cause voltages to appear on both the first gate and the second gate, eliminating the need to provide multiple input signal lines and input ports, thereby reducing occupied space and resources. By ensuring that the potential on the first gate is equal to the potential on the second gate when the semiconductor device is in an operating state, the same potential can be input to the first gate and the second gate, reducing the occupation of input ports, reducing occupied space and resources.

[0060] Specifically, when the first gate and the second gate are connected, the first gate and the second gate may be connected through a hole in the display area, or the first gate and the second gate may be connected through a hole in the non-display area.

[0061] Specifically, when the potential on the first gate and the potential on the second gate are made equal, the first gate and the second gate can be connected to the same wiring, so that the same voltage is input to the first gate and the second gate through the wiring.

[0062] Specifically, the above embodiment is described by taking the case where the potentials of the first gate and the second gate are the same or connected as an example, but the embodiments of the present application are not limited thereto, and the potentials of the first gate and the second gate may be unequal.

[0063] In some embodiments, as shown in FIG3 , the second doped portion 208 b overlaps the second electrode 207 and contacts the sidewall of the second electrode 207. By overlapping the second doped portion on the second electrode and contacting the sidewall of the second electrode, the contact between the second doped portion and the second electrode can be improved, thereby improving the yield of the thin film transistor.

[0064] In some embodiments, as shown in FIG. 3 , the semiconductor device 2 further includes a buffer layer 202 .

[0065] Specifically, the material of the buffer layer includes one or more stacked layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium dioxide.

[0066] Specifically, the material of the buffer layer may be silicon nitride, thereby shielding metal ions in the substrate.

[0067] Specifically, the material of the first interlayer insulating layer includes one or more stacked layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium dioxide.

[0068] Specifically, the material of the first gate insulating layer includes one or more stacked layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium dioxide.

[0069] Specifically, the material of the second gate insulating layer includes one or more stacked layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium dioxide.

[0070] Specifically, the material of the second interlayer insulating layer includes one or more stacked layers of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, and hafnium dioxide.

[0071] Specifically, the materials of the first interlayer insulating layer, the first gate insulating layer and the second gate insulating layer can be silicon oxide, which can fill the oxygen vacancies in the active layer, reduce the risk of channel conductorization of the thin film transistor, and match the dielectric constant and work function.

[0072] Specifically, the material of the second gate insulating layer is a stack of silicon oxide and silicon nitride, thereby improving the barrier capability of the thin film transistor to hydrogen and water.

[0073] In some embodiments, as shown in FIG. 3 , the semiconductor device 2 further includes a pixel electrode layer 212 and a planarization layer 213 .

[0074] Specifically, the first electrode is a source electrode and the second electrode is a drain electrode; or the first electrode is a drain electrode and the second electrode is a source electrode.

[0075] Specifically, the material of the first electrode includes a single layer or a stack of multiple layers formed by one of aluminum, molybdenum, tungsten, and titanium. However, the embodiment of the present application is not limited thereto, and the first electrode can be a light-transmitting metal with low impedance.

[0076] Specifically, the material of the first gate includes a single layer or a stack of multiple layers formed by one of aluminum, molybdenum, tungsten, and titanium. However, the embodiment of the present application is not limited thereto, and the first gate can be a light-transmitting metal with low impedance.

[0077] Specifically, the material of the second electrode includes a single layer or a stack of multiple layers formed by one of aluminum, molybdenum, tungsten, and titanium. However, the embodiment of the present application is not limited thereto, and the second electrode can be a light-transmitting metal with low impedance.

[0078] Specifically, the material of the second gate includes a single layer or a stack of multiple layers formed by one of aluminum, molybdenum, tungsten, and titanium. However, the embodiment of the present application is not limited thereto, and the second gate can be a light-transmitting metal with low impedance.

[0079] Specifically, the active pattern material can be a stack of one or more of polysilicon and metal oxide. When the active pattern material is polysilicon, the active pattern can be formed using processes such as plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition. When the active pattern material is an oxide, it can be formed using processes such as atomic layer deposition or physical vapor deposition.

[0080] Specifically, the material of the active pattern includes indium gallium zinc oxide.

[0081] At the same time, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising:

[0082] Providing a substrate, and forming a buffer layer and a first electrode on the substrate; the structure of the semiconductor device corresponding to this step is shown in (a) of FIG5 ;

[0083] A first interlayer insulating layer and a first gate are formed on the first electrode; the structure of the semiconductor device corresponding to this step is shown in (b) of FIG5 ;

[0084] A first gate insulating layer and a second electrode are formed on the first gate. The structure of the semiconductor device corresponding to this step is shown in (c) of FIG. 5 ;

[0085] An active pattern is formed on the second electrode; the structure of the semiconductor device corresponding to this step is shown in (d) of FIG5 ;

[0086] A second gate insulating layer and a second gate are formed on the active pattern; the structure of the semiconductor device corresponding to this step is shown in (a) of FIG6 ;

[0087] A second interlayer insulating layer is formed on the second gate. The structure of the semiconductor device corresponding to this step is shown in (b) of FIG6 .

[0088] The second interlayer insulating layer is etched, and a pixel electrode layer is formed on the second interlayer insulating layer. The structure of the semiconductor device corresponding to this step is shown in (c) of FIG. 6 ;

[0089] A planarization layer is formed on the pixel electrode layer; the structure of the semiconductor device corresponding to this step is shown in FIG3 .

[0090] At the same time, an embodiment of the present application provides an electronic device, which includes the semiconductor device as described in any of the above embodiments.

[0091] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0092] The above is a detailed introduction to a semiconductor device and an electronic device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device comprising: substrate; A first electrode is provided on one side of the substrate; a first gate, disposed on a side of the first electrode away from the substrate; a first gate insulating layer, disposed on a side of the first gate away from the first electrode; a second electrode, disposed on a side of the first gate insulating layer away from the first gate; an active pattern comprising a channel portion and a first doped portion and a second doped portion located at both ends of the channel portion, wherein the first doped portion is connected to the first electrode, and the second doped portion is connected to the second electrode; and a second gate, disposed on a side of the active pattern away from the second electrode; The first gate insulating layer is disposed between the first gate and the channel portion, the channel portion overlaps the sidewall of the first gate insulating layer, and the first gate and the second gate are respectively disposed on both sides of the channel portion.

2. The semiconductor device according to claim 1, wherein The active pattern is non-annular, one end of the active pattern contacts the first electrode, the other end of the active pattern contacts the second electrode, the first gate is correspondingly arranged on one side of the channel portion, and the second gate is correspondingly arranged on the other side of the channel portion.

3. The semiconductor device according to claim 1, wherein The active pattern is ring-shaped, the second gate is arranged in the ring-shaped channel portion, and the first gate is arranged on a side of the channel portion away from the second gate.

4. The semiconductor device according to claim 3, wherein Either the first gate or the second gate is non-annular, the first gate is disposed on at least two sides of the active pattern, the second gate is disposed on at least two sides of the channel portion, and the first gate and the second gate are disposed opposite to each other.

5. The semiconductor device according to claim 3, wherein At least one of the first gate and the second gate is in a ring shape, and the ring-shaped one of the first gate and the second gate is disposed corresponding to the ring-shaped channel portion.

6. The semiconductor device according to claim 5, wherein The first gate is in a ring shape, the second gate is in a ring shape, the first gate is arranged around the channel portion, and the channel portion is arranged around the second gate.

7. The semiconductor device according to claim 6, wherein The semiconductor device further includes: a first interlayer insulating layer, disposed between the first electrode and the first gate, wherein the first interlayer insulating layer is disposed around the active pattern; a second gate insulating layer, disposed between the active pattern and the second gate; a second interlayer insulating layer, disposed on a side of the second gate away from the second gate insulating layer; The first gate insulating layer is arranged around the channel portion, the second gate insulating layer is arranged around the second gate, and the second gate is arranged around the second interlayer insulating layer.

8. The semiconductor device according to claim 1, wherein The first gate is connected to the second gate, or when the semiconductor device is in an operating state, the potential on the first gate is equal to the potential on the second gate.

9. The semiconductor device according to claim 1, wherein The second doped portion overlaps the second electrode, and the second doped portion contacts a sidewall of the second electrode.

10. The semiconductor device according to claim 1, wherein The first electrode is a source electrode, and the second electrode is a drain electrode; or the first electrode is a drain electrode, and the second electrode is a source electrode.

11. An electronic device comprising a semiconductor device, wherein the semiconductor device comprises: substrate; A first electrode is provided on one side of the substrate; a first gate, disposed on a side of the first electrode away from the substrate; a first gate insulating layer, disposed on a side of the first gate away from the first electrode; a second electrode, disposed on a side of the first gate insulating layer away from the first gate; an active pattern comprising a channel portion and a first doped portion and a second doped portion located at both ends of the channel portion, wherein the first doped portion is connected to the first electrode, and the second doped portion is connected to the second electrode; and a second gate, disposed on a side of the active pattern away from the second electrode; The first gate insulating layer is disposed between the first gate and the channel portion, the channel portion overlaps the sidewall of the first gate insulating layer, and the first gate and the second gate are respectively disposed on both sides of the channel portion.

12. The electronic device according to claim 11, wherein: The active pattern is non-annular, one end of the active pattern contacts the first electrode, the other end of the active pattern contacts the second electrode, the first gate is correspondingly arranged on one side of the channel portion, and the second gate is correspondingly arranged on the other side of the channel portion.

13. The electronic device according to claim 11, wherein: The active pattern is ring-shaped, the second gate is arranged in the ring-shaped channel portion, and the first gate is arranged on a side of the channel portion away from the second gate.

14. The electronic device according to claim 13, wherein: Either the first gate or the second gate is non-annular, the first gate is disposed on at least two sides of the active pattern, the second gate is disposed on at least two sides of the channel portion, and the first gate and the second gate are disposed opposite to each other.

15. The electronic device according to claim 13, wherein: At least one of the first gate and the second gate is in a ring shape, and the ring-shaped one of the first gate and the second gate is disposed corresponding to the ring-shaped channel portion.

16. The electronic device according to claim 15, wherein: The first gate is in a ring shape, the second gate is in a ring shape, the first gate is arranged around the channel portion, and the channel portion is arranged around the second gate.

17. The electronic device according to claim 16, wherein: The semiconductor device further includes: a first interlayer insulating layer, disposed between the first electrode and the first gate, wherein the first interlayer insulating layer is disposed around the active pattern; a second gate insulating layer, disposed between the active pattern and the second gate; a second interlayer insulating layer, disposed on a side of the second gate away from the second gate insulating layer; The first gate insulating layer is arranged around the channel portion, the second gate insulating layer is arranged around the second gate, and the second gate is arranged around the second interlayer insulating layer.

18. The electronic device according to claim 11, wherein: The first gate is connected to the second gate, or when the semiconductor device is in an operating state, the potential on the first gate is equal to the potential on the second gate.

19. The electronic device according to claim 11, wherein: The second doped portion overlaps the second electrode, and the second doped portion contacts a sidewall of the second electrode.

20. The electronic device according to claim 11, wherein The first electrode is a source electrode, and the second electrode is a drain electrode; or the first electrode is a drain electrode, and the second electrode is a source electrode.

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