RISC-v CPU-based instruction scheduling method and system

Abstract

The present invention relates to the technical field of computers, and disclosed are a RISC-V CPU-based instruction scheduling method and system. An instruction temporary storage cell is provided to store instructions having data correlation, so as to optimize an instruction scheduling mode; OITF detects a long-cycle instruction, and then related source and destination registers are stored in the OITF; upon detection of an instruction having correlation, the instruction that is being dispatched is stored in the instruction temporary storage cell, and the instruction temporary storage cell is controlled by means of the OITF so that the dispatching of previously correlated instructions from the instruction temporary storage cell can be continued when the long-cycle instruction is written back; and when the result of the long-cycle instruction is not returned, the instruction having data correlation dispatched each time is replaced with a nop instruction for execution. The present invention can temporarily store instructions having a dependency relationship with a long-cycle instruction, without blocking a pipeline, and can further improve the efficiency of the pipeline.

Description

A RISC-V CPU-based instruction scheduling method and system Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an instruction scheduling method and system based on a RISC-V CPU. Background Art

[0002] The Hummingbird E203 processor is an open-source embedded processor that outperforms the ARM Cortex-M series processors in both power consumption and performance. The Hummingbird E203 features a two-stage, in-order, single-issue architecture. The first stage is the instruction fetch unit (IFU), which performs simple decoding, retrieves the instruction type, performs simple branch prediction for branch instructions, and generates the program counter (PC) for the next instruction. The second stage is the execution unit (EXU), which includes decode, execute, fetch, commit, and writeback modules. The Hummingbird E203 needs to maintain and resolve pipeline conflicts during the execution phase, including data and resource conflicts. Common data conflicts include WAR (Write-After-Read), WAW (Write-After-Write), and RAW (Read-After-Write). A WAR dependency means that the target register of a later instruction is the same as the source register of a previous instruction. A WAW dependency means that the target register of a later instruction is the same as the source register of a previous instruction. Finally, a RAW dependency means that the source register of a later instruction is the same as the target register of a previous instruction. The Hummingbird E203 is a sequential, single-issue, write-back microarchitecture, so WAR dependencies are impossible. For single-cycle instructions, WAW and RAW dependencies cannot occur because the subsequent instruction must execute and write back after the previous instruction. For long-cycle instructions, since they require multiple cycles to execute before write back, WAW and RAW dependencies can arise when the subsequent instruction is dispatched.

[0003] To address the RAW and WAW issues, the Hummingbird E203 utilizes the Outstanding Instruction Trace FIFO (OTIF) module, a small-depth FIFO. When a dispatched instruction is a long-cycle instruction, an entry is allocated in the OTIF to store the index of the target register to which the instruction will be written back. Once the long-cycle instruction is executed and written back, the relevant information is deleted from the OTIF. However, this mechanism can block the pipeline, affecting execution efficiency.

[0004] Summary of the Invention

[0005] The technical task of the present invention is to address the above shortcomings and provide an instruction scheduling method and system based on RISC-V CPU, which can temporarily store instructions that have a dependency relationship with long-cycle instructions without blocking the pipeline, and can further improve the efficiency of the pipeline.

[0006] The technical solution adopted by the present invention to solve its technical problem is:

[0007] An instruction scheduling method based on RISC-V CPU optimizes instruction scheduling by setting an instruction temporary storage unit to store instructions with data dependency;

[0008] The OITF detects long-cycle instructions and stores the associated source and destination registers in the OITF. Upon detecting a dependent instruction, the currently dispatched instruction is stored in the instruction temporary storage unit. The OITF controls the instruction temporary storage unit so that when the long-cycle instruction is written back, the previously dispatched dependent instruction can continue to be dispatched from the instruction temporary storage unit. If the long-cycle instruction result is not returned, each dispatched instruction with data dependency is replaced with a nop instruction. When the instruction temporary storage unit is full, the pipeline is blocked.

[0009] Furthermore, the implementation of this method includes:

[0010] Instruction fetch unit, used to fetch instructions from storage and perform simple decoding;

[0011] A two-or-one selector is used to select between the instruction in the value unit and the instruction in the instruction temporary storage unit;

[0012] Instruction register, used to temporarily store instructions;

[0013] Decoding and dispatching unit, used to decode instructions and issue instructions;

[0014] Execution unit;

[0015] OTIF (Outstanding Instructions Track FIFO), which allocates an entry to store the index of the target register to which the instruction is written back;

[0016] When encountering data-related dependencies of long-cycle instructions, the temporary storage unit temporarily stores the dependent instructions in the instruction temporary storage unit, executes other instructions first, and then executes the instructions stored in the instruction temporary storage unit after the long-cycle instruction returns.

[0017] Furthermore, once the OTIF executes and writes back the long-cycle instruction, the relevant information of the long-cycle instruction will be deleted by the OTIF.

[0018] Furthermore, assuming that the temporary instruction storage unit is named TSC, the specific implementation process of the method is as follows:

[0019] 1) After the instruction is issued, determine whether OITF is empty;

[0020] 2) If OITF is empty, determine whether the current instruction is a long-cycle instruction;

[0021] 3) If it is a long-cycle instruction, check whether OITF is full;

[0022] 4) If the OITF is not full, the long-cycle instruction is written into the OITF; return to step 1) and distribute the next instruction;

[0023] 5) If it is detected that the OITF is not empty, determine whether the currently distributed instruction has data dependency with the long-cycle instruction stored in the OITF;

[0024] 6) If there is no data dependency, determine whether it is a long-cycle instruction;

[0025] 7) If it is a long cycle instruction, execute step 3);

[0026] 8) If it is determined that there is data dependency, determine whether the TSC is full;

[0027] 9) If the TSC is full, the pipeline is blocked;

[0028] 10) If the TSC is not full, write the instruction that has data dependency on the long-cycle instruction into the TSC and distribute a nop instruction to the execution unit as a replacement.

[0029] 11) If the next long-cycle instruction is not completed, the next instruction obtained by the instruction fetch unit that is not related to the long-cycle instruction will continue to be executed without blocking the pipeline;

[0030] 12) Until the long-cycle instruction is executed and the result is written back, the instructions stored in the TSC are continued to be distributed to the execution unit for execution, avoiding data dependencies.

[0031] The present invention also claims protection for an instruction scheduling system based on a RISC-V CPU, comprising an OITF module and an instruction temporary storage unit, wherein the instruction temporary storage unit is used to store instructions with data dependencies, thereby optimizing the instruction scheduling method;

[0032] The OITF detects long-cycle instructions and stores the associated source and destination registers in the OITF. Upon detecting a dependent instruction, the currently dispatched instruction is stored in the instruction temporary storage unit. The OITF controls the instruction temporary storage unit so that when the long-cycle instruction is written back, the previously dispatched dependent instruction can continue to be dispatched from the instruction temporary storage unit. If the long-cycle instruction result is not returned, each dispatched instruction with data dependency is replaced with a nop instruction. When the instruction temporary storage unit is full, the pipeline is blocked.

[0033] Furthermore, the system specifically includes:

[0034] Instruction fetch unit, used to fetch instructions from storage and perform simple decoding;

[0035] A two-or-one selector is used to select between the instruction in the value unit and the instruction in the instruction temporary storage unit;

[0036] Instruction register, used to temporarily store instructions;

[0037] Decoding and dispatching unit, used to decode instructions and issue instructions;

[0038] Execution unit;

[0039] OTIF (Outstanding Instructions Track FIFO), which allocates an entry to store the index of the target register to which the instruction is written back;

[0040] When encountering data-related dependencies of long-cycle instructions, the temporary storage unit temporarily stores the dependent instructions in the instruction temporary storage unit, executes other instructions first, and then executes the instructions stored in the instruction temporary storage unit after the long-cycle instruction returns.

[0041] Furthermore, once the OTIF executes and writes back the long-cycle instruction, the relevant information of the long-cycle instruction will be deleted by the OTIF.

[0042] Furthermore, assuming that the temporary instruction storage unit is named TSC, the specific implementation of the system is as follows:

[0043] 1) After the instruction is issued, determine whether OITF is empty;

[0044] 2) If OITF is empty, determine whether the current instruction is a long-cycle instruction;

[0045] 3) If it is a long-cycle instruction, check whether OITF is full;

[0046] 4) If the OITF is not full, the long-cycle instruction is written into the OITF; return to step 1) and distribute the next instruction;

[0047] 5) If it is detected that the OITF is not empty, determine whether the currently distributed instruction has data dependency with the long-cycle instruction stored in the OITF;

[0048] 6) If there is no data dependency, determine whether it is a long-cycle instruction;

[0049] 7) If it is a long cycle instruction, execute step 3);

[0050] 8) If it is determined that there is data dependency, determine whether the TSC is full;

[0051] 9) If the TSC is full, the pipeline is blocked;

[0052] 10) If the TSC is not full, write the instruction that has data dependency on the long-cycle instruction into the TSC and distribute a nop instruction to the execution unit as a replacement.

[0053] 11) If the next long-cycle instruction is not completed, the next instruction obtained by the instruction fetch unit that is not related to the long-cycle instruction will continue to be executed without blocking the pipeline;

[0054] 12) Until the long-cycle instruction is executed and the result is written back, the instructions stored in the TSC are continued to be distributed to the execution unit for execution, avoiding data dependencies.

[0055] The present invention also claims protection for an instruction scheduling device based on a RISC-V CPU, comprising: at least one memory and at least one processor;

[0056] The at least one memory is configured to store a machine-readable program;

[0057] The at least one processor is configured to call the machine-readable program to implement the above method.

[0058] The present invention also claims protection for a computer-readable medium having computer instructions stored thereon, which, when executed by a processor, cause the processor to perform the above-mentioned method.

[0059] Compared with the prior art, the RISC-V CPU-based instruction scheduling method and system of the present invention have the following beneficial effects:

[0060] The present invention provides a temporary storage control unit (TSC), which can temporarily store instructions that have a dependency relationship with long-cycle instructions without blocking the pipeline, thereby further improving the efficiency of the pipeline;

[0061] The present invention can be applied to the RISC-V processor pipeline architecture, optimizes the instruction scheduling method, and improves the pipeline execution efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 is a flowchart of an E203 OITF scheduling method according to an embodiment of the present invention;

[0063] FIG2 is a flow chart of scheduling optimization provided by one embodiment of the present invention;

[0064] FIG3 is a diagram of an E203 optimized pipeline framework provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0065] The present invention will be further described below with reference to specific embodiments.

[0066] An embodiment of the present invention provides an instruction scheduling method based on a RISC-V CPU, whose architecture includes an instruction fetch unit (IFU), a binary selector (MUX), an instruction register (IR), a decode and dispatch unit (Decode and dispatch), an execution unit (EXU), an Outstanding Instructions Track FIFO (OITF), and a temporary storage unit (TSC).

[0067] The instruction acquisition unit will fetch instructions from the storage and perform simple decoding;

[0068] The two-or-one selector selects between the instruction in the value acquisition unit and the instruction in the instruction temporary storage unit;

[0069] The instruction register temporarily stores instructions;

[0070] The decoding and dispatching unit decodes the instruction and issues the instruction;

[0071] The OTIF (Outstanding Instructions Track FIFO) allocates an entry to store the index of the target register to which the instruction is written back; once the long-cycle instruction is executed and written back, the relevant information of the long-cycle instruction will be deleted by the OTIF.

[0072] When encountering data-related dependencies of long-cycle instructions, the temporary storage unit (TSC) will temporarily store the dependent instructions in the instruction temporary storage unit (TSC), execute other instructions first, and then execute the instructions stored in the instruction temporary storage unit (TSC) after the long-cycle instruction returns.

[0073] The OITF is essentially a first-in, first-out FIFO, with a default FIFO depth of 2 entries. Each time a long-cycle instruction is dispatched at the pipeline dispatch point, an entry is allocated in the OITF, in which the source operand register index and result register index of the long-cycle instruction are stored. At the pipeline writeback point, each time a long-cycle instruction is written back in sequence, the entry for this instruction in the OITF is removed, that is, it is withdrawn from its FIFO and completes its historical mission. Therefore, what is stored in the OITF is the information of long-cycle instructions that have been dispatched and not yet written back. When each instruction is dispatched, the source operand register index and result register index of this instruction are compared with the various entries in the OITF to determine whether this instruction has RAW and WAW dependencies with long-cycle instructions that have been dispatched and not yet written back.

[0074] Figure 1 shows the E203 scheduling flow chart, which is divided into the following steps:

[0075] 1. First, when the instruction is distributed, determine whether OITF is empty;

[0076] 2. If it is empty, determine whether it is a long-cycle instruction;

[0077] 3. If it is a long-cycle instruction, determine whether OITF is full. If not, write the long-cycle instruction into OITF. If full, block the pipeline.

[0078] 4. Then go back to step 1. If OITF is not empty, it means there is a long-cycle instruction in it. It is necessary to determine whether the current instruction is related to the long-cycle instruction.

[0079] 5. If there is no correlation, return to determine whether it is a long-cycle instruction, and then follow the same process as after step 3;

[0080] 6. If it is determined to be relevant, the pipeline is blocked.

[0081] This is the original E203 OITF scheduling process.

[0082] From the above process, we can see that when OITF encounters long-cycle instructions and triggers data dependencies, it will block the pipeline and reduce pipeline efficiency. Therefore, the following improvements are made to the pipeline:

[0083] Figure 2 shows the scheduling optimization flow chart. A TSC unit is added to the OITF. The OITF still detects long-cycle instructions and then stores the relevant source and destination registers in the OITF. However, after detecting a related instruction, the pipeline is not blocked. Instead, the instruction being dispatched is stored in the TSC. The OITF controls the TSC so that when the long-cycle instruction is written back, it can continue to dispatch the previously related instructions from the TSC. When the result of the long-cycle instruction is not returned, each dispatched instruction with data dependency is replaced with a nop instruction for execution. When the TSC is full, the pipeline is blocked.

[0084] Figure 3 shows the optimized scheduling flow chart. The specific execution steps are as follows:

[0085] 1. After the instruction is issued, determine whether OITF is empty;

[0086] 2. If OITF is empty, determine whether the current instruction is a long-cycle instruction;

[0087] 3. If it is a long-cycle instruction, check whether OITF is full;

[0088] 4. If the OITF is not full, the long-cycle instruction is written into the OITF;

[0089] 5. Return to step 1 and dispatch the next instruction. If it is detected that OITF is not empty, determine whether the currently dispatched instruction has data correlation with the long-cycle instruction stored in OITF.

[0090] 6. If there is no data correlation, determine whether it is a long-cycle instruction;

[0091] 7. If it is a long-cycle instruction, execute step 3;

[0092] 8. If it is determined that there is data dependency, determine whether the TSC is full;

[0093] 9. If the TSC is full, the pipeline is blocked;

[0094] 10. If the TSC is not full, write the instruction that has data dependency on the long-cycle instruction into the TSC and distribute a nop instruction to the execution unit as a replacement.

[0095] 11. If the next long-cycle instruction is not completed, the next instruction obtained by the instruction fetch unit that is not related to the long-cycle instruction will continue to be executed without blocking the pipeline;

[0096] 12. Until the long-cycle instruction is executed and the result is written back, the instructions stored in the TSC will continue to be distributed to the execution unit for execution, avoiding data dependencies.

[0097] An embodiment of the present invention further provides an instruction scheduling system based on a RISC-V CPU, comprising an OITF module and an instruction temporary storage unit, wherein the instruction temporary storage unit (TSC) is used to store instructions with data dependencies, thereby optimizing the instruction scheduling method;

[0098] The OITF detects long-cycle instructions and stores the associated source and destination registers in the OITF. Upon detecting a dependent instruction, the dispatched instruction is stored in the instruction temporary storage unit. The OITF controls the instruction temporary storage unit so that when the long-cycle instruction is written back, the previously dispatched dependent instruction can be continued from the instruction temporary storage unit. If the long-cycle instruction result is not returned, each dispatched instruction with data dependency is replaced with a nop instruction. When the instruction temporary storage unit (TSC) is full, the pipeline is blocked.

[0099] The system specifically includes: instruction fetch unit (IFU), binary selector (MUX), instruction register (IR), decode and dispatch unit (Decodeanddispatch), execution unit (EXU), Outstanding Instructions Track FIFO (OITF), and temporary storage unit (TSC).

[0100] The instruction acquisition unit will fetch instructions from the storage and perform simple decoding;

[0101] The two-or-one selector selects between the instruction in the value acquisition unit and the instruction in the instruction temporary storage unit;

[0102] The instruction register temporarily stores instructions;

[0103] The decoding and dispatching unit decodes the instruction and issues the instruction;

[0104] The Outstanding Instructions Track FIFO (OTIF) allocates an entry to store the index of the target register to which the instruction is written back. Once a long-cycle instruction is executed and written back, the relevant information of the long-cycle instruction will be deleted by the OTIF.

[0105] When encountering data-dependent dependencies of long-cycle instructions, the temporary storage unit (TSC) temporarily stores the dependent instructions in the TSC, executes other instructions first, and then executes the instructions stored in the TSC after the long-cycle instruction returns.

[0106] The specific implementation of the system is as follows:

[0107] 1) After the instruction is issued, determine whether OITF is empty;

[0108] 2) If OITF is empty, determine whether the current instruction is a long-cycle instruction;

[0109] 3) If it is a long-cycle instruction, check whether OITF is full;

[0110] 4) If the OITF is not full, the long-cycle instruction is written into the OITF; return to step 1) and distribute the next instruction;

[0111] 5) If it is detected that the OITF is not empty, determine whether the currently distributed instruction has data dependency with the long-cycle instruction stored in the OITF;

[0112] 6) If there is no data dependency, determine whether it is a long-cycle instruction;

[0113] 7) If it is a long cycle instruction, execute step 3);

[0114] 8) If it is determined that there is data dependency, determine whether the TSC is full;

[0115] 9) If the TSC is full, the pipeline is blocked;

[0116] 10) If the TSC is not full, write the instruction that has data dependency on the long-cycle instruction into the TSC and distribute a nop instruction to the execution unit as a replacement.

[0117] 11) If the next long-cycle instruction is not completed, the next instruction obtained by the instruction fetch unit that is not related to the long-cycle instruction will continue to be executed without blocking the pipeline;

[0118] 12) Until the long-cycle instruction is executed and the result is written back, the instructions stored in the TSC are continued to be distributed to the execution unit for execution, avoiding data dependencies.

[0119] An embodiment of the present invention further provides an instruction scheduling device based on a RISC-V CPU, comprising: at least one memory and at least one processor;

[0120] The at least one memory is configured to store a machine-readable program;

[0121] The at least one processor is used to call the machine-readable program to implement the instruction scheduling method based on the RISC-V CPU described in the above embodiment.

[0122] An embodiment of the present invention further provides a computer-readable medium having computer instructions stored thereon. When executed by a processor, the computer instructions cause the processor to execute the RISC-V CPU-based instruction scheduling method described in the above embodiment. Specifically, a system or device equipped with a storage medium can be provided, on which software program code implementing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or device can be caused to read and execute the program code stored in the storage medium.

[0123] In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, and thus the program code and the storage medium storing the program code constitute part of the present invention.

[0124] Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, the program code can be downloaded from a server computer via a communication network.

[0125] In addition, it should be clear that the functions of any of the above embodiments can be achieved not only by executing the program code read by the computer, but also by enabling the operating system operating on the computer to complete part or all of the actual operations based on the instructions of the program code.

[0126] In addition, it can be understood that the program code read from the storage medium is written into the memory provided in the expansion board inserted into the computer or into the memory provided in the expansion unit connected to the computer, and then based on the instructions of the program code, the CPU installed on the expansion board or expansion unit is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above embodiments.

[0127] The present invention has been shown and described in detail above through the accompanying drawings and preferred embodiments. However, the present invention is not limited to these disclosed embodiments. Based on the above multiple embodiments, those skilled in the art can know that the code review methods in the above different embodiments can be combined to obtain more embodiments of the present invention, and these embodiments are also within the scope of protection of the present invention.

Claims

1. An instruction scheduling method based on RISC-V CPU, characterized in that: By setting up a temporary instruction storage unit to store instructions with data dependencies, the instruction scheduling method is optimized; OITF detects long-cycle instructions and then stores the relevant source register and destination register into OITF; After detecting the instructions with correlation, the instructions being dispatched are stored in the instruction temporary storage unit, and the instruction temporary storage unit is controlled by OITF so that when the long-cycle instruction is written back, the previously related instructions can be continued to be dispatched from the instruction temporary storage unit; when the result of the long-cycle instruction is not returned, each instruction with data correlation dispatched will be replaced by a nop instruction for execution.

2. The RISC-V CPU-based instruction scheduling method according to claim 1, wherein: The implementation of this method includes: Instruction fetch unit, used to fetch instructions from storage and perform simple decoding; A two-or-one selector is used to select between the instruction in the value unit and the instruction in the instruction temporary storage unit; Instruction register, used to temporarily store instructions; Decoding and dispatching unit, used to decode instructions and issue instructions; Execution unit; OTIF, used to allocate an entry to store the index of the target register that the instruction writes back; When encountering data-related dependencies of long-cycle instructions, the temporary storage unit temporarily stores the dependent instructions in the instruction temporary storage unit, executes other instructions first, and then executes the instructions stored in the instruction temporary storage unit after the long-cycle instruction returns.

3. The RISC-V CPU-based instruction scheduling method according to claim 2, wherein: Once the OTIF executes and writes back the long-cycle instruction, the relevant information of the long-cycle instruction will be deleted by the OTIF.

4. The RISC-V CPU-based instruction scheduling method according to claim 1, wherein: The temporary instruction storage unit is named TSC, and the specific implementation process of this method is as follows: 1) After the instruction is issued, determine whether OITF is empty; 2) If OITF is empty, determine whether the current instruction is a long-cycle instruction; 3) If it is a long-cycle instruction, check whether OITF is full; 4) If the OITF is not full, the long-cycle instruction is written into the OITF; Go back to step 1) and distribute the next instruction; 5) If it is detected that the OITF is not empty, determine whether the currently distributed instruction has data dependency with the long-cycle instruction stored in the OITF; 6) If there is no data dependency, determine whether it is a long-cycle instruction; 7) If it is a long cycle instruction, execute step 3); 8) If it is determined that there is data dependency, determine whether the TSC is full; 9) If the TSC is full, the pipeline is blocked; 10) If the TSC is not full, write the instruction that has data dependency on the long-cycle instruction into the TSC and distribute a nop instruction to the execution unit as a replacement. 11) If the next long-cycle instruction is not completed, the next instruction obtained by the instruction fetch unit that is not related to the long-cycle instruction will continue to be executed without blocking the pipeline; 12) Until the long-cycle instruction is executed and the result is written back, the instructions stored in the TSC are continuously distributed to the execution unit for execution.

5. An instruction scheduling system based on RISC-V CPU, characterized in that: It includes an OITF module and an instruction temporary storage unit, wherein the instruction temporary storage unit is used to store instructions with data dependency, thereby optimizing the instruction scheduling method; OITF detects long-cycle instructions and then stores the relevant source register and destination register into OITF; After detecting the instructions with correlation, the instructions being dispatched are stored in the instruction temporary storage unit, and the instruction temporary storage unit is controlled by OITF so that when the long-cycle instruction is written back, the previously related instructions can be continued to be dispatched from the instruction temporary storage unit; when the result of the long-cycle instruction is not returned, each instruction with data correlation dispatched will be replaced by a nop instruction for execution.

6. The RISC-V CPU-based instruction scheduling system according to claim 5, characterized in that: The system specifically includes: Instruction fetch unit, used to fetch instructions from storage and perform simple decoding; A two-or-one selector is used to select between the instruction in the value unit and the instruction in the instruction temporary storage unit; Instruction register, used to temporarily store instructions; Decoding and dispatching unit, used to decode instructions and issue instructions; Execution unit; OTIF, used to allocate an entry to store the index of the target register that the instruction writes back; When encountering data-related dependencies of long-cycle instructions, the temporary storage unit temporarily stores the dependent instructions in the instruction temporary storage unit, executes other instructions first, and then executes the instructions stored in the instruction temporary storage unit after the long-cycle instruction returns.

7. The RISC-V CPU-based instruction scheduling system according to claim 6, characterized in that: Once the OTIF executes and writes back the long-cycle instruction, the relevant information of the long-cycle instruction will be deleted by the OTIF.

8. The RISC-V CPU-based instruction scheduling system according to claim 5, wherein: The temporary instruction storage unit is named TSC, and the specific implementation of the system is as follows: 1) After the instruction is issued, determine whether OITF is empty; 2) If OITF is empty, determine whether the current instruction is a long-cycle instruction; 3) If it is a long-cycle instruction, check whether OITF is full; 4) If the OITF is not full, the long-cycle instruction is written into the OITF; Go back to step 1) and distribute the next instruction; 5) If it is detected that the OITF is not empty, determine whether the currently distributed instruction has data dependency with the long-cycle instruction stored in the OITF; 6) If there is no data dependency, determine whether it is a long-cycle instruction; 7) If it is a long cycle instruction, execute step 3); 8) If it is determined that there is data dependency, determine whether the TSC is full; 9) If the TSC is full, the pipeline is blocked; 10) If the TSC is not full, write the instruction that has data dependency on the long-cycle instruction into the TSC and distribute a nop instruction to the execution unit as a replacement. 11) If the next long-cycle instruction is not completed, the next instruction obtained by the instruction fetch unit that is not related to the long-cycle instruction will continue to be executed without blocking the pipeline; 12) Until the long cycle instruction is executed and the result is written back, the instruction stored in TSC is further divided into Send it to the execution unit for execution.

9. An instruction scheduling device based on RISC-V CPU, characterized in that: include: at least one memory and at least one processor; The at least one memory is configured to store a machine-readable program; The at least one processor is configured to call the machine-readable program to implement the method according to any one of claims 1 to 4.

10. A computer-readable medium, characterized in that The computer readable medium stores computer instructions, which, when executed by a processor, enable the processor to perform the method according to any one of claims 1 to 4.

Images