Memory and access control method therefor, and electronic device

Abstract

A memory and an access method therefor, and an electronic device. The memory comprises at least one storage array and a plurality of sensing amplifiers connected to the storage array; the storage array comprises at least one memory cell array, and the memory cell array comprises a plurality of memory cells and a plurality of bit lines; read transistors of the memory cells are respectively connected to the bit lines and a first reference voltage end or a read word line; the bit lines are connected to a common bit line; the common bit line is connected to a switch sub-circuit (12); and the switch sub-circuit (12) is configured to: in a signal sensing stage, connect a third reference voltage end to the common bit line; and in a signal amplification stage, disconnect the third reference voltage end from the common bit line, and in the signal sensing stage, output different voltages in the common bit line on the basis of different data stored in the memory cells.

Description

Memory and access control method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed on March 6, 2024, with application number 202410255545.0 and invention name “A memory and its access control method, and electronic device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, device design in the field of semiconductor technology, and in particular to a memory and an access control method thereof, and an electronic device. Background Art

[0003] With the advancement of integrated circuit technology, the critical dimensions of devices are shrinking, and the variety and number of devices contained in a single chip are increasing. This means that any slight difference in process production may affect device performance. To minimize product costs, people hope to produce as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. For example, 3D stacking of memory cells can cause coupling between the memory cells in 3D stacked devices, which can affect data readout.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The present application provides a memory, comprising:

[0007] At least one memory array, the memory array comprising at least one memory cell array and a sense amplifier connected to the memory cell array, the memory cell array comprising a plurality of memory cells and a plurality of bit lines; the memory cell comprising a read transistor, the read transistor comprising a first electrode and a second electrode, the first electrode being connected to the bit line, the second electrode being connected to a first reference voltage terminal or a read word line; the sense amplifier being connected to a second reference voltage terminal, and using a second reference voltage at the second reference voltage terminal as a reference voltage;

[0008] At least one common bit line, the common bit line corresponds to the memory cell array one-to-one, the common bit line is connected to multiple bit lines in the corresponding memory cell array, each common bit line corresponds to one sense amplifier, each common bit line is connected to a switch sub-circuit, and the switch sub-circuit is also connected to a third reference voltage terminal, wherein,

[0009] The switch subcircuit is configured to: connect the third reference voltage terminal and the common bit line in a signal sensing phase; and disconnect the third reference voltage terminal and the common bit line in a signal amplification phase;

[0010] The third reference voltage, the second reference voltage, and the first reference voltage of the third reference voltage terminal satisfy the following conditions: in a signal sensing phase, when the data stored in the memory cell is different, the common bit line outputs different voltages, and the output voltages have different magnitude relationships with the second reference voltage;

[0011] The first reference voltage is the voltage applied to the read word line during the signal sensing phase, or is the voltage at the first reference voltage terminal.

[0012] In some embodiments, the memory array includes multiple layers of the memory cell arrays stacked in a direction perpendicular to the substrate, and each layer of the memory cell array corresponds to one of the common bit lines.

[0013] In some embodiments, the voltage of the third reference voltage terminal is a fixed voltage; or, the voltage of the third reference voltage terminal is a variable voltage.

[0014] In some embodiments, the voltage of the third reference voltage terminal is a fixed voltage, and the third reference voltage < the second reference voltage < the first reference voltage, and the third reference voltage and the first reference voltage satisfy: when the switching sub-circuit and the read transistor are both turned on, the voltage of the common bit line is greater than the second reference voltage.

[0015] In some embodiments, the voltage of the third reference voltage terminal is a fixed voltage, the third reference voltage>the second reference voltage>the first reference voltage, and the third reference voltage and the first reference voltage satisfy: when the switching sub-circuit and the read transistor are both turned on, the voltage of the common bit line is less than the second reference voltage.

[0016] In some embodiments, the switching subcircuit includes a switching transistor, a gate electrode of the switching transistor is connected to a control line, a first electrode of the switching transistor is connected to the common bit line and an input terminal of the sense amplifier, and a second electrode of the switching transistor is connected to the third reference voltage terminal.

[0017] In some embodiments, gate control terminals of a plurality of the switch sub-circuits connected to a plurality of common bit lines of a same memory array are connected to a same control line, and the control line is configured to simultaneously turn on or off the plurality of the switch sub-circuits.

[0018] In some embodiments, the memory cell further includes a write transistor, and the bit line is a bit line shared by the read transistor and the write transistor.

[0019] In some embodiments, the memory cell further includes a write transistor, and the bit line is a read bit line connected only to the read transistor.

[0020] In some embodiments, the memory includes multiple memory arrays, and multiple sense amplifiers are arranged between two adjacent memory arrays along the extension direction of the common bit line, and every two common bit lines belonging to adjacent memory arrays are connected to the same sense amplifier, wherein one common bit line is connected to one end of the sense amplifier and the first switch sub-circuit, and the other common bit line is connected to the other end of the sense amplifier and the second switch sub-circuit.

[0021] An embodiment of the present disclosure provides a method for controlling access to a memory, including:

[0022] In the signal sensing phase, the switch sub-circuit connected to the common bit line of the memory cell to be accessed is controlled to be turned on, so as to connect the third reference voltage terminal and the common bit line;

[0023] During the signal amplification phase, the switch sub-circuit connected to the common bit line of the memory cell to be accessed is controlled to be closed, so that the common bit line is disconnected from the third reference voltage terminal.

[0024] In some embodiments, the method further includes: during the data write-back phase, turning off the switch sub-circuit connected to the common bit line of the memory cell to be accessed, so that the common bit line is disconnected from the third reference voltage terminal.

[0025] In some embodiments, the method further includes: in a pre-charging stage before the signal sensing stage, closing the switch sub-circuit connected to the common bit line of the memory cell to be accessed, so that the common bit line is disconnected from the third reference voltage terminal, and loading the second reference voltage to the common bit line.

[0026] An embodiment of the present disclosure provides an electronic device, comprising the memory described in any of the above embodiments.

[0027] In some embodiments, the electronic device further includes a control circuit, and the control circuit is configured to perform access control on the memory according to the above-mentioned memory access control method.

[0028] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0030] Summary of the Figures

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0032] FIG1 is a schematic diagram of a storage array provided by a technical solution;

[0033] FIG2A is a schematic diagram of a memory provided in an embodiment of the present application;

[0034] FIG2B is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment;

[0035] FIG2C is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment;

[0036] FIG3A is a schematic diagram of a memory provided by other embodiments;

[0037] FIG3B is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment;

[0038] FIG3C is a schematic diagram of an equivalent circuit of a memory cell provided by an exemplary embodiment;

[0039] FIG. 3D is a schematic diagram of an equivalent circuit of a sense amplifier provided by an exemplary embodiment.

[0040] Details

[0041] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0042] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0043] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0044] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0045] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0046] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to physical or signal connections, contact connections, or integral connections. They can be direct connections, indirect connections through intermediaries, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0047] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. The gate electrode may be single-gate or double-gate, and the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0048] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0049] In this disclosure, "connection" includes the connection of components via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0050] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0051] Memory can include multiple memory cells in a memory array. Capacitive coupling may exist between adjacent bit lines within multiple memory cells, particularly in 3D stacked memory cell applications. In this case, strong capacitive coupling between bit lines can affect signal sensing and amplification during readout, potentially leading to malfunctions.

[0052] FIG1 is a schematic diagram of a 3D stacked memory array provided by a technical solution. As shown in FIG1 , the memory may include a multi-layer memory cell array (memory cell arrays L1, L2, and L3 shown in FIG1 ), wherein the memory cell array includes a plurality of memory cells, each of which may be a 2T0C memory cell. The memory cell may include a read transistor and a write transistor, wherein the gate electrode of the write transistor is connected to a write word line WWL, the first electrode of the write transistor is connected to a write bit line WBL, the second electrode of the write transistor is connected to the first gate electrode of the read transistor, the second gate electrode of the read transistor is connected to a read word line RWL, the first electrode of the read transistor is connected to a read bit line RBL, and the second electrode of the read transistor is connected to a reference voltage terminal. Each layer of the memory cell array may correspond to a common read bit line, and the read bit line RBL may be connected to the corresponding common read bit line via a switch transistor. When a common read bit line is selected, one of the multiple switch transistors connected to the common read bit line is turned on, thereby conducting between the corresponding read bit line RBL and the common read bit line, and the other switch transistors are turned off, thereby disconnecting the other read bit lines RBL from the common read bit line. Each time a signal of a memory cell is read, it is electrically connected to a read bit line RBL through the corresponding common read bit line, and the data stored in the memory cell is determined by the signal of the read bit line RBL. For example, when data is read, when the data stored in the memory cell is "0", the voltage of the read bit line RBL is the precharge voltage; when the data stored in the memory cell is "1", according to the different relationship between the reference voltage terminal connected to the other electrode of the read transistor (the electrode not connected to the read bit line RBL, in this embodiment, the second electrode of the read transistor) and the precharge voltage of the read bit line RBL, through charge sharing, the voltage of the read bit line RBL can be greater than the precharge voltage (when the voltage of the reference voltage terminal is greater than the precharge voltage), or the voltage of the read bit line RBL can be less than the precharge voltage (when the voltage of the reference voltage terminal is less than the precharge voltage). That is, when the data stored in the memory cell is the logical value "0" or "1", the voltage of the read bit line RBL is different, so that "0" and "1" can be distinguished. However, when the data stored in a memory cell is "0," the read transistor is turned off during data reading, and the read bit line RBL is floating. At this point, if the coupling between the read bit line RBL and other read bit lines RBL is large, the voltage of the read bit line RBL may vary, resulting in data reading errors. Taking the three memory cells in Figure 1 as an example, the memory cell in memory cell array L2 stores data "0," the memory cells in memory cell arrays L1 and L3 store data "1," and the voltage at the reference voltage terminal connected to the second electrode of the read transistor is less than the precharge voltage Vpre of the read bit line RBL, then:

[0053] When reading data, the data stored in the memory cells of memory cell arrays L1 and L3 is "1," the read transistors are turned on, and charge is shared between read bit line RBL1 and the reference voltage terminal. The voltage of read bit line RBL1 drops from the precharge voltage Vpre, for example, by approximately 160 millivolts (mV). Similarly, the voltage of read bit line RBL3 drops from the precharge voltage Vpre, for example, by approximately 160 millivolts (mV). The voltages of read bit lines RBL1 and RBL3 are lower than the reference voltage of the sense amplifier.

[0054] The data stored in the memory cell of the memory cell array L2 is "0", and the read transistor is turned off. Under normal circumstances, the voltage of the read bit line RBL2 is maintained at the precharge voltage Vpre, which is greater than the reference voltage of the sense amplifier, so that "0" and "1" can be correctly distinguished; however, when there is a strong coupling capacitance between RBL1 and RBL2, RBL3 and RBL2 (i.e., the capacitance C shown in FIG1 ), BL_BL ), the voltage of RBL2 follows the voltages of RBL1 and RBL3, and therefore, the voltage of RBL2 decreases, making it impossible to distinguish data “0” from data “1”.

[0055] In an embodiment of the present disclosure, a switch sub-circuit connected to the common bit line is added. During the signal sensing stage, the switch sub-circuit is turned on so that the common bit line is connected to a preset reference voltage terminal through the switch sub-circuit, thereby preventing the common bit line from floating. Moreover, the influence of the preset reference voltage terminal connected to the switch sub-circuit on the voltage of the common bit line is smaller than the influence of the read transistor on the voltage of the common bit line, thereby allowing the data of the storage unit to be correctly read.

[0056] An embodiment of the present disclosure provides a memory, which may include:

[0057] At least one memory array and at least one sense amplifier connected to the memory array, the memory cell array including a plurality of memory cells and a plurality of bit lines; the memory cell including a read transistor, the read transistor including a first electrode and a second electrode, the first electrode being connected to the bit line, and the second electrode being connected to a first reference voltage terminal; the sense amplifier being connected to a second reference voltage terminal, the sense amplifier using a second reference voltage at the second reference voltage terminal as a reference voltage, i.e., a reference voltage for comparison with a signal detected from the memory cell;

[0058] At least one common bit line, the common bit line corresponds to the memory cell array one-to-one, the common bit line is connected to multiple bit lines in the corresponding memory cell array, each common bit line corresponds to one sense amplifier, each common bit line is connected to a switch sub-circuit, and the switch sub-circuit is also connected to a third reference voltage terminal, wherein,

[0059] The switch subcircuit is configured to: connect the third reference voltage terminal and the common bit line in a signal sensing phase; and disconnect the third reference voltage terminal and the common bit line in a signal amplification phase;

[0060] The third reference voltage, the second reference voltage, and the first reference voltage of the third reference voltage terminal satisfy the following conditions: in a signal sensing phase, when the data stored in the memory cells are different, the voltage output by the common bit line has a different magnitude relationship with the second reference voltage;

[0061] The first reference voltage is the voltage applied to the read word line during the signal sensing phase, or is the voltage at the first reference voltage terminal.

[0062] The solution provided in this embodiment, by setting a switch sub-circuit connected to the common bit line, connects the switch sub-circuit during the signal sensing stage, avoids the common bit line from floating, eliminates the influence of coupling between the common bit lines on the voltage of the common bit line, and by setting the relationship between the third reference voltage, the second reference voltage, and the first reference voltage, different voltages can be output on the common bit line when the data stored in the storage unit is different, thereby realizing correct reading of the data.

[0063] In some embodiments, the memory array may include a layer of memory cell array, or may include multiple layers of the memory cell array stacked in a direction perpendicular to the substrate, and each layer of the memory cell array may correspond to one of the common bit lines.

[0064] In some embodiments, the voltage of the third reference voltage terminal may be a fixed voltage; or the voltage of the third reference voltage terminal may be a variable voltage. The voltage of the common bit line after the switch sub-circuit is turned on can be changed by adjusting the voltage of the third reference voltage terminal.

[0065] In some embodiments, the third reference voltage, the second reference voltage, and the first reference voltage at the third reference voltage terminal satisfy the following relationship: the third reference voltage < the second reference voltage < the first reference voltage, and the third reference voltage and the first reference voltage satisfy the following relationship: when the switch sub-circuit and the read transistor are both turned on, the voltage of the common bit line is greater than the second reference voltage. In other words, the third reference voltage and the first reference voltage are appropriately configured such that, when the switch sub-circuit and the read transistor are both turned on, the charging effect of the first reference voltage terminal on the common bit line is greater than the discharging effect of the third reference voltage terminal on the common bit line, thereby bringing the voltage of the common bit line closer to the first reference voltage.

[0066] In some embodiments, the third reference voltage > the second reference voltage > the first reference voltage, and the third reference voltage and the first reference voltage satisfy the following condition: when the switch sub-circuit and the read transistor are both turned on, the voltage of the common bit line is less than the second reference voltage. That is, the third reference voltage and the first reference voltage are appropriately configured so that, when the switch sub-circuit and the read transistor are both turned on, the discharge effect of the first reference voltage terminal on the common bit line is greater than the charge effect of the third reference voltage terminal on the common bit line, thereby bringing the voltage of the common bit line closer to the first reference voltage.

[0067] In some embodiments, the memory cell further includes a write transistor, and the write bit line and the read bit line of the memory cell can be connected together. The read transistor and the write transistor of the same memory cell share a bit line, that is, the bit line connects the read transistor and the write transistor, and the bit line connected to the common bit line is the bit line shared by the read transistor and the write transistor.

[0068] In some embodiments, the write bit line and read bit line connected to the memory cell can be independently set, that is, the read transistor is connected to the read bit line, the write transistor is connected to the write bit line, and the bit line connected to the common bit line is the read bit line.

[0069] In some embodiments, the memory may include multiple memory arrays, wherein in two adjacent memory arrays, each two common bit lines belonging to the adjacent memory arrays are connected to the same sense amplifier, wherein one common bit line is connected between one end of the sense amplifier and the first switch sub-circuit, and another common bit line is connected between the other end of the sense amplifier and the second switch sub-circuit. The multiple sense amplifiers may be arranged between two adjacent memory arrays along the extension direction of the common bit lines.

[0070] In some embodiments, the storage unit may be a 2T0C storage unit, but is not limited thereto, and may be a 3T0C storage unit, etc. The storage unit may be a storage structure in which the read bit line may float during the signal sensing phase when the switch sub-circuit is not set.

[0071] The following describes the independent configuration of the read bit line and the write bit line, and the connection of the read bit line and the write bit line.

[0072] FIG2A is a schematic diagram of a memory circuit provided by some embodiments. As shown in FIG2A , embodiments of the present disclosure provide a memory device comprising at least one memory array, the memory array comprising a plurality of memory cell arrays (m memory cell arrays are shown in FIG2A ) stacked vertically on a substrate (i.e., stacked in a direction perpendicular to substrate 1). Each layer of the memory cell array comprises multiple rows and columns of memory cells 11 and multiple read bit lines RBL. Each column or every two columns of memory cells 11 is connected to a read bit line RBL. Each layer of the memory cell array corresponds to a common read bit line CRBL (e.g., m common read bit lines CRBL1 to CRBLm corresponding to the m memory cell arrays, respectively, as shown in FIG2A ). The common read bit line CRBL may be parallel to substrate 1. The memory cell 11 may include a read transistor T1 and a write transistor T2. The read transistor T1 may include a first gate electrode, a second gate electrode, a first electrode, and a second electrode. The first gate electrode of the read transistor T1 is connected to a read word line RWL, and the second gate electrode is connected to the first electrode of the write transistor T2. The first electrode of the read transistor T1 is connected to a read bit line RBL, and the read bit line RBL is connected to a common read bit line CRBL. The read bit line RBL may be connected to the common read bit line CRBL via a switching transistor, and the conduction and disconnection between the read bit line RBL and the common read bit line CRBL are controlled by the switching transistor (the switching transistor is omitted in FIG. 2A ). The second electrode of the read transistor T1 is connected to a first reference voltage terminal Vref1 (the voltage value of the first reference voltage terminal Vref1 is also represented by Vref1). The second electrode of the write transistor T2 is connected to the write bit line WBL, and the gate electrode of the write transistor T2 is connected to the write word line WWL. The memory cell 11 also includes a storage node SN, and the storage node SN includes the second gate electrode of the read transistor T1.

[0073] The memory may further include: multiple sense amplifiers SA and multiple switch sub-circuits 12. In this embodiment, the sense amplifier SA can determine whether the data stored in the memory cell 11 is a logical value of "1" or "0" by sensing signal changes on the common read bit line CRBL. Each common read bit line CRBL is connected to the first terminal of a switch sub-circuit 12, and the second terminal of the switch sub-circuit 12 is connected to the third reference voltage terminal Vref3. The switch sub-circuit 12 can control the connection (electrical connection) and disconnection between the common read bit line CRBL and the third reference voltage terminal Vref3. The sense amplifier SA may include two input ports: a first input terminal S1 and a second input terminal S2. One of the first input terminal S1 and the second input terminal S2 can serve as a signal detection terminal, and the other can serve as a signal reference terminal. For example, for the sense amplifier SA in FIG2A, the second input terminal S2 can serve as a signal reference terminal and be connected to the second reference voltage terminal Vref2; the first input terminal S1 serves as a signal detection terminal and is connected to the common read bit line RBL. It can detect signal changes on the common read bit line RBL and amplify and read the stored data of the memory cell connected to the first input terminal S1. A first terminal of the switch sub-circuit 12 may also be connected to a first input terminal S1 of the sense amplifier SA.

[0074] In some embodiments, the switch sub-circuit 12 may be a switch transistor, namely, a third transistor T3. A gate electrode of the third transistor T3 is connected to a control line CTRL, which is connected to a gate control terminal of a peripheral circuit via the control line CTRL. A first electrode of the third transistor T3 is connected to the common read bit line CRBL and the first input terminal of the sense amplifier SA. A second electrode of the third transistor T3 is connected to the third reference voltage terminal Vref3. However, the embodiments of the present disclosure are not limited thereto. The switch sub-circuit 12 may be other circuits capable of implementing a switch function.

[0075] In some embodiments, the voltages of the first reference voltage terminal Vref1, the second reference voltage terminal Vref2, and the third reference voltage terminal Vref3 may satisfy: Vref3>Vref2>Vref1. However, the embodiments of the present disclosure are not limited thereto. The voltages of the first reference voltage terminal Vref1, the second reference voltage terminal Vref2, and the third reference voltage terminal Vref3 may satisfy: Vref3>Vref2>Vref1. <Vref2<Vref1。

[0076] When Vref3>Vref2>Vref1, an example is provided for describing a memory cell in the first layer storing data "1" and a memory cell in the second layer storing data "0." The memory cell in the first layer stores data "1." During the signal sensing phase, read transistor T1 is turned on, and the first reference voltage terminal Vref1 discharges the first common read bit line CRBL1 (before the signal sensing phase, the voltage of CRBL1 is Vref2). Switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 charges the first common read bit line CRBL1. By at least one of setting the on-resistance of switch sub-circuit 12 and read transistor T1 (i.e., the third transistor T3 and read transistor T1), and setting the difference between Vref3 and Vref1, the effect of the first reference voltage terminal Vref1 discharging the first common read bit line CRBL1 can be greater than the effect of the third reference voltage terminal Vref3 charging the first common read bit line CRBL1, thereby causing the voltage of the first common read bit line CRBL1 to drop from Vref2 to less than Vref2.

[0077] The data stored in the storage cell of the second layer is "0". In the signal sensing stage, the read transistor T1 is turned off, the switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 charges the second common read bit line CRBL2, so that the voltage of the second common read bit line CRBL2 rises from Vref2 to greater than Vref2. Even if there are surrounding common read bit lines coupled with the second common read bit line CRBL2, since the second common read bit line CRBL2 is in a non-floating state, the voltage of the second common read bit line CRBL2 can still rise to greater than Vref2. It can be seen that when the data stored in the storage cell is different, "1" and "0" respectively, the voltage of the common read bit line CRBL is different, so that the data of the storage cell can be correctly read.

[0078] When Vref3 < Vref2 < Vref1, taking a memory cell 11 in the first layer with the stored data being "1" and a memory cell 11 in the second layer with the stored data being "0" as an example for illustration. The data stored in the memory cell 11 in the first layer is "1". In the signal sensing stage, the read transistor T1 is turned on, and the first reference voltage terminal Vref1 charges the first common read bit line CRBL1 (before the signal sensing stage, the voltage of CRBL1 is Vref2). The switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 discharges the first common read bit line CRBL1. By setting at least one of the following: setting the on-resistances of the switch sub-circuit 12 and the read transistor T1 (i.e., the third transistor T3 and the read transistor T1), and setting the magnitude between Vref3 and Vref1, the charging effect of the first reference voltage terminal Vref1 on the first common read bit line CRBL1 can exceed the discharging effect of the third reference voltage terminal Vref3 on the first common read bit line CRBL1, so that the voltage of the first common read bit line CRBL1 rises from Vref2 to a value greater than Vref2.

[0079] The data stored in the memory cell 11 in the second layer is "0". In the signal sensing stage, the read transistor T1 is turned off, the switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 discharges the second common read bit line CRBL2, causing the voltage of the second common read bit line CRBL2 to drop from Vref2 to a value less than Vref2. Even if there is coupling between the surrounding common read bit lines and the second common read bit line CRBL2, since the second common read bit line CRBL2 is in a non-floating state, the voltage of the second common read bit line CRBL2 can still drop to a value less than Vref2. It can be seen that when the data stored in the memory cell 11 is different, being "1" and "0" respectively, the voltages of the common read bit line CRBL are different (one is greater than Vref2 and the other is less than Vref2), so that the data of the memory cell 11 can be correctly read out.

[0080] In some embodiments, the equivalent resistance when the read transistor T1 is turned on can be less than the equivalent resistance when the switch sub-circuit 12 is turned on. In this embodiment, when both the read transistor T1 and the switch sub-circuit 12 are turned on, the voltage of the common read bit line CRBL is closer to the voltage of the first reference voltage terminal Vref1. When Vref3 > Vref2 > Vref1, the voltage of the common read bit line CRBL can drop to a value less than Vref2; when Vref3 < Vref2 < Vref1, the voltage of the common read bit line CRBL can rise to a value greater than Vref2.

[0081] In some embodiments, as shown in FIG2A , the switch sub-circuit 12 may include a third transistor T3. A gate electrode of the third transistor T3 is connected to a gate control terminal of a peripheral circuit via a control line CTRL. A first electrode of the third transistor T3 is connected to the common read bit line CRBL and the first input terminal S1 of the sense amplifier. A second electrode of the third transistor T3 is connected to the third reference voltage terminal Vref3. The third transistor T3 may be an N-type transistor, but the present disclosure is not limited thereto. The third transistor T3 may be a P-type transistor.

[0082] In some embodiments, the on-resistance of the third transistor T3 can be changed by changing the voltage of the control line CTRL. In addition, changing the third reference voltage Vref3 can also change the voltage of the common read bit line CRBL. Therefore, the voltage of the common read bit line CRBL can be changed by changing at least one of the voltages of CTRL and the third reference voltage Vref3.

[0083] In some embodiments, the multiple switch sub-circuits 12 connected to multiple common read bit lines CRBL of the same memory array are connected to the same control line CTRL, and the control line CTRL is configured to simultaneously turn on or off the multiple switch sub-circuits 12 connected to the control line CTRL.

[0084] The memory cell 11 shown in FIG2A is merely an example, and the present disclosure is not limited thereto. In some embodiments, as shown in FIG2B , the memory cell 11 may include a read transistor T1 and a write transistor T2. The read transistor T1 has a first electrode connected to a read bit line RBL, a second electrode connected to a first reference voltage terminal Vref1, a first gate electrode connected to a read word line RWL, and a second gate electrode connected to a first electrode of a write transistor T2. The write transistor T2 has a second electrode connected to a write bit line WBL, a first gate electrode connected to a first write word line WWL1, and a second gate electrode connected to a second write word line WWL2. The memory cell 11 also includes a storage node SN, which includes the second gate electrode of the read transistor T1. The operating state of the read transistor T1 in the memory cell 11 is similar to that of the read transistor T1 in the memory cell 11 in FIG2A and will not be further described.

[0085] In some embodiments, as shown in FIG2C , the memory cell 11 may include a read transistor T1 and a write transistor T2. The read transistor T1 has a first electrode connected to a read bit line RBL, a second electrode connected to a read word line RWL, and a gate electrode connected to a first electrode of the write transistor T2. The write transistor T2 has a second electrode connected to a write bit line WBL, and a gate electrode connected to a write word line WWL. The memory cell 11 also includes a storage node SN, which includes the gate electrode of the read transistor T1.

[0086] When the memory cell 11 is as shown in FIG2C , in the signal sensing phase, the read word line RWL is loaded with the first reference voltage Vref1 , and the first reference voltage Vref1 , the third reference voltage Vref3 , and the second reference voltage Vref2 satisfy the following conditions: Vref3>Vref2>Vref1 ; or Vref3 <Vref2<Vref1。

[0087] When the memory cell 11 is as shown in FIG2C and Vref3>Vref2>Vref1, a memory cell 11 storing data "1" in the first layer and a memory cell 11 storing data "0" in the second layer are used as examples for explanation. The data stored in the memory cell 11 in the first layer is "1". During the signal sensing phase, the read transistor T1 is turned on, the read word line RWL (the voltage loaded at this time is Vref1) discharges the first common read bit line CRBL1 (before the signal sensing phase, the voltage of CRBL1 is Vref2), the switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 charges the first common read bit line CRBL1, through at least one of the following: the on-resistance of the switch sub-circuit 12 and the on-resistance of the read transistor T1 (the on-resistance is the same as the on-resistance of the third transistor T3 or the read transistor T1) is connected. The on-resistance can be changed by changing the size of the transistor and the voltage loaded on the gate electrode of the third transistor T3 or the read transistor T1), and the size relationship between Vref3 and Vref1 can be set so that the effect of the read word line RWL discharging the first common read bit line CRBL1 exceeds the effect of the third reference voltage terminal Vref3 charging the first common read bit line CRBL1, thereby causing the voltage of the first common read bit line CRBL1 to drop from Vref2 to less than Vref2.

[0088] The data stored in the memory cell 11 of the second layer is "0". In the signal sensing stage, the read transistor T1 is turned off, the switch sub-circuit 12 is turned on, and the third reference voltage terminal Vref3 charges the second common read bit line CRBL2, so that the voltage of the second common read bit line CRBL2 rises from Vref2 to greater than Vref2. Even if there are surrounding common read bit lines coupled with the second common read bit line CRBL2, since the second common read bit line CRBL2 is in a non-floating state, the voltage of the second common read bit line CRBL2 can still rise to greater than Vref2. It can be seen that when the data stored in the memory cell 11 is different, namely "1" and "0" respectively, the voltage of the common read bit line CRBL is different, so that the data of the memory cell 11 can be correctly read.

[0089] The above solution can be applied to multi-bit memory cells. For example, the memory cell 11 can output more than two states. That is, the read transistor T1 can have multiple states with different conduction degrees. Correspondingly, the common read bit line presents different voltages under different conduction states of the read transistor T1. By sensing the voltage of the common read bit line CRBL, different logical data can be read out. In some embodiments, the voltage value of the third reference voltage terminal Vref3 can be changed according to different conduction states of the read transistor, so that the third reference voltage terminal Vref3 and the first reference voltage terminal Vvef1 can charge or discharge the common read bit line CRBL under different conduction states of the read transistor T1, making the common read bit line CRBL present different voltages under different conduction states, and realizing the correct reading of the data stored in the memory cell. For example, the read transistor T1 can include four states: off, the first conduction state, the second conduction state, and the third conduction state (the conduction degrees of the subsequent three conduction states increase in sequence), corresponding to four different logical data respectively. When the read transistor T1 is in the off state, the third reference voltage terminal Vref3 (taking Vref3 > Vref2 > Vref1 as an example) charges the common read bit line CRBL, making the voltage of the common read bit line CRBL rise from Vref2 to a voltage greater than Vref2. When the read transistor T1 is in the first conduction state, the third reference voltage terminal Vref3 charges the common read bit line CRBL, and the first reference voltage terminal Vref1 discharges the common read bit line CRBL, making the voltage of the common read bit line CRBL drop from Vref2 to a voltage V1 less than Vref2; when the read transistor T1 is in the second conduction state, the third reference voltage terminal Vref3 charges the common read bit line CRBL, and the first reference voltage terminal Vref1 discharges the common read bit line CRBL, making the voltage of the common read bit line CRBL drop from Vref2 to a voltage V2 less than Vref2; when the read transistor T1 is in the third conduction state, the third reference voltage terminal Vref3 charges the common read bit line CRBL, and the first reference voltage terminal Vref1 discharges the common read bit line CRBL, making the voltage of the common read bit line CRBL drop from Vref2 to a voltage V3 less than Vref2. The voltage value of the third reference voltage terminal Vref3 can be adjusted so that V3 < V2 < V1, so that the common read bit line CRBL presents different voltages under different conduction states, and realizes the correct reading of the data stored in the memory cell. The above four states are only examples, and the memory cell 11 can be other multi-bit memory cells.

[0090] FIG3A is a schematic diagram of a memory circuit provided in some other embodiments. As shown in FIG3A , the memory provided in this embodiment may include: multiple memory arrays 1, with two adjacent memory arrays 1 shown in FIG3A . The memory arrays 1 include multiple layers of memory cell arrays 10 stacked vertically on a substrate. Each layer of the memory cell array 10 includes multiple rows and columns of memory cells 11 and multiple bit lines (not shown in FIG3A ), with each column or every two columns of memory cells 11 connected to a bit line. Each layer of the memory cell array 10 corresponds to a common bit line CBL (such as CBL1 to CBLk and CBLk to CBLn shown in FIG3A ). The memory may also include: multiple sense amplifiers SA and multiple switching sub-circuits 12. The two input terminals of the sense amplifier SA are respectively connected to the common bit lines of adjacent memory arrays 1. If the common bit lines of two adjacent memory arrays share SA, the two input terminals of SA are respectively connected to the common bit lines of the two memory arrays. When detecting a signal change in one of the common bit lines, the other common bit line serves as the signal reference terminal. For example, for the memory array 1 on the left side of FIG3A , the second input terminal S2 can serve as a signal reference terminal, and the first input terminal S1 is connected to the common bit line CBL and serves as a signal detection terminal. Signal changes of the common bit line CBL can be detected through the first input terminal S1 to amplify and read the storage data of the memory cell 11 connected to the first input terminal S1.

[0091] Alternatively, for the memory array 1 on the right side of FIG3A , the first input terminal S1 can be used as a signal reference terminal, and the second input terminal S2 can be used as a signal detection terminal to detect signal changes of the common bit line CBL, thereby reading the storage data of the memory cell 11 connected to the second input terminal S2.

[0092] Each common bit line CBL is connected to the first end of a switch sub-circuit 12, and the second end of the switch sub-circuit 12 is connected to the third reference voltage terminal Vref3. The switch sub-circuit 12 can control the connection (electrical connection) and disconnection between the common bit line CBL and the third reference voltage terminal Vref3. The first end of the switch sub-circuit 12 can also be connected to the input terminal of the sense amplifier SA connected to the common bit line CBL. For example, for the memory array 1 on the left, the first end of the switch sub-circuit 12 is connected to the first input terminal S1 of the sense amplifier SA, and for the memory array 1 on the right, the first end of the switch sub-circuit 12 is connected to the second input terminal S2 of the sense amplifier SA.

[0093] As shown in FIG3B , the memory cell 11 may include a read transistor T1 and a write transistor T2. The first gate electrode of the read transistor T1 is connected to a read word line RWL, and the second gate electrode is connected to the first electrode of the write transistor T2. The first electrode of the read transistor T1 is connected to a bit line BL, which is connected to a common bit line CBL. The bit line BL may be connected to the common bit line CBL via a switching transistor, and the switching transistor controls the conduction and disconnection between the bit line BL and the common bit line CBL (the switching transistor is omitted in FIG3A ). The second electrode of the read transistor T1 is connected to a first reference voltage terminal Vref1, the second electrode of the write transistor T2 is connected to the bit line BL, and the gate electrode of the write transistor T2 is connected to the write word line WWL. That is, in this embodiment, the read bit line and the write bit line are connected to form a single bit line. The memory cell 11 also includes a storage node SN, which includes the second gate electrode of the read transistor T1.

[0094] Alternatively, as shown in FIG3C , the memory cell 11 may include a read transistor T1 and a write transistor T2. The first gate electrode of the read transistor T1 is connected to a read word line RWL, and the second gate electrode is connected to the first electrode of the write transistor T2. The first electrode of the read transistor T1 is connected to a bit line BL, which is connected to a common bit line CBL. The bit line BL may be connected to the common bit line CBL via a switching transistor, and the switching transistor controls the conduction and disconnection between the bit line BL and the common bit line CBL (the switching transistor is omitted in FIG3A ). The second electrode of the read transistor T1 is connected to a first reference voltage terminal Vref1, and the second electrode of the write transistor T2 is connected to the bit line BL. The first gate electrode of the write transistor T2 is connected to a first write word line WWL1, and the second gate electrode is connected to a second write word line WWL2. The memory cell 11 also includes a storage node SN, which includes the second gate electrode of the read transistor T1.

[0095] In some embodiments, the memory may include a first memory array and a second memory array. The multiple switch sub-circuits 12 respectively connected to the multiple common bit lines of the first memory array may be connected to the same control line, for example, the first control line CTRL1; the multiple switch sub-circuits 12 respectively connected to the multiple common bit lines of the second memory array may be connected to the same control line, for example, the second control line CTRL2. When the switch sub-circuit 12 includes a third transistor T3, the gate electrodes of the multiple third transistors T3 respectively connected to the multiple common bit lines of the first memory array may be connected to the first control line CTRL1, and the gate electrodes of the multiple third transistors T3 respectively connected to the multiple common bit lines of the second memory array may be connected to the second control line CTRL2.

[0096] In some embodiments, as shown in FIG3D , the sense amplifier SA may include a pre-charge sub-circuit 31 and a differential amplification sub-circuit 32 , wherein:

[0097] The pre-charging sub-circuit 31 is connected to the first input terminal S1, the second input terminal S2, the first control terminal EQ_ctrl, and the second reference voltage terminal Vref2, and is configured to, under the control of the first control terminal EQ_ctrl, load the voltage of the second reference voltage terminal Vref2 to the first input terminal S1 and the second input terminal S2;

[0098] The differential amplifier sub-circuit 32 is connected to the first input terminal S1, the second input terminal S2, the first enable terminal SAP_EN, the first voltage control terminal SAP, the second enable terminal SAN_EN, and the second voltage control terminal SAN, and is configured to amplify the differential input between the first input terminal S1 and the second input terminal S2 and output it through the first input terminal S1 and the second input terminal S2 under the control of the first enable terminal SAP_EN, the second enable terminal SAN_EN, the first voltage control terminal SAP, and the second voltage control terminal SAN.

[0099] In some embodiments, as shown in FIG3D , the pre-charge sub-circuit 31 may include a fourth transistor T4 and a fifth transistor T5 , wherein:

[0100] A first electrode of the fourth transistor T4 is connected to the first input terminal S1, a second electrode is connected to the first electrode of the fifth transistor T5 and is connected to the second reference voltage terminal Vref2, a second electrode of the fifth transistor T5 is connected to the second input terminal S2, and a gate electrode of the fourth transistor T4 and a gate electrode of the fifth transistor T5 are connected to the first control terminal EQ_ctrl;

[0101] In some embodiments, as shown in FIG3D , the differential amplifier sub-circuit 32 may include a sixth transistor T6 , a seventh transistor T7 , an eighth transistor T8 , a ninth transistor T9 , a tenth transistor T10 , and an eleventh transistor T11 , wherein:

[0102] The gate electrode of the sixth transistor T6 and the gate electrode of the eighth transistor T8 are connected to the second input terminal S2, the first electrode of the sixth transistor T6 is connected to the first electrode of the tenth transistor T10, and the second electrode of the sixth transistor T6 is connected to the first input terminal S1;

[0103] The gate electrode of the seventh transistor T7 and the gate electrode of the ninth transistor T9 are connected to the first input terminal S1, the first electrode of the seventh transistor T7 is connected to the first electrode of the tenth transistor T10, and the second electrode of the seventh transistor T7 is connected to the second input terminal S2;

[0104] A first electrode of the eighth transistor T8 is connected to the first input terminal S1, and a second electrode of the eighth transistor T8 is connected to the first electrode of the eleventh transistor T11;

[0105] A first electrode of the ninth transistor T9 is connected to the second input terminal S2, and a second electrode of the ninth transistor T9 is connected to the first electrode of the eleventh transistor T11;

[0106] A second electrode of the tenth transistor T10 is connected to the first voltage control terminal SAP, and a gate electrode of the tenth transistor T10 is connected to the first enable terminal SAP_EN;

[0107] A second electrode of the eleventh transistor T11 is connected to the second voltage control terminal SAN, and a gate electrode of the eleventh transistor T11 is connected to the second enable terminal SAN_EN.

[0108] In some embodiments, the sixth transistor T6 , the seventh transistor T7 , and the tenth transistor T10 may be P-type transistors, and the fourth transistor T4 , the fifth transistor T5 , the eighth transistor T8 , the ninth transistor T9 , and the eleventh transistor T11 may be N-type transistors.

[0109] In some embodiments, the first voltage control terminal SAP may be, for example, a high-level signal, and the second voltage control terminal SAN may be, for example, a low-level signal.

[0110] The sense amplifier circuit shown in FIG3D is only an example, and the embodiments of the present disclosure are not limited thereto. Any circuit that can implement sense amplification can be applied in the embodiments of the present application.

[0111] The following describes the operation of the memory shown in FIG3A using an example. In this embodiment, the memory cell 11 is shown in FIG3B , the sense amplifier is shown in FIG3D , and Vref1>Vref2>Vref3. In this embodiment, the access process to a memory cell 11 (taking a memory cell 11 of the first memory array as an example) may include a precharge phase t1, a signal sensing phase t2, a signal amplification phase t3, and a data write-back phase t4, where:

[0112] Precharge phase t1: The first control terminal EQ_ctrl is loaded with a conduction signal, the fourth transistor T4 and the fifth transistor T5 are turned on, and the voltage of the second reference voltage terminal Vref2 is loaded to the first input terminal S1 and the second input terminal S2. The voltage of the first input terminal S1 is loaded to the common bit line CBL, that is, the voltage of the common bit line CBL is Vref2; the first control line CTRL1 is loaded with a shutdown signal, so that the third transistor T3 is turned off; the read word line RWL and the write word line WWL are loaded with a shutdown signal, and the read transistor T1 and the write transistor T2 are turned off;

[0113] Signal sensing phase t2: The first control terminal EQ_ctrl applies a shutdown signal, turning off the fourth and fifth transistors T4 and T5. The first control line CTRL1 applies a turn-on signal, turning on the third transistor T3. The read word line RWL applies a turn-on signal. When the data stored in the memory cell is "0," the read transistor T1 is turned off, and the third reference voltage terminal Vref3 discharges the common bit line CBL (e.g., to a voltage Vref3 on the common bit line CBL), causing the voltage on the common bit line CBL to be less than Vref2. When the data stored in the memory cell is "1," the read transistor T1 is turned on, and the first reference voltage terminal Vref1 charges the common bit line CBL, while the third reference voltage terminal Vref3 discharges the common bit line CBL. The charging effect of the first reference voltage terminal Vref1 on the common bit line CBL is greater than the discharging effect of the third reference voltage terminal Vref3 on the common bit line CBL, thereby boosting the voltage on the common bit line CBL to a voltage greater than Vref2.

[0114] Signal amplification stage t3: the first control line CTRL1 is loaded with a shutdown signal, so that the third transistor T3 is turned off; the read word line RWL is loaded with a shutdown signal, so that the read transistor T1 is turned off; the first enable terminal SAP_EN and the second enable terminal SAN_EN are loaded with an enable signal (in the remaining stages, the first enable terminal SAP_EN and the second enable terminal SAN_EN can be loaded with a non-enable signal), so that the tenth transistor T10 is turned on and the eleventh transistor T11 is turned on, so that the differential sub-circuit 32 can amplify the signal. According to the data stored in the storage cell 11, the first input terminal S1 and the second input terminal S2 output corresponding voltages. For example, if the data stored in the storage cell is "1", the voltage of the first input terminal S1 is pulled up to the voltage corresponding to the data "1", the common bit line CBL is the voltage corresponding to the data "1", and the second input terminal S2 is pulled down to the voltage corresponding to the data "0". The data "1" can be read by reading the level of the first input terminal S1. If the data stored in the memory cell 11 is "0", the voltage of the first input terminal S1 is pulled down to the voltage corresponding to the data "0", the common bit line CBL is the voltage corresponding to the data "0", and the second input terminal S2 is pulled up to the voltage corresponding to the data "1". The data "0" can be read by reading the level of the first input terminal S1.

[0115] Data write-back phase t4: The read word line RWL is loaded with a shutdown signal, turning off the read transistor T1. The first control line CTRL1 is loaded with a shutdown signal, keeping the third transistor T3 off. The write word line WWL is loaded with a conduction signal, turning on the write transistor T2. The common bit line CBL and the storage node SN share charge, writing the voltage corresponding to the data "1" or "0" to the storage node SN. The precharge phase then re-enters, waiting for the read and write operations to be performed.

[0116] The above-mentioned on- and off-signals depend on the transistor type. For N-type transistors, the on-signal is a high-level signal, and the off-signal is a low-level signal. For P-type transistors, the on-signal is a low-level signal, and the off-signal is a high-level signal. The enable and disable signals depend on the transistor type. The enable signal turns the transistor on, and the disable signal turns it off.

[0117] The present disclosure provides an access control method for the above-mentioned memory, which may include:

[0118] In a signal sensing phase, controlling a switch subcircuit connected to a common bit line of the memory cell to be accessed to be turned on, so as to connect the third reference voltage terminal and the common bit line;

[0119] During the signal amplification phase, the switch sub-circuit connected to the common bit line of the memory cell to be accessed is controlled to be closed, so that the common bit line is disconnected from the third reference voltage terminal.

[0120] The solution provided in this embodiment prevents the common bit line from floating by connecting the third reference voltage terminal and the common bit line during the signal sensing phase, eliminates the influence of common bit line coupling on data reading, and realizes correct data reading.

[0121] In some embodiments, the method may further include: during the data write-back phase, turning off the switch sub-circuit connected to the common bit line of the memory cell to be accessed, so that the common bit line is disconnected from the third reference voltage terminal.

[0122] In some embodiments, the method may further include: in a pre-charging stage before the signal sensing stage, closing the switch sub-circuit connected to the common bit line of the memory cell to be accessed, so that the common bit line is disconnected from the third reference voltage terminal, and loading the second reference voltage to the common bit line.

[0123] The present disclosure also provides an electronic device comprising the memory device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include, but is not limited to, computer memory.

[0124] In some embodiments, the electronic device may further include a control circuit configured to control access to the memory according to any of the access control methods described above. The control circuit may include circuits and control lines capable of generating control signals to control the switch subcircuit, thereby implementing access control to the memory. The control circuit, together with the SA and the like, implements access to the memory.

[0125] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A memory comprising: At least one memory array and at least one sense amplifier connected to the memory array, the memory array including at least one memory cell array, the memory cell array including a plurality of memory cells and a plurality of bit lines; the memory cell including a read transistor, the read transistor including a first electrode and a second electrode, the first electrode connected to the bit line, the second electrode connected to a first reference voltage terminal or a read word line; the sense amplifier connected to a second reference voltage terminal, using a second reference voltage at the second reference voltage terminal as a reference voltage; At least one common bit line, the common bit line corresponds to the memory cell array one-to-one, the common bit line is connected to multiple bit lines in the corresponding memory cell array, each common bit line corresponds to one sense amplifier, each common bit line is connected to a switch sub-circuit, and the switch sub-circuit is also connected to a third reference voltage terminal, wherein, The switch subcircuit is configured to: connect the third reference voltage terminal and the common bit line in a signal sensing phase; and disconnect the third reference voltage terminal and the common bit line in a signal amplification phase; The third reference voltage, the second reference voltage, and the first reference voltage of the third reference voltage terminal satisfy the following conditions: in a signal sensing phase, when the data stored in the memory cell is different, the common bit line outputs different voltages, and the output voltages have different magnitude relationships with the second reference voltage; The first reference voltage is the voltage applied to the read word line during the signal sensing phase, or is the voltage at the first reference voltage terminal.

2. The memory according to claim 1, wherein The memory array includes multiple layers of memory cell arrays stacked in a direction perpendicular to the substrate, and each layer of the memory cell array corresponds to one common bit line.

3. The memory according to claim 1, wherein The voltage of the third reference voltage terminal is a fixed voltage; or, the voltage of the third reference voltage terminal is a variable voltage.

4. The memory according to claim 1, wherein The voltage of the third reference voltage terminal is a fixed voltage, and the third reference voltage < the second reference voltage < the first reference voltage, and the third reference voltage and the first reference voltage satisfy: when the switch sub-circuit and the read transistor are both turned on, the voltage of the common bit line is greater than the second reference voltage.

5. The memory according to claim 1, wherein The voltage of the third reference voltage terminal is a fixed voltage, the third reference voltage>the second reference voltage>the first reference voltage, and the third reference voltage and the first reference voltage satisfy: when the switch sub-circuit and the read transistor are both turned on, the voltage of the common bit line is less than the second reference voltage. The memory according to claim 1 , wherein: The switch subcircuit includes a switch transistor, a gate electrode of the switch transistor is connected to the control line, a first electrode of the switch transistor is connected to the common bit line and an input terminal of the sense amplifier, and a second electrode of the switch transistor is connected to the third reference voltage terminal.

7. The memory according to claim 6, wherein The gate control terminals of the plurality of switch sub-circuits connected to the plurality of common bit lines of the same memory array are connected to the same control line, and the control line is configured to simultaneously turn on or off the plurality of switch sub-circuits.

8. The memory according to claim 1, wherein The memory cell further includes a write transistor, and the bit line is a bit line shared by the read transistor and the write transistor of the same memory cell.

9. The memory according to claim 1, wherein The memory cell further includes a write transistor, and the bit line is a read bit line connected only to the read transistor.

10. The memory according to claim 1, wherein The memory includes multiple memory arrays, and the multiple sense amplifiers are arranged between two adjacent memory arrays along the extension direction of the common bit line. Every two common bit lines belonging to adjacent memory arrays are connected to the same sense amplifier, wherein one common bit line is connected to one end of the sense amplifier and the first switch sub-circuit, and the other common bit line is connected to the other end of the sense amplifier and the second switch sub-circuit.

11. A method for controlling access to a memory according to any one of claims 1 to 10, comprising: In a signal sensing phase, controlling a switch subcircuit connected to a common bit line of the memory cell to be accessed to be turned on, so as to connect the third reference voltage terminal and the common bit line; During the signal amplification phase, the switch sub-circuit connected to the common bit line of the memory cell to be accessed is controlled to be closed, so that the common bit line is disconnected from the third reference voltage terminal.

12. The memory access control method according to claim 11, further comprising: In the data write-back phase, the switch sub-circuit connected to the common bit line of the memory cell to be accessed is turned off, so that the common bit line is disconnected from the third reference voltage terminal.

13. The memory access control method according to claim 11, further comprising: In the precharge phase before the signal sensing phase, the switch subcircuit connected to the common bit line of the memory cell to be accessed is turned off, so that the common bit line is disconnected from the third reference voltage terminal, and the second reference voltage is loaded to the common bit line.

14. An electronic device comprising the memory according to any one of claims 1 to 10.

15. The electronic device according to claim 14, wherein The electronic device further includes a control circuit, and the control circuit is configured to perform access control on the memory according to the memory access control method according to any one of claims 11 to 13.

Images