Chip packaging structure, manufacturing method therefor and electronic device

Abstract

The present application provides a chip packaging structure, a manufacturing method therefor and an electronic device. The chip packaging structure comprises a substrate; a chip, the chip being arranged on the substrate; a packaging layer, the packaging layer being arranged on the substrate and surrounding the chip. At least one first chamfer structure is formed on the packaging layer, and the first chamfer structure is arranged between two adjacent side walls on the packaging layer. The present application can reduce the stress at corners of the chip packaging structure, thereby reducing the risk of cracks or even fractures in the packaging layer.

Description

Chip packaging structure and manufacturing method thereof, and electronic equipment Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the continuous development of artificial intelligence and big data, the size of chip packaging structures is required to be larger and larger. Wafer-level chip packaging can meet the requirements of large-size packaging. The chip packaging structure can usually include a multi-layer structure, and the coefficient of thermal expansion (CTE) between the layers is quite different. During the temperature cycling test, the larger the package size and the greater the difference in CTE between the layers, the greater the deformation after heating, resulting in greater stress on the chip packaging structure, especially at the corners where the stress is the greatest, which in turn leads to layer cracking or even layer breakage in the chip packaging structure, thereby affecting the performance of the chip. Summary of the Invention

[0003] In order to solve the above technical problems, the present application provides a chip packaging structure and its manufacturing method, and an electronic device, which can reduce the stress at the corners of the chip packaging structure and reduce the risk of cracks or even breakage in the packaging layer.

[0004] The first aspect of the present application provides a chip packaging structure, comprising: a substrate, a chip and a packaging layer. The chip may be an unpackaged chip, that is, a bare chip. The chip may be provided on a substrate. The packaging layer is provided on the substrate and surrounds the chip, and at least one first chamfered structure is formed on the packaging layer, and the first chamfered structure is provided between two adjacent side walls on the packaging layer. In this way, at least one sharp corner on the packaging layer can be removed, thereby reducing the stress at the corner caused by the sharp corner, thereby reducing the risk of cracks or even breakage in the packaging layer. In addition, providing at least one first chamfered structure on the packaging layer can also reduce the occupied area of ​​the packaging layer, thereby improving the utilization rate of the wafer surface and reducing costs.

[0005] To further reduce stress concentration, a first chamfered structure is formed between each pair of adjacent sidewalls on the encapsulation layer. Typically, the encapsulation layer includes four sidewalls connected end to end. In this application, a first chamfered structure is formed between each pair of adjacent sidewalls. In other words, four first chamfered structures can be formed on the encapsulation layer. This removes each sharp corner on the encapsulation layer, thereby reducing stress at the connection between each pair of adjacent sidewalls and further reducing the risk of cracks or even breakage in the encapsulation layer.

[0006] Based on this, the chip packaging structure includes a connection layer, which is located between the packaging layer and the substrate. In other words, the connection layer and the packaging layer are stacked. The packaging layer surrounds the chip, and therefore, the connection layer is also located between the chip and the substrate, and the connection layer serves to connect the chip to the substrate. The packaging layer has a circular arc surface, which is located between two adjacent side walls.

[0007] Similarly, the second chamfered structure is an oblique angle structure or a rounded angle structure. The oblique angle structure may mean that the connecting layer includes a side plane, the side plane is located between two adjacent side walls, and the angles between the side plane and the two adjacent side walls are both obtuse angles. The rounded angle structure may mean that the connecting layer includes an arc surface, and the arc surface is located between two adjacent side walls.

[0008] Regarding the structure of the connection layer, in one possible embodiment, the connection layer includes a wiring layer and an interposer, and the wiring layer is located between the interposer and the substrate, that is, the wiring layer, the interposer, and the packaging layer are stacked in sequence. A second chamfered structure is provided on both the wiring layer and the interposer. Both the wiring layer and the interposer include a dielectric portion and a conductive portion, the conductive portion is located within the dielectric portion, and the top and bottom surfaces are exposed to the dielectric portion. In this way, the chip can be electrically connected to the pads on the substrate through the conductive portion of the wiring layer and the conductive portion of the interposer. Since a first chamfered structure is formed on the packaging layer and a second chamfered structure is formed on the wiring layer and the interposer, chamfered structures are formed on the packaging layer, the interposer, and the wiring layer, thereby reducing the stress of the three-layer structure, thereby reducing the phenomenon of delamination due to excessive stress.

[0009] In another possible embodiment, the connection layer includes one of a wiring layer and an interposer. Exemplarily, the connection layer includes a wiring layer, and a second chamfer structure is provided on the wiring layer. Since a first chamfer structure is formed on the encapsulation layer and a second chamfer structure is formed on the wiring layer, chamfer structures are formed on both the encapsulation layer and the wiring layer, thereby reducing the stress of the encapsulation layer and the wiring layer, thereby reducing the phenomenon of delamination due to excessive stress. Alternatively, the connection layer includes an interposer, and a second chamfer structure is provided on the interposer. Similarly, the stress of the encapsulation layer and the interposer can also be reduced, thereby reducing the phenomenon of delamination due to excessive stress.

[0010] In addition, in other possible ways, the connecting layer may include a conductive layer, a wiring layer and an intermediate layer, wherein the wiring layer is located between the intermediate layer and the substrate, and the conductive layer is located between the packaging layer and the intermediate layer, that is, the wiring layer, the intermediate layer, the conductive layer and the packaging layer are stacked in sequence.

[0011] In some embodiments, the chip packaging structure further includes an adhesive layer, the adhesive layer being disposed on the substrate. The adhesive layer includes an adhesive layer body and a protrusion disposed on the adhesive layer body. The adhesive layer body surrounds the packaging layer, and the protrusion contacts the first chamfered structure. Because the present application can remove sharp corners on the packaging layer, and the adhesive layer body surrounds the packaging layer and the protrusion contacts the first chamfered structure, the shape of the surface of the adhesive layer surrounding the packaging layer matches the shape of the packaging layer, and the sharp corners on the adhesive layer can also be removed. This can reduce the phenomenon of excessive stress on the adhesive layer caused by the sharp corners, thereby reducing the stress on the adhesive layer, and further reducing the phenomenon of cracks in the adhesive layer caused by excessive stress.

[0012] Furthermore, the adhesive layer body surrounds the connection layer, and the protrusion contacts the second chamfered structure. Since the present application can remove sharp corners on the connection layer, and the adhesive layer body surrounds the connection layer and the protrusion contacts the first chamfered structure, the shape of the surface of the adhesive layer surrounding the connection layer matches the shape of the connection layer, and the sharp corners on the adhesive layer can also be removed, thereby reducing the phenomenon of excessive stress on the adhesive layer caused by the sharp corners, thereby reducing the stress on the adhesive layer, and further reducing the phenomenon of cracks in the adhesive layer caused by excessive stress.

[0013] In a second aspect of the present application, an electronic device is provided, comprising a housing and a chip packaging structure according to any one of the above embodiments, wherein the chip packaging structure is fixed in the housing. The electronic device can achieve all the effects of the chip packaging structure.

[0014] A third aspect of the present application provides a method for manufacturing a chip packaging structure, comprising: securing a chip to a substrate; encapsulating the chip to form an initial packaging layer, the initial packaging layer being able to surround the chip; removing the substrate; forming a first chamfered structure on the initial packaging layer to form a packaging layer; and securing the chip and packaging layer to the substrate. This removes sharp corners from the packaging layer, thereby reducing stress at the corners caused by the sharp corners and, in turn, lowering the risk of cracks or even breakage in the packaging layer. Furthermore, providing the first chamfered structure on the packaging layer can also reduce the footprint of the packaging layer, thereby improving wafer surface utilization and reducing costs.

[0015] In some embodiments, before the step of fixing the chip on the substrate, the manufacturing method further includes: forming an initial connection layer on the substrate; and the step of fixing the chip on the substrate includes: fixing the chip on the initial connection layer. Afterwards, the chip can be packaged to form an initial packaging layer, and the initial packaging layer surrounds the chip, so that the initial connection layer and the initial packaging layer are stacked. The top surface shape of the initial connection layer is rectangular, that is, the initial connection layer includes four side walls connected end to end in sequence. When making the second chamfered structure, the sharp corners at the connection between two adjacent side walls on the initial connection layer can be cut off with a laser or a tool to form a connection layer. In this way, the sharp corners on the packaging layer and the connection layer can be removed, thereby reducing the stress at the corners caused by the sharp corners, and further reducing the risk of cracks or even fractures in the packaging layer and the connection layer. Moreover, after the stress on the packaging layer and the connection layer is reduced, the phenomenon of delamination of the packaging layer and the connection layer can be reduced.

[0016] It can be seen that it is necessary to make a second chamfered structure on the initial connection layer, and it is also necessary to make a first chamfered structure on the initial packaging layer. Therefore, in a possible embodiment, the first chamfered structure and the second chamfered structure are made in the same process. For example, an initial connection layer is made on a substrate, the chip is fixed on the initial connection layer, and the chip is packaged to form an initial packaging layer. Then, the substrate is removed, and a laser or a tool is used to cut from the top surface of the initial packaging layer to the bottom surface of the initial connection layer, thereby cutting off the sharp corners at the connection between the adjacent side walls on the initial packaging layer and the initial connection layer, forming a packaging layer with a first chamfered structure and a connection layer with a second chamfered structure, thereby simplifying the manufacturing process of the chip packaging structure and reducing the manufacturing cost.

[0017] In another possible embodiment, the first chamfered structure and the second chamfered structure are produced in different processes. For example, an initial connection layer is produced on a substrate, the substrate is removed, and the second chamfered structure is cut into the initial connection layer using a laser or a tool. The chip is secured to the initial connection layer, the chip is packaged to form an initial packaging layer, and the first chamfered structure is cut into the initial packaging layer using a laser or a tool.

[0018] In some embodiments, the initial connection layer includes a wiring layer, the wiring layer including a dielectric portion and a conductive portion disposed within the dielectric portion, wherein a gap exists between the conductive portion and two adjacent sidewalls. It is understood that, before forming the second chamfered structure on the wiring layer of the initial connection layer, the top surface of the wiring layer of the initial connection layer is rectangular, i.e., the wiring layer of the initial connection layer includes four sidewalls connected end to end. When forming the second chamfered structure, a laser or a cutter can be used to cut away the sharp corners at the connection between two adjacent sidewalls on the wiring layer. The conductive portion is typically made of metal, which has a high hardness and is difficult to cut. Therefore, when there is a gap between the conductive portion and the two adjacent sidewalls, the gap region between the conductive portion and the connection can be a metal clearance region, i.e., an area without metal, or an area where only the dielectric portion is disposed. Cutting can be performed within this region to remove the sharp corners and form the second chamfered structure, thereby reducing the difficulty of processing.

[0019] In some embodiments, after the step of fixing the chip and the packaging layer to the substrate, the manufacturing method further includes: forming an adhesive layer on the substrate, the adhesive layer including an adhesive layer body and a protrusion provided on the adhesive layer body, the adhesive layer body surrounding the packaging layer, and the protrusion contacting the first chamfer structure. Because the present application can remove sharp corners on the packaging layer, and the adhesive layer body surrounding the packaging layer and the protrusion contacting the first chamfer structure, the shape of the surface of the adhesive layer surrounding the packaging layer matches the shape of the packaging layer, and can also remove sharp corners on the adhesive layer, thereby reducing the phenomenon of excessive stress on the adhesive layer caused by sharp corners, thereby reducing the stress on the adhesive layer, and further reducing the phenomenon of cracks in the adhesive layer caused by excessive stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] FIG1 is a schematic structural diagram of a chip packaging structure according to a first embodiment of the present application;

[0022] FIG2 is a cross-sectional view at AA in FIG1 ;

[0023] FIG3 is another cross-sectional view at AA in FIG1 ;

[0024] FIG4 is a schematic structural diagram of a chip packaging structure in a second embodiment of the present application;

[0025] FIG5 is a schematic structural diagram of a chip packaging structure in a third embodiment of the present application;

[0026] FIG6 is a schematic structural diagram of a chip packaging structure in a fourth embodiment of the present application;

[0027] FIG7 is a cross-sectional view taken along line BB in FIG6 ;

[0028] FIG8 is another cross-sectional view taken along line BB in FIG6 ;

[0029] FIG9 is a schematic diagram of the manufacturing process of the chip packaging structure shown in FIG1 ;

[0030] FIG10 a is a planar structural diagram after an initial connection layer is formed on a substrate;

[0031] FIG10 b is a planar structural diagram after a second chamfered structure is formed on the initial connection layer shown in FIG10 a ;

[0032] FIG11a is a schematic diagram of the planar structure of the chip after packaging;

[0033] FIG. 11 b is a planar structural diagram after a first chamfered structure is formed on the initial encapsulation layer shown in FIG. 11 a .

[0034] Icons: 1-chip packaging structure; 10-substrate; 20-chip; 30-packaging layer; 31-first chamfered structure; 311-side plane; 312-side wall; 313-arc surface; 40-connection layer; 41-second chamfered structure; 42-intermediary layer; 421, 431-dielectric part; 422, 432-conductive part; 43-wiring layer; 50-adhesive layer; 51-adhesive layer body; 52-protrusion; 61-heat dissipation bottom plate; 62-heat dissipation top plate; 63-rectifier; 64-connector; 71-substrate; 72-initial connection layer; 73-initial wiring layer; 74-initial packaging layer. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one (item)" refers to one or more, and "plurality" refers to two or more. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0037] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0038] "Connected", "connected" and similar words are used to express the intercommunication or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. "Up", "down", "left", "right" and the like are only used with respect to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for description and clarification relative to the description, which may change accordingly according to the change in the orientation of the components in the drawings.

[0039] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0040] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0041] With the continuous development of artificial intelligence and big data, the size of the chip packaging structure 1 is required to be larger and larger. Wafer-level chip packaging can meet the requirements of large-size packaging. The chip packaging structure 1 can usually include a multi-layer structure, and the CTE between the layers is quite different. During the temperature cycle test, the greater the difference in CTE between the layers and the larger the package size, the greater the deformation after heating, resulting in greater stress on the chip packaging structure 1, which in turn causes the chip packaging structure 1 to crack, break or delaminate, thereby affecting the performance of the chip.

[0042] Therefore, in the related art, materials with smaller CTE value differences are usually selected for each layer structure in the chip packaging structure 1 to balance the stress problem caused by CTE imbalance. However, different layer structures in the chip packaging structure 1 may have different functions. After meeting the CTE requirements, they cannot meet their corresponding functions and bring other process problems, such as poor processability, unsatisfactory performance and other process problems.

[0043] Based on this, an embodiment of the present application provides a chip packaging structure 1, which can reduce the stress of each layer structure. In this embodiment, the chip packaging structure 1 can be applied to electronic devices such as computers or mobile phones, and the chip packaging structure 1 can be the structure shown in Figure 1. In this application scenario, in addition to the chip packaging structure 1, the electronic device can also include a shell and a circuit board. The circuit board is fixed in the shell, and the chip packaging structure 1 is fixed on the circuit board and electrically connected to the circuit board. In addition to fixing the chip packaging structure 1 on the circuit board, other electronic devices such as resistors, capacitors, etc. can also be fixed.

[0044] As shown in FIG1 , a chip package structure 1 may include: a substrate 10, a chip 20, and a packaging layer 30. The chip 20 may be an unpackaged chip, i.e., a bare chip; or it may be a packaged functional module. Exemplarily, the chip 20 may be a system on chip (SOC), a test or dummy chip, a central processing unit (CPU), a graphics processing unit (GPU), a memory, an input / output (I / O) chip, an integrated passive device (IPD), etc. It may also be an integrated packaged functional module, such as a high bandwidth memory (HBM), a die on silicon interposer (DOI), a fan-out RDL interpose (FOI), etc. In practical applications, multiple chips 20 may be provided as needed. The multiple chips 20 may include at least one of the chips listed above. Exemplarily, some of the multiple chips 20 may be SOC chips, some may be IO chips, and the remaining chips may be dummy chips. For example, as shown in FIG2 , the three chips 20 located in the center may be SOC chips, and the six chips 20 located at the edge may be IO chips.

[0045] As shown in FIG1 , the chip 20 can be disposed on a substrate 10. An encapsulation layer 30 is disposed on the substrate 10 and surrounds the chip 20. The encapsulation layer 30 is formed with at least one first chamfered structure 31, which is disposed between two adjacent sidewalls of the encapsulation layer 30. This removes at least one sharp corner from the encapsulation layer 30, thereby reducing stress at the corner caused by the sharp corner and, in turn, lowering the risk of cracks or even breakage in the encapsulation layer 30. Furthermore, providing at least one first chamfered structure 31 on the encapsulation layer 30 can also reduce the area occupied by the encapsulation layer 30, thereby improving the utilization of the wafer surface and reducing costs.

[0046] To further reduce stress concentration, as shown in Figures 2 and 3, a first chamfered structure 31 is formed between each pair of adjacent sidewalls 312 on the encapsulation layer 30. Typically, the encapsulation layer 30 includes four sidewalls 312, two of which are opposite each other and enclose a rectangular structure. In this embodiment, a first chamfered structure 31 is formed between each pair of adjacent sidewalls 312. In other words, four first chamfered structures 31 can be formed on the encapsulation layer 30. This removes each sharp corner on the encapsulation layer 30, thereby reducing stress at the connection between each pair of adjacent sidewalls 312, further reducing the risk of cracks or even breakage in the encapsulation layer 30.

[0047] Based on this, as shown in Figure 1, the chip packaging structure 1 may further include a connection layer 40, which is located between the packaging layer 30 and the substrate 10, that is, the connection layer 40 and the packaging layer 30 are stacked. Since the packaging layer 30 surrounds the chip 20, the connection layer 40 is also located between the chip 20 and the substrate 10. The connection layer 40 can connect the chip 20 to the substrate 10 and can also realize signal interconnection between the chips 20 and 20 and between the chips 20 and the substrate 10. At least one second chamfer structure 41 is formed on the connection layer 40, and the second chamfer structure 41 is provided between two adjacent side walls on the connection layer 40. In this way, at least one sharp corner on the connection layer 40 can be removed, thereby reducing the stress at the corner caused by the sharp corner, and further reducing the risk of cracks or even fractures in the connection layer 40. Moreover, after the stress on the packaging layer 30 and the connection layer 40 is reduced, the phenomenon of delamination of the packaging layer 30 and the connection layer 40 can be reduced.

[0048] To further reduce stress concentration, a second chamfered structure 41 is formed between each pair of adjacent sidewalls on the connecting layer 40. Typically, the connecting layer 40 includes four sidewalls, two of which face each other and together form a rectangular structure. In this embodiment, a second chamfered structure 41 is formed between each pair of adjacent sidewalls, as shown in Figures 2 and 3. In other words, four second chamfered structures 41 can be formed on the connecting layer 40. This removes each sharp corner on the connecting layer 40, thereby reducing stress at the connection between each pair of adjacent sidewalls and further reducing the risk of cracks or even breakage in the connecting layer 40.

[0049] Regarding the structure of the connection layer 40, in one possible embodiment, as shown in FIG1 , the connection layer 40 includes a wiring layer 43 and an interposer 42 arranged in a stacked manner. The wiring layer 43 is located between the interposer 42 and the substrate 10. That is, the wiring layer 43, the interposer 42, and the packaging layer 30 are stacked in sequence. The wiring layer 43 and the interposer 42 are both provided with a second chamfered structure 41 as shown in FIG2 . The interposer 42 includes a dielectric portion 421 and a conductive portion 422. The conductive portion 422 is located within the dielectric portion 421, with both the top and bottom surfaces exposed to the dielectric portion 421. The wiring layer 43 includes a dielectric portion 431 and a conductive portion 432. The conductive portion 432 is located within the dielectric portion 431, with both the top and bottom surfaces exposed to the dielectric portion 431. In this way, the chip 20 can be electrically connected to the pads (not shown in FIG1 ) on the substrate 10 through the conductive portion 432 of the wiring layer 43 and the conductive portion 422 of the interposer 42. Since the first chamfered structure 31 shown in Figure 2 is formed on the packaging layer 30, and the second chamfered structure 41 shown in Figure 2 is formed on the wiring layer 43 and the intermediary layer 42, chamfered structures are formed on the packaging layer 30, the intermediary layer 42 and the wiring layer 43, thereby reducing the stress of the three-layer structure and reducing the phenomenon of delamination due to excessive stress.

[0050] In another possible embodiment, the connection layer 40 includes one of a wiring layer 43 and an interposer 42. In one example, as shown in FIG4 , the connection layer 40 includes a wiring layer 43, and the wiring layer 43 is provided with a second chamfered structure 41 as shown in FIG2 . Moreover, in this embodiment, the connection layer 40 includes a single wiring layer 43. In other embodiments, the connection layer 40 may include multiple stacked wiring layers 43. Since the first chamfered structure 31 as shown in FIG2 is formed on the packaging layer 30, and the second chamfered structure 41 as shown in FIG2 is formed on the wiring layer 43, the packaging layer 30 and the wiring layer 43 are both formed with chamfered structures, thereby reducing the stress of the packaging layer 30 and the wiring layer 43, thereby reducing the phenomenon of delamination due to excessive stress.

[0051] In another example, as shown in FIG5 , the connection layer 40 includes an interposer 42 , on which the second chamfered structure 41 shown in FIG2 is provided. Furthermore, in this embodiment, the connection layer 40 includes a single interposer 42. In other embodiments, the connection layer 40 may include multiple interposers 42 stacked together. Similarly, this can reduce stress in the packaging layer 30 and the interposer 42 , thereby reducing delamination caused by excessive stress.

[0052] Furthermore, each sidewall on the connection layer 40 is flush with each sidewall on the encapsulation layer 30, and the projection of the second chamfered structure 41 on the substrate 10 coincides with the projection of the first chamfered structure 31 on the substrate 10. The number of second chamfered structures 41 may be the same as the number of first chamfered structures 31. For example, when there is one second chamfered structure 41, there is also one first chamfered structure 31, and the projection of the second chamfered structure 41 on the substrate 10 coincides with the projection of the first chamfered structure 31 on the substrate 10, that is, the second chamfered structure 41 corresponds to the first chamfered structure 31 in position. When there are multiple second chamfered structures 41, there are also multiple first chamfered structures 31, and the projection of each second chamfered structure 41 on the substrate 10 coincides with the projection of each first chamfered structure 31 on the substrate 10, that is, each second chamfered structure 41 corresponds to the position of each first chamfered structure 31. In this way, the first chamfered structure 31 and the second chamfered structure 41 can be manufactured in the same process, thereby simplifying the manufacturing process of the chip package structure 1 and reducing the manufacturing cost. Of course, in other embodiments, the first chamfered structure 31 and the second chamfered structure 41 can also be manufactured in different processes.

[0053] Regarding the shape of the first chamfered structure 31, in one possible embodiment, as shown in FIG2 , the first chamfered structure 31 on the encapsulation layer 30 is an oblique angle structure. The oblique angle structure may mean that the encapsulation layer 30 has a side plane 311, which is located between two adjacent side walls 312 and has an obtuse angle with the two adjacent side walls 312.

[0054] In another possible embodiment, as shown in FIG3 , the first chamfered structure 31 on the encapsulation layer 30 is a rounded structure. The rounded structure may mean that the encapsulation layer 30 has an arc surface 313 , and the arc surface 313 is located between two adjacent sidewalls 312 .

[0055] Regarding the shape of the second chamfered structure 41, in one possible embodiment, as shown in Figure 2, the second chamfered structure 41 is an oblique angle structure. In another possible embodiment, as shown in Figure 3, the second chamfered structure 41 is a rounded angle structure.

[0056] It can be understood that in this embodiment, the structures of the first chamfer structure 31 and the second chamfer structure 41 are the same, and illustratively, both are bevel structures, or both are rounded structures. In other embodiments, the structures of the first chamfer structure 31 and the second chamfer structure 41 may be different. illustratively, the first chamfer structure 31 may be a bevel structure, and the second chamfer structure 41 may be a rounded structure; or, the second chamfer structure 41 may be a bevel structure, and the first chamfer structure 31 may be a rounded structure.

[0057] As shown in FIG1 , the chip package structure 1 may further include an adhesive layer 50, which is disposed on the substrate 10. As shown in FIG2 , the adhesive layer 50 includes an adhesive layer body 51 and a protrusion 52 disposed on the adhesive layer body 51. The adhesive layer body 51 surrounds the encapsulation layer 30, and the protrusion 52 is located on the side of the adhesive layer body 51 facing the encapsulation layer 30 and in contact with the first chamfer structure 31. Because this embodiment can remove sharp corners on the encapsulation layer 30, and the adhesive layer body 51 surrounds the encapsulation layer 30 and the protrusion 52 contacts the first chamfer structure 31, the shape of the surface of the adhesive layer 50 surrounding the encapsulation layer 30 matches the shape of the encapsulation layer 30, and can also remove sharp corners on the adhesive layer 50. This can reduce the phenomenon of excessive stress on the adhesive layer 50 caused by the sharp corners, thereby reducing the stress on the adhesive layer 50 and further reducing the phenomenon of cracks in the adhesive layer 50 caused by excessive stress.

[0058] Furthermore, the adhesive layer body 51 also surrounds the connection layer 40, and the protrusion 52 contacts the second chamfer structure 41. Because this embodiment can eliminate sharp corners on the connection layer 40, and the adhesive layer body 51 surrounds the connection layer 40 and the protrusion 52 contacts the second chamfer structure 41, the shape of the surface of the adhesive layer 50 surrounding the connection layer 40 matches the shape of the connection layer 40, and the sharp corners on the adhesive layer 50 can also be eliminated. This can reduce the phenomenon of excessive stress on the adhesive layer 50 caused by the sharp corners, thereby reducing the stress on the adhesive layer 50 and further reducing the phenomenon of cracks in the adhesive layer 50 caused by excessive stress.

[0059] In other embodiments of the present application, as shown in Figure 6, the difference between the embodiment shown in Figure 1 lies in the application scenario of this embodiment, the structure of the substrate 10, and the removal of the adhesive layer 50 on the basis of the embodiment shown in Figure 1, and the addition of a heat dissipation top plate 62, a heat dissipation bottom plate 61, a rectifier 63 and a connector 64.

[0060] The chip packaging structure 1 of this embodiment can be applied to electronic devices such as servers. Electronic devices can also be consumer electronic products, home electronic products, vehicle-mounted electronic products, financial terminal products, communication electronic products, etc., and the embodiments of this application do not limit this. For example, the above-mentioned consumer electronic products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (for example, smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products can be smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Vehicle-mounted electronic products can be car navigation systems, car displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service transactions, etc. Communication electronic products can be servers, storage devices, radars, base stations, and other communication equipment.

[0061] In addition to the chip package structure 1, the server may also include a housing. The chip package structure 1 can serve as an independent computing unit and is fixed within the server housing. The computing unit can receive data, perform calculations on the data, obtain processing results, and output them.

[0062] 6 , the chip package structure 1 includes a plurality of substrates 10 , which are arranged in the same layer and spaced apart from each other. A connection layer 40 is provided on the plurality of substrates 10 .

[0063] As shown in FIG6 , multiple connectors 64 are provided, spaced apart and arranged on the same layer. Connectors 64 are located on the side of substrate 10 facing away from connection layer 40 , and are connected to two substrates 10 located at the edge of the substrates 10 . Connectors 64 can be used to connect wires for signal input and output within chip package structure 1 .

[0064] As shown in FIG6 , there are multiple rectifiers 63 , which are spaced apart and arranged on the same layer, and are spaced apart and arranged on the same layer as the connector 64 . The multiple rectifiers 63 are located on a side of the substrate 10 facing away from the connection layer 40 , and the multiple rectifiers 63 are respectively connected to two substrates 10 located in the middle of the multiple substrates 10 .

[0065] As shown in FIG6 , the heat dissipation top plate 62 is located on the side of the packaging layer 30 away from the connection layer 40 , and the heat dissipation bottom plate 61 is located on the side of the rectifier 63 away from the substrate 10 , so as to dissipate heat from the chip 20 from two directions respectively.

[0066] As shown in Figure 7, the first chamfered structure 31 on the encapsulation layer 30 and the second chamfered structure 41 on the connection layer 40 can both be beveled structures. Alternatively, as shown in Figure 8, the first chamfered structure 31 on the encapsulation layer 30 and the second chamfered structure 41 on the connection layer 40 can both be rounded structures.

[0067] In other embodiments of the present application, a method for manufacturing a chip package structure 1 is further provided. The method is used to manufacture the chip package structure 1 shown in FIG. 1 . As shown in FIG. 9 , the method may include:

[0068] S91, forming an initial connection layer on the substrate.

[0069] As shown in FIG10 a , the projection of the initial connection layer 72 on the substrate 71 may be rectangular, that is, the initial connection layer 72 may include four sidewalls 312 connected end to end. In this embodiment, the initial connection layer 72 may include an initial interposer and an initial wiring layer 73. In other embodiments, the initial connection layer 72 may include either an initial interposer or an initial wiring layer 73.

[0070] S92, fixing the chip on the initial connection layer.

[0071] The chip 20 may be packaged in a flip-chip manner to fix the chip 20 on the initial connection layer 72 .

[0072] S93, encapsulating the chip to form an initial encapsulation layer.

[0073] The chip 20 may be packaged to form an initial packaging layer 74 as shown in FIG. 11 a . The initial packaging layer 74 surrounds the chip 20 . Therefore, the initial connection layer 72 and the initial packaging layer 74 are stacked.

[0074] S94, removing the substrate.

[0075] The substrate 71 can be removed from the chip package structure by debonding (DB).

[0076] S95 , forming a second chamfered structure on the initial connection layer and a first chamfered structure on the initial encapsulation layer to form an encapsulation layer and a connection layer.

[0077] In this embodiment, the first chamfered structure 31 and the second chamfered structure 41 can be manufactured in the same process. For example, a laser or a cutting tool can be used to cut from the top surface of the initial packaging layer 74 to the bottom surface of the initial connection layer 722, thereby removing the sharp corners at the connection between the adjacent sidewalls 312 on the initial packaging layer 74 and the initial connection layer 72, forming the packaging layer 30 having the first chamfered structure 31 as shown in FIG11b and the connection layer 40 having the second chamfered structure 41 as shown in FIG10b. This simplifies the manufacturing process of the chip packaging structure 1 and reduces manufacturing costs. Moreover, since the sharp corners on the packaging layer 30 and the connection layer 40 are removed, the stress at the corners caused by the sharp corners is reduced, thereby reducing the risk of cracks or even fractures in the packaging layer 30 and the connection layer 40. Moreover, after the stress on both the packaging layer 30 and the connection layer 40 is reduced, the phenomenon of delamination of the packaging layer 30 and the connection layer 40 can be reduced.

[0078] As shown in FIG10 a , the initial connection layer 72 includes an initial wiring layer 73, which includes a dielectric portion 431 and a conductive portion 432 disposed within the dielectric portion 431. A gap exists between the conductive portion 432 and two adjacent sidewalls 312. When forming the second chamfered structure 41, a laser or a cutter can be used to cut away the sharp corner at the connection between two adjacent sidewalls 312 on the initial wiring layer 73. The conductive portion 432 is typically made of metal, which has high hardness and is difficult to cut. Therefore, when there is a gap between the conductive portion 432 and two adjacent sidewalls 312, the gap between the conductive portion 432 and the connection can be a metal clearance area, that is, an area without metal, or in other words, an area where only the dielectric portion 431 is disposed. Cutting can be performed in this area to remove the sharp corner and form the second chamfered structure 41, thereby reducing the difficulty of processing.

[0079] It is understood that in other embodiments, the first chamfered structure 31 in FIG. 11b and the second chamfered structure 41 in FIG. 10b are fabricated in different processes. For example, after performing step S91 to fabricate the initial connection layer 72 on the substrate 71, the second chamfered structure 41 can be fabricated on the initial connection layer 72. Furthermore, after performing step S93 to package the chip 20 and form the initial packaging layer 74, the first chamfered structure 31 can be fabricated on the initial packaging layer 74.

[0080] S96, fixing the chip, the packaging layer and the connection layer on the substrate.

[0081] In this way, forming the first chamfered structure 31 on the packaging layer 30 and the second chamfered structure 41 on the connection layer 40 can also reduce the area occupied by the packaging layer 30 on the substrate 10, thereby improving the utilization rate of the wafer surface and reducing costs.

[0082] S97, forming an adhesive layer on the substrate.

[0083] During the process of forming the adhesive layer 50 on the substrate 10 , the adhesive layer 50 may spread to contact the first chamfered structure 31 and the second chamfered structure 41 .

[0084] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip packaging structure, characterized in that: include: substrate; a chip, wherein the chip is disposed on the substrate; The packaging layer is provided on the substrate and surrounds the chip. At least one first chamfered structure is formed on the packaging layer. The first chamfered structure is provided between two adjacent side walls on the packaging layer.

2. The chip packaging structure according to claim 1, wherein: The first chamfered structure is formed between every two adjacent side walls of the packaging layer.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The chip packaging structure includes a connection layer, the connection layer is located between the packaging layer and the substrate, at least one second chamfered structure is formed on the connection layer, and the second chamfered structure is arranged between two adjacent side walls on the connection layer.

4. The chip packaging structure according to claim 3, wherein: The second chamfered structure is formed between every two adjacent side walls of the connection layer.

5. The chip packaging structure according to claim 3 or 4, characterized in that: A projection of the second chamfered structure on the chip coincides with a projection of the first chamfered structure on the chip.

6. The chip packaging structure according to any one of claims 3 to 5, characterized in that: The first chamfered structure is a beveled structure or a rounded structure, and / or the second chamfered structure is a beveled structure or a rounded structure.

7. The chip packaging structure according to any one of claims 3 to 6, wherein: The connection layer includes a wiring layer, and the wiring layer is provided with the second chamfer structure; And / or the connecting layer includes an intermediate layer, and the second chamfer structure is provided on the intermediate layer.

8. The chip packaging structure according to claim 3, 4 or 7, characterized in that: The chip packaging structure further includes an adhesive layer, which is disposed on the substrate. The adhesive layer includes an adhesive layer body and a protrusion disposed on the adhesive layer body. The adhesive layer body surrounds the packaging layer, and the protrusion contacts the first chamfered structure.

9. The chip packaging structure according to claim 8, wherein: The adhesive layer body surrounds the connection layer, and the protrusion contacts the second chamfered structure.

10. An electronic device, characterized in that: It comprises a shell and the chip packaging structure according to any one of claims 1 to 9, wherein the chip packaging structure is fixed in the shell.

11. A method for manufacturing a chip packaging structure, characterized in that: include: fixing the chip on the substrate; Encapsulating the chip to form an initial encapsulation layer; removing the substrate; Making a first chamfered structure on the initial encapsulation layer to form an encapsulation layer; Fix the chip and packaging layer on the substrate.

12. The manufacturing method according to claim 11, characterized in that: Before the step of fixing the chip on the substrate, the manufacturing method further includes: forming an initial connection layer on the substrate; The production method further comprises: A second chamfered structure is fabricated on the initial connection layer to form a connection layer.

13. The manufacturing method according to claim 12, characterized in that: The first chamfered structure and the second chamfered structure are manufactured in the same process.

14. The production method according to claim 12 or 13, characterized in that: The initial connection layer includes a wiring layer, and the wiring layer includes a dielectric portion and a conductive portion disposed in the dielectric portion. A distance exists between the conductive portion and two adjacent side walls.

15. The production method according to any one of claims 11 to 14, characterized in that: After the step of fixing the chip and the packaging layer on the substrate, the manufacturing method further includes: An adhesive layer is manufactured on the substrate. The adhesive layer includes an adhesive layer body and a protrusion provided on the adhesive layer body. The adhesive layer body surrounds the packaging layer, and the protrusion contacts the first chamfered structure.

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