Service processing apparatus, method, and device

Abstract

Embodiments of the present application relate to the technical field of electronics, and provide a service processing apparatus, method, and device, for use in improving the operation efficiency of periodic services. The apparatus comprises: at least one processing core, used for operating a first periodic service among periodic services and acquiring historical operation information corresponding to one or more sub services in the first periodic service, the periodic service having a plurality of periods, and the first periodic service being within a first period among the plurality of periods; and a memory, used for storing the historical operation information. The at least one processing core is further used for operating a second periodic service among the periodic services on the basis of the historical operation information, wherein the second periodic service is within a second period among the plurality of periods; for example, the second period is adjacent to the first period.

Description

Business processing device, method and equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 4, 2024, with application number 202410244996.4 and application name “A business processing device, method and equipment”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a business processing device, method, and equipment. Background Art

[0003] To improve instruction per clock (IPC) and reduce memory access latency during business processing, processor systems typically use various speculative algorithms, such as branch prediction algorithms for instruction speculation and prefetch algorithms for address speculation. However, these algorithms are limited by currently available hardware information and cannot simultaneously meet accuracy and coverage requirements. Ineffective speculation also wastes processor system performance and power consumption. Consequently, these various speculative algorithms are ineffective. Summary of the Invention

[0004] The present application provides a service processing apparatus, method and device for improving the operating efficiency of periodic services.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a business processing device is provided, which includes: at least one processing core, used to run a first periodic business in a periodic business, and obtain historical operation information corresponding to one or more sub-businesses in the first periodic business (for example, calling a specific function, accessing a specific address, accessing specific data, or executing a specific branch, etc.), the periodic business has multiple cycles, for example, the periodic business can be a periodic image processing or image display business (for example, a frame drawing business involved in image display), a periodic transmission business or a scheduling business, etc., and the first periodic business is located in the first cycle of the multiple cycles; a memory, used to store the historical operation information; wherein the at least one processing core is also used to run a second periodic business in the periodic business according to the historical operation information, for example, using the historical operation information as pre-fetch information to run the second periodic business, and the second periodic business is located in the second cycle of the multiple cycles.

[0007] In the above technical solution, the at least one processing core can be used to run the first periodic business in the periodic business and obtain historical operation information corresponding to one or more sub-businesses, the memory can be used to store the historical operation information, and the at least one processing core can also be used to run the second periodic business in the periodic business based on the historical operation information, and the first periodic business and the second periodic business are respectively located in the first cycle and the second cycle of the multiple cycles. Since there is a large similarity between different cycles of the periodic business, the memory stores the historical operation information corresponding to one or more sub-businesses in the first periodic business, and the at least one processing core obtains the required operation information from the memory when running the second periodic business. This can reduce the cache miss rate of the at least one processing core when processing the second periodic business, improve the prediction accuracy and IPC (number of instructions / clock cycle), and thus improve the operation efficiency of the periodic business.

[0008] In one possible implementation of the first aspect, the second period is adjacent to the first period. For example, the first period service and the second period service are services of two adjacent frames in a frame drawing service. In this possible implementation, when the second period is adjacent to the first period, the similarity between the first period service and the second period service is higher. This can further improve the operational efficiency of the periodic service when the second period service is operated based on historical operation information corresponding to one or more sub-services in the first period service.

[0009] In a possible implementation of the first aspect, each of the multiple periods includes at least one of the following: a transmission time interval (TTI), a frame, or a time slice. In the above possible implementation, when each of the multiple periods is a TTI, a frame, or a time slice, the operating efficiency of the periodic services corresponding to the different periods can be improved.

[0010] In one possible implementation of the first aspect, the first periodic service and the second periodic service include the same one or more sub-services, such as the same function calls, address accesses, data accesses, or branches. In this possible implementation, when the first periodic service and the second periodic service include the same one or more sub-services, and the at least one processing core obtains historical operation information of the one or more sub-services, operating the second periodic service based on the historical operation information can further improve prediction accuracy, thereby further improving the operational efficiency of the periodic service.

[0011] In one possible implementation of the first aspect, the at least one processing core is further configured to determine one or more sub-services within the periodic service. For example, the at least one processing core may be configured to mark the one or more sub-services within the periodic service. In this possible implementation, by determining the one or more sub-services within the periodic service and using historical operating information of the one or more sub-services within the first periodic service as pre-fetch information for the second periodic service when the periodic service is running, the accuracy and coverage of speculation can be improved.

[0012] In one possible implementation of the first aspect, the historical operation information includes at least one of the following: branch history information, instruction traces, data traces, cache hot and cold information, page table history information, or quality of service (QoS) information. In these possible implementations, when the historical operation information includes the above different information, it can improve branch prediction accuracy and coverage, data prefetch accuracy and coverage, instruction prefetch accuracy and coverage, cache utilization, page table hit rate, etc. during the periodic service processing.

[0013] In a possible implementation of the first aspect, the memory includes at least one of the following: an on-chip dedicated memory, an on-chip shared buffer, or an off-chip memory. The above possible implementation can improve the diversity and selection flexibility of the memory.

[0014] According to a second aspect, a service processing device is provided. The device includes: a service execution unit configured to drive at least one processing core to execute a first periodic service among periodic services, and to obtain historical operation information corresponding to one or more sub-services within the first periodic service, wherein the periodic service has multiple periods, and the first periodic service is within a first period among the multiple periods; and a storage unit configured to store the historical operation information in a memory. The service execution unit is further configured to drive the at least one processing core to execute a second periodic service among the periodic services based on the historical operation information, wherein the second periodic service is within a second period among the multiple periods, and the second period is adjacent to the first period.

[0015] In a possible implementation manner of the second aspect, each of the multiple periods includes at least one of the following: a transmission time interval TTI, a frame, or a time slice.

[0016] In a possible implementation manner of the second aspect, the first periodic service and the second periodic service include the same one or more sub-services.

[0017] In a possible implementation manner of the second aspect, the apparatus further includes: a scheduling unit, configured to determine one or more sub-services in the periodic service.

[0018] In a possible implementation of the second aspect, the scheduling unit is further used to: generate configuration information, which is used to allocate storage space in the memory for the periodic service; and the storage unit is further used to: store the historical operation information in the storage space according to the configuration information.

[0019] In a possible implementation of the second aspect, the scheduling unit is also used to: when the second period business switches from the first processing core to the second processing core, send an indication message to the business execution unit, where the indication message is used to indicate the storage space; and the business execution unit is used to drive the second processing core to obtain the historical operation information from the storage space according to the indication message.

[0020] In a possible implementation manner of the second aspect, the scheduling unit is further configured to: release the storage space when the periodic service processing is completed.

[0021] In a possible implementation of the second aspect, the historical operation information includes at least one of the following: branch history information, instruction trace, data trace, cache hot and cold information, page table history information, or quality of service (QoS) information.

[0022] In a possible implementation manner of the second aspect, the memory includes at least one of the following: an on-chip dedicated memory, an on-chip shared buffer, or an off-chip memory.

[0023] According to a third aspect, a service processing method is provided, the method comprising: operating a first periodic service in a periodic service, and obtaining historical operation information corresponding to one or more sub-services in the first periodic service, wherein the periodic service has multiple periods, and the first periodic service is in a first period of the multiple periods; storing the historical operation information in a memory; and operating a second periodic service in the periodic service based on the historical operation information, wherein the second periodic service is in a second period of the multiple periods. Optionally, the second period is adjacent to the first period.

[0024] In a possible implementation manner of the third aspect, each of the multiple periods includes at least one of the following: a transmission time interval TTI, a frame, or a time slice.

[0025] In a possible implementation manner of the third aspect, the first periodic service and the second periodic service include the same one or more sub-services.

[0026] In a possible implementation manner of the third aspect, the method further includes: determining one or more sub-services in the periodic service.

[0027] In a possible implementation of the third aspect, the method further includes: generating configuration information, the configuration information being used to allocate storage space in the memory for the periodic service; and storing the historical operation information in the memory, including: storing the historical operation information in the storage space according to the configuration information.

[0028] In a possible implementation of the third aspect, the method further includes: when the second periodic service is switched from the first processing core to the second processing core, sending indication information to the second processing core, the indication information being used to indicate the storage space; the second processing core obtaining the historical operation information from the storage space according to the indication information; and then operating the second periodic service in the periodic service according to the historical operation information, including: the second processing core operating the second periodic service in the periodic service according to the historical operation information.

[0029] In a possible implementation manner of the third aspect, the method further includes: releasing the storage space when the periodic service processing is completed.

[0030] In a possible implementation of the third aspect, the at least one historical operation information includes at least one of the following: branch history information, instruction trace, data trace, cache hot and cold information, page table history information, or quality of service QoS information.

[0031] In a possible implementation manner of the third aspect, the memory includes at least one of the following: an on-chip dedicated memory, an on-chip shared buffer, or an off-chip memory.

[0032] In a fourth aspect, an electronic device is provided, which includes a processor and a memory, the memory being used to store computer instructions, and the processor being used to execute the computer instructions so that the electronic device implements the business processing method provided by the third aspect or any possible implementation of the third aspect.

[0033] In a fifth aspect, a readable storage medium is provided, which stores computer instructions. When the computer instructions are executed on a device, the device executes the business processing method provided in the third aspect or any possible implementation of the third aspect.

[0034] In a sixth aspect, a computer program product is provided, which includes computer instructions. When the computer instructions are executed on a device, the device executes the business processing method provided in the third aspect or any possible implementation of the third aspect.

[0035] It can be understood that the beneficial effects that can be achieved by the above-mentioned second to sixth aspects can correspond to the beneficial effects provided by the above-mentioned first aspect or any possible implementation method of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] FIG1 shows a schematic diagram of a processing behavior corresponding to each frame in drawing a plurality of frames;

[0037] FIG2 is a schematic diagram of the structure of a processor system provided in an embodiment of the present application;

[0038] FIG3 is a software structure diagram of an electronic device provided in an embodiment of the present application;

[0039] FIG4 is a schematic diagram of the structure of a service processing device provided in an embodiment of the present application;

[0040] FIG5 is a flow chart of a business processing method provided in an embodiment of the present application;

[0041] FIG6 is a schematic diagram of multiple periods of a periodic service provided in an embodiment of the present application;

[0042] FIG7 is a schematic diagram of obtaining and storing historical operation information provided by an embodiment of the present application;

[0043] FIG8 is a schematic diagram of a method for processing periodic services according to an embodiment of the present application;

[0044] FIG9 is a flow chart of another service processing method provided in an embodiment of the present application;

[0045] FIG10 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0046] FIG11 is a flowchart of software for business processing provided in an embodiment of the present application;

[0047] FIG12 is a schematic diagram of the structure of another service processing device provided in an embodiment of the present application;

[0048] FIG13 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will discuss in detail the making and use of various embodiments. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use the present application and technology and do not limit the scope of this application.

[0050] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0051] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0052] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

[0053] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0054] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0055] Before introducing the embodiments of the present application, the relevant technical background of the present application is first introduced.

[0056] During business processing, processor systems typically use various speculative algorithms to improve instruction per clock (IPC) and reduce memory access latency, such as branch prediction algorithms for instruction speculation and prefetch algorithms for address speculation. However, these speculative algorithms are often limited by currently available hardware information and cannot simultaneously meet accuracy and coverage requirements. Ineffective speculation also wastes processor system performance and power consumption. Furthermore, the same business can frequently migrate between different processing cores (or cores, also known as processor cores). In these cases, caches and history tables are virtually impossible to retain, resulting in significant switching costs and hindering processing performance and user experience.

[0057] Coverage and accuracy are two metrics used to evaluate the performance of processor systems using speculative algorithms. Coverage refers to the percentage of all data used by the processing core that is prefetched into the cache. A higher coverage is better. Accuracy refers to the percentage of prefetched data accessed by the processing core out of all prefetched data. A higher accuracy is better. If the accuracy is too low, useless prefetched data will pollute the cache and consume memory bandwidth.

[0058] Furthermore, current processor architectures often use benchmarks as design targets, leaving room for optimization in real-world scenarios. For example, the processor's cache size and branch target buffer (BTB) size are set based on the benchmark's sweet spot (or profit point). In reality, real-world business requirements often exceed the designed size. While blindly increasing size can improve performance, it comes at a significant cost in power performance and area (PPA). Therefore, processor optimization for real-world applications requires a new perspective, examining its characteristics and designing the processor architecture accordingly.

[0059] Currently, for services that contain rhythmic information (or periodic services with multiple periods), such as image-related tasks with a frame period, control services and scheduling services with a transmission time interval (TTI) or time slice period, there is a problem of low speculative efficiency under the above-mentioned technical background. In addition, due to the lack of transmission of this rhythmic information between software and hardware in traditional processors, it cannot be effectively utilized, resulting in low operating efficiency of such services.

[0060] For example, in the terminal user scenario, frame drawing is a type of business that accounts for a high proportion. For this type of business, all the visual information received by the user comes from the screen, and the screen display is based on the granularity of frames, so a large part of the tasks processed by the processor in the user terminal are performed for the goal of "displaying a frame of image", and other tasks include receiving user feedback operations, service classes, etc. In order to "display a frame of image", some tasks are directly related to the display, while other tasks indirectly support the display of each frame, which all fall within the scope of optimization of this application. For the processor in the user terminal, the running entities of this type of business are usually the rendering thread (render thread) and the display synthesis thread (surface flinger) in the processing core, and the processing behaviors corresponding to the rendering thread and the display synthesis thread in different frames are relatively similar, that is, this type of business shows strong inter-frame similarity. Figure 1 shows the processing behavior corresponding to each frame when multiple processing cores draw multiple frames of this type of business, as well as the processing cores involved in the drawing of each frame. In the figure, the multiple frames include frame 1, frame 2 and frame 3, the processing behavior corresponding to each frame includes a, b, c, d, e, f, g and h, and the multiple processing cores include core 0 to core 5. The rectangle on the straight line corresponding to each core in the figure is used to indicate that the rendering thread and display synthesis thread in the core are in running state.

[0061] Based on this, an embodiment of the present application provides a business processing device that can be used to process periodic business with multiple cycles, and the business processing device includes at least one processing core and a memory. In the business processing device, the at least one processing core can be used to run the first period business in the periodic business and obtain historical operation information corresponding to one or more sub-businesses in the first period business, the memory can be used to store the historical operation information, and the at least one processing core can also be used to run the second period business in the periodic business according to the historical operation information, and the first period business and the second period business are respectively located in the first cycle and the second cycle of the multiple cycles. In this way, the memory stores the historical operation information corresponding to one or more sub-businesses in the first period business, and the at least one processing core obtains the required operation information from the memory when running the second period business, which can reduce the cache miss rate of the at least one processing core when processing the second period business, improve the prediction accuracy and IPC (number of instructions / clock cycle), and thus improve the operation efficiency of the business.

[0062] The service processing device provided in the embodiment of the present application can be applied to a processor system, which can also be called a processor subsystem. For example, the processor subsystem can be a CPU subsystem. The structure of the processor system is described below with an example.

[0063] Figure 2 is a schematic diagram of the structure of a processor system provided by an embodiment of the present application. The processor system includes at least one processing core, each processing core may be provided with a corresponding private cache (for example, a first-level cache and a second-level cache), and the private caches of different processing cores may be coupled to a shared cache (for example, a third-level cache) through a bus, and different processing cores in the multiple processing cores may access the shared cache. Among them, the multiple processing cores can be used to deploy periodic services, and the services in different periods of the periodic services may have the same one or more sub-services, and the one or more sub-services may include calling one or more functions, accessing data and / or accessing instructions, etc. during operation.

[0064] In the processor system, the multiple processing cores may include multiple different processing cores of the same processor, or the multiple processing cores may include processing cores of multiple different processors, that is, the multiple processing cores may form one or more processors. The processors include, but are not limited to, CPUs, general-purpose processors, graphics processing units (GPUs), image signal processors (ISPs), digital signal processors (DSPs), network processing units (NPUs), artificial intelligence (AI) processors, and the like. Optionally, the structures of any two of the multiple processing cores and the sizes of their respective hardware resources (e.g., cache resources) may be the same or different, and this embodiment of the application does not impose any specific restrictions on this.

[0065] Furthermore, the processor system also includes at least one memory coupled to the multiple processing cores, and the at least one memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. Exemplarily, the RAM may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), and a double data rate synchronous dynamic random access memory (DDR SDRAM). In a possible embodiment, the at least one memory includes at least one of the following: a dedicated memory or an external memory. For example, the dedicated memory may be an on-chip dedicated memory, and the external memory may be an off-chip memory.

[0066] The processor system may be an electronic device, or a system on chip (SoC) or a chipset comprising multiple chips applied to an electronic device, or a module comprising the SoC or chipset. The electronic device may be used as a terminal device or a server. Optionally, the electronic device includes but is not limited to: mobile phones, tablet computers, laptops, desktop computers, PDAs, ultra-mobile personal computers (umPCs), mobile internet devices (MIDs), netbooks, camcorders, cameras, wearable devices (such as smart watches and smart bracelets, etc.), vehicle-mounted equipment (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed railways, etc.), virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electric meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flying equipment (such as intelligent robots, hot air balloons, drones, airplanes), etc.

[0067] The software system of the electronic device can adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a micro-service architecture or a cloud architecture. The embodiment of the present application takes the Android system with a layered architecture as an example to illustrate the software structure of the electronic device.

[0068] Figure 3 is a software architecture diagram of an electronic device provided in an embodiment of the present application. This layered architecture divides the software into several layers, each with clear roles and divisions of labor. Layers communicate with each other via software interfaces. In some embodiments, the Android system is divided into four layers: from top to bottom, the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer.

[0069] The application layer may include a series of application packages. In one possible example, the application package may include camera, gallery, calendar, call, map, navigation, wireless local area network (WLAN), Bluetooth, music, video, short message and other applications.

[0070] The application framework layer provides an application programming interface (API) and programming framework for applications in the application layer. The application framework layer includes some predefined functions. In one possible example, the application framework layer may include a window manager, a content provider, a view system, a telephony manager, a resource manager, a notification manager, and so on. The window manager manages window programs. For example, the window manager can obtain the display screen size, determine whether there is a status bar, lock the screen, and take screenshots. The content provider stores and retrieves data and makes it accessible to applications. For example, this data includes video, images, audio, dialed and received calls, browsing history and bookmarks, and the phone book. The view system includes visual controls, such as controls for displaying text and images, and can be used to build applications. The display interface can be composed of one or more views, such as a display interface including a text notification icon, or a view that displays text and a view that displays images. The telephony manager provides communication functions for the electronic device, such as managing call status (including connected and disconnected calls). The resource manager provides various resources for applications, such as localized strings, icons, images, layout files, and video files. The notification manager enables applications to display notification information in the status bar. It can be used to convey informational messages and can disappear automatically after a short period of time without user interaction. For example, the notification manager is used to notify the completion of downloads or message reminders. The notification manager can also be used to display notifications in the status bar at the top of the system in the form of icons or scrolling text, such as notifications from applications running in the background. It can also be used to display notifications in the form of dialog windows on the screen, such as text messages in the status bar, beeps, vibrates electronic devices, flashes indicator lights, etc.

[0071] The Android runtime is responsible for scheduling and management of the Android system. It includes core libraries and a virtual machine. The core libraries consist of two parts: one for Java language functions and the other for the Android core library. The application layer and the application framework layer run in the virtual machine. The virtual machine executes the Java files in the application layer and application framework layer as binary files. The virtual machine performs functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0072] The system library can include multiple functional modules. For example: surface manager, media libraries, 3D graphics processing library (such as OpenGL ES), and 2D graphics engine (such as SGL). The surface manager is used to manage the display subsystem and provides the fusion of 2D and 3D layers for multiple applications. The media library supports playback and recording of various common audio and video formats, as well as static image files. The media library can support multiple audio and video encoding formats, such as MPEG4, H.264, MP3, AAC, AMR, JPG, PNG, etc. The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, synthesis, and layer processing. The 2D graphics engine is a drawing engine for 2D drawing.

[0073] The kernel layer, serving as a layer between hardware and software, is the core program within the operating system and is also known as the operating system kernel. The kernel layer provides programs with interfaces to access system hardware, such as memory, graphics cards, and some external devices. In one possible embodiment, the kernel layer includes at least a display driver, a camera driver, an audio driver, and a sensor driver.

[0074] Figure 4 is a schematic diagram of the structure of a service processing device provided in an embodiment of the present application, which is applied to the processor system provided above. The service processing device includes at least one processing core and memory. When the at least one processing core is multiple processing cores, the multiple processing cores can share the memory. Figure 5 is a schematic flow diagram of a service processing method provided in an embodiment of the present application. The method can be executed by the service processing device shown in Figure 4 and includes the following steps.

[0075] S301: The at least one processing core runs a first periodic service in a periodic service and obtains historical operation information corresponding to one or more sub-services in the first periodic service, where the periodic service has multiple periods and the first periodic service is in the first period of the multiple periods.

[0076] The periodic service may refer to a service with multiple periods, each of which includes at least one of the following: a transmission time interval (TTI) in communications, a frame in video images, or a time slice in operating system scheduling. FIG6 shows a schematic diagram of multiple periods of the periodic service, taking each of the multiple periods as a frame and a TTI as an example. The multiple periods may be represented as frame 0 to frame 3 or TTI 0 to TTI 3. In one possible example, the periodic service may include: image-related tasks with a frame period, communication transmission services with a TTI period, control services with a time slice period, scheduling services with a TTI period, or scheduling services with a time slice period. A TTI may be a subframe, time slot, or other time unit in communications. A time slice may be a time scheduling unit in an operating system or operating system kernel. A time slice may be the allowed runtime allocated by the operating system or operating system kernel to a program (or a thread running the program). That is, each time the program runs is a time slice, and a time slice allocated to the program can be used to run a portion of the program.

[0077] In addition, the one or more sub-services may refer to one or more service segments or program segments included in the periodic service. In a possible example, the one or more sub-services may include at least one of the following: calling a specific function, accessing a specific address, accessing specific data, or executing a specific branch.

[0078] In one possible embodiment, the historical operation information (or metadata) corresponding to the one or more sub-services includes at least one of the following: branch history information, instruction trace, data trace, cache hot and cold information, page table history information, or quality of service (QoS) information. Branch history information refers to information related to executed branches, such as branch addresses and jump information. The address includes a source address and a target address, which form an address pair. The jump information may include a jump direction and a jump destination, where the jump direction indicates the jump direction of the jump instruction (i.e., jump or not jump), and the jump destination refers to the destination address after the jump. The instruction trace indicates the trace of accessed instructions and may also be referred to as instruction memory access history information. The data trace indicates the trace of accessed data and may also be referred to as data memory access history information. The cache hot and cold information indicates the hotness of data and / or instructions in the cache (e.g., the first, second, and third level caches). The page table history information is used to indicate the correspondence between the virtual address and physical address of the accessed data and / or instruction. The QoS information is used to indicate the scheduling policy recommended based on QoS during the scheduling process.

[0079] Furthermore, before the at least one processing core executes the first periodic service, the at least one processing core may also determine the one or more sub-services within the periodic service, that is, determine which sub-services are applicable to the solution of this embodiment. The action of determining the one or more sub-services within the periodic service may be specifically performed by software running on the at least one processing core, such as an operating system kernel.

[0080] In one possible embodiment, the operating system kernel running on the at least one processing core may mark the one or more sub-services in the periodic service. For example, the operating system kernel may add marking information to the start and end positions of the program segments corresponding to the one or more sub-services in the periodic service to mark the one or more sub-services in the periodic service. The operating system kernel may then send the periodic service carrying the marking information to the at least one processing core, so that the at least one processing core, when running the first periodic service in the periodic service, obtains historical operation information corresponding to the one or more sub-services in the first periodic service.

[0081] S302: The at least one processing core stores the historical operation information in the memory.

[0082] When the at least one processing core obtains historical operation information of one or more sub-services in the first period service, the at least one processing core may store the historical operation information in the memory. Optionally, the memory includes at least one of the following: on-chip dedicated memory, on-chip shared buffer, or off-chip memory. Exemplarily, the on-chip shared buffer may be a third-level cache, the off-chip memory may be a main memory or a main memory, and the on-chip dedicated memory may be a first-level or second-level cache, or a storage space dedicated to certain specific services including the current service.

[0083] Optionally, the storage space in the above-mentioned memory for storing the historical operation may be allocated by the operating system kernel running on the at least one processing core. In a possible embodiment, before the periodic service runs, the operating system kernel may generate configuration information and send the configuration information to the at least one processing core in the hardware layer. The configuration information is used to allocate storage space in the memory for the periodic service; when the at least one processing core receives the configuration information, it stores the historical operation information in the storage space in the memory according to the configuration information. Exemplarily, the configuration information may include the starting address and the ending address of the storage space, or include one of the starting address or the ending address of the storage space, and the capacity of the storage space, etc. The address included in the configuration information may be a virtual address.

[0084] Furthermore, after obtaining the historical operation information, the at least one processing core may output the historical operation information to the memory via a cache queue (or historical queue). The cache queue may receive and filter duplicate information from the historical operation information, such as filtering duplicate addresses from the historical operation information before sending it to the memory. The cache queue may be a multiple-input, one-output cache queue. In addition to filtering duplicate information, it may also be used to balance the bandwidth difference between input and output to improve the transmission efficiency of the historical operation information.

[0085] For example, as shown in FIG7 , assuming that the one or more sub-services include sub-service 0, sub-service 1, and sub-service 2, the first processing core executes the program corresponding to the first periodic service and, in the process of executing context 1, context 2, and context 3 corresponding to sub-service 0, sub-service 1, and sub-service 2, respectively, the first processing core obtains historical operation information of sub-service 0, sub-service 1, and sub-service 2, filters the historical operation information through the cache queue, and stores it in the storage space. The storage space may have a ring storage structure.

[0086] S303: The at least one processing core runs a second periodic service in the periodic service according to the historical operation information, where the second periodic service is in a second period among the multiple periods.

[0087] The second cycle is located after the first cycle, i.e., the second cycle service runs after the first cycle service runs. Optionally, the interval between the second cycle and the first cycle is less than a preset number of cycles, i.e., the interval between the second cycle and the first cycle is closer. Exemplarily, the second cycle is adjacent to the first cycle, i.e., it is the next cycle after the first cycle.

[0088] In a possible embodiment, when the periodic service includes a first cycle service located in a first cycle and a second cycle service located in a second cycle, and the second cycle is adjacent to the first cycle, the at least one processing core can obtain the historical operation information from the memory during the process of running the second cycle service, and run the second cycle service based on the historical operation information, such as using the historical operation information as pre-fetch information to run the second cycle service.

[0089] Prefetch information may refer to information required for the operation of a service that is acquired in advance before the service is executed, such as instructions and / or data. Using the historical operation information as prefetch information may mean writing the historical operation information into the hardware prefetcher of the currently running processing core, so that the hardware prefetcher, after caching and address translation, sends the information to the first, second, or third level caches according to policy settings. This means that the instructions and / or data needed for future use are pre-populated into the corresponding caches. Subsequently, the second-cycle service is executed based on the instructions and / or data in the cache to improve the operational efficiency of the second-cycle service.

[0090] Optionally, the first periodic service and the second periodic service include the same one or more sub-services. In one possible embodiment, when the at least one processing core is used to run the periodic service, the operating system kernel running on the at least one processing core may determine, before running the periodic service, that the first periodic service and the second periodic service include the same one or more sub-services. Thereafter, the at least one processing core may confirm that the periodic service is run according to the method of the present application.

[0091] Optionally, when the at least one processing core is not running a periodic business, or when the at least one processing core is running a periodic business but different periodic businesses of the periodic business do not include the same one or more sub-businesses, the operating system kernel may not add marking information to the periodic business. At this time, the at least one processing core executes according to the process in the prior art, that is, the at least one processing core does not obtain the historical operation information of the above-mentioned one or more sub-businesses in the process of running the business. That is, the operating system kernel can automatically determine whether the first periodic business and the second periodic business include the same one or more sub-businesses (that is, automatically determine whether it belongs to a profit scenario), thereby avoiding erroneous triggering of improper operations and negative profits in non-target scenarios.

[0092] When the first-period business and the second-period business include the same one or more sub-businesses, the at least one processing core uses the historical operation information of the one or more sub-businesses obtained in the first-period business as pre-fetch information to run the second-period business during the operation of the second-period business. This can greatly reduce the cache miss rate in the second-period business processing process, improve the prediction accuracy and IPC, and thereby improve the operation efficiency of the periodic business.

[0093] The following examples illustrate the beneficial effects that can be achieved by this method when the historical operation information includes different information. Specifically, if the historical operation information includes branch history information, when the at least one processing core uses the branch history information as prefetch information to guide branch prediction during the second cycle business operation, the branch prediction accuracy and coverage rate during the second cycle business processing can be improved; if the historical operation information includes data access history information, when the at least one processing core uses the data access history information as prefetch information to guide data prefetching during the second cycle business operation, the data prefetch accuracy and coverage rate during the second cycle business processing can be improved; if the historical operation information includes instruction access history information, when the at least one processing core uses the instruction access history information as prefetch information When the prefetch information is used to guide instruction prefetching during the second-cycle business operation process, the instruction prefetching accuracy and coverage during the second-cycle business processing process can be improved; if the historical operation information includes cold data historical information, when the at least one processing core uses the cold data historical information as prefetch information to guide cache replacement during the second-cycle business operation process, the cache utilization rate during the second-cycle business processing process can be improved; if the historical operation information includes page table miss historical information, when the at least one processing core uses the page table miss historical information as prefetch information to guide page table prefetching during the second-cycle business operation process, the page table hit rate during the second-cycle business processing process can be improved.

[0094] Exemplarily, as shown in FIG8 , assuming that the periodic service is a frame drawing service and includes drawing of frames 1 and 2, frame 2 being the next frame after frame 1, and a first processing core among the at least one processing core is used to run the frame drawing service, then: the first processing core obtains historical operation information (or recorded key information) of multiple marked sub-services during the drawing of frame 1, for example, the historical operation information includes branch history information, instruction traces, data traces, cache hot and cold information, page table history information, etc.; the first processing core stores the obtained historical operation information in a storage space of a memory; thereafter, the first processing core obtains the historical operation information from the memory and uses the historical operation information as prefetch information for drawing frame 2, for example, caching corresponding information in the historical operation information in a branch prediction buffer, an instruction cache, a shuffle engine, a register, and a data cache, etc., that is, when drawing frame 2, the first processing core can retrieve the stored key information for executing the drawing of frame 2, thereby improving the drawing efficiency of frame 2 and achieving performance benefits.

[0095] Furthermore, if the periodic service migrates between different processing cores in the at least one processing core, that is, the periodic service undergoes inter-core migration (or inter-core switching), in combination with FIG5 , as shown in FIG9 , the method further includes S304 - S305 .

[0096] S304: When the second period service is switched from the first processing core to the second processing core, the operating system kernel sends indication information to the second processing core, where the indication information is used to indicate the storage space.

[0097] In a possible embodiment, the at least one processing core includes a first processing core and a second processing core. If, after the first processing core completes running the first periodic service in the periodic service, the periodic service migrates from the first processing core to the second processing core, that is, the second periodic service in the periodic service is run by the second processing core, the operating system kernel can send indication information to the second processing core, and the indication information can be used to indicate the storage space in the memory for storing historical operation information of the above-mentioned one or more sub-services.

[0098] S305: The second processing core obtains the historical operation information from the storage space according to the instruction information.

[0099] In a possible embodiment, during the process of the second processing core running the second cycle business, the second processing core can obtain the historical operation information from the storage space according to the indication information sent by the operating system kernel when receiving the indication information, and use the historical operation information as pre-fetched information to run the second cycle business.

[0100] Optionally, the indication information may also be used to indicate the storage address of the historical operation information currently to be read. For example, the indication information may also be used to indicate a read pointer, which may also be referred to as a read address offset value. Upon receiving the indication information, the second processing core may determine the storage address currently to be read based on the read pointer and the starting address of the storage space, thereby retrieving the corresponding historical operation information from the storage space based on the storage address.

[0101] Furthermore, during the process of running the second periodic business, the second processing core can also obtain the historical operation information of one or more sub-businesses in the second periodic business, and update the historical operation information stored in the storage space based on the historical operation information, so as to provide more accurate, comprehensive and fresh historical operation information for the operation of subsequent periods in the periodic business.

[0102] Optionally, the second processing core may store historical operation information of the one or more sub-services in the second periodic service in the storage space via a write pointer, which may also be referred to as a write address offset value. The length between the write pointer and the read pointer may be fixed and may be set based on actual needs. This embodiment of the present application does not impose any specific limitations on this.

[0103] In one possible example, as shown in FIG7 above, the storage space can be a ring-shaped storage structure, which can also be called a naturally winding storage structure. The information stored in the storage structure can be naturally refreshed by continuous writing. In this way, the second processing core can read the historical operation information of one or more sub-services in the first cycle service from the storage space while storing the historical operation information of one or more sub-services in the second cycle service in the storage space during the operation of the second cycle service. The read pointer is represented as rptr in the figure, and the write pointer is represented as wptr.

[0104] In another possible example, as shown in FIG10 , the memory may include a write cache, a read cache, an address translation unit, and a system memory. The write cache and the read cache are coupled to the address translation unit and the system memory, and the aforementioned storage space is specifically storage space within the system memory. The following describes the operation of the memory using the write and read operations of the second processing core as an example.

[0105] Specifically, when the second processing core needs to write the first historical operation information, the second processing core can place the first historical operation information in the cache queue of the second processing core. When the first historical operation information is evicted from the cache queue, the first historical operation information enters the write cache of the memory. The write cache determines the first virtual address of the first historical operation queue based on the write pointer wptr corresponding to the first historical operation information and the starting address of the storage space, and obtains the first physical address corresponding to the first virtual address through the address conversion unit, and then stores the first historical operation information in the system memory according to the first physical address. When the cache queue of the second processing core is evicted or the second processing core has a first-level cache miss, the second processing core can determine the second virtual address based on the read instruction rptr and the starting address of the storage space, and obtain the second physical address corresponding to the second virtual address through the address conversion unit, and then read the second historical operation information from the system memory according to the second physical address, and store the second historical operation information in the prefetch cache as prefetch information.

[0106] The following examples illustrate the structures and characteristics of the various components described above. For example, the cache queue is a table storage structure with a corresponding capacity of 4KB, which can be used to store instructions and / or data. The cache queue can trigger the storage and prefetching of historical execution information when dequeuing. The cache queue transmission width can be 16 bytes (bytes). The write cache is a cache structure that can be used to manage write requests. For example, four dequeues from the cache queue can trigger a write to the write cache, and the amount of data written per write can be 64B. The read cache is a cache structure that can be used to manage read requests. The read cache can initiate a read when encountering a new cache line. The amount of data read per read can be 64B, and a read can trigger four prefetches. The address translation unit is a table structure, which can be a mini-translation lookaside buffer (mini-TLB), used to manage address translation. When a page table miss occurs, the mini-TLB can retrieve the corresponding page table from the primary TLB and / or the secondary TLB. The prefetch cache is a cache structure that can be used to manage prefetch requests and is responsible for high-order translation filtering.

[0107] During the write and read processes of the second processing core, historical operation information written to the system memory is first collected in a cache queue and then moved to the write cache. This two-level cache allows for writing historical operation information, balancing the external and internal processing bandwidth of the memory. Furthermore, the second processing core can use stream writes to write the historical operation information collected in the cache queue to the system memory to improve write performance.

[0108] Optionally, the operating system kernel may further release the storage space when the periodic service processing is completed. In one example, when the periodic service is running on the first processing core and has not been migrated, the operating system kernel may release the storage space when the first processing core completes processing the periodic service. In another example, when the periodic service is migrated from the first processing core to the second processing core, the operating system kernel may release the storage space when the second processing core completes processing the periodic service.

[0109] For ease of understanding, the following illustrates the software flow involved in the execution of the above-described method by the service processing device, using each period of the periodic service as an example frame. The software may include an application and an operating system kernel. The application may be an application that triggers the periodic service. Optionally, the application may be a predefined key application.

[0110] Exemplarily, as shown in FIG11 , the software process may specifically include: S1, application startup; S2, the operating system kernel recognizes the process of the application, and turns on the frame learning optimization (FLO) master switch, where the FLO refers to the solution provided by the present application; S3, when the periodic service is started (or called frame startup), the operating system kernel allocates storage space and enables the FLO of the currently running first processing core, so that the first processing core runs the first periodic service, obtains the corresponding historical operation information at the location of the marking information and stores it in the storage space, where the marking information is used to mark one or more sub-services; S4, when the periodic service migrates to the second processing core (i.e., switching occurs), the operating system kernel records the current storage location in the storage space and turns off the first processing core. The operating system kernel turns off the FLO of the second processing core; S5, the operating system kernel sends the recorded storage location to the second processing core, and enables the FLO of the second processing core, so that the second processing core obtains the historical operation information from the storage space and runs the second periodic business according to the FLO function. The second processing core can also obtain the historical operation information of one or more sub-businesses in the second periodic business and update the storage space; S6, when the periodic business processing is completed (or called the frame end) or the one or more sub-businesses end, the operating system kernel turns off the FLO of the second processing core; S7, the operating system kernel releases the storage space; S8, the application exits.

[0111] Furthermore, in addition to being applied to the periodic services provided above, the solutions in the embodiments of the present application can also be applied to other services with multiple cycles, or scenarios that require cyclic processing. The duration of each of the multiple cycles, or the duration of each cyclic processing, can be longer or shorter than the duration of the frame, TTI, and time slice provided above, and the embodiments of the present application do not impose specific restrictions on the duration of each cycle. In one example, the solutions in the embodiments of the present application can also be applied to scenarios of wireless communications, such as user management functions in wireless communications that are usually triggered by periodic events or sudden events. The periodic events can include TTI level and 10ms+ level. When performing the user management, it is usually necessary to cyclically process the data of the same type of users. The cyclically processed data may include, but is not limited to, measurement feedback, scheduling results, or business demands.

[0112] In an embodiment of the present application, the at least one processing core can be used to run the first periodic business in the periodic business and obtain historical operation information corresponding to one or more sub-businesses, the memory can be used to store the historical operation information, and the at least one processing core can also be used to run the second periodic business in the periodic business based on the historical operation information, and the first periodic business and the second periodic business are respectively located in the first period and the second period of the multiple periods. Since there is a large similarity between different cycles of the periodic business, the memory stores the historical operation information corresponding to one or more sub-businesses in the first periodic business, and the at least one processing core obtains the required operation information from the memory when running the second periodic business. This can reduce the cache miss rate of the at least one processing core when processing the second periodic business, improve the prediction accuracy and IPC (number of instructions / clock cycle), and thus improve the operation efficiency of the business.

[0113] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the interaction between at least one processing core and the memory in the business processing device. It can be understood that in order to realize the above functions, the business processing device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0114] The embodiment of the present application can divide the functional modules of the business processing device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The following is an example of dividing each functional module according to each function.

[0115] Figure 12 is a schematic diagram of the structure of a service processing device provided in an embodiment of the present application. The device includes: a service execution unit 401 and a storage unit 402. The service execution unit 401 can be used to support the device in driving at least one processing core to execute S301 and S303 in the above-mentioned method embodiment; the storage unit 402 can be used to support the device in executing S302 in the above-mentioned method embodiment. Furthermore, the device also includes: a scheduling unit 403, which is used to support the device in executing S304 in the above-mentioned method embodiment, allocating storage space for periodic services using configuration information, releasing the storage space when the periodic service processing is completed, and determining one or more sub-services in the periodic service. All relevant content of each step involved in the above-mentioned method embodiment can be referenced to the functional description of the corresponding functional module and will not be repeated in this embodiment of the present application. The above-mentioned units can exist in the form of software, hardware, or a combination of the two. For example, if a unit exists in the form of software, it can be a software unit located in the kernel of the operating system running on the processing core or other software-driven unit of the processing core. If a unit exists in the form of hardware, it can be a functional hardware component within a processing core, and can include digital logic circuits, storage / cache circuits, or other circuits, which are not limited in this embodiment. It is understood that all relevant content of each step involved in the above method embodiment can be referenced to the functional description of the corresponding functional module, and this embodiment of the application will not be repeated here.

[0116] In another embodiment of the present application, an electronic device is provided, as shown in FIG13 . The electronic device includes a processor 501 and a memory 502. The memory 502 is used to store computer instructions, and the processor 501 is used to execute the computer instructions, so that the electronic device implements the multiple steps of the method embodiment provided above. Furthermore, the electronic device also includes a communication interface 503 and a bus 504. The processor 501, the memory 502, and the communication interface 503 are coupled via the bus 504. The communication interface 503 can be used to support communication with the electronic device.

[0117] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another device, or ignoring or not implementing certain features.

[0118] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. The readable storage medium may include: a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc., which can store program code. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0120] In another embodiment of the present application, a readable storage medium is also provided, which stores computer execution instructions. When a device (which may be a single-chip microcomputer, chip, etc.) or a processor executes the steps in the above method embodiment.

[0121] In another embodiment of the present application, a computer program product is provided, which includes computer instructions stored in a readable storage medium; at least one processor of the device can read the computer instructions from the readable storage medium, and at least one processor executes the computer instructions so that the device performs the steps in the above method embodiment.

[0122] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A business processing device, characterized in that: The device comprises: at least one processing core, configured to run a first periodic service in a periodic service and obtain historical operation information corresponding to one or more sub-services in the first periodic service, wherein the periodic service has multiple periods and the first periodic service is in a first period of the multiple periods; A memory, configured to store the historical operation information; The at least one processing core is further configured to run a second periodic service in the periodic service according to the historical operation information, where the second periodic service is located in a second period among the multiple periods.

2. The device according to claim 1, characterized in that The second period is adjacent to the first period.

3. The device according to claim 1 or 2, characterized in that Each of the multiple periods includes at least one of the following: a transmission time interval TTI, a frame, or a time slice.

4. The device according to any one of claims 1 to 3, characterized in that The first periodic service and the second periodic service include the same one or more sub-services.

5. The device according to any one of claims 1 to 4, characterized in that: The at least one processing core is further configured to determine the one or more sub-services in the periodic service.

6. The device according to any one of claims 1 to 5, characterized in that The historical operation information includes at least one of the following: branch history information, instruction trace, data trace, cache hot and cold information, page table history information, or quality of service (QoS) information.

7. The device according to any one of claims 1 to 6, characterized in that The memory includes at least one of the following: an on-chip dedicated memory, an on-chip shared buffer, or an off-chip memory.

8. A business processing device, characterized in that: The device comprises: a service execution unit, configured to drive at least one processing core to execute a first periodic service among periodic services, and obtain historical operation information corresponding to one or more sub-services in the first periodic service, wherein the periodic service has multiple periods, and the first periodic service is in a first period among the multiple periods; A storage unit, configured to store the historical operation information in a memory; The service execution unit is further configured to drive the at least one processing core to execute a second periodic service in the periodic service according to the historical operation information, where the second periodic service is located in a second period among the multiple periods.

9. The device according to claim 8, characterized in that The second period is adjacent to the first period.

10. The device according to claim 8 or 9, characterized in that Each of the multiple periods includes at least one of the following: a transmission time interval TTI, a frame, or a time slice.

11. The device according to any one of claims 8 to 10, characterized in that: The first periodic service and the second periodic service include the same one or more sub-services.

12. The device according to any one of claims 8 to 11, characterized in that The device further comprises: The scheduling unit is configured to determine the one or more sub-services in the periodic service.

13. The device according to claim 12, characterized in that The scheduling unit is further configured to generate configuration information, wherein the configuration information is used to allocate storage space in the memory for the periodic service; The storage unit is further configured to store the historical operation information in the storage space according to the configuration information.

14. The device according to claim 13, characterized in that The scheduling unit is further configured to send indication information to the service execution unit when the second periodic service is switched from the first processing core to the second processing core, wherein the indication information is used to indicate the storage space; The service execution unit is configured to drive the second processing core to obtain the historical operation information from the storage space according to the instruction information.

15. The device according to claim 13 or 14, characterized in that The scheduling unit is further configured to release the storage space when the periodic service processing is completed.

16. The device according to any one of claims 8 to 15, characterized in that The historical operation information includes at least one of the following: branch history information, instruction trace, data trace, cache hot and cold information, page table history information, or quality of service (QoS) information.

17. The device according to any one of claims 8 to 16, characterized in that The memory includes at least one of the following: an on-chip dedicated memory, an on-chip shared buffer, or an off-chip memory.

18. A business processing method, characterized in that: The method comprises: Running a first periodic service in a periodic service, and obtaining historical operation information corresponding to one or more sub-services in the first periodic service, wherein the periodic service has multiple periods, and the first periodic service is in a first period of the multiple periods; Storing the historical operation information in a memory; A second periodic service among the periodic services is run according to the historical operation information, where the second periodic service is located in a second period among the multiple periods.

19. The method according to claim 18, characterized in that The second period is adjacent to the first period.

20. The method according to claim 18 or 19, characterized in that Each of the multiple periods includes at least one of the following: a transmission time interval TTI, a frame, or a time slice.

21. The method according to any one of claims 18 to 20, characterized in that The first periodic service and the second periodic service include the same one or more sub-services.

22. The method according to any one of claims 18 to 21, characterized in that The method further comprises: The one or more sub-services in the periodic service are determined.

23. The method according to claim 22, characterized in that The method further comprises: generating configuration information, wherein the configuration information is used to allocate storage space in the memory for the periodic service; The storing the historical operation information in the memory includes: storing the historical operation information in the storage space according to the configuration information.

24. The method according to claim 23, wherein The method further comprises: When the second periodic service is switched from the first processing core to the second processing core, sending indication information to the second processing core, where the indication information is used to indicate the storage space; The second processing core obtains the historical operation information from the storage space according to the instruction information; The running of the second periodic service among the periodic services according to the historical running information includes: the second processing core running the second periodic service among the periodic services according to the historical running information.

25. The method according to claim 23 or 24, characterized in that The method further comprises: When the periodic service processing is completed, the storage space is released.

26. The method according to any one of claims 18 to 25, characterized in that The at least one historical operation information includes at least one of the following: branch history information, instruction trace, data trace, cache hot and cold information, page table history information, or quality of service (QoS) information.

27. The method according to any one of claims 18 to 26, characterized in that The memory includes at least one of the following: an on-chip dedicated memory, an on-chip shared buffer, or an off-chip memory.

28. An electronic device, characterized in that: The electronic device includes a processor and a memory, the memory is used to store computer instructions, and the processor is used to execute the computer instructions, so that the electronic device implements the business processing method according to any one of claims 18 to 27.

29. A readable storage medium, characterized in that The readable storage medium stores computer instructions, and when the computer instructions are executed on a device, the device executes the business processing method according to any one of claims 18 to 27.

30. A computer program product, characterized in that The computer program product includes computer instructions, and when the computer instructions are executed on a device, the device is caused to execute the service processing method according to any one of claims 18 to 27.

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