Arithmetic unit and computing device

Abstract

The present application discloses an arithmetic unit and a computing device. The arithmetic unit comprises: a plurality of processing modules connected in series; at least one communication link arranged on the processing modules; and a signal duty cycle adjusting circuit arranged on the communication link and used to perform duty cycle adjustment on transmission signals on the communication link, wherein the signal duty cycle adjusting circuit comprises a timing logic device used to solve the problem of signal duty cycle distortion during cross-voltage domain transmission.

Description

A computing unit and computing device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202420420117.4 filed on March 5, 2024, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present application relates to the field of computing devices, and in particular to a computing unit and a computing device with a signal duty cycle adjustment function. Background Art

[0004] Currently, multi-chip series connection is widely used to process application scenarios with large amounts of data. Inter-chip communication under multi-chip series power supply usually involves signal communication scenarios that cross voltage domains, and crossing voltage domains will cause the signal duty cycle to shift.

[0005] When a signal is transmitted from a high-voltage domain to a low-voltage domain, the signal output from the high-voltage domain is raised by a fixed voltage value, while the decision level of the low-voltage domain is not raised. Therefore, the duty cycle of the signal after the decision in the low-voltage domain is high, that is, the low-level pulse width becomes narrower and the high-level pulse width becomes wider. Similarly, when a signal is transmitted from a low-voltage domain to a high-voltage domain, the signal output from the low-voltage domain is not raised by a fixed voltage value, while the decision level of the high-voltage domain is raised by a fixed voltage value. Therefore, the duty cycle of the signal after the decision in the high-voltage domain is low, that is, the high-level pulse width becomes narrower and the low-level pulse width becomes wider.

[0006] Currently, the commonly used technical solution is to connect resistors in series between the series-connected chips and adjust the IO drive method to alleviate the offset of the duty cycle, or use a controller and feedback interface to check and monitor the pulse width to obtain the corrected expected value, monitor the pulse width changes of the high and low levels of the signal, and use digital operations such as AND gates, OR gates, and inverters to compensate for signal delays of different time lengths.

[0007] Connecting resistors in series between chips combined with adjusting IO drivers can only mitigate duty cycle offsets; this offset worsens as the number of series connections increases. Delay compensation, which uses digital calculations to monitor the pulse width of high and low levels, is a complex circuit and requires numerous feedback interfaces and control circuits. It also requires a large number of delay cell arrays to cover a wide range of delays. This approach has limitations when considering transmission scenarios such as source synchronization, and increases chip power consumption, chip area, and chip and packaging costs.

[0008] Therefore, there is a need for a computing device with a simple structure, no need for feedback and monitoring circuits, saving chip area, reducing chip power consumption, and having signal duty cycle adjustment, saving chip area, and reducing chip power consumption. Summary of the Invention

[0009] In order to solve the above problems, the present application discloses an operation unit, including: multiple processing modules, which are connected in series; at least one communication link, which is arranged on the processing module; a duty cycle adjustment circuit, which is arranged on the communication link, for adjusting the duty cycle of the transmission signal on the communication link; wherein the duty cycle adjustment circuit includes a timing logic device.

[0010] In the above-mentioned operation unit, the sequential logic device is a trigger.

[0011] In the above-mentioned operation unit, the trigger is a rising edge trigger or a falling edge trigger.

[0012] In the above-mentioned operation unit, the trigger is a single-stage or multi-stage trigger.

[0013] The above-mentioned operation unit, wherein the trigger is a D trigger.

[0014] The above-mentioned computing unit, wherein the processing module further includes:

[0015] An input processing module further comprises:

[0016] an input terminal for receiving a first input signal;

[0017] an output terminal, configured to output a first output signal;

[0018] The above-mentioned operation unit, wherein the sequential logic device further includes:

[0019] a first input terminal for receiving a second input signal;

[0020] a second input terminal for receiving a clock signal;

[0021] An output terminal is used to output a second output signal.

[0022] The above-mentioned computing unit, wherein the processing module further includes:

[0023] An output processing module further comprises:

[0024] an input terminal for receiving a third input signal;

[0025] An output terminal is used to output a third output signal.

[0026] The above-mentioned operation unit, wherein the processing module also includes an internal circuit for performing operations and transmission on signals, including an input end and an output end, and the internal circuit is arranged between the input processing module and the output processing module.

[0027] in,

[0028] The input end of the internal circuit is electrically connected to the output end of the input processing module, and the output end of the internal circuit is electrically connected to the first input end of the sequential logic device; or

[0029] The input end of the internal circuit is electrically connected to the output end of the sequential logic device, and the output end of the internal circuit is electrically connected to the input end of the output processing module.

[0030] In the above-mentioned computing unit, the communication link is provided between the input processing module and the output processing module.

[0031] The above-mentioned computing unit is characterized in that the processing module further includes:

[0032] a first voltage interface, configured to provide a reference low voltage to the input processing module and the output processing module;

[0033] A second voltage interface is used to provide a reference high voltage to the input processing module and the output processing module.

[0034] In the above-mentioned operation unit, the input processing module operates in a first voltage domain, the output processing module operates in a second voltage domain, and the internal circuit operates in a third voltage domain.

[0035] In the above-mentioned operation unit, the processing module further includes a clock module for generating the clock signal, and the clock module is electrically connected to the sequential logic device.

[0036] The above-mentioned operation unit, wherein the frequency of the clock signal is greater than the frequency of the input signal.

[0037] The above-mentioned operation unit, wherein the frequency of the clock signal is twice the frequency of the input signal.

[0038] The above-mentioned operation unit, wherein the duty cycle of the clock signal is the same as the duty cycle of the first input signal.

[0039] The present application also discloses a computing device comprising at least one computing unit as described above.

[0040] The operation unit and computing device disclosed in the present application rely on timing logic devices for clock sampling to achieve the purpose of correcting the duty cycle offset during cross-voltage domain signal transmission. The duty cycle can be corrected without changing the data period, which can greatly simplify the duty cycle optimization logic. There is no need for complex feedback and control circuits, and there is no need to deliberately distinguish between high levels or low levels, so as to achieve duty cycle correction while keeping the period unchanged.

[0041] The present application is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 shows a schematic block diagram of a computing unit in the prior art.

[0043] FIG2 is a schematic diagram showing a waveform of a signal duty cycle offset.

[0044] FIG3 shows a schematic block diagram of a computing unit according to an embodiment of the present application.

[0045] FIG4 shows a schematic block diagram of a processing module according to an embodiment of the present application.

[0046] FIG5 is a schematic diagram showing waveforms after adjusting the duty cycle of a signal according to an embodiment of the present application.

[0047] FIG6 shows a schematic block diagram of a processing module according to another embodiment of the present application.

[0048] FIG7 shows a schematic block diagram of a processing module according to another embodiment of the present application.

[0049] FIG8 shows a schematic block diagram of a processing module according to another embodiment of the present application.

[0050] FIG9 shows a schematic block diagram of a computing unit according to another embodiment of the present application.

[0051] 1 : In the accompanying drawings, reference numerals are as follows: 1, 2, 6: arithmetic units; 10, 20, 30, 40, 50: processing modules; 101, 201: uplink communication links; 100, 200: downlink communication links; 202, 602: signal duty cycle adjustment circuits; 2020: D-type flip-flop; 203: input processing module; 204, 304, 404, 504: internal circuits; 205: clock module; 206: output processing module; DI_rx1: uplink input signal receiving port; DO_tx1: uplink output signal transmitting port; DI_rx2: downlink input signal receiving port; DO_tx2: downlink output signal transmitting port; DI1: first input signal; DI2: second input signal; DI3: third input signal; DO1: first output signal; DO2: second output signal; DO3: third output signal; D: first input terminal; CLK: second input terminal; Q: output terminal; V_NEG: first voltage interface; V_POS: second voltage interface; VCC: power supply; GND: ground. DETAILED DESCRIPTION

[0052] The technical solution of the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments to further understand the purpose, solution and efficacy of the present application, but it is not intended to limit the scope of protection of the claims attached to the present application.

[0053] Explanation of terms,

[0054] Duty cycle: refers to the proportion of the high level time in a cycle of a periodic signal to the total time of the cycle.

[0055] Decision level: The decision voltage threshold when judging whether the signal is high or low. For example, the low-level decision level is 0V and the high-level decision level is 0.3V. A voltage signal less than or equal to 0V is a low-level signal, and a voltage signal greater than or equal to 0.3V is a high-level signal.

[0056] Figure 1 shows a schematic block diagram of a conventional computing unit. The computing unit 1 includes multiple processing modules 10, which are connected in series between a power supply and ground. Each processing module 10 has a voltage difference, VCE, between one end closest to the power supply and the other end closest to ground. This voltage difference, VCE, provides the operating voltage required for normal operation of the processing module 10. For example, if VCE is 0.3V, when the power supply is 12V, the voltage across the processing module 10 closest to the power supply is 11.7-12V, while the voltage across the processing module 10 closest to ground is 0-0.3V. When the power supply is 12V, 40 processing modules 10 can be connected in series, and when the power supply is 24V, 80 processing modules 10 can be connected in series.

[0057] The computing unit 1 also includes at least one communication link, which is provided within the processing module 10. Specifically, it may include two communication links, such as an uplink communication link 101 and a downlink communication link 100. The processing module 10 includes an uplink input signal receiving port DI_rx1, an uplink output signal transmitting port DO_tx1, a downlink input signal receiving port DI_rx2, and a downlink output signal transmitting port DO_tx2. The communication links include the uplink communication link 101 and the downlink communication link 100. The uplink signal transmission path of the multiple processing modules 10 is as follows: the signal output by DO_tx1 of the previous processing module 10 is transmitted to DI_rx1 of the current processing module 10. The signal then passes through the uplink communication link 101, is output by DO_tx1 of the current processing module 10, and is then transmitted to DI_rx1 of the next processing module 10. This continues in this order until the signal is output by DO_tx1 of the last processing module. Similarly, the downlink signal transmission path is: the signal output by DO_tx2 of the previous processing module 10 is transmitted to DI_rx2 of the current processing module 10, the signal passes through the downlink communication link 100, and is output by DO_tx2 of the current processing module 10, and then transmitted to DI_rx2 of the next processing module 10, and so on, until the signal is output through DO_tx2 of the last processing module 10.

[0058] For example, when a processing module 10 calculates a result, it converts the result into an output signal and transmits it via a communication link to a control board, a remote chip, or m processing modules 10 above or below it. For example, when a processing module 10 transmits intermediate data, it converts the intermediate data into an output signal and transmits it via a communication link to a control board, a remote chip, or m processing modules 10 above or below it.

[0059] Serial communication has relatively low requirements for signal timeliness, but has high requirements for signal duty cycle. The signal duty cycle has a very large impact on the success rate of communication and the transmission speed. In particular, when a large number of processing modules 10 are connected in series, the signal duty cycle will gradually deteriorate due to changes in the voltage domain or other reasons such as digital signal jitter when the signal is transmitted across multiple levels. In low-speed mode or when the number of series-connected stages is small, the impact of the signal duty cycle offset is not obvious. However, when the number of series-connected processing modules 10 increases and the signal is transmitted at high speed, the impact of the duty cycle offset will be very obvious.

[0060] As shown in Figure 2, which shows a waveform diagram of a signal duty cycle offset, multiple processing modules are powered in series, and signals are transmitted across voltage domains, which can cause a signal duty cycle offset during transmission.

[0061] Specifically, when a signal is transmitted from a low-voltage domain to a high-voltage domain, the decision level of the signal output by the low-voltage domain does not rise as a whole, while the decision level of the high-voltage domain is raised by a fixed voltage value. This causes the duty cycle of the signal after the high-voltage domain passes the decision to be low, that is, the high-level pulse width becomes narrower and the low-level pulse width becomes wider. In the above case, the waveform of the original signal signal is a periodic square wave signal. After the first transmission transmission1, the duty cycle duty 1 of the signal becomes smaller, that is, the duration of the high-level signal decreases. When the number of processing modules 10 connected in series increases, during the nth signal transmission transmission n, the signal received by the processing module 10 will accumulate duty cycle offsets, causing the duty cycle duty n of the signal high level to become smaller, that is, the duration of the high-level signal is shorter, which will lead to poor signal transmission quality and affect system performance. When the number of series stages is large, it may even cause a high-level bit to disappear, resulting in information errors and system failure.

[0062] When a signal is transmitted from a high-voltage domain to a low-voltage domain, the signal output by the high-voltage domain is raised as a whole by a fixed voltage value, while the decision level of the low-voltage domain does not rise. Therefore, the duty cycle of the signal after the decision in the low-voltage domain is high, that is, the low-level pulse width becomes narrower and the high-level pulse width becomes wider. After the signal is transmitted between multiple processing modules 10, the duration of the high-level signal becomes longer and the duration of the low-level signal becomes shorter, which will also cause the signal transmission quality to deteriorate, affecting system performance and even transmitting information errors.

[0063] FIG3 shows a schematic block diagram of an arithmetic unit 2 according to an embodiment of the present application. To address the aforementioned signal duty cycle offset issue, the present application discloses an arithmetic unit 2 comprising a plurality of processing modules 20 connected in series; at least one communication link provided in the processing module 20; and a signal duty cycle adjustment circuit 202 provided on the communication link for adjusting the duty cycle of a transmission signal on the communication link. The signal duty cycle adjustment circuit 202 comprises a sequential logic device. The sequential logic device is configured to sample the transmission signal and, upon sampling a high or low level of the transmission signal, adjust the transmission signal according to a fixed initial duty cycle.

[0064] Specifically, in one embodiment, the communication link may include at least one of an uplink communication link 201 and a downlink communication link 200. The processing module 20 includes an uplink input signal receiving port DI_rx1, an uplink output signal transmitting port DO_tx1, a downlink input signal receiving port DI_rx2, and a downlink output signal transmitting port DO_tx2. A signal duty cycle adjustment circuit 202 is configured to adjust the signal duty cycle offset of the uplink communication link 200 and / or downlink communication link 200. The uplink signal transmission path is as follows: the signal output by DO_tx1 of the previous processing module 20 is transmitted to DI_rx1 of the current processing module 20. The signal passes through the uplink communication link 201, and the duty cycle offset is adjusted by the signal duty cycle adjustment circuit 202. The signal is then output by DO_tx1 of the current processing module 20. The downlink signal transmission path is as follows: the signal output by DO_tx2 of the previous processing module 20 is transmitted to DI_rx2 of the current processing module 20. The signal passes through the downlink communication link 200, and the duty cycle offset is adjusted by the signal duty cycle adjustment circuit 202, and the signal is output by DO_tx2 of the current processing module 20.

[0065] Optionally, the signal duty cycle adjustment circuit 202 includes a sequential logic device, which is a trigger. The trigger may be a rising edge trigger or a falling edge trigger.

[0066] In the above embodiment, a rising-edge trigger triggers on the rising edge of the clock signal, sampling the high or low level of the transmission signal; a falling-edge trigger triggers on the falling edge of the clock signal, sampling the high or low level of the transmission signal. Each time a high or low level is sampled, a high or low signal of a fixed length is output, ensuring that the duty cycle offset of the transmission signal is corrected.

[0067] Optionally, the trigger may be a single-stage trigger or a multi-stage trigger. The trigger may be of any type of a D trigger, an RS trigger, a JK trigger, or a T trigger.

[0068] In the above embodiment, it is sufficient to acquire the high level or low level of the transmission signal, and by setting the clock signal connected to the trigger, the signal output by it is consistent with the frequency of the transmission signal of the communication link, so that the signal output by it is the forward signal or reverse signal of the transmission signal of the communication link, thereby solving the duty cycle offset problem of the transmission signal.

[0069] Those skilled in the art will appreciate that, in the above embodiments, the triggering mode, the number of trigger levels and the type of trigger are intended to more clearly express the intention of the present application and are not intended to limit the present application.

[0070] As shown in Figure 4, it is a schematic block diagram of the processing module 20 of an embodiment of the present application. In this embodiment, the processing module 20 also includes an input processing module 203. The input processing module 203 includes an input end and an output end. The input end is used to receive a first input signal DI1, and the output end is used to output a first output signal DO1.

[0071] In the above embodiment, the first input signal DI1 can be the output signal of the previous processing module 20. For the first processing module 20 in the signal transmission path, the first input signal DI1 can also be a signal sent by the control board or a remote chip. The first input signal DI1 can be an uplink signal or a downlink signal. The input processing module 203 connects the output signal of the previous processing module 20 or the signal sent by the control board to the communication link.

[0072] Typically, the first input signal DI1 is transmitted inward via a signal transmission line external to the chip. To ensure that the transmitted signal is not lost along the signal transmission line, the voltage is typically relatively high. However, chip design typically requires low internal voltages for power consumption and internal wiring considerations. Therefore, the input processing module 203 must also include a step-down conversion function to ensure that the voltage of the first output signal DO1 is lower than the voltage of the first input signal DI1. In this case, the input processing module 203 includes an input unit and a step-down unit. If signal transmission line voltage loss or chip power consumption and internal wiring are not a concern, the input processing module 203 may not need to include a step-down conversion function; in this case, the input processing module 203 only includes an input unit.

[0073] The signal duty cycle adjustment circuit 202 can be arranged between the input unit and the step-down unit, or after the step-down unit, as long as it can adjust the duty cycle of the transmission signal on the communication link inside the chip.

[0074] Optionally, in this embodiment, the trigger type in the signal duty cycle adjustment circuit 202 is a D trigger, which includes a first input terminal D for receiving a second input signal DI2, a second input terminal CLK for receiving a clock signal, and an output terminal Q for outputting a second output signal DO2.

[0075] In the above embodiment, the second input signal DI2 is the first output signal DO1 of the input processing module 203, which can be the output signal of the input unit or the output signal of the step-down unit. The D flip-flop captures the high or low level of the transmission signal, and the second output signal DO2 is the forward or reverse signal of the transmission signal of the communication link.

[0076] Optionally, the clock module 205 is used to generate a clock signal to provide a clock signal input for the second input terminal CLK of the D flip-flop. The clock module can be a clock tree within the chip or an external crystal oscillator plus an internal clock generator. This application is not limited to this.

[0077] In the above embodiment, the frequency of the clock signal is set according to the frequency of the transmission signal, ensuring that the D flip-flop accurately captures the high level and low level of the second input signal DI2 when activated by the clock signal.

[0078] Optionally, the processing module 20 further includes an output processing module 206 , which includes an input end and an output end. The input end is used to receive a third input signal DI3 , ie, the second output signal DO2 , and the output end is used to output a third output signal DO3 .

[0079] In the above embodiment, when the processing module 20 is the last processing module 20 on the signal transmission path, the second output signal DO2 can also be output to the control board or the remote chip. The second output signal DO2 can be an uplink signal or a downlink signal.

[0080] Typically, the third output signal DO3 is transmitted externally via signal transmission lines external to the chip. To ensure that the transmitted signal is not lost along the signal transmission lines, the voltage is typically relatively high. However, chip design typically requires low internal voltages for power consumption and internal wiring considerations. Therefore, the output processing module 206 must also include a boost conversion function to ensure that the voltage of the third output signal DO3 is higher than the voltage of the third input signal DI3. In this case, the output processing module 206 includes a boost unit and an output unit. If signal transmission line voltage loss or chip power consumption and internal wiring are not a concern, the output processing module 206 may not need to include a buck conversion function; in this case, the output processing module 206 only includes an output unit.

[0081] The signal duty cycle adjustment circuit 202 can be arranged between the boost unit and the output unit, or before the boost unit, as long as it can adjust the duty cycle of the transmission signal on the communication link inside the chip.

[0082] Optionally, the processing module 20 further includes an internal circuit 204 for performing operations or transmitting signals received by the processing module 20. The internal circuit 204 includes an input terminal and an output terminal, and is disposed between the input processing module and the output processing module.

[0083] In the above embodiment, the internal circuit 204 may be a repeater that retransmits or forwards data signals to extend the network transmission distance. It is provided on the communication link within the chip to ensure the transmission stability of the transmitted signal. The internal circuit 204 may be a computing circuit that receives the transmitted signal and performs operations on the data.

[0084] Optionally, a communication link is provided between the input processing module 203 and the output processing module 206 , and the communication link can transmit an uplink signal or a downlink signal.

[0085] In the above embodiment, the signal duty cycle adjustment circuit 202 may be provided on the communication link between the processing module 203 and the output processing module 206 to adjust the duty cycle of the transmission signal.

[0086] Optionally, the processing module 20 also includes a first voltage interface V_NEG, which is electrically connected to the input processing module 203 and the output processing module 206 and is used to provide a reference low voltage to the input processing module 203 and the output processing module 206, and a second voltage interface V_POS, which is electrically connected to the input processing module 203 and the output processing module 206 and is used to provide a reference high voltage to the input processing module 203 and the output processing module 206.

[0087] In the above embodiment, the operating voltage of the internal core computing circuit of the chip is relatively low. In addition, some peripheral circuits of the chip need to provide additional auxiliary voltage. At this time, the auxiliary voltage is relatively high. The second voltage interface V_POS can be connected to the auxiliary voltage, thereby providing a reference high voltage for the input processing module 203 and the output processing module 206.

[0088] Optionally, there are three voltage domains in the present application, the input processing module 203 operates in a first voltage domain, the output processing module 206 operates in a second voltage domain, and the internal circuit 204 operates in a third voltage domain.

[0089] In the above embodiment, the input processing module 203 is used to step down the voltage and provide it to the chip for signal calculation and processing, while the output processing module 206 is used to step up the voltage for signal transmission. Of course, if the voltage loss of the signal transmission line or the power consumption and internal wiring of the chip are not considered, the input processing module 203 does not need to step down the voltage, and the output processing module 206 does not need to step up the voltage. In this case, the second voltage domain and the third voltage domain are equal.

[0090] Optionally, the processing module 20 further includes a clock module 205 for generating a clock signal. The clock module 205 is electrically connected to the second input terminal CLK of the D flip-flop.

[0091] In the above embodiment, the frequency of the clock signal generated by the clock module 205 must be greater than the frequency of the first input signal DI1. Preferably, the frequency of the clock signal is twice the frequency of the first input signal DI1. Of course, the frequency of the clock signal can be an even or odd multiple of the frequency of the first input signal DI1, but a higher frequency of the clock signal also results in higher power consumption. The phase of the clock signal should be set within a reasonable range of the phase of the first input signal DI1. For example, with the first high-level signal as the starting point of the transmission signal, it is necessary to ensure that the clock signal is sampled near the middle of the high-level signal. Otherwise, when the duty cycle of the transmission signal decreases, the trigger will not be able to sample the high-level signal when triggered by the clock signal. Instead, it may directly sample the position where the high-level signal is offset, resulting in the high-level signal being sampled as a low-level signal. Preferably, the phase of the clock signal is one-quarter of the phase of the first input signal DI1. The duty cycle of the clock signal can be the same as that of the first input signal DI1, both being 50%.

[0092] Next, the working principle of the signal duty cycle adjustment circuit 202 for solving the signal duty cycle offset problem caused by cross-stage transmission will be described with reference to FIG. 4 and FIG. 5 .

[0093] First, the signal offset is described in detail. Multiple processing modules are connected in series. For example, each processing module 20 has a voltage difference VCE between one end close to the ground and the other end close to the power supply. VCE is, for example, 0.3V, and the voltage range of the transmitted signal is 0 to 1.8V.

[0094] In a scenario where a signal is transmitted from a low-voltage domain to a high-voltage domain, for example, the voltage across the previous processing module 20 is 0.3-0.6V, the voltage across the current processing module 20 is 0.6-0.9V, and the voltage across the next processing module 20 is 0.9-1.2V. The voltage range of the signal output by the previous processing module 20 is 0.3-2.4V, with a reference low voltage of 0.3V and a reference high voltage of 2.4V. The signal is transmitted to the current processing module 20. The voltage of the current processing module 20 is raised by VCE as a whole. The reference low voltage is 0.6V and the reference high voltage is 2.7V. When the input processing module 203 of the current processing module 20 receives and processes it, a cross-voltage domain transmission from the low voltage domain (0.3~2.4V) to the high voltage domain (0.6~2.7V) occurs. The decision level of the signal output by the low voltage domain (0.3~2.4V) does not rise as a whole, while the decision level of the high voltage domain (0.6~2.7V) is raised by a fixed voltage value (0.3V). Therefore, the duty cycle of the signal after the high voltage domain passes the judgment will become lower, that is, the high-level pulse width becomes narrower and the low-level pulse width becomes wider. The first output signal DO1 output by the current input processing module 203 has a signal duty cycle offset.

[0095] The current input processing module 203 then steps down the voltage, and the adjusted voltage domain, i.e., the third voltage domain, is used internally by the chip. The receiving end of the internal circuit 204 processes the received first output signal DO1 and outputs it through the output end. The first input end of the D-type flip-flop receives the signal outputted by the internal circuit's output end, samples it based on the clock signal, and outputs the second output signal DO2, adjusting the signal's duty cycle offset. The input end of the output processing module 206 receives the second output signal DO2, which it then steps up to adjust the voltage domain. The adjusted voltage domain is 0.6-2.7V, i.e., the second voltage domain. The output end of the output processing module 206 then outputs the third output signal DO3 to the next processing module 20.

[0096] The processing process of the next processing module 20 is the same as that of the current processing module 20, and so on.

[0097] Similarly, in a scenario where a signal is transmitted from a high voltage domain to a low voltage domain, for example, the voltage across the previous processing module 20 is 0.9-1.2V, the voltage across the current processing module 20 is 0.6-0.9V, and the voltage across the next processing module 20 is 0.3-0.6V.

[0098] The voltage range of the signal output by the previous processing module 20 output processing unit 20 is 0.9 to 3.0V, with a reference low voltage of 0.9V and a reference high voltage of 3.0V. The signal is transmitted to the current processing module 20, and the voltage of the current processing module 20 is reduced by one VCE as a whole, with a reference low voltage of 0.6V and a reference high voltage of 2.7V. After the signal is transmitted and received and processed by the input processing module 203 of the current processing unit 20, a cross-voltage domain transmission from the high voltage domain (0.9 to 3.0V) to the low voltage domain (0.6 to 2.7V) occurs. The signal output by the high voltage domain is raised by a fixed voltage value as a whole, while the decision level of the low voltage domain does not rise. Therefore, the duty cycle of the signal after the decision in the low voltage domain is high, that is, the low-level pulse width becomes narrower and the high-level pulse width becomes wider. The first output signal DO1 output by the current input processing module 203 has a signal duty cycle offset.

[0099] The current input processing module 203 then steps down the voltage, and the adjusted voltage domain, i.e., the third voltage domain, is used by the internal circuit. The receiving end of the internal circuit 204 performs operations on the received first output signal DO1 and outputs the signal through the output end. The first input end of the D flip-flop receives the signal output from the output end of the internal circuit, samples it according to the clock signal, and outputs the second output signal DO2, adjusting the signal duty cycle offset. The input end of the output processing module 206 then receives the second output signal DO2, and the output processing module 206 then steps up the voltage domain. The adjusted voltage domain is 0.6-2.7V, i.e., the second voltage domain. The output end of the output processing module 206 outputs the third output signal DO3 to the next processing module 20.

[0100] The processing process of the next processing module 20 is the same as that of the current processing module 20, and so on.

[0101] During each signal transmission across voltage domains, the signal duty cycle offset is adjusted in a timely manner through the above processing to ensure that after the signal is transmitted across voltage domains between multiple serially connected processing modules 20, the final output signal has no duty cycle offset from the initial input signal.

[0102] Those skilled in the art will understand that, in the above embodiments, the range of the signal voltage, the values ​​of the first voltage domain, the second voltage domain, the third voltage domain, and the voltage difference VCE are all for the purpose of more clearly expressing the intention of the present application, and are not used to limit the present application.

[0103] Referring now to Figure 5, Figure 5 is a schematic diagram of a D-type flip-flop adjusting a signal's duty cycle. The D-type flip-flop's first input terminal, D, is electrically connected to the output terminal of an internal circuit. The received signal undergoes a duty cycle offset (duty refers to the duty cycle offset, meaning the duration of the high level decreases) relative to the first input signal, DI1. The clock signal's frequency is twice that of the first input signal, DI1. After receiving the signal output from the internal circuit's output terminal, the D-type flip-flop awaits the next rising edge of the clock. At this point, the D-type flip-flop is enabled at the rising edge of the clock, and outputs the same level as the signal at the first input terminal, D, at its output terminal, Q. This level is maintained for one clock cycle. Upon the next rising edge of the clock, the D-type flip-flop samples and outputs the signal again, and so on. This ensures that, with a delay of less than one clock cycle, the duty cycle of the signal at output terminal Q remains consistent with that of the first input signal, DI1. By sampling the clock signal, delaying its output, and maintaining the signal, the duty cycle offset can be adjusted in a timely manner. Through serial transmission through hundreds of processing modules 20, the signal maintains the same duty cycle as the input signal.

[0104] In addition, the D flip-flop can be rising-edge triggered or falling-edge triggered. The D flip-flop also has another output terminal, the signal output by this output terminal is the opposite signal to the signal output by the output terminal Q. The other output terminal of the D flip-flop can also be used to adjust the duty cycle offset, but this application is not limited to this.

[0105] FIG4 is a schematic block diagram of a processing module 20 according to an embodiment of the present application. In this embodiment, the input of internal circuit 204 is electrically connected to the output of input processing module 203. That is, the input of internal circuit 204 receives the first output signal DO1, and the output of internal circuit 204 is electrically connected to the first input D of a D flip-flop. In this case, processing module 20 can be a repeater, which extends the distance of network transmission by retransmitting or forwarding data signals. It is provided on the communication link within the chip to ensure the transmission stability of the transmitted signal.

[0106] FIG6 is a schematic block diagram of a processing module 30 according to another embodiment of the present application. This differs from processing module 20 in that the input of internal circuit 304 is electrically connected to the output of the D flip-flop, meaning the signal received by the input of internal circuit 304 is the second output signal DO2, while the output of internal circuit 304 is electrically connected to the input of output processing module 206, meaning the signal output by internal circuit 304 is the third input signal DI3. In this case, processing module 20 can function as a repeater, extending the distance of network transmission by retransmitting or forwarding data signals. This repeater is located within the chip's internal communication link to ensure signal transmission stability.

[0107] FIG7 is a schematic block diagram of a processing module 40 according to another embodiment of the present application. This differs from processing module 20 in that the input of internal circuit 404 is electrically connected to the output of input processing module 203. Internal circuit 404 processes the transmitted signal internally, and then, when the result or intermediate data is obtained, transmits it via a communication link to a control board, a remote chip, or m-level processing modules 10 above or below. In this case, processing module 20 may be a computational circuit, such as an adder, subtractor, or other functional calculator, configured to receive the transmitted signal and perform operations on the data.

[0108] FIG8 is a schematic block diagram of a processing module 50 according to another embodiment of the present application. This differs from processing module 30 in that the input of internal circuit 304 is electrically connected to the output of a D-type flip-flop. Internal circuit 504 processes the transmitted signal internally, and then, when the result or intermediate data is obtained, transmits it via a communication link to a control board, a remote chip, or m-level processing modules 10 above or below. In this case, processing module 20 may be a computational circuit, such as an adder, subtractor, or other functional calculator, configured to receive the transmitted signal and perform operations on the data.

[0109] As shown in Figure 9, Figure 9 shows a schematic block diagram of an operation unit of another embodiment of the present application. The operation unit 6 includes n processing module groups connected in series, each processing module group includes m processing modules 60 connected in parallel. A power supply VCC is used to power multiple processing module groups, a ground GND, and the n processing module groups connected in series are arranged between the power supply VCC and the ground GND. There is a voltage difference VCE between adjacent processing module groups. For example, if VCE is 0.3V, when the power supply is 12V, the voltage across the processing module group Group n close to the ground end is 0~0.3V, and the voltage across the processing module group Group n-1 connected to it is 0.3~0.6V. And so on. The voltage across the processing module group Group 1 closest to the power supply is 11.7~12V. When the power supply is 12V, 40 processing module groups can be connected in series, and each processing module group contains m parallel processing modules 60. Under this connection method, for example, m is 4, and each processing module group contains the first to fourth processing modules from left to right, then the operation unit 6 can include 120 processing modules 60.

[0110] The computing unit 6 includes an uplink input signal receiving port DI_rx1, an uplink output signal transmitting port DO_tx1, a downlink input signal receiving port DI_rx2, and a downlink output signal transmitting port DO_tx2. The signal transmission paths of the multiple processing modules 60 in the computing unit 6 are serial. The uplink communication path is where DI_rx1, the first processing module 60 in the processing module group connected to ground GND, receives an input signal. Through the transmission of the multiple processing modules 60 along the serial signal transmission path, DO_tx1, the first processing module 60 in the processing module group connected to power supply VCC, transmits an output signal. The downlink communication path is where DI_rx2, the first processing module 60 in the processing module group connected to power supply VCC, receives an input signal. Through the transmission of the multiple processing modules 60 along the serial signal transmission path, DO_tx2, the first processing module 60 in the processing module group connected to ground GND, transmits an output signal.

[0111] Because there is a voltage difference between adjacent processing module groups, signals are transmitted across voltage domains between adjacent processing module groups, which will cause a signal duty cycle offset. In order to adjust this duty cycle offset, a signal duty cycle adjustment circuit 602 is set in at least the first and last processing modules 60 of each processing module group.

[0112] It will be understood by those skilled in the art that, in the above embodiments, the values ​​of m and n, and the power supplies VCC and VCE are intended to more clearly express the intention of the present application, and are not intended to limit the present application.

[0113] The present application also discloses a computing device, comprising at least one computing unit as described above.

[0114] Of course, the present application may have many other embodiments. Without departing from the spirit and essence of the present application, technicians familiar with the field can make various corresponding changes and modifications based on the present application, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present application.

[0115] Industrial Applicability:

[0116] In summary, the operation unit and computing device disclosed in the present application rely on sequential logic devices to use clock sampling to achieve the purpose of correcting the duty cycle offset during cross-voltage domain signal transmission. The duty cycle can be corrected without changing the data period, which can greatly simplify the duty cycle optimization logic. There is no need for complex feedback and control circuits, and there is no need to deliberately distinguish between high levels or low levels. The duty cycle can be corrected while keeping the period unchanged. The structure is simple, chip area is saved, and chip power consumption is low.

Claims

1. A computing unit, characterized in that: include: a plurality of processing modules, wherein the plurality of processing modules are connected in series; at least one communication link provided in the processing module; a duty cycle adjustment circuit, provided on the communication link, for adjusting the duty cycle of a transmission signal on the communication link; Wherein, the duty cycle adjustment circuit includes a sequential logic device.

2. The computing unit according to claim 1, wherein: The sequential logic device is a trigger.

3. The computing unit according to claim 2, wherein: The trigger is a rising edge trigger or a falling edge trigger.

4. The computing unit according to claim 2, wherein: The trigger is a single-stage or multi-stage trigger.

5. The computing unit according to claim 2, wherein: The trigger is a D trigger.

6. The computing unit according to claim 1, wherein: The processing module further includes: An input processing module further comprises: an input terminal for receiving a first input signal; An output terminal is used to output a first output signal.

7. The computing unit according to claim 6, wherein: The sequential logic device further comprises: a first input terminal for receiving a second input signal; a second input terminal for receiving a clock signal; An output terminal is used to output a second output signal.

8. The computing unit according to claim 7, wherein: The processing module further includes: An output processing module further comprises: an input terminal for receiving a third input signal; An output terminal is used to output a third output signal.

9. The computing unit according to claim 8, wherein: The processing module further includes an internal circuit for performing operations or transmission on signals, including an input end and an output end. The internal circuit is arranged between the input processing module and the output processing module.

10. The computing unit according to claim 9, wherein: in, The input end of the internal circuit is electrically connected to the output end of the input processing module, and the output end of the internal circuit is electrically connected to the first input end of the sequential logic device; or The input end of the internal circuit is electrically connected to the output end of the sequential logic device, and the output end of the internal circuit is electrically connected to the input end of the output processing module.

11. The computing unit according to claim 8, wherein: The communication link is provided between the input processing module and the output processing module.

12. The computing unit according to claim 8, wherein: The processing module further includes: a first voltage interface, configured to provide a reference low voltage to the input processing module and the output processing module; A second voltage interface is used to provide a reference high voltage to the input processing module and the output processing module.

13. The computing unit according to claim 9, wherein: The input processing module operates in a first voltage domain, the output processing module operates in a second voltage domain, and the internal circuit operates in a third voltage domain.

14. The computing unit according to claim 1, wherein: The processing module further includes a clock module for generating a clock signal, and the clock module is electrically connected to the sequential logic device.

15. The computing unit according to claim 14, wherein: The frequency of the clock signal is greater than the frequency of the transmission signal.

16. The computing unit according to claim 15, wherein: The frequency of the clock signal is twice the frequency of the transmission signal.

17. A computing device comprising at least one computing unit according to any one of claims 1 to 16.

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