Chip system and electronic device

Abstract

The present application relates to the technical field of chips, and provides a chip system and an electronic device. The chip system comprises a mainboard, a physical module and a physical adapter board, wherein a plurality of first chips in the mainboard are communicatively interconnected, and a plurality of second chips in the physical module are communicatively interconnected; N groups of physical communication interfaces are arranged in the physical adapter board; the plurality of first chips and the plurality of second chips are respectively coupled to the N groups of physical communication interfaces, and the N groups of physical communication interfaces transmit S types of communication signals in a time division manner, S being greater than N. The plurality of first chips in the mainboard are communicatively interconnected, and the plurality of second chips in the physical module are communicatively interconnected, so that the number of groups of communication interfaces arranged in the physical adapter board is less than the number of types of communication signals transmitted between the mainboard and the physical module; on this basis, the number of connecting pins in the physical adapter board can be reduced. In addition, different types of communication signals are transmitted in a time division manner, so that signal crosstalk caused by simultaneous signal transmission is avoided.

Description

Chip system and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 7, 2024, with application number 202410274917.4 and application name "A Chip System and Electronic Device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of chip technology, and in particular to a chip system and electronic equipment. Background Art

[0004] In existing terminal devices, such as smartphones (including different forms such as candy-bar phones and foldable phones), tablets, and laptops, the communication between their motherboards and peripheral physical modules (such as the display chip and touch chip in the screen module) usually adopts independent connection solutions. As shown in Figure 1, the motherboard is equipped with an application processor (AP) chip and a power management integrated circuit (PMIC) chip, and the screen module side is equipped with a display driver integrated circuit (DDIC) and a touch chip. The middle shaded area is a physical adapter board. Among them, three groups of physical communication interfaces are set on the physical adapter board, including the mobile industry processor interface (MIPI) that supports communication between the AP chip and the DDIC chip, the serial peripheral interface (SPI) that supports communication between the AP chip and the touch chip, and the swire interface or I2C interface that supports communication between the PMIC chip and the DDIC.

[0005] Because each chip uses a separate physical communication interface, a large number of connection pins are required on the physical adapter board, which takes up a lot of physical space. To reduce the physical space occupied, the distance between the connection pins can be shortened. However, when the communication interfaces transmit signals simultaneously, signal crosstalk will occur, affecting the accuracy of signal transmission. Summary of the Invention

[0006] The present application provides a chip system and an electronic device to reduce the physical space occupied by connection pins in a physical adapter board and avoid signal crosstalk.

[0007] In the first aspect, an embodiment of the present application provides a chip system, comprising: a main board, a physical module and a physical adapter board; wherein, the main board comprises a plurality of first chips, which are communicatively interconnected with each other, and the physical module comprises a plurality of second chips, which are communicatively interconnected with each other; N groups of physical communication interfaces are provided in the physical adapter board, where N is a positive integer; the plurality of first chips and the plurality of second chips are respectively coupled to the N groups of physical communication interfaces, and the N groups of physical communication interfaces transmit S types of communication signals in a time-sharing manner, where S is greater than N and S is a positive integer.

[0008] It should be noted that the above-mentioned main board can be understood as the main board of an electronic device. For example, the main board of a mobile phone, the main board of a tablet computer, the main board of a smart speaker, etc., are only illustrative and not specifically limited here. The above-mentioned physical module can be understood as a chip module that communicates with the main board. For example, a screen module (including a touch chip, a display chip, etc.), a perception module (including: a gravity sensor chip, an image sensor chip, etc.), are only illustrative and not specifically limited here. The above-mentioned physical adapter board can be understood as a bridge for communication between the main board and the physical module.

[0009] In this application, because the multiple first chips in the mainboard communicate with each other, and the multiple second chips in the physical module communicate with each other, the number of communication interface groups provided in the physical adapter board is smaller than the number of communication signal types transmitted between the mainboard and the physical module. This reduces the number of connection pins in the physical adapter board. In addition, different types of communication signals are transmitted in a time-sharing manner, avoiding signal crosstalk caused by simultaneous signal transmission.

[0010] In an optional manner, multiple first chips include an application chip and a power management chip; multiple second chips include a touch chip and a display chip; N is 1; in the first time period, the physical communication interface is MIPI, and the physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; in the second time period, the physical communication interface is SPI, and the physical communication interface transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the physical communication interface is a swire interface or an I2C interface, and the physical communication interface transmits a power signal, which is a communication signal between the power management chip and the display chip, and the second time period is different from the first time period.

[0011] Based on the above solution, it can be seen that the multiple first chips in the mainboard communicate and interconnect with each other, and the multiple second chips in the physical module also communicate and interconnect with each other. Therefore, a set of physical communication interfaces can be provided on the physical adapter board. Based on this, the number of connection pins on the physical adapter board can be reduced. In addition, communication between the mainboard and the physical module can be guaranteed by transmitting different types of signals at different time periods.

[0012] In an optional manner, the communication interconnection mode is a bridging mode.

[0013] In an optional manner, the bridging method includes one of the following:

[0014] Communication and interconnection are achieved through a bridge chip; or, a bridge functional unit is set in one or more chips.

[0015] In the second aspect, an embodiment of the present application provides a chip system, including: a main board, a physical module and a physical adapter board; wherein, the main board includes multiple first chips, and the multiple first chips are communicated and interconnected, and the physical module includes multiple second chips, and the multiple second chips are independent of each other; N groups of physical communication interfaces are provided in the physical adapter board, where N is a positive integer; the multiple first chips and the multiple second chips are respectively coupled to the N groups of physical communication interfaces, and the N groups of physical communication interfaces transmit S types of communication signals in time-sharing, where S is greater than N and S is a positive integer.

[0016] In this application, the multiple second chips in the physical module are independent of each other (i.e., the multiple second chips are not connected), and the multiple first chips in the mainboard are communicatively interconnected. This makes the number of communication interface groups provided in the physical adapter board smaller than the number of communication signal types transmitted between the mainboard and the physical module. Based on this, the number of connection pins in the physical adapter board can be reduced. In addition, different types of communication signals are transmitted in a time-sharing manner, avoiding signal crosstalk caused by simultaneous signal transmission.

[0017] In an optional manner, multiple first chips include an application chip and a power management chip; multiple second chips include a touch chip and a display chip; N is 2; N groups of physical communication interfaces include: SPI and a first physical communication interface; in a first time period, the first physical communication interface is MIPI, and the first physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; in a second time period, SPI transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the first physical communication interface is a swire interface or an I2C interface, and the first physical communication interface transmits a power signal, which is a communication signal between the power management chip and the display chip, and the second time period is different from the first time period.

[0018] Based on the above solution, it can be seen that the multiple first chips in the mainboard communicate and interconnect with each other, so two sets of physical communication interfaces can be provided on the physical adapter board. Based on this, the number of connection pins on the physical adapter board can be reduced. In addition, communication between the mainboard and the physical module can be ensured by transmitting different types of signals at different time periods.

[0019] In an optional manner, the communication interconnection mode is a bridging mode.

[0020] In an optional manner, the bridging method includes one of the following:

[0021] Communication and interconnection are achieved through a bridge chip; or, a bridge functional unit is set in one or more chips.

[0022] In a third aspect, an embodiment of the present application provides a chip system, comprising: a main board, a physical module and a physical adapter board; wherein, the main board comprises a plurality of first chips, which are independent of each other, and the physical module comprises a plurality of second chips, which are communicatively interconnected with each other; N groups of physical communication interfaces are provided in the physical adapter board, where N is a positive integer; the plurality of first chips and the plurality of second chips are respectively coupled to the N groups of physical communication interfaces, and the N groups of physical communication interfaces transmit S types of communication signals in a time-sharing manner, where S is greater than N and S is a positive integer.

[0023] In this application, the multiple first chips in the mainboard are independent of each other (i.e., the multiple first chips are not connected), and the multiple second chips in the physical module are interconnected and communicate with each other. This makes the number of communication interface groups provided in the physical adapter board smaller than the number of types of communication signals transmitted between the mainboard and the physical module. Based on this, the number of connection pins in the physical adapter board can be reduced. In addition, different types of communication signals are transmitted in a time-sharing manner, avoiding signal crosstalk caused by simultaneous signal transmission.

[0024] In an optional manner, multiple first chips include an application chip and a power management chip; multiple second chips include a touch chip and a display chip; N is 2; N groups of physical communication interfaces include: a second physical communication interface and a third physical communication interface, the second physical communication interface is a swire interface or an I2C interface; in the first time period, the third physical communication interface is MIPI, and the third physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; in the second time period, the third physical communication interface is SPI, and the third physical communication interface transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the second physical communication interface transmits a power signal, which is a communication signal between the power management chip and the display chip, and the second time period is different from the first time period.

[0025] Based on the above solution, it can be seen that the multiple second chips in the physical module communicate and interconnect with each other, so two sets of physical communication interfaces can be provided on the physical adapter board. Based on this, the number of connection pins on the physical adapter board can be reduced. In addition, communication between the mainboard and the physical module can be guaranteed by transmitting different types of signals at different time periods.

[0026] In an optional manner, the communication interconnection mode is a bridging mode.

[0027] In an optional manner, the bridging method includes one of the following:

[0028] Communication and interconnection are achieved through a bridge chip; or, a bridge functional unit is set in one or more chips.

[0029] In a fourth aspect, an embodiment of the present application provides an electronic device, which may include any of the above-mentioned chip systems.

[0030] For the technical effects that can be achieved in the second to fourth aspects mentioned above, please refer to the description of the technical effects that can be achieved by the corresponding possible design schemes in the first aspect mentioned above, and this application will not repeat them here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 shows a schematic diagram of a chip system;

[0032] FIG2A shows a schematic diagram of a chip system provided in an embodiment of the present application;

[0033] FIG2B shows a schematic diagram of a chip system provided in an embodiment of the present application;

[0034] FIG2C shows a schematic diagram of a chip system provided in an embodiment of the present application;

[0035] FIG3 is a schematic diagram showing the communication and interconnection of multiple first chips in a mainboard provided by an embodiment of the present application;

[0036] FIG4 shows a schematic structural diagram of a mainboard provided in an embodiment of the present application;

[0037] FIG5 shows a schematic structural diagram of a screen module provided in an embodiment of the present application;

[0038] FIG6A shows a schematic diagram of a chip system provided in an embodiment of the present application;

[0039] FIG6B shows a schematic diagram of a chip system provided in an embodiment of the present application;

[0040] FIG6C shows a schematic diagram of a chip system provided in an embodiment of the present application;

[0041] FIG7 shows a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of this application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to the device embodiments or system embodiments. In the description of this application, unless otherwise specified, "multiple" means two or more. Therefore, the implementation of the device and method can refer to each other, and the repeated parts will not be repeated.

[0043] In addition, it should be understood that, in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0044] It should be noted that in the embodiments of the present application, "coupling" refers to an electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components. For example, the connection between A and B can also be a direct connection between A and C, a direct connection between C and B, and an indirect connection between A and B through C.

[0045] As described in the background, each chip uses a separate physical communication interface, requiring a large number of connection pins on the physical adapter board, which consumes a significant amount of physical space. To reduce this physical space, the distance between the connection pins can be shortened. However, when signals are transmitted simultaneously between the various communication interfaces, crosstalk can occur, affecting the accuracy of signal transmission.

[0046] Based on this, the present application provides a chip system to reduce the physical space occupied by the connecting pins in the physical adapter board and avoid the occurrence of signal crosstalk. As shown in Figure 2A, the chip system includes: a mainboard, a physical module and a physical adapter board, wherein the mainboard may include multiple first chips, and the physical module may also include multiple second chips. Figure 2A takes the example of the mainboard including X first chips and the physical module including X second chips as an example, wherein X is an integer greater than or equal to 2. In Figure 2A, the X first chips in the mainboard communicate and interconnect with each other, and the X second chips in the physical module communicate and interconnect with each other; N groups of physical communication interfaces are provided in the physical adapter board, where N is a positive integer; multiple first chips and multiple second chips are respectively coupled to the N groups of physical communication interfaces, and the N groups of physical communication interfaces transmit S types of communication signals in time-sharing, where S is greater than N and S is a positive integer. In addition, it should be noted that when multiple first chips are communicated and interconnected, and multiple second chips are communicated and interconnected, when N is equal to 1, the physical space occupied by the connecting pins in the physical adapter board is the least, and there is no crosstalk in the signals, and the communication effect between the mainboard and the physical module is the best.

[0047] The chip system may also be shown in FIG2B , including: a mainboard, a physical module, and a physical adapter board. FIG2B takes an example in which the mainboard includes X first chips and the physical module includes X second chips, where X is an integer greater than or equal to 2. The X first chips are interconnected and communicate with each other, and the X second chips are independent of each other (i.e., there is no connection or the second chips are not interconnected); the physical adapter board is provided with N groups of physical communication interfaces, where N is a positive integer; the plurality of first chips and the plurality of second chips are respectively coupled to the N groups of physical communication interfaces, and the N groups of physical communication interfaces transmit S types of communication signals in a time-sharing manner, where S is greater than N and is a positive integer.

[0048] The chip system may also be shown in FIG2C , including: a mainboard, a physical module, and a physical adapter board. FIG2C takes an example in which the mainboard includes X first chips and the physical module includes X second chips, where X is an integer greater than or equal to 2. The X first chips are independent of each other (i.e., there is no connection or the first chips do not communicate or interconnect with each other), and the X second chips communicate and interconnect with each other; the physical adapter board is provided with N groups of physical communication interfaces, where N is a positive integer; the multiple first chips and the multiple second chips are respectively coupled to the N groups of physical communication interfaces, and the N groups of physical communication interfaces transmit S types of communication signals in a time-sharing manner, where S is greater than N and is a positive integer.

[0049] The above-mentioned main board can be understood as the main board of an electronic device. For example, the main board of a mobile phone, the main board of a tablet computer, the main board of a smart speaker, etc., are only illustrative here and not specifically limited. The above-mentioned physical module can be understood as a chip module that communicates with the main board. For example, a screen module (including a touch chip, a display chip (for example, a DDIC chip), etc.), a perception module (including: a gravity sensor chip, an image sensor chip, etc.), are only illustrative here and not specifically limited. The above-mentioned physical adapter board can be understood as a bridge for communication between the main board and the physical module. Specifically, the physical adapter board can support the transmission of different types of signals between the main board and the physical module. For example, SPI signals, MIPI signals, etc. This is only an illustrative description and does not specifically limit the type of signal.

[0050] Optionally, the motherboard may include multiple first chips, which may be of the same type or different types, and this application does not specifically limit this. For example, the motherboard may include one AP chip and one PMIC chip; or one MCU chip and two PMIC chips. This is merely an example, and does not specifically limit the number and type of chips in the motherboard. The physical module may include multiple second chips, which may be of the same type or different types, and this application does not specifically limit this. For example, the physical module may be a screen module, wherein the screen module includes one touch chip and one display chip; or the physical module includes two touch chips and one display chip. The physical module may be a sensing module, wherein the sensing module includes one gravity sensor chip, one image sensor chip, and one touch chip. This is merely an example, and does not specifically limit the number and type of chips in the physical module.

[0051] Assume that the mainboard includes three first chips, namely the first chip 1, the first chip 2 and the first chip 3, as shown in Figure 3. Among them, the first chip 1 in Figure 3 (a) communicates and interconnects with the first chip 2, and the first chip 2 communicates and interconnects with the first chip 3. The first chip 1 in Figure 3 (b) communicates and interconnects with the first chip 3, and the first chip 3 communicates and interconnects with the first chip 2. The first chip 1 in Figure 3 (c) communicates and interconnects with the first chip 3, and the first chip 1 communicates and interconnects with the first chip 2. This is not specifically limited here, only exemplified. The communication and interconnection of multiple second chips in the physical module can also be understood with reference to Figure 3, and will not be explained in detail here.

[0052] The communication interconnection method of the multiple first chips in the above-mentioned mainboard can be a bridging method. The communication interconnection method of the multiple second chips in the above-mentioned physical module can also be a bridging method. Among them, bridging can build a channel for chip communication, so that more types of signals can be transmitted between chips. Specifically, the bridging method can be to communicate and interconnect through a bridge chip, or to set a bridge function unit in one or more chips. As shown in Figure 4, the mainboard includes: 1 AP chip and 1 PMIC chip. In Figure 4 (a), a bridge chip is set between the AP chip and the PMIC chip. The bridge chip can transmit swire signals or I2C signals (for example, power signals) between the AP chip and the PMIC chip. In Figure 4 (b), a bridge function unit is set in the AP chip. The bridge function unit can transmit swire signals or I2C signals between the AP chip and the PMIC chip. In Figure 4 (c), a bridge function unit is set in the PMIC chip. The bridge function unit can transmit swire signals or I2C signals between the AP chip and the PMIC chip. A bridging function unit is usually provided in the AP chip, which can reduce the physical space occupied in the motherboard, and the integration of the bridging function unit in the AP chip can ensure data processing efficiency.

[0053] As shown in Figure 5, the screen module includes: a touch chip and a display chip. In Figure 5 (a), a bridge chip is provided between the touch chip and the display chip. The bridge chip enables SPI signal transmission between the touch chip and the display chip. In Figure 5 (b), a bridge function unit is provided in the touch chip. The bridge function unit enables SPI signal transmission between the touch chip and the display chip. In Figure 5 (c), a bridge function unit is provided in the display chip. The bridge function unit enables SPI signal transmission between the touch chip and the display chip. Generally, a bridge function unit is provided in the display chip to reduce the physical space occupied in the screen module, and the display chip integrated bridge function unit can ensure data processing efficiency.

[0054] It should be noted that the signal types transmitted between the motherboard and the physical module in different time periods may be different. By statistically analyzing the signal types transmitted in different time periods, the signal transmission pattern can be obtained. Among them, the signal transmission pattern can be understood with reference to the following Table 1. In the Active phase, the signal transmitted between the motherboard and the physical module is the display signal. In the Blank phase (that is, the blanking area of ​​the display chip), the signal transmitted between the motherboard and the physical module is the touch signal or PMIC signal or swire signal (I2C signal). Based on this, different types of signals can be transmitted between the motherboard and the physical module in different time periods.

[0055] Table 1

[0056] Specifically, the duration of the Active phase may be the working duration of the display chip (eg, DDIC chip), which is merely an example and not a limitation.

[0057] For example, four different types of signals can be transmitted between the motherboard and the screen module. These signals are display signals, touch signals, PMIC signals, and power signals. The chips in the motherboard and the screen module communicate with each other via a bridge chip, and the physical adapter board is equipped with a set of physical communication interfaces. Referring to Table 1, in the Active phase, display signals are transmitted between the motherboard and the screen module, so the physical communication interfaces in the physical adapter board transmit display signals. In the Blank phase, touch signals are transmitted between the motherboard and the screen module.

[0058] In this application, because the multiple first chips in the mainboard communicate with each other, and the multiple second chips in the physical module communicate with each other, the number of communication interface groups provided in the physical adapter board is smaller than the number of communication signal types transmitted between the chips in the mainboard and the chips in the physical module. This reduces the number of connection pins in the physical adapter board. In addition, different types of communication signals are transmitted in a time-sharing manner, avoiding signal crosstalk caused by simultaneous signal transmission.

[0059] In order to better illustrate the solution of this application, the following situations are explained, specifically as follows:

[0060] Case 1: Multiple first chips in the mainboard communicate and interconnect, and multiple second chips in the physical module communicate and interconnect

[0061] Among them, the multiple first chips include application chips (such as AP chips) and power management chips (such as PMIC chips); the multiple second chips include touch chips and display chips (for example, DDIC chips); N is 1; in the first time period (that is, the Active stage in Table 1 above), the physical communication interface is MIPI, and the physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; in the second time period (that is, the Blank stage in Table 1 above), the physical communication interface is SPI, and the physical communication interface transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the physical communication interface is a swire interface or an I2C interface, and the physical communication interface transmits a power signal, which is a communication signal between the power management chip and the display chip. The second time period is different from the first time period.

[0062] As shown in Figure 6A, the motherboard includes an AP chip and a PMIC chip, and the physical module is a screen module, which includes a touch chip and a DDIC chip. The AP chip is equipped with a bridging function unit, which enables Swire signals or I2C signals (illustrated as power signals in Figure 6A) to be transmitted between the AP chip and the PMIC chip. The DDIC chip is equipped with a bridging function unit, which enables SPI signals to be transmitted between the touch chip and the DDIC chip. The motherboard and the screen module transmit different types of signals in a time-sharing manner via a set of physical communication interfaces on the physical adapter board. In the first time period (i.e., the Active phase in Table 1 above), the physical communication interface is MIPI, and the AP chip transmits display signals to the DDIC chip via the physical communication interface. In the second time period (i.e., the Blank phase in Table 1 above), the physical communication interface is SPI, and the AP chip transmits touch signals to the touch chip via the physical communication interface. Alternatively, in the second time period, the physical communication interface is a Swire interface or an I2C interface, and the PMIC chip transmits power signals via the physical communication interface.

[0063] Based on the above solution, it can be seen that the multiple first chips in the mainboard communicate and interconnect with each other, and the multiple second chips in the physical module also communicate and interconnect with each other. Therefore, a set of physical communication interfaces can be provided on the physical adapter board. Based on this, the number of connection pins on the physical adapter board can be reduced. In addition, communication between the mainboard and the physical module can be guaranteed by transmitting different types of signals at different time periods.

[0064] Case 2: Multiple first chips in the mainboard communicate and interconnect, and multiple second chips in the physical module are independent of each other

[0065] Among them, the multiple first chips include application chips and power management chips; the multiple second chips include touch chips and display chips; N is 2; N groups of physical communication interfaces include: SPI and a first physical communication interface; in the first time period, the first physical communication interface is MIPI, and the first physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; in the second time period, SPI transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the first physical communication interface is a swire interface or an I2C interface, and the first physical communication interface transmits a power signal, which is a communication signal between the power management chip and the display chip, and the second time period is different from the first time period.

[0066] As shown in Figure 6B, the mainboard includes: an AP chip and a PMIC chip, and the physical module is a screen module, wherein the screen module includes: a touch chip and a DDIC chip. The AP chip is provided with a bridging function unit, based on which a swire signal or an I2C signal can be transmitted between the AP chip and the PMIC chip (illustrated as a power signal in Figure 6B). The mainboard and the screen module transmit different types of signals in a time-sharing manner through two sets of physical communication interfaces in the physical adapter board. In the first time period (i.e., the Active phase in Table 1 above), the first physical communication interface is MIPI, and the AP chip transmits display signals to the DDIC chip through the first physical communication interface; in the second time period (i.e., the Blank phase in Table 1 above), the AP chip transmits touch signals to the touch chip through SPI; alternatively, in the second time period, the first physical communication interface is a swire interface or an I2C interface, and the PMIC chip transmits power signals through the first physical communication interface.

[0067] Based on the above solution, it can be seen that the multiple first chips in the mainboard communicate and interconnect with each other, so two sets of physical communication interfaces can be provided on the physical adapter board. Based on this, the number of connection pins on the physical adapter board can be reduced. In addition, communication between the mainboard and the physical module can be ensured by transmitting different types of signals at different time periods.

[0068] Case 3: Multiple second chips in the physical module communicate and interconnect, and multiple first chips in the mainboard are independent of each other

[0069] Among them, the multiple first chips include application chips and power management chips; the multiple second chips include touch chips and display chips; N is 2; N groups of physical communication interfaces include: a second physical communication interface and a third physical communication interface, the second physical communication interface is a swire interface or an I2C interface; in the first time period, the third physical communication interface is MIPI, and the third physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; in the second time period, the third physical communication interface is SPI, and the third physical communication interface transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the second physical communication interface transmits a power signal, which is a communication signal between the power management chip and the display chip, and the second time period is different from the first time period.

[0070] As shown in Figure 6C, the motherboard includes an AP chip and a PMIC chip, and the physical module is a screen module, wherein the screen module includes a touch chip and a DDIC chip. The DDIC chip is provided with a bridge function unit, based on which SPI signals can be transmitted between the touch chip and the DDIC chip. The motherboard and the screen module transmit different types of signals in a time-sharing manner through two sets of physical communication interfaces in the physical adapter board. In the first time period (i.e., the Active phase in Table 1 above), the third physical communication interface is MIPI, and the AP chip transmits display signals to the DDIC chip via the third physical communication interface; in the second time period (i.e., the Blank phase in Table 1 above), the PMIC chip transmits power signals via the second physical communication interface; alternatively, in the second time period, the third physical communication interface is SPI, and the AP chip transmits touch signals to the touch chip via SPI.

[0071] Based on the above solution, it can be seen that the multiple second chips in the physical module communicate and interconnect with each other, so two sets of physical communication interfaces can be provided on the physical adapter board. Based on this, the number of connection pins on the physical adapter board can be reduced. In addition, communication between the mainboard and the physical module can be guaranteed by transmitting different types of signals at different time periods.

[0072] FIG7 shows an electronic device applicable to the above-mentioned chip system, which may include a mainboard (specifically, different devices (or chips) may be provided in the mainboard, such as the processor, charging management module, and power management module described below) and multiple physical modules, wherein the physical module may be a screen module (specifically, different devices (or chips) may be provided in the screen module, such as the display screen, touch sensor, etc. described below), a sensing module (specifically, different devices (or chips) may be provided in the screen module, such as the camera, distance sensor, etc. described below), etc. Here, taking a mobile phone as an electronic device as an example, a schematic diagram of the structure of a mobile phone that can be applied to this application is introduced.

[0073] The following embodiments are described in detail using mobile phone 100 as an example. It should be understood that the illustrated mobile phone 100 is merely an example, and that mobile phone 100 may have more or fewer components than those shown in FIG7 , may combine two or more components, or may have a different component configuration. The various components shown in FIG7 may be implemented in hardware, including one or more signal processing and / or application-specific integrated circuits, software, or a combination of hardware and software.

[0074] The following is a detailed introduction to the various components of the mobile phone 100 with reference to FIG7 :

[0075] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Among them, different processing units can be independent devices or integrated into one or more processors. Among them, the controller can be the nerve center and command center of the mobile phone 100. The controller can generate an operation control signal based on the instruction opcode and timing signal to complete the control of instruction fetching and execution.

[0076] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly retrieve it from the memory, thus avoiding repeated accesses and reducing processor 110 latency, thereby improving system efficiency.

[0077] When the processor 110 integrates different devices, such as a central processing unit (CPU) and a GPU, the CPU and the GPU can cooperate to execute the operation prompt method provided in the embodiment of the present application. For example, part of the algorithm in the operation prompt method is executed by the CPU, and the other part of the algorithm is executed by the GPU to obtain faster processing efficiency.

[0078] In some embodiments, the processor 110 may include one or more interfaces. For example, the interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0079] Display screen 194 is used to display images, videos, and the like. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, electronic device 100 may include one or N display screens 194, where N is a positive integer greater than one.

[0080] The internal memory 121 can be used to store computer executable program codes, and the executable program codes include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the terminal device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the mobile phone 100 by running instructions stored in the internal memory 121 and / or instructions stored in a memory provided in the processor.

[0081] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be provided in the processor 110, or some functional modules of the audio module 170 can be provided in the processor 110.

[0082] The speaker 170A, also called a "speaker", is used to convert audio electrical signals into sound signals. The terminal device 100 can listen to music or listen to hands-free calls through the speaker 170A.

[0083] Microphone 170C, also known as "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to the microphone 170C to input the sound signal into the microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In other embodiments, the mobile phone 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the mobile phone 100 can also be provided with three, four or more microphones 170C to realize sound signal collection, noise reduction, and identification of sound sources, and realize directional recording function, etc.

[0084] In addition to the above contents, as shown in Figure 7, the mobile phone 100 may also include an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, a receiver 170B, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc. Although not shown in FIG7 , the mobile phone 100 may further include a Bluetooth device, a positioning device, a flashlight, a micro-projection device, a near field communication (NFC) device, etc., which are not described in detail here.

[0085] As used in this specification, the terms "component," "module," "system," and the like are used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on one computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, through local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as an internet that interacts with other systems via signals).

[0086] Those skilled in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0087] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0088] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0089] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0090] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0091] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0092] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A chip system, characterized in that: include: Mainboard, physical module and physical adapter board; The mainboard includes a plurality of first chips, the plurality of first chips are interconnected and communicate with each other, and the physical module includes a plurality of second chips, the plurality of second chips are interconnected and communicate with each other; the physical adapter board is provided with N groups of physical communication interfaces, where N is a positive integer; The plurality of first chips and the plurality of second chips are respectively coupled to the N groups of physical communication interfaces. The N groups of physical communication interfaces transmit S types of communication signals in a time-sharing manner. The S is greater than the N and is a positive integer.

2. The system according to claim 1, wherein: The plurality of first chips include an application chip and a power management chip; the plurality of second chips include a touch chip and a display chip; N is 1; In the first time period, the physical communication interface is a mobile industry processor interface (MIPI), and the physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; In the second time period, the physical communication interface is a serial peripheral interface SPI, and the physical communication interface transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the physical communication interface is a swire interface or an I2C interface, and the physical communication interface transmits a power signal, which is a communication signal between the power management chip and the display chip. The second time period is different from the first time period.

3. The system according to claim 1 or 2, characterized in that The communication interconnection mode is a bridging mode.

4. The system according to claim 3, characterized in that The bridging method includes one of the following: Communication interconnection via a bridge chip; or, A bridging functional unit is provided in one or more chips.

5. A chip system, characterized in that: include: Mainboard, physical module and physical adapter board; The mainboard includes a plurality of first chips, the plurality of first chips are interconnected and communicate with each other, and the physical module includes a plurality of second chips, the plurality of second chips are independent of each other; the physical adapter board is provided with N groups of physical communication interfaces, where N is a positive integer; The plurality of first chips and the plurality of second chips are respectively coupled to the N groups of physical communication interfaces. The N groups of physical communication interfaces transmit S types of communication signals in a time-sharing manner. The S is greater than the N and is a positive integer.

6. The system according to claim 5, characterized in that The plurality of first chips include an application chip and a power management chip; the plurality of second chips include a touch chip and a display chip; N is 2; The N groups of physical communication interfaces include: a serial peripheral interface SPI and a first physical communication interface; In the first time period, the first physical communication interface is a mobile industry processor interface (MIPI), and the first physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; In the second time period, the SPI transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the first physical communication interface is a swire interface or an I2C interface, which transmits a power signal, which is a communication signal between the power management chip and the display chip. The second time period is different from the first time period.

7. The system according to claim 5 or 6, characterized in that The communication interconnection mode is a bridging mode.

8. The system according to claim 7, characterized in that The bridging method includes one of the following: Communication interconnection via a bridge chip; or, A bridging functional unit is provided in one or more chips.

9. A chip system, characterized in that: include: Mainboard, physical module and physical adapter board; The mainboard includes a plurality of first chips, which are independent of each other, and the physical module includes a plurality of second chips, which are communicatively interconnected with each other; the physical adapter board is provided with N groups of physical communication interfaces, where N is a positive integer; The plurality of first chips and the plurality of second chips are respectively coupled to the N groups of physical communication interfaces. The N groups of physical communication interfaces transmit S types of communication signals in a time-sharing manner. The S is greater than the N and is a positive integer.

10. The system according to claim 9, characterized in that The plurality of first chips include an application chip and a power management chip; the plurality of second chips include a touch chip and a display chip; N is 2; The N groups of physical communication interfaces include: a second physical communication interface and a third physical communication interface, the second physical communication interface being a swire interface or an I2C interface; In the first time period, the third physical communication interface is a mobile industry processor interface (MIPI), and the third physical communication interface transmits a display signal, which is a communication signal between the application chip and the display chip; In the second time period, the third physical communication interface is a serial peripheral interface SPI, and the third physical communication interface transmits a touch signal, which is a communication signal between the application chip and the touch chip; or, in the second time period, the second physical communication interface transmits a power signal, which is a communication signal between the power management chip and the display chip, and the second time period is different from the first time period.

11. The system according to claim 9 or 10, characterized in that The communication interconnection mode is a bridging mode.

12. The system according to claim 11, wherein: The bridging method includes one of the following: Communication interconnection via a bridge chip; or, A bridging functional unit is provided in one or more chips.

13. An electronic device, characterized in that: include: The chip system according to any one of claims 1 to 12.

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