Ferroelectric memory and preparation method therefor, and electronic device

Abstract

Provided in the present application are a ferroelectric memory (1) and a preparation method therefor, and an electronic device. The ferroelectric memory (1) comprises: a substrate (301) and a plurality of memory cells (10) formed on the substrate (301), wherein each memory cell (10) comprises a ferroelectric capacitor (C); the ferroelectric capacitor (C) comprises a first electrode (302) and a second electrode (304), which are stacked, and a ferroelectric layer (303); the ferroelectric layer (303) comprises at least one of hafnium oxide and zirconium oxide, and doping elements; and the electronegativity of the doping elements is lower than that of oxygen, and the doping elements may be, for example, sulfur, selenium and tellurium. Thus, anions formed by doping the ferroelectric layer (303) with these elements are more prone to displace under the action of an electric field, an electric polarization state is more prone to switch, and a coercive electric field of a ferroelectric thin film is reduced; in addition, a rectangular electric hysteresis loop can be maintained, so that the operating voltage of a ferroelectric memory device can be reduced, and the anti-interference capability can be improved.

Description

Ferroelectric memory and preparation method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 6, 2024, with application number 202410260069.1 and invention name “Ferroelectric memory and its preparation method, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor storage, and in particular to a ferroelectric memory, a preparation method thereof, and an electronic device. Background Art

[0003] The development of technologies such as cloud computing, AI big data models, and 5G communications has led to new demands for data processing volume and speed. New memory devices with high read / write speeds, large capacity, and low power consumption have become a research hotspot. Currently, hafnium oxide-based ferroelectric random access memory (FeRAM) offers extremely low read / write power consumption (1fJ / bit) and high read / write speeds (<50ns). Therefore, hafnium oxide-based ferroelectric memory devices have become the most promising technology for new memory devices.

[0004] The magnitude of a ferroelectric material's coercive field and the shape of its hysteresis loop are key factors influencing its performance. The magnitude of the coercive field directly affects the memory's operating voltage. The shape of the hysteresis loop determines the ferroelectric film's ability to resist interference. Therefore, reducing the coercive field and maintaining a rectangular hysteresis loop are crucial for novel ferroelectric memories.

[0005] Among existing implementations, some methods alter the intrinsic properties of ferroelectric materials by doping them with cations, increasing the remnant polarization and reducing the coercive field. However, because currently prepared ferroelectric materials are primarily polycrystalline, this increases the power consumption of memory devices, makes breakdown more likely, and reduces the lifespan of ferroelectric films. Others use cyclic alternating electric field wake-up techniques. By applying an alternating electric field to the ferroelectric material, the pinned ferroelectric domains gradually become reversible ferroelectric domains with increasing cycles, resulting in an increase in remnant polarization, a decrease in coercive field, and a more symmetrical rectangular hysteresis loop. However, this method sacrifices the lifespan of the ferroelectric device and reduces device production efficiency, making it unsuitable for mass production. Another approach involves introducing a functional intercalation material between the ferroelectric storage layer and the electrode. The intercalation forms an electric dipole at the interface. During annealing and crystallization, the electric field of the electric dipole guides the ferroelectric polarization axis along the direction of the electric dipole. In ferroelectric devices, this manifests as an increase in remnant polarization and a decrease in coercive field. However, because the intercalation material lacks ferroelectricity, this method can easily cause Pr loss, causing the hysteresis loop to become skewed and deviate from a rectangular shape, thereby reducing the anti-interference ability of the ferroelectric memory device. Therefore, a method is needed to manufacture semiconductor devices that reduce device power consumption, have strong anti-interference capabilities, are not easily broken down, and have a long lifespan. Summary of the Invention

[0006] The present application provides a ferroelectric memory, a preparation method thereof, and an electronic device. The method reduces the coercive electric field of the ferroelectric device and maintains a rectangular hysteresis loop by doping an element with a lower electronegativity than oxygen, thereby reducing the operating voltage of the ferroelectric memory device and improving its anti-interference capability.

[0007] In a first aspect, the present application provides a ferroelectric memory comprising a substrate; and a plurality of memory cells formed on the substrate, each memory cell comprising a ferroelectric capacitor; the ferroelectric capacitor comprising: a first electrode, a second electrode and a ferroelectric layer; the ferroelectric layer comprising a ferroelectric material and a doping element; the electronegativity of the doping element is less than that of the oxygen element, and the electronegativity of the oxygen element is 3.44.

[0008] It should be noted that the doping element can be an element in Group VI other than oxygen, such as sulfur (S) (electronegativity 2.58), selenium (Se) (electronegativity 2.48), or tellurium (Te) (2.10), or a non-Group VI element other than oxygen, such as carbon (C) (electronegativity 2.55) or phosphorus (P) (electronegativity 2.19). The doping element can be one or a combination of multiple elements.

[0009] Because the elements doped into the anions of the ferroelectric film are less electronegative than oxygen, these anions are more likely to shift under the action of an electric field, making the polarization state more easily flipped. This reduces the coercive electric field of the ferroelectric film and thus reduces the power consumption of the device. At the same time, doping with anions prevents the hysteresis loop from becoming skewed, maintaining a rectangular hysteresis loop and improving the device's anti-interference ability.

[0010] In one possible implementation, the doping element is one or more elements in Group VI other than oxygen. It should be noted that the doping element is an element in Group VI other than oxygen. Compared with non-Group VI elements, the anions of such elements are chemically closer to oxygen O and are more likely to produce a ferroelectric phase. The doping element is an element in Group VI other than oxygen, mainly sulfur S, selenium Se, and tellurium Te. The doping element can be one or a combination of multiple elements. For example, sulfur S can be doped alone, sulfur S and selenium Se can be doped at the same time, or sulfur S, selenium Se, and tellurium Te can be doped at the same time.

[0011] It can be seen from this that since the doping element is an element of Group VI other than oxygen, it is closer to oxygen O in chemical coordination and is more likely to produce a ferroelectric phase, thereby maintaining a rectangular hysteresis loop. At the same time, the bond energy of HfS is smaller than that of HfO, making it easier to achieve the flipping of the ferroelectric state, reduce the coercive electric field, and achieve the effect of reducing device power consumption.

[0012] In a possible implementation, the ferroelectric layer is formed between the first electrode and the second electrode; the second electrode, the ferroelectric layer and the first electrode are stacked sequentially from top to bottom on the substrate, and the first electrode is in contact with the substrate.

[0013] It should be noted that the ferroelectric layer is formed between the first electrode and the second electrode, with the upper and lower surfaces directly contacting the first and second electrodes. The stacking order of the stacking structure is to first deposit the first electrode on the substrate, then deposit the ferroelectric layer on the first electrode, and finally deposit the second electrode on the ferroelectric layer.

[0014] By doping elements into the ferroelectric layer and forming a stacked structure arranged in sequence, it is possible to better dope the elements into the ferroelectric layer.

[0015] In one possible implementation, the first electrode or the second electrode is alternately stacked with an insulating layer to obtain a stacked structure; a hole is formed in the stacked structure, a ferroelectric layer is formed on the inner wall of the hole, and a second electrode is formed on the inner wall of the ferroelectric layer.

[0016] It should be noted that the first electrode and the insulating layer are alternately stacked to form a stacked structure, and the number of stacked layers can be one or more. A hole, such as a cylindrical hole, is formed in the stacked structure. The hole may or may not penetrate the stacked structure, that is, the ferroelectric layer and / or the second electrode may or may not contact the substrate. The second electrode and the ferroelectric layer formed in the hole have a certain thickness, and their surfaces are in contact with each other, for example, there is no gap between the second electrode cylinder and the ferroelectric layer ring cylinder.

[0017] By forming a three-dimensional stacking structure, the integration dimension in the vertical direction can be increased, thereby achieving a higher degree of integration and realizing large-capacity storage.

[0018] In one possible implementation, the material forming the substrate or insulating layer includes silicon, germanium, gallium nitride, gallium arsenide, and the present application does not specifically limit the material of the substrate or insulating layer. The material forming the first electrode or the second electrode can be made of a metal-containing material, such as a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. Including TiN, W, Ni, TaN, polysilicon, Ru or Ir materials, the present application does not specifically limit the material forming the first electrode or the second electrode. It should be noted that the first electrode and the second electrode can be of the same material, or different materials.

[0019] In a possible implementation, the ferroelectric material includes at least one of a hafnium oxide-based material and a zirconium oxide-based material.

[0020] It should be noted that the ferroelectric material can be hafnium oxide-based, zirconium oxide-based, or a combination of hafnium oxide-based and zirconium oxide-based. On this basis, it can also include other metal materials. This application does not limit ferroelectric materials other than hafnium oxide-based or zirconium oxide-based.

[0021] In one possible implementation, the ferroelectric memory includes a ferroelectric tunneling junction (FTJ), a ferroelectric field effect transistor (FeFET), and a ferroelectric random access memory (FeRAM).

[0022] Since the doping method proposed in this application tunes the hafnium oxide-based ferroelectric film and is compatible with CMOS technology, it can be integrated into memory devices such as ferroelectric tunneling junctions (FTJs), ferroelectric field-effect transistors (FeFETs), and ferroelectric random access memories (FeRAMs), enabling the memory devices to have the characteristics of low operating voltage and strong anti-interference capabilities.

[0023] In one possible implementation, the method of doping the dopant element into the ferroelectric layer includes a lamination method, an alloying method, atomic layer deposition (ALD), chemical vapor deposition (CVD), or chemical solution deposition. These methods can better dope the element into the ferroelectric layer.

[0024] In a second aspect, the present application provides a method for preparing a ferroelectric memory, which includes the following steps: forming a first electrode on one side of a substrate; forming a ferroelectric layer, the ferroelectric layer including a doping element and a ferroelectric material, the electronegativity of the doping element being less than that of oxygen; and forming a second electrode on one side of the first electrode.

[0025] Because the elements doped into the anions of the ferroelectric film are less electronegative than oxygen, these anions are more likely to shift under the action of an electric field, making the polarization state more easily flipped. This reduces the coercive electric field of the ferroelectric film and thus reduces the power consumption of the device. At the same time, doping with anions prevents the hysteresis loop from becoming skewed, maintaining a rectangular hysteresis loop and improving the device's anti-interference ability.

[0026] In one possible implementation, a ferroelectric layer is formed between the first electrode and the second electrode. The first electrode, the ferroelectric layer, and the second electrode are stacked in sequence. The ferroelectric layer is made of at least one material selected from the group consisting of doped elements, hafnium oxide-based materials, and / or zirconium oxide-based materials.

[0027] In one possible implementation, a first electrode and an insulating layer are alternately stacked at least one layer to form a stacked structure. A hole, such as a cylindrical hole, is formed in the stacked structure. A second electrode and a ferroelectric layer are sequentially formed within the cylindrical hole from the inside out, such as forming a second electrode cylinder and a ferroelectric layer ring cylinder. A hole, such as a cylindrical hole, is formed in the stacked structure. The hole may or may not penetrate the stacked structure, i.e., the ferroelectric layer and / or the second electrode may or may not contact the substrate.

[0028] In a third aspect, the present application provides a semiconductor device comprising a controller, and the ferroelectric memory as described in the first aspect or the ferroelectric memory prepared by the preparation method of the second aspect; wherein the controller and the ferroelectric memory are electrically connected.

[0029] In a fourth aspect, the present application provides an electronic device comprising a circuit board, and the ferroelectric memory as described in the first aspect and the ferroelectric memory prepared by the preparation method as described in the second aspect; the circuit board and the ferroelectric memory are electrically connected.

[0030] In the present application, compared to the technology of doping cations in the ferroelectric layer, the present application does not need to introduce oxygen vacancies to reduce the coercive electric field of the HZO material, thereby reducing the operating voltage and power consumption of the ferroelectric memory device, and avoiding the reduction of device life due to the accumulation of oxygen vacancies. Compared with the cyclic alternating electric field awakening technology, the doping method of this embodiment does not affect the life of the ferroelectric layer, because the metal binding force of this type of anion is weaker than that of oxygen and the electron affinity is lower than that of oxygen, making it easier to displace under the action of the electric field, and the electric polarization state is easier to flip, achieving the beneficial effect of reducing the coercive electric field and making the hysteresis loop tend to be rectangular. Compared with the method of introducing interface intercalation, the doping method of this embodiment can avoid the hysteresis loop from becoming oblique and deviating from the rectangle, and achieve the effect of strong anti-interference ability of the ferroelectric memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a diagram illustrating an electronic device according to an embodiment of the present invention;

[0032] FIG2a is a schematic structural diagram of a ferroelectric memory provided in an embodiment of the present application;

[0033] FIG2 b is a schematic diagram of a circuit structure of a storage unit provided in an embodiment of the present application;

[0034] FIG2c is a schematic diagram of a circuit structure of a memory array provided in an embodiment of the present application;

[0035] FIG2 d is a schematic diagram of the composition structure of a ferroelectric capacitor provided in this application;

[0036] FIG3 is a schematic structural diagram of a ferroelectric capacitor provided in an embodiment of the present application;

[0037] FIG4 a is a flow chart of a method for preparing a ferroelectric capacitor provided in an embodiment of the present application;

[0038] FIG4 b is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application;

[0039] FIG4 c is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application;

[0040] FIG4 d is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application;

[0041] FIG5 is a schematic structural diagram of another ferroelectric capacitor provided in an embodiment of the present application;

[0042] FIG6 a is a schematic flow chart of another method for preparing a ferroelectric capacitor provided in an embodiment of the present application;

[0043] FIG6 b is a schematic structural diagram of components of a ferroelectric capacitor provided in an embodiment of the present application;

[0044] FIG6 c is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application;

[0045] FIG6 d is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application;

[0046] FIG6e is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application;

[0047] FIG6 f is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application;

[0048] FIG6g is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application;

[0049] FIG6h is a schematic structural diagram of components of another ferroelectric capacitor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] Before introducing the embodiments involved in this application, the technical terms involved in this application are first introduced as follows:

[0051] Ferroelectric phase crystal: The structure of the unit cell makes the centers of positive and negative charges not coincide, resulting in an electric dipole moment, which produces an electric polarization intensity that is not equal to zero, making the crystal have spontaneous polarization, and the direction of the electric dipole moment can be changed by an external electric field, showing characteristics similar to those of a ferromagnet.

[0052] Ferroelectric materials: materials that can maintain spontaneous polarization by aligning their internal electric dipole moment through the application of an electric field, even when the externally applied electric field is removed. In other words, ferroelectrics are materials in which the polarization (polarization) value (or electric field) is semi-permanently retained, even after a constant voltage is applied and the voltage is returned to zero volts.

[0053] Ferroelectric memory: It stores data based on the ferroelectric effect of ferroelectric materials. Ferroelectric memory is expected to become a major competitor to dynamic random access memory (DRAM) due to its advantages such as ultra-high storage density, low power consumption and high speed. The storage unit in ferroelectric memory contains a ferroelectric capacitor, which includes two electrodes and a ferroelectric material, such as a ferroelectric layer, disposed between the two electrodes. Due to the nonlinear characteristics of ferroelectric materials, the dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric layer is flipped is very large, which makes the ferroelectric capacitor smaller than other capacitors. For example, it is much smaller than the capacitor used to store charge in DRAM.

[0054] Electronegativity is a measure of the ability of an element's atoms to attract electrons in a compound. The greater the element's electronegativity, the stronger its ability to attract electrons in the compound. This is also known as relative electronegativity, electronegativity for short, or electronegativity. Electronegativity takes into account both ionization energy and electron affinity, and represents the relative strength of the electron-attracting ability of two atoms when forming a chemical bond. It represents the ability of an element's atoms to attract shared electrons in a molecule.

[0055] The hysteresis loop is a key characteristic parameter of ferroelectric thin films and a crucial indicator of whether a material possesses ferroelectric properties. When a high-voltage AC electric field is applied between the upper and lower electrodes of a ferroelectric, the polarization intensity of the ferroelectric does not change linearly with the electric field, but instead exhibits a hysteresis relationship, known as the hysteresis loop. Measuring the hysteresis loop is a simple and effective method for understanding the properties of ferroelectric thin films. The principle is that when a ferroelectric crystal undergoes spontaneous polarization under the influence of an applied electric field, depolarization fields and strain are generated along with the polarization. To maintain stable polarization, the crystal is divided into many small regions. The electric dipoles in each region align in the same direction, but the orientations of the dipoles vary from region to region. These small regions are called domains, and the boundaries between domains are called domain walls. The presence of domains reduces the strain energy and electrostatic energy of the crystal, while the presence of domain walls increases the energy. The stability of domains is determined by the minimum value of the total free energy. Understanding the domain structure can help us better understand the mechanism of polarization reversal. As the applied electric field changes, the polarization strength of the ferroelectric changes accordingly. When the applied electric field strength is high, the relationship between the polarization strength and the electric field strength is nonlinear. Under the continuous action of the electric field, new domains nucleate and gradually grow, and the domain walls rotate, resulting in polarization rotation.

[0056] Remanent polarization is a key property of ferroelectrics. After a ferroelectric is polarized and the external electric field is removed, the polarization remains constant, not zero. This is called remanent polarization (Pr). Generally speaking, the greater the remanent polarization, the better the ferroelectric performance.

[0057] Coercive field: The reverse electric field required to restore the remanent polarization of a ferroelectric to zero. The coercive field is larger at low temperatures, corresponding to the greater energy required for domain wall reorientation. At higher temperatures, the coercive field decreases. Ferroelectrics of different compositions exhibit varying coercive field strengths, which significantly influence the material's dielectric constant and piezoelectric effect.

[0058] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0059] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0060] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0061] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0062] The transistors involved in the embodiments of the present application may be metal oxide semiconductor (MOS) field effect transistors (hereinafter referred to as MOS transistors). In the embodiments of the present application, the control terminal of the transistor may refer to the gate of the transistor; in one possible embodiment, the first terminal of the transistor may refer to the source, and the second terminal may refer to the drain; in another possible embodiment, the first terminal of the transistor may refer to the drain, and the second terminal may refer to the source.

[0063] FIG1 is an electronic device 200 provided in an embodiment of the present application, wherein the electronic device 200 is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, consumer electronic products include mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products include smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products include car navigation systems, car high-density digital video discs (DVDs), etc. Financial terminal products include automated teller machines (ATMs), self-service terminals, etc. Communication electronic products include communication equipment such as servers, storage devices, radars, and base stations. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device.

[0064] The electronic device 200 includes a bus 205, and a system on chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205. The SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. The ROM 220 can be used to store non-volatile data, such as audio files, video files, etc. The ROM 220 can be a PROM (programmable read-only memory), an EPROM (erasable programmable read-only memory), a flash memory, etc. In addition, the electronic device 200 can also include a communication chip 230 and a power management chip 240. The communication chip 230 can be used to process the protocol stack, or to amplify and filter analog radio frequency signals, or to achieve the above functions simultaneously. The power management chip 240 can be used to power other chips.

[0065] In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing application programs, a graphics processing unit (GPU) 212 for processing image data, and a random access memory (RAM) 213 for caching data. The AP 211, GPU 212, and RAM 213 may be integrated into a single die, or integrated into multiple dies and packaged into a single package structure, such as using 2.5D (dimension), 3D packaging, or other advanced packaging technologies. In one embodiment, the AP 211 and GPU 212 are integrated into one die, and the RAM 213 is integrated into another die. The two dies are packaged into a single package structure to achieve faster inter-die data transfer rates and higher data transfer bandwidth.

[0066] Figure 2a is a schematic diagram of the structure of a ferroelectric memory provided in an embodiment of the present application. The ferroelectric memory 1 can be the RAM 213 shown in Figure 1. Referring to Figure 2a, the ferroelectric memory 1 includes a memory array 11 and a peripheral circuit 12, wherein the peripheral circuit 12 includes one or more circuit structures of a decoder 121, a driver 122, a timing controller 123, a buffer 124 or an input / output driver 125. In one embodiment, the memory array 11 includes a plurality of memory cells 10 arranged in an array, and the memory cell 10 may include a selection transistor and at least one ferroelectric capacitor. Each memory cell 10 can be used to store 1 bit (bit) or multiple bits of data. The memory cell 10 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 10 is electrically connected to the corresponding signal lines (WL, BL, etc.). The memory cell 10 to be read or written in the memory array 11 is selected by receiving a control level output by a control circuit on one or more signal lines, such as word lines WL and bit lines BL, thereby changing the polarization direction of the ferroelectric capacitor in the memory cell 10 and implementing data read and write operations. Decoder 121 is used to decode the address of the memory cell 10. Decoder 121 decodes the received address to determine the memory cell 10 to be accessed. Driver 122 controls the signal line level based on the decoding result generated by decoder 121, thereby enabling access to the specified memory cell 10. Buffer 124 is used to cache read data, for example, using a FIFO (first-in, first-out) buffer. Timing controller 123 controls the timing of buffer 124 and controls driver 122 to drive the signal lines in the memory array 11. Input / output driver 125 drives transmission signals, such as received data signals and transmitted data signals, allowing data signals to be transmitted over long distances. The storage principle of ferroelectric memory (FeRAM) is to change the polarization direction of ferroelectric capacitors through an electric field, thereby storing different amounts of charge to represent different data storage states. Since the polarization direction of ferroelectric capacitors can be maintained even after the electric field is removed, ferroelectric memory is a non-volatile memory. The stored data does not need to be refreshed regularly and can be stored for a long time, thereby significantly reducing power consumption. The above-mentioned storage array 11 can be integrated with one or more circuit structures in the peripheral circuit 12 (i.e., one or more of 121, 122, 123, 124, 125) into a memory chip.

[0067] FIG2 b shows a circuit structure diagram of a memory cell 10 of a FeRAM. As shown in FIG2 b , the memory cell 10 includes at least two ferroelectric capacitors C and a transistor Tr. For example, FIG2 b shows three ferroelectric capacitors (such as ferroelectric capacitor C1, ferroelectric capacitor C2, and ferroelectric capacitor C3 in FIG2 b ). Such a memory cell can be called a 1TnC memory cell. The transistor Tr here can be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0068] In addition, the memory cell 10 further includes wordline (WL), bitline (BL), and plateline (PL) signal lines. In the memory cell 10, a first terminal of transistor Tr is electrically connected to the bitline BL, a control terminal of transistor Tr is electrically connected to the wordline WL, a second terminal of transistor Tr is electrically connected to a first electrode of ferroelectric capacitor C, and a second electrode of ferroelectric capacitor C is electrically connected to the plateline PL. The drain or source of transistor Tr is referred to as the first terminal, and the other terminal is referred to as the second terminal. The control terminal of transistor Tr is referred to as the gate.

[0069] The memory cell 10 shown in FIG2 b can be used to store multiple bits of data, thereby increasing the storage capacity of each memory cell. In particular, the ferroelectric capacitors C share a transistor Tr, thereby reducing the number of transistors in each memory cell 10 and improving storage density.

[0070] By arranging the memory cells 10 shown in FIG. 2 b in an array, a memory array can be obtained, wherein each memory cell 10 has the same circuit structure. For example, the memory array shown in FIG. 2 c exemplifies a memory array including four memory cells: memory cell 101, memory cell 102, memory cell 103, and memory cell 104. Those skilled in the art can design the arrangement and number of memory cells 10 in the memory array based on the storage capacity requirements of the ferroelectric memory. In one embodiment, the memory array can further include more memory cells 10, and these memory cells 10 can be arranged in mutually perpendicular X, Y, and Z directions to form a three-dimensional memory array.

[0071] Figure 2d is a schematic diagram of the composition structure of a ferroelectric capacitor provided by the present application. The ferroelectric capacitor provided by the present application can be applied to the memory cell 10 of the ferroelectric memory of Figures 2a and 2b, and the memory array of the four memory cells of memory cell 101, memory cell 102, memory cell 103 and memory cell 104 of Figure 2c. The ferroelectric memory formed on the substrate includes a plurality of memory cells, each of which includes a ferroelectric capacitor. The ferroelectric capacitor includes: a first electrode, a second electrode and a ferroelectric layer. The ferroelectric memory can be a ferroelectric tunneling junction (FTJ), a ferroelectric field effect transistor (FeFET) and a ferroelectric random access memory (FeRAM). The ferroelectric capacitor is formed on the substrate, and the structure specifically forming the ferroelectric capacitor can be a two-dimensional planar type or a three-dimensional vertical type.

[0072] FIG3 is a schematic diagram of a ferroelectric capacitor structure provided by an embodiment of the present application. The embodiment of the present application provides a ferroelectric capacitor, which can be used in the memory cell 10 of FIG2a and FIG2b, and in the memory array of four memory cells of memory cell 101, memory cell 102, memory cell 103 and memory cell 104 of FIG2c. As shown in FIG3, the ferroelectric capacitor includes a substrate 301, a first electrode 302, a ferroelectric layer 303 and a second electrode 304. The ferroelectric capacitor structure is a two-dimensional metal-ferroelectric thin film-metal (MFM) structure, in which the ferroelectric layer is formed between the first electrode and the second electrode, and there is no gap between the ferroelectric layer and the first electrode and the second electrode. The second electrode, the ferroelectric layer and the first electrode are stacked on the substrate from top to bottom, and the first electrode is in contact with the substrate, or in other words, each layer structure of the first electrode, the ferroelectric layer and the second electrode is arranged parallel to the substrate. The first electrode or the second electrode may be made of TiN, W, Ni, TaN, polysilicon, Ru, or Ir. The material forming the ferroelectric layer may be at least one of hafnium oxide and zirconium oxide.

[0073] Figure 4a is a schematic diagram of a method for preparing a ferroelectric capacitor provided in an embodiment of the present application. The method for preparing the structure is as follows:

[0074] In step 400 , as shown in FIG4 b , a first electrode 302 is formed on a substrate 301 .

[0075] In a possible implementation, a physical vapor deposition (PVD) process, such as magnetron sputtering, is used to deposit a metal on a substrate as a first electrode, for example, a tungsten (W) electrode is deposited on a silicon substrate.

[0076] In another possible implementation, chemical vapor deposition (CVD) is used to deposit metal on a silicon substrate as the first electrode. For example, 50 nm W is deposited as the first electrode by CVD.

[0077] In step 401 , as shown in FIG4 c , a ferroelectric layer 303 is formed on the first electrode 302 .

[0078] In one possible implementation, a ferroelectric material is deposited on the first electrode using atomic layer deposition (ALD), for example, a ferroelectric material hafnium zirconium oxide (HZO) having a hafnium (Hf) to zirconium (Zr) ratio of 1:1 is deposited using ALD to a thickness of 8 nm to form a ferroelectric layer.

[0079] In another possible implementation, the ferroelectric material is deposited using an ALD deposition method, for example, 8 nm Hf and Zr with a ratio of 1:1 are deposited on the W surface. 0.5 Z 0.5 O2 ferroelectric material forms a ferroelectric layer;

[0080] Step 402 : doping elements into the ferroelectric layer 303 .

[0081] In one possible implementation, an element with a weaker electronegativity than oxygen, such as S, is doped using an ALD method. The oxygen source used in this doping method is ozone (O3), which reacts with Hf and Zr precursors attached to the surface to form atomic layers of HfO2 and ZrO2. The sulfur source used is hydrogen sulfide (H2S), which reacts with hafnium and zirconium precursors attached to the surface to form atomic layers of HfS2 and ZrS2. By controlling the deposition order of the HfO2, ZrO2, HfS2, and ZrS2 atomic layers, HfS2 and ZrS2 are uniformly distributed throughout the HZO ferroelectric material.

[0082] In another possible implementation, CVD is used to dope an element with a lower electronegativity than oxygen and / or a lower electron affinity than oxygen, such as S or Se, into the ferroelectric layer. In this embodiment, doping with elements by CVD can improve doping efficiency and yield.

[0083] Step 403, as shown in FIG4d, forms a second electrode 304 on the ferroelectric layer.

[0084] In a possible implementation, an ALD deposition method is used to deposit a metal compound as the second electrode, for example, 50 nm titanium nitride (TiN) is deposited as the second electrode.

[0085] In another possible implementation, a metal compound is deposited as the second electrode using a PVD method, for example, 50 nm TiN is deposited as the second electrode.

[0086] Step 404 , performing crystallization treatment on the ferroelectric layer 303 .

[0087] In one possible implementation, rapid thermal annealing (RTA) is performed on the ferroelectric layer to crystallize the HZO and form a ferroelectric phase.

[0088] In this embodiment, compared with the technology of doping cations in the ferroelectric layer, this embodiment does not need to introduce oxygen vacancies to reduce the coercive electric field of the HZO material, thereby reducing the operating voltage and power consumption of the ferroelectric memory device, and avoiding the reduction of device life due to the accumulation of oxygen vacancies. Compared with the cyclic alternating electric field awakening technology, the doping method of this embodiment does not affect the life of the ferroelectric layer, because the metal binding force of this type of anion is lower than that of oxygen, making it easier to displace under the action of the electric field, and the electric polarization state is easier to flip, achieving the beneficial effect of reducing the coercive electric field and making the hysteresis loop tend to be rectangular. Compared with the method of introducing interface intercalation, the doping method of this embodiment can avoid the hysteresis loop from becoming oblique and deviating from the rectangle, achieving the effect of strong anti-interference ability of the ferroelectric memory device.

[0089] FIG5 is a schematic diagram of another ferroelectric capacitor structure provided in an embodiment of the present application.

[0090] The embodiment of the present application provides a ferroelectric memory, which can be used in the memory cell 10 of Figures 2a and 2b, and in the memory array of four memory cells, namely, memory cell 101, memory cell 102, memory cell 103, and memory cell 104 of Figure 2c. As shown in Figure 4, the ferroelectric memory adopts a 3D stacked structure 500, including a substrate 501, a first electrode 502, an insulating layer 503, a second electrode 504, and a ferroelectric layer 505. The first electrode layer 502 and the insulating layer 503 are alternately stacked in at least one layer, and a hole 506 is provided that penetrates the stacked structure. The second electrode 504 and the ferroelectric layer 505 are sequentially formed in the hole 506 from the inside to the outside. When a three-dimensional stacked capacitor structure is used, three-dimensional stacking can be achieved to improve storage density and storage capacity.

[0091] The first electrode 01 and the second electrode 02 can be made of a metal-containing material, such as a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the first electrode 01 can include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), niobium nitride (NbN), molybdenum nitride (MoN), or a combination thereof. The second electrode 02 can include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO2), silicon (Si), germanium (Ge), silicon germanium (SiGe), or a combination thereof. Furthermore, the materials of the first electrode 01 and the second electrode 02 may be the same or different.

[0092] The ferroelectric layer 03 can be made of hafnium oxide-based or zirconium oxide-based materials. Compared with other ferroelectric materials, the thickness of hafnium oxide-based or zirconium oxide-based ferroelectric capacitors can be miniaturized to ten nanometers or even sub-ten nanometers. In this way, high-density integration and even three-dimensional integration can be achieved, which has a great advantage in building ultra-high-density memory chips. In addition, the preparation process of hafnium oxide-based or zirconium oxide-based ferroelectric capacitors has good compatibility with silicon-based semiconductor processes, so that the ferroelectric capacitors can be made using mature manufacturing processes without increasing manufacturing costs.

[0093] FIG6a is a schematic diagram of another method for preparing a ferroelectric capacitor provided in an embodiment of the present application. The method for preparing the structure is as follows:

[0094] In step 600, as shown in FIG6b, a substrate 501 is deposited. In one possible implementation, the substrate 501 is deposited by plasma enhanced chemical vapor deposition (PECVD), for example, a SiO2 substrate is deposited.

[0095] In step 601, as shown in FIG6c, an insulating layer 503 is formed on a substrate. In a possible implementation, the insulating layer is an oxide, such as a silicon dioxide layer.

[0096] In step 602 , as shown in FIG6 d , a first electrode 502 is formed on the insulating layer. In a possible implementation, metal is deposited by PVD as the first electrode 502 , for example, a W electrode is deposited by PVD.

[0097] In a possible implementation, as shown in FIG6e, a stacked structure of a first electrode 502 and an insulating layer 503 is formed. In a possible implementation, the stacked structure is a stacked structure of oxide and metal, such as a SiO2 / W stacked structure.

[0098] In step 603, as shown in FIG6f , a hole 506 is formed in the stacked structure of the first electrode and the insulating layer. In one possible implementation, the hole 506, such as a cylindrical hole, is formed by dry etching through the stacked structure. It should be noted that in other possible implementations, the hole may not penetrate the stacked structure.

[0099] In step 604, as shown in FIG6g , a ferroelectric layer 505 is formed on the inner wall of the hole. In one possible implementation, atomic layer deposition (ALD) is used to deposit a ferroelectric material, such as hafnium zirconium oxide (HZO), a ferroelectric material having a hafnium (Hf) to zirconium (Zr) ratio of 1:1, to a thickness of 8 nm to form a cylindrical ferroelectric layer.

[0100] Step 605: Doping the ferroelectric layer 505 with an element. In one possible implementation, CVD is used to dope an element with a lower electronegativity than oxygen, such as diffusing S into the ferroelectric layer. In this embodiment, doping with elements using CVD can improve doping efficiency and yield.

[0101] Step 606, as shown in FIG6h, forms a second electrode 504 on the inner wall of the ferroelectric layer.

[0102] In one possible implementation, ALD is used to deposit TiN on the inner wall of the HZO to form a TiN column.

[0103] In another possible implementation, ALD is used to deposit TiN on the inner wall of the HZO to form a TiN ring column, and then CVD is used to fill W in the TiN ring column.

[0104] Step 607 : performing a crystallization process on the ferroelectric layer. In a possible implementation, performing RTA to crystallize the HZO to form a ferroelectric phase.

[0105] In this embodiment, the ferroelectric memory adopts a 3D structure and can be stacked in the vertical direction. Compared with the planar structure, it has an additional integration dimension, a higher degree of integration, and can achieve large-capacity storage.

[0106] The doping elements can be elements other than oxygen in Group VI, such as sulfur S (electronegativity of 2.58), selenium Se (electronegativity of 2.48) or tellurium Te (2.10). The doping elements are elements other than oxygen in Group VI. The anions of such elements are chemically closer to oxygen O than those in non-Group VI, and are more likely to produce ferroelectric phases. The doping elements are mainly elements other than oxygen in Group VI, such as sulfur S, selenium Se, and tellurium Te. The doping elements can be one or a combination of multiple elements. For example, sulfur S can be doped alone, or sulfur S and selenium Se can be doped simultaneously, or sulfur S and tellurium Te can be doped simultaneously, or selenium Se and tellurium Te can be doped simultaneously, or sulfur S, selenium Se, and tellurium Te can be doped simultaneously.

[0107] Because the elements doped into the anions of the ferroelectric film are less electronegative than oxygen, these anions are more likely to shift under the action of an electric field, making the polarization state more easily flipped. This reduces the coercive electric field of the ferroelectric film and thus reduces the power consumption of the device. At the same time, doping with anions prevents the hysteresis loop from becoming skewed, maintaining a rectangular hysteresis loop and improving the device's anti-interference ability.

[0108] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0109] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A ferroelectric memory, characterized in that: include, substrate; A plurality of memory cells are formed on the substrate, each of the memory cells comprises a ferroelectric capacitor; the ferroelectric capacitor comprises: a first electrode, a second electrode and a ferroelectric layer; the ferroelectric layer comprises a ferroelectric material and a doping element; the electronegativity of the doping element is less than that of oxygen.

2. The ferroelectric memory according to claim 1, wherein The doping element includes at least one of sulfur (S), selenium (Se) or tellurium (Te).

3. The ferroelectric memory according to claim 1 or 2, wherein: The ferroelectric layer is formed between the first electrode and the second electrode; the first electrode, the ferroelectric layer and the second electrode are stacked in sequence on the substrate.

4. The ferroelectric memory according to claim 1 or 2, wherein: The ferroelectric memory also includes an insulating layer, and the first electrode and the insulating layer are alternately stacked at least one layer and arranged on the substrate to obtain a stacked structure; a hole is formed in the stacked structure, a ferroelectric layer is formed on the inner wall of the hole, and a second electrode is formed on the inner wall of the ferroelectric layer.

5. The ferroelectric memory according to any one of claims 1 to 4, characterized in that: The substrate is formed of materials including silicon, germanium, gallium nitride, and gallium arsenide. The first electrode or the second electrode is formed of materials including TiN, W, Ni, TaN, polysilicon, Ru, or Ir.

6. The ferroelectric memory according to any one of claims 1 to 5, characterized in that: The ferroelectric material includes hafnium oxide and / or zirconium oxide.

7. The ferroelectric memory according to any one of claims 1 to 6, wherein: The ferroelectric memory includes a ferroelectric tunneling junction (FTJ), a ferroelectric field effect transistor (FeFET) and a ferroelectric random access memory (FeRAM).

8. The ferroelectric memory according to any one of claims 1 to 7, wherein: Methods for doping the doping element into the ferroelectric layer include a lamination method, an alloy method, atomic layer deposition ALD, chemical vapor deposition CVD, or chemical solution deposition.

9. A method for preparing a ferroelectric memory, characterized in that: include: forming a first electrode on one side of the substrate; forming a ferroelectric layer, the ferroelectric layer comprising a doping element and a ferroelectric material, wherein the electronegativity of the doping element is less than that of oxygen; A second electrode is formed on one side of the first electrode.

10. The method for preparing a ferroelectric memory according to claim 9, wherein: A ferroelectric layer is formed between the first electrode and the second electrode. The first electrode, the ferroelectric layer and the second electrode are stacked in sequence. The ferroelectric layer is made of doped elements, hafnium oxide-based materials and / or zirconium oxide-based materials.

11. The method for preparing a ferroelectric memory according to claim 9, wherein: The ferroelectric memory also includes an insulating layer, and the first electrode and the insulating layer are alternately stacked at least one layer and arranged on the substrate to obtain a stacked structure; a hole is formed in the stacked structure, a ferroelectric layer is formed on the inner wall of the hole, and a second electrode is formed on the inner wall of the ferroelectric layer.

12. A semiconductor device, characterized in that: It comprises a controller and the ferroelectric memory according to any one of claims 1 to 8 or the ferroelectric memory prepared by the preparation method of the ferroelectric memory according to any one of claims 9 to 11; wherein the controller and the ferroelectric memory are electrically connected.

13. An electronic device, characterized in that: It comprises a circuit board and a ferroelectric memory according to any one of claims 1 to 8 or a ferroelectric memory prepared by the preparation method of a ferroelectric memory according to any one of claims 9 to 11; wherein the circuit board and the ferroelectric memory are electrically connected.

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