Diagnostic circuit and diagnostic method

Abstract

This diagnostic circuit includes: a plurality of comparison circuits which detect whether a detected value is within a predetermined normal range; a first determining circuit which determines that the detected value is normal when all comparison results of the plurality of comparison circuits are within the normal range; a second determining circuit which determines that the detected value is normal when at least one of the comparison results of the plurality of comparison circuits is within the normal range; a test signal output circuit that outputs the same test signal simulating a detected value outside the normal range to the plurality of comparison circuits; and an abnormality determining circuit which determines that an abnormality has occurred in the plurality of comparison circuits when the determination result of the first determining circuit and the determination result of the second determining circuit differ when the test signal is input to the plurality of comparison circuits.

Description

Diagnostic circuit and diagnostic method

[0001] The present invention relates to a diagnostic circuit and a diagnostic method.

[0002] Output monitoring mechanisms that monitor the output of a sensor to detect specific conditions are widely used. Because malfunctions in the output monitoring mechanism may occur, testing of the output monitoring mechanism is required. Patent Document 1 discloses a motor control device that includes a voltage detection means that detects a voltage that serves as a substitute for the current flowing through a motor inverter, an overcurrent detection means that compares the detected voltage from the voltage detection means with a reference voltage for overcurrent determination, and an overcurrent determination means that determines whether an overcurrent exists based on a detection signal from the overcurrent detection means. The motor control device also includes an overcurrent inspection means that sends a test voltage equal to or higher than the reference voltage to the overcurrent detection means instead of the detected voltage when the motor is not rotating, and an abnormality diagnosis means that determines that an abnormality has occurred in the overcurrent detection means when the overcurrent determination means determines that no overcurrent exists based on the test voltage from the overcurrent inspection means.

[0003] JP 2010-279125 A

[0004] In the invention described in Patent Document 1, it takes time for the output monitoring mechanism to detect an abnormality.

[0005] A diagnostic circuit according to a first aspect of the present invention comprises a plurality of comparison circuits that detect whether a detection value is within a predetermined normal range; a first judgment circuit that judges that a detection value is normal when all of the comparison results of the plurality of comparison circuits are within the normal range; a second judgment circuit that judges that a detection value is normal when at least one of the comparison results of the plurality of comparison circuits is within the normal range; a test signal output circuit that simultaneously outputs test signals that simulate detection values ​​outside the normal range to the plurality of comparison circuits; and an abnormality judgment circuit that judges that an abnormality has occurred in the plurality of comparison circuits when the judgment result of the first judgment circuit and the judgment result of the second judgment circuit differ when the test signals are input to the plurality of comparison circuits. A diagnostic method according to a second aspect of the present invention is a diagnostic method executed by a diagnostic circuit connected to a plurality of comparison circuits that detect whether a detection value is within a predetermined normal range and that can indirectly detect the output of the comparison circuits, and includes: obtaining a logical sum of the comparison results of the plurality of comparison circuits; obtaining a logical product of the comparison results of the plurality of comparison circuits; simultaneously outputting test signals that simulate detection values ​​outside the normal range to the plurality of comparison circuits; and determining that an abnormality has occurred in the plurality of comparison circuits if the logical sum and the logical product differ.

[0006] According to the present invention, an abnormality in a comparison circuit can be easily detected.

[0007] A diagram of the diagnostic circuit. A time series diagram showing an example of the operation of the first determination circuit and the second determination circuit when normal. A time series diagram showing an example of the operation of the first determination circuit and the second determination circuit when a high-fixed abnormality occurs. A time series diagram showing an example of the operation of the first determination circuit and the second determination circuit when a low-fixed abnormality occurs. A diagram showing the identification of a high-fixed state of the first comparison circuit. A diagram showing the identification of a low-fixed state of the first comparison circuit.

[0008] -First Embodiment- A first embodiment of a diagnostic circuit will be described below with reference to FIGS.

[0009] Fig. 1 is a diagram showing the configuration of the diagnostic circuit 1. In Fig. 1, white circles indicate connections between wires. In other words, intersections between wires without white circles indicate that they are not electrically connected.

[0010] The diagnostic circuit 1 includes a calculation device 10, a first comparison circuit 21, a second comparison circuit 22, a third comparison circuit 23, a first judgment circuit 31, a second judgment circuit 32, and a reference voltage circuit 40. The diagnostic circuit 1 monitors the outputs of a first sensor 91, a second sensor 92, and a third sensor 93. However, the diagnostic circuit 1 can also perform self-diagnosis, as described below. That is, the diagnostic circuit 1 has a sensor monitoring mode and a self-diagnosis mode. The operating mode of the diagnostic circuit 1 may be specified externally, or the diagnostic circuit 1 may monitor the outputs of the first sensor 91, etc. and switch the operating mode autonomously.

[0011] Each of the first sensor 91, the second sensor 92, and the third sensor 93 is a sensor IC, such as a current sensor, that outputs a detection result as a voltage signal. For example, each sensor detects the current of each phase in the three-phase output of the power conversion device. The output of the first sensor 91 is input to the first comparison circuit 21. The output of the second sensor 92 is input to the second comparison circuit 22. The output of the third sensor 93 is input to the third comparison circuit 23.

[0012] The reference voltage circuit 40 is configured with resistors interposed between a voltage source and ground. The reference voltage circuit 40 outputs voltages stepped down by the resistors as a first reference voltage 41 and a second reference voltage 42. In the following description, the first reference voltage 41 is assumed to be higher than the second reference voltage 42. For example, there are three resistors, and the three resistance values ​​may be equal or different. For example, if the voltage source is 5.0 V and the three resistance values ​​from the voltage source to ground are 10 kΩ, 80 kΩ, and 10 kΩ, the first reference voltage 41 is 4.5 V and the second reference voltage 42 is 0.5 V.

[0013] In this embodiment, the range from the first reference voltage 41 to the second reference voltage 42 is called a "normal range voltage," a voltage higher than the first reference voltage 41 is called an "overvoltage," and a voltage lower than the second reference voltage 42 is called an "undervoltage." In addition, the overvoltage and undervoltage are collectively called an "out-of-range voltage."

[0014] Each of the first comparison circuit 21, the second comparison circuit 22, and the third comparison circuit 23 is a window comparator. Because the first comparison circuit 21, the second comparison circuit 22, and the third comparison circuit 23 have similar functions and configurations, the first comparison circuit 21 will be described here as a representative of the three. The first comparison circuit 21 outputs a high signal when the output V1 of the first sensor 91 is within a normal voltage range, i.e., within the range between the first reference voltage 41 and the second reference voltage 42. The first comparison circuit 21 outputs a low signal when the output V1 of the first sensor 91 is outside the normal voltage range. The normal voltage range can also be considered a voltage between a predetermined upper limit and a predetermined lower limit. The first comparison circuit 21 may be composed of, for example, two operational amplifiers. The first operational amplifier receives the output V1 of the first sensor 91 and the first reference voltage 41, and the second operational amplifier receives the output V1 of the first sensor 91 and the second reference voltage 42.

[0015] The second comparison circuit 22 outputs High when the output V2 of the second sensor 92 is within the normal voltage range, and outputs Low when the output V2 is not within the normal voltage range. The third comparison circuit 23 outputs High when the output V3 of the third sensor 93 is within the normal voltage range, and outputs Low when the output V3 is not within the normal voltage range.

[0016] The first determination circuit 31 is a logical product circuit that outputs the logical product of the first comparison circuit 21 to the third comparison circuit 23. The first determination circuit 31 has three diodes corresponding to the first comparison circuit 21 to the third comparison circuit 23, respectively, and a pull-up circuit. The anodes of the three diodes are connected together, and the pull-up circuit is further connected to this common connection point. The first determination circuit 31 outputs HIGH when the outputs of the first comparison circuit 21 to the third comparison circuit 23 are all HIGH, and outputs LOW when even one output is LOW. The output of the first determination circuit 31 is input to the first input unit 11. Hereinafter, the output of the first determination circuit 31 will be referred to as the first determination result R1.

[0017] The second determination circuit 32 is a logical sum circuit that outputs the logical sum of the first comparison circuit 21 to the third comparison circuit 23. The second determination circuit 32 has three diodes corresponding to the first comparison circuit 21 to the third comparison circuit 23, respectively, and a pull-up circuit. The cathodes of the three diodes are connected together, and the pull-up circuit is connected to the anodes of the three diodes. The second determination circuit 32 outputs HIGH when at least one of the first comparison circuit 21 to the third comparison circuit 23 is HIGH, and outputs LOW when all outputs are LOW. The output of the second determination circuit 32 is input to the second input unit 12. Hereinafter, the output of the second determination circuit 32 will be referred to as the second determination result R2.

[0018] The arithmetic device 10 includes a first input unit 11, a second input unit 12, an abnormality determination unit 13, and a test output unit 14. The arithmetic device 10 is, for example, a microcomputer. The first input unit 11 and the second input unit 12 are AD converters or digital input interfaces. The first input unit 11 and the second input unit 12 output the input signals to the abnormality determination unit 13 as a first determination result R1 and a second determination result R2.

[0019] The test output unit 14 simultaneously outputs a first test signal 141 that is input to the first comparison circuit 21, a second test signal 142 that is input to the second comparison circuit 22, and a third test signal 143 that is input to the third comparison circuit 23. Each of the first test signal 141 to the third test signal 143 has the same voltage at each time. The test output unit 14 operates based on an operation command from the abnormality determination unit 13.

[0020] The abnormality determination unit 13 determines that the system is normal when the signal levels of the first determination result R1 and the second determination result R2 match, and determines that the system is abnormal when the signal levels of the first determination result R1 and the second determination result R2 do not match. The abnormality determination unit 13 does not output an operation command to the test output unit 14 in the sensor monitoring mode, but outputs an operation command to the test output unit 14 in the self-diagnosis mode. This operation command switches the output voltage sequentially between three voltages: normal range voltage, overvoltage, and undervoltage. The order of output is not important. The abnormality determination unit 13 determines that the system is normal when the first determination result R1 and the second determination result R2 match in all cases where the output of the test output unit 14 is normal range voltage, overvoltage, or undervoltage.

[0021] The abnormality determination unit 13 outputs the determination result by some means. In particular, the abnormality determination unit 13 outputs the result when it determines that an abnormality exists. For example, if a signal line (not shown) is connected to the diagnostic circuit 1, the abnormality detection may be output using the signal line, or an operation command resulting from the abnormality detection may be output to a device external to the diagnostic circuit 1. For example, assume that the first sensor 91 or the like is measuring a power conversion device mounted on a vehicle. Under this assumption, when the abnormality determination unit 13 detects an abnormality, the abnormality determination unit 13 may output a command to a control unit of the vehicle to perform a fallback operation that does not require the power conversion device.

[0022] 2 to 4 are time-series diagrams showing examples of operation of the first determination circuit 31 and the second determination circuit 32. FIG. 2 shows an example of operation when the circuit is normal, FIG. 3 shows an example of operation when a high-level fixed abnormality occurs, and FIG. 4 shows an example of operation when a low-level fixed abnormality occurs. In each diagram, the upper row shows the test signal, the middle row shows the output of the first determination circuit 31, and the lower row shows the output of the second determination circuit 32. In each example shown in each diagram, the test output unit 14 inputs the same signal to each comparison circuit. The first reference voltage 41 output by the reference voltage circuit 40 is 4.5 V, and the second reference voltage 42 is 0.5 V. Therefore, when the output of each sensor is within the range of 0.5 V to 4.5 V, it is determined to be normal. The diagrams show time-series changes from time t0 to time t5. The output voltage of the test output unit 14 is 3 V from time t0 to time t1, 5 V from time t1 to time t2, 3 V from time t2 to time t3, 0 V from time t3 to time t4, and 3 V from time t4 to time t5. That is, from time t1 to t2, an abnormal state occurs in which the voltage exceeds the upper limit, and from time t3 to time t4, an abnormal state occurs in which the voltage falls below the lower limit.

[0023] When the circuit shown in FIG. 2 is normal, all of the first comparison circuit 21 to the third comparison circuit 23 are normal. Therefore, from time t0 to time t1, from time t2 to time t3, and from time t4 to time t5, all three comparison circuits output High, so that OUT1, which is the logical product, and OUT2, which is the logical sum, are both High. From time t1 to time t2 and from time t3 to time t4, all three comparison circuits output Low, so that OUT1, which is the logical product, and OUT2, which is the logical sum, are both Low. Therefore, in the example shown in FIG. 2, the first determination result R1 and the second determination result R2 always match, so the abnormality determination unit 13 always determines that the circuit is normal.

[0024] During the stuck-high abnormality shown in Figure 3, two comparison circuits operate normally, but the output of one comparison circuit is fixed at high and always outputs high. In this case, one comparison circuit always outputs high, so the second judgment result R2, which is the logical sum of the three, is always high. The other two comparison circuits are normal, so their outputs are low from time t1 to time t2 and from time t3 to time t4, and the first judgment result R1, which is the logical product of the three, changes in the same way as in Figure 2. Therefore, in the example shown in Figure 3, the first judgment result R1 and the second judgment result R2 do not match, so the abnormality judgment unit 13 judges that an abnormality has occurred.

[0025] During the fixed-low abnormality shown in Figure 4, two comparison circuits operate normally, but the output of one comparison circuit is fixed at low and always outputs low. In this case, one comparison circuit always outputs low, so the first determination result R1, which is the logical product of the three, is always low. The other two comparison circuits are normal, so their outputs are high from time t0 to time t1, from time t2 to time t3, and from time t4 to time t5, and the second determination result R2, which is the logical sum of the three, changes in the same way as in Figure 2. Therefore, in the example shown in Figure 4, the first determination result R1 and the second determination result R2 do not match, so the abnormality determination unit 13 determines that an abnormality has occurred.

[0026] The first embodiment described above provides the following advantageous effects: (1) The diagnostic circuit 1 includes the first comparison circuit 21 to the third comparison circuit 23 that detect whether a detected value is within a predetermined normal range, the first determination circuit 31 that determines that a value is normal when all of the comparison results of the first comparison circuit 21 to the third comparison circuit 23 are within the normal range, the second determination circuit 32 that determines that a value is normal when at least one of the comparison results of the first comparison circuit 21 to the third comparison circuit 23 is within the normal range, the test output unit 14 that simultaneously outputs test signals that simulate detected values ​​outside the normal range to the first comparison circuit 21 to the third comparison circuit 23, and the abnormality determination unit 13 that determines that an abnormality has occurred in the plurality of comparison circuits when the determination result of the first determination circuit 31 and the determination result of the second determination circuit 32 differ when the test signals are input to the first comparison circuit 21 to the third comparison circuit 23. Therefore, regardless of the number of comparison circuits, abnormality detection of the comparison circuits can be completed simply by comparing the judgment result of the first judgment circuit 31, which is a logical product, with the judgment result of the second judgment circuit 32, which is a logical sum, which is simple and can be completed in a short time.

[0027] For example, anomalies can be detected by individually checking the outputs of multiple comparison circuits. However, this method requires the same number of checking circuits as the number of comparison circuits, and has the disadvantage that the number of checks, i.e., the processing load, increases with the number of comparison circuits. However, with the method of this embodiment, anomaly detection can be completed in a short time, regardless of the number of comparison circuits.

[0028] (2) The first determination circuit 31 is a logical product circuit including a plurality of diodes. The anodes of the plurality of diodes are commonly connected to a pull-up circuit. Therefore, the first determination circuit 31 can be realized at low cost.

[0029] (3) The second determination circuit 32 is a logical OR circuit including a plurality of diodes. The cathodes of the plurality of diodes are connected together, and the anodes of the plurality of diodes are connected to a pull-up circuit. This allows the second determination circuit 32 to be implemented at low cost.

[0030] (Variation 1) In the above-described embodiment, each comparison circuit is a window comparator. However, each comparison circuit may be a comparator. In this case, each comparison circuit can be configured with a single operational amplifier, and the reference voltage circuit 40 only needs to be able to output a single reference voltage. This reference voltage may be used as either an upper limit value or a lower limit value.

[0031] (Modification 2) In the above-described embodiment, the diagnostic circuit 1 includes three comparison circuits. However, the number of comparison circuits included in the diagnostic circuit 1 may be two or more, and there is no upper limit.

[0032] (Variation 3) In the above-described embodiment, the diagnostic circuit 1 includes the reference voltage circuit 40. However, the diagnostic circuit 1 may not include the reference voltage circuit 40, and the first reference voltage 41 and the second reference voltage 42 may be input from outside the diagnostic circuit 1.

[0033] (Modification 4) The first determination circuit 31 and the second determination circuit 32 may be realized using logic circuits such as AND elements and OR elements.

[0034] (Variation 5) When it is determined that an abnormality has occurred in any of the comparison circuits, the abnormality determination unit 13 may cause the test output unit 14 to output a cause identification pattern signal for identifying the comparison circuit in which the abnormality has occurred. The cause identification pattern signal is a signal that outputs a test signal simulating a detection value within a normal range to a target comparison circuit, which is a selected portion of the multiple comparison circuits, and outputs a test signal simulating a detection value outside the normal range to comparison circuits other than the target comparison circuit, thereby changing the target comparison circuit in order.

[0035] For example, by applying a normal range voltage to two of the three comparator circuits and an out-of-range voltage to the remaining comparator circuit, and sequentially changing the comparator circuit to which the out-of-range voltage is applied, it is possible to identify a comparator circuit that is stuck at low.Furthermore, by applying a normal range voltage to one of the three comparator circuits and an out-of-range voltage to the remaining two comparator circuits, and sequentially changing the comparator circuit to which the normal range voltage is applied, it is possible to identify a comparator circuit that is stuck at high.

[0036] FIG. 5 is a diagram illustrating how the first comparison circuit 21 is identified as being stuck at a high level. FIG. 5 shows the voltages output by the test output unit 14 to each comparison circuit, the outputs of the comparison circuits, the outputs of the judgment circuits, and the judgment results of the abnormality judgment unit 13 for each of six tests. The test output unit 14 outputs six test signal patterns, Tests 1 to 6, based on instructions from the abnormality judgment unit 13. Tests 1 to 3 are for detecting a stuck-high level, and Tests 4 to 6 are for detecting a stuck-low level. In Tests 1 to 3, a normal range voltage is applied to two comparison circuits, and an out-of-range voltage is applied to one comparison circuit. In Tests 4 to 6, a normal range voltage is applied to one comparison circuit, and an out-of-range voltage is applied to two comparison circuits. In the example shown in FIG. 5, the out-of-range voltage is set to 0 V, but it may also be set to an excessive voltage, such as 5 V.

[0037] 5, the output of the first comparison circuit 21 in tests 1, 4, and 5, which are shaded, is different from the intended output due to being stuck at High. In each test, an out-of-range voltage is input to at least one comparison circuit, so the output of the first judgment circuit 31 should always be Low. However, because the first comparison circuit 21 is stuck at High, the output of the first judgment circuit 31 is High only in test 1. The abnormality judgment unit 13 outputs an operation command to the test output unit 14 and knows the input voltage to each comparison circuit in each test, so it can identify from the abnormality judgment results that the first comparison circuit 21 is stuck at High.

[0038] Fig. 6 is a diagram showing how to identify a low-level fixation in the first comparison circuit 21. The content of the six tests shown in Fig. 6 is the same as that in Fig. 5, and therefore a description thereof will be omitted. Fig. 6 shows an example in which a low-level fixation has occurred in the first comparison circuit 21, and the outputs of the first comparison circuit 21 in the shaded tests 2, 3, and 6 are different from the intended outputs due to the low-level fixation.

[0039] According to this fifth modification, the following advantageous effects can be obtained. (4) When it is determined that an abnormality has occurred in a comparison circuit, the abnormality determination unit 13 causes the test output unit 14 to output a cause-identification pattern signal. The cause-identification pattern signal is a signal that outputs a test signal simulating a detection value within a normal range to a target comparison circuit, which is one comparison circuit selected from the plurality of comparison circuits, and outputs test signals simulating detection values ​​outside the normal range to comparison circuits other than the target comparison circuit, thereby switching the target comparison circuit in sequence. Therefore, the abnormality determination unit 13 can determine which comparison circuit has an abnormality and whether it is fixed high or fixed low.

[0040] (Variation 6) In the above-described embodiment, the test output unit 14 simultaneously applied the same voltage to the three comparison circuits 21 to 23 in order to detect abnormalities in the first comparison circuit 21 to the third comparison circuit 23. However, the voltages input to the three comparison circuits do not have to be exactly the same. That is, as long as the voltage range is the same, for example, if the normal range voltage is 0.5 V to 4.5 V, 1.0 V, 1.5 V, and 2.0 V may be input to the first comparison circuit 21 to the third comparison circuit 23 at one timing, and 4.8 V, 4.9 V, and 5.0 V may be input at another timing.

[0041] The above-described embodiments and modifications may be combined with each other. Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments conceivable within the scope of the technical concept of the present invention are also included within the scope of the present invention.

[0042] 1: Diagnostic circuit 10: Arithmetic unit 11: First input unit 12: Second input unit 13: Abnormality determination unit 14: Test output unit 21: First comparison circuit 22: Second comparison circuit 23: Third comparison circuit 31: First determination circuit 32: Second determination circuit 40: Reference voltage circuit

Claims

1. A diagnostic circuit comprising: a plurality of comparison circuits that detect whether a detected value is within a predetermined normal range; a first judgment circuit that judges that a detection value is normal when all of the comparison results of the plurality of comparison circuits are within the normal range; a second judgment circuit that judges that a detection value is normal when at least one of the comparison results of the plurality of comparison circuits is within the normal range; a test output unit that simultaneously outputs test signals that simulate detection values ​​outside the normal range to the plurality of comparison circuits; and an abnormality judgment unit that judges that an abnormality has occurred in the plurality of comparison circuits when the judgment result of the first judgment circuit and the judgment result of the second judgment circuit differ when the test signals are input to the plurality of comparison circuits.

2. A diagnostic circuit according to claim 1, wherein the first determination circuit is a logical product circuit including a plurality of diodes, and the anodes of the plurality of diodes are connected in common and then connected to a pull-up circuit.

3. A diagnostic circuit according to claim 1, wherein the second determination circuit is a logical OR circuit including a plurality of diodes, the cathodes of the plurality of diodes being connected together, and the anodes of the plurality of diodes being connected to a pull-up circuit.

4. A diagnostic circuit according to claim 1, wherein, when it is determined that an abnormality has occurred in the plurality of comparison circuits, the abnormality determination section causes the test output section to output a pattern signal for identifying a cause, the pattern signal for identifying a cause being a pattern signal in which a test signal simulating a detection value within the normal range is output to a target comparison circuit, which is a selected portion of the plurality of comparison circuits, and a test signal simulating a detection value outside the normal range is output to comparison circuits other than the target comparison circuit, thereby changing the target comparison circuits in order.

5. A diagnostic method performed by a diagnostic circuit connected to a plurality of comparison circuits that detect whether a detection value is within a predetermined normal range and that can indirectly detect the output of the comparison circuits, the diagnostic method comprising: obtaining a logical sum of the comparison results of the plurality of comparison circuits; obtaining a logical product of the comparison results of the plurality of comparison circuits; simultaneously outputting test signals that simulate detection values ​​outside the normal range to the plurality of comparison circuits; and determining that an abnormality has occurred in the plurality of comparison circuits if the logical sum and the logical product differ.

Images