Semiconductor module and power conversion device

Abstract

The purpose of the present invention is to provide a technique with which it is possible to reduce thermal stress with respect to temperature change in a semiconductor module. This semiconductor module comprises: a first semiconductor device having a package for sealing a semiconductor element, as well as having a P electrode and an N electrode protruding from the package; a second semiconductor device having a package for sealing the semiconductor element, as well as having a P electrode and an N electrode protruding from the package, the second semiconductor device being arranged adjacent to the first semiconductor device so that the P electrode and the N electrode of the second semiconductor device are mirror-symmetric to the P electrode and the N electrode of the first semiconductor device; a P bus bar for connecting the P electrodes of the first semiconductor device and the second semiconductor device; and an N bus bar for connecting the N electrodes of the first semiconductor device and the second semiconductor device. The P bus bar and the N bus bar partially overlap in top view.

Description

Semiconductor module and power conversion device

[0001] The present disclosure relates to a semiconductor module and a power conversion device.

[0002] Power semiconductor devices used in inverters and the like may be connected in parallel when used in large current applications. For example, Patent Document 1 discloses a structure in which the positive and negative terminals corresponding to one circuit block and the positive and negative terminals corresponding to the other circuit block are arranged in mirror symmetry in order to reduce variations in inductance between the parallel-connected circuit blocks.

[0003] Japanese Patent Application Laid-Open No. 2014-225706

[0004] However, in the technology described in Patent Document 1, multiple circuit blocks are arranged in mirror symmetry within a single package in a semiconductor module, which causes the package to become larger and increases thermal stress due to temperature changes.

[0005] Therefore, an object of the present disclosure is to provide a technique capable of reducing thermal stress due to temperature changes in a semiconductor module.

[0006] The semiconductor module according to the present disclosure comprises: a first semiconductor device having a package that encapsulates a semiconductor element and a P-electrode and an N-electrode protruding from the package; a second semiconductor device having a package that encapsulates a semiconductor element and a P-electrode and an N-electrode protruding from the package, the second semiconductor device being arranged adjacent to the first semiconductor device so that the P-electrode and the N-electrode are mirror-symmetric to the P-electrode and the N-electrode of the first semiconductor device; a P-bus bar connecting the P-electrodes of the first semiconductor device and the second semiconductor device; and an N-bus bar connecting the N-electrodes of the first semiconductor device and the second semiconductor device, the P-bus bar and the N-bus bar partially overlapping when viewed from above.

[0007] According to the present disclosure, since the first semiconductor device and the second semiconductor device each having a built-in semiconductor element are arranged adjacent to each other, the package dimensions of each semiconductor device can be made smaller than when all the semiconductor elements are built into a single package, thereby reducing thermal stress due to temperature changes.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] Fig. 10 is a top view of a semiconductor module according to a first embodiment. Fig. 11 is a top view showing an internal layout of the semiconductor module according to the first embodiment. Fig. 12 is a diagram for comparing voltage waveforms at the time of switching on. Fig. 13 is a top view of a semiconductor module according to a second embodiment. Fig. 14 is a top view of a semiconductor module according to a third embodiment. Fig. 15 is a top view of a semiconductor module according to a fourth embodiment. Fig. 16 is a top view of a semiconductor module according to a fifth embodiment. Fig. 17 is a cross-sectional view showing a state in which a heat sink is fixed to the semiconductor module according to the fifth embodiment. Fig. 18 is a top view of a semiconductor module according to a sixth embodiment. Fig. 19 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to a seventh embodiment is applied.

[0010] First Preferred Embodiment A first preferred embodiment will be described below with reference to the drawings. Fig. 1 is a top view of a semiconductor module 202 according to the first preferred embodiment.

[0011] 1, the semiconductor module 202 includes a first semiconductor device 10, a second semiconductor device 11, a P bus bar 20, an N bus bar 21, and an AC bus bar 22. The second semiconductor device 11 is disposed adjacent to the first semiconductor device 10. In FIG. 1, the first semiconductor device 10 is disposed on the left side, and the second semiconductor device 11 is disposed on the right side.

[0012] The first semiconductor device 10 includes a P-electrode 4, an N-electrode 5, an AC terminal 6, a P-side control terminal 7, an N-side control terminal 8, and a package 9. The package 9 is formed in a quadrangular shape (more specifically, a rectangular shape) when viewed from above, and is made of, for example, epoxy resin or silicone gel. The P-electrode 4, the N-electrode 5, and the N-side control terminal 8 protrude from a first side of the package 9. The AC terminal 6 and the P-side control terminal 7 protrude from a second side of the package 9 that faces the first side. Here, the first side is the upper short side in FIG. 1 , and the second side is the lower short side in FIG. 1 .

[0013] The second semiconductor device 11, like the first semiconductor device 10, includes a P-electrode 4, an N-electrode 5, an AC terminal 6, a P-side control terminal 7, an N-side control terminal 8, and a package 9, but the arrangement of the P-electrode 4, the N-electrode 5, the N-side control terminal 8, the AC terminal 6, and the P-side control terminal 7 is different from that of the first semiconductor device 10. Only the differences will be described here.

[0014] The P-electrode 4, N-electrode 5, and N-side control terminal 8 of the second semiconductor device 11 are arranged in mirror symmetry with the P-electrode 4, N-electrode 5, and N-side control terminal 8 of the first semiconductor device 10 with respect to the boundary line A. The P-electrode 4, N-electrode 5, and N-side control terminal 8 are arranged on the first side of the package 9 of the first semiconductor device 10 and the second semiconductor device 11 in the order of N-side control terminal 8, N-electrode 5, and P-electrode 4, along a direction approaching the other adjacently arranged semiconductor device. Therefore, the P-electrodes 4 of the first semiconductor device 10 and the second semiconductor device 11 are close to each other.

[0015] Furthermore, the AC terminal 6 and P-side control terminal 7 of the second semiconductor device 11 are arranged in mirror symmetry with the AC terminal 6 and P-side control terminal 7 of the first semiconductor device 10 with respect to the boundary line A. The AC terminal 6 and P-side control terminal 7 are arranged in this order on the second side of the package 9 of the first semiconductor device 10 and the second semiconductor device 11, along a direction approaching the other adjacently arranged semiconductor device. Therefore, the P-side control terminals 7 of the first semiconductor device 10 and the second semiconductor device 11 are close to each other.

[0016] This arrangement allows the N-side control terminal 8 and the N-electrode 5, and the AC terminal 6 and the P-side control terminal 7 to be disposed close to each other. As a result, the short sides of the packages 9 of the first semiconductor device 10 and the second semiconductor device 11 can be shortened, thereby enabling the semiconductor module 202 to be made smaller.

[0017] The P bus bar 20 connects the P electrodes 4 of the first semiconductor device 10 and the second semiconductor device 11 to each other. The P bus bar 20 has a straight portion 20a that is a main wiring extending parallel to the direction in which the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacent to each other, and a first connection portion 20b that connects the P electrodes 4 to the straight portion 20a. The N bus bar 21 is arranged below the P bus bar 20 and connects the N electrodes 5 of the first semiconductor device 10 and the second semiconductor device 11 to each other. The N bus bar 21 has a straight portion (not shown) that is a main wiring extending parallel to the direction in which the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacent to each other, and a second connection portion 21b that connects the N electrodes 5 to the straight portion.

[0018] The P bus bar 20 and the N bus bar 21 partially overlap in top view. Specifically, in order to minimize the inductance of the path to the smoothing capacitor (not shown) in the first semiconductor device 10 and the path to the smoothing capacitor (not shown) in the second semiconductor device 11, the straight portion 20a of the P bus bar 20 and the straight portion of the N bus bar 21 are arranged to overlap in top view, and an insulating layer (not shown) is arranged between them. Furthermore, the first semiconductor device 10 and the second semiconductor device 11 are connected in parallel so that the overlapping portions of the P bus bar 20 and the N bus bar 21, i.e., the straight portion 20a of the P bus bar 20 and the straight portion of the N bus bar 21, extend in a straight line in top view.

[0019] On the other hand, the first connection portion 20b of the P bus bar 20 and the second connection portion 21b of the N bus bar 21 do not overlap in a top view.

[0020] Next, a description will be given of the internal layout of the first semiconductor device 10 and the second semiconductor device 11. Fig. 2 is a top view showing the internal layout of the semiconductor module 202 according to the first embodiment.

[0021] 2, the first semiconductor device 10 and the second semiconductor device 11 have a 2-in-1 configuration. The first semiconductor device 10 and the second semiconductor device 11 have the same structure except that the electrodes and terminals are mirror-symmetrical with respect to the boundary line A. Therefore, only the internal layout of the first semiconductor device 10 will be described here.

[0022] The first semiconductor device 10 includes a P-electrode 4, an N-electrode 5, an AC terminal 6, a P-side control terminal 7, an N-side control terminal 8, and a package 9, as well as an insulating substrate 1, a circuit pattern 2, and a plurality of (e.g., two) semiconductor elements 3.

[0023] The insulating substrate 1 is formed in a quadrangular shape (specifically, a rectangular shape) when viewed from above. A circuit pattern 2 is provided on the upper surface of the insulating substrate 1. The circuit pattern 2 is divided into multiple pieces, and multiple semiconductor elements 3 are mounted on the upper surface of the circuit pattern 2. The semiconductor elements 3 are power semiconductor elements, such as switching elements such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), or an RC-IGBT (Reverse Conducting IGBT), or diodes. The semiconductor material of the semiconductor elements 3 may be Si or SiC, but is preferably SiC.

[0024] One end of the P-electrode 4 is connected to the circuit pattern 2, and the other end of the P-electrode 4 protrudes from the package 9 and is connected to the first connection portion 20b of the P-bus bar 20. One end of the N-electrode 5 is connected to an upper surface electrode (not shown) of one of the semiconductor elements 3, and the other end of the N-electrode 5 protrudes from the package 9 and is connected to the second connection portion 21b of the N-bus bar 21. One end of the AC terminal 6 is connected to an upper surface electrode (not shown) of the other semiconductor element 3 and the circuit pattern 2, and the other end of the AC terminal 6 is connected to the AC bus bar 22. In this way, even within the package 9, the electrodes and terminals are arranged in mirror symmetry with respect to the boundary line A. Because the first semiconductor device 10 and the second semiconductor device 11 have a 2-in-1 configuration, it is possible to reduce the size of the semiconductor module 202.

[0025] 3A and 3B are diagrams for comparing voltage waveforms at the time of switching on, in which Fig. 3A shows the voltage waveform at the time of switching on when the electrodes and terminals are not arranged in mirror symmetry with respect to the boundary line A, and Fig. 3B shows the voltage waveform at the time of switching on when the electrodes and terminals are arranged in mirror symmetry with respect to the boundary line A, i.e., in the case of embodiment 1.

[0026] 3(a) and 3(b), it can be seen that the noise waveform at switching on is significantly reduced in the first embodiment compared to when the electrodes and terminals are not arranged in mirror symmetry with respect to the boundary line A. In this way, the configuration of the first embodiment suppresses resonance between the semiconductor elements 3, making it possible to significantly reduce noise.

[0027] As described above, the semiconductor module 202 according to the first embodiment includes the first semiconductor device 10 having the package 9 that seals the semiconductor element 3 and the P-electrode 4 and the N-electrode 5 protruding from the package 9, the second semiconductor device 11 having the package 9 that seals the semiconductor element 3 and the P-electrode 4 and the N-electrode 5 protruding from the package 9 and disposed adjacent to the first semiconductor device 10 such that the P-electrode 4 and the N-electrode 5 are mirror-symmetric to the P-electrode 4 and the N-electrode 5 of the first semiconductor device 10, the P-bus bar 20 connecting the P-electrodes 4 of the first semiconductor device 10 and the second semiconductor device 11, and the N-bus bar 21 connecting the N-electrodes 5 of the first semiconductor device 10 and the second semiconductor device 11. The P-bus bar 20 and the N-bus bar 21 partially overlap when viewed from above.

[0028] Therefore, since the first semiconductor device 10 and the second semiconductor device 11, each having a built-in semiconductor element 3, are arranged adjacent to each other, the dimensions of the package 9 for each semiconductor element 3 can be made smaller than if all the semiconductor elements 3 were built into a single package 9. This reduces thermal stress due to temperature changes. As a result, the durability of the semiconductor module 202 is improved.

[0029] Furthermore, the P bus bar 20 and the N bus bar 21 partially overlap in top view, specifically, the straight portion 20a of the P bus bar 20 overlaps the straight portion of the N bus bar 21 in top view. Therefore, while suppressing the inductance of the entire semiconductor module 202, the difference in inductance between the first semiconductor device 10 and the second semiconductor device 11 is reduced, and there is no difference between the first semiconductor device 10 and the second semiconductor device 11 in the paths from the semiconductor elements 3 of the first semiconductor device 10 and the second semiconductor device 11 to the smoothing capacitor (not shown), making it possible to suppress resonance and oscillation.

[0030] Furthermore, the first semiconductor device 10 and the second semiconductor device 11 have a 2-in-1 configuration, the packages 9 of the first semiconductor device 10 and the second semiconductor device 11 are both formed in a rectangular shape when viewed from above, and both the first semiconductor device 10 and the second semiconductor device 11 further have an AC terminal 6 protruding from the package 9. The AC terminal 6 of the first semiconductor device 10 is arranged on a second side opposite to the first side of the package 9 on which the P-electrode 4 and the N-electrode 5 of the first semiconductor device 10 are arranged, and the AC terminal 6 of the second semiconductor device 11 is arranged on the second side opposite to the first side of the package 9 on which the P-electrode 4 and the N-electrode 5 of the second semiconductor device 11 are arranged. This makes it possible to miniaturize the semiconductor module 202.

[0031] Furthermore, since the semiconductor material of the semiconductor element 3 is SiC, it is possible to increase the output of the semiconductor module 202 .

[0032] Second Embodiment Next, a semiconductor module 202 according to a second embodiment will be described. Fig. 4 is a top view of the semiconductor module 202 according to the second embodiment. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0033] As shown in FIG. 4, in the second embodiment, the semiconductor module 202 includes three sets of the first semiconductor device 10 and the second semiconductor device 11, and the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacent to each other in each set.

[0034] The three sets of first semiconductor devices 10 and second semiconductor devices 11 are arranged in the order of phase A, phase B, and phase C from the left in Fig. 4. The P bus bar 20 connects the P electrodes 4 of the three sets of first semiconductor devices 10 and second semiconductor devices 11 together. The N bus bar 21 connects the N electrodes 5 of the three sets of first semiconductor devices 10 and second semiconductor devices 11 together.

[0035] The straight portions 20a of the P bus bar 20 and the straight portions of the N bus bar 21 are arranged to overlap in top view to minimize the inductance of the path to the smoothing capacitor (not shown) in the first semiconductor device 10 and the path to the smoothing capacitor (not shown) in the second semiconductor device 11, and an insulating layer (not shown) is arranged between them. Furthermore, the three sets of first semiconductor devices 10 and second semiconductor devices 11 are connected in parallel so that the overlapping portions of the P bus bar 20 and the N bus bar 21, i.e., the straight portions 20a of the P bus bar 20 and the straight portions of the N bus bar 21, extend in a straight line in top view.

[0036] On the other hand, the first connection portion 20b of the P bus bar 20 and the second connection portion 21b of the N bus bar 21 do not overlap in a top view. The configuration of the second embodiment can also be adopted in the third to sixth embodiments described below.

[0037] As described above, in the second embodiment, the semiconductor module 202 includes three sets of the first semiconductor device 10 and the second semiconductor device 11, and the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacent to each other in each set.

[0038] Therefore, it is possible to reduce thermal stress due to temperature changes and obtain a three-phase AC output required for driving an AC motor.

[0039] Both the first semiconductor device 10 and the second semiconductor device 11 further have an N-side control terminal 8 and a P-side control terminal 7 protruding from the package 9. On a first side of the package 9 of the first semiconductor device 10 and the second semiconductor device 11, the N-side control terminal 8, the N-electrode 5, and the P-electrode 4 are arranged in this order along the direction toward the other adjacent semiconductor device. On a second side of the package 9 of the first semiconductor device 10 and the second semiconductor device 11, the AC terminal 6 and the P-side control terminal 7 are arranged in this order along the direction toward the other adjacent semiconductor device. The first semiconductor device 10 and the second semiconductor device 11 are connected in parallel so that the overlapping portions of the P bus bar 20 and the N bus bar 21 extend in a straight line in a top view.

[0040] Therefore, the N-side control terminal 8 and the N-electrode 5, and the AC terminal 6 and the P-side control terminal 7 can be arranged close to each other, thereby shortening the short sides of the first semiconductor device 10 and the second semiconductor device 11. As a result, the semiconductor module 202 can be made smaller.

[0041] Furthermore, since the positive control terminal 7 is located in the center of each phase, an insulation distance between the phases can be ensured, which makes it easier to design the insulation of the driver board connected to each phase.

[0042] Third Embodiment Next, a semiconductor module 202 according to a third embodiment will be described. Fig. 5 is a top view of the semiconductor module 202 according to the third embodiment. Note that in the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0043] As shown in FIG. 5, in the third embodiment, the first semiconductor device 10 and the second semiconductor device 11 are configured so that the semiconductor devices 10 and 11 can be connected to each other at the source potential of the semiconductor element 3 of the first semiconductor device 10 and the second semiconductor device 11 .

[0044] Specifically, the middle portions of the N-electrodes 5 of the first semiconductor device 10 and the second semiconductor device 11 are connected to the top surface electrodes (not shown) of one semiconductor element 3, and one end of the N-electrode 5 protrudes from the third side of the package 9 (see FIG. 1) located on the side of the other adjacent semiconductor device. The first semiconductor device 10 and the second semiconductor device 11 each have one end of the AC terminal 6 that is bifurcated, with one end of the AC terminal 6 being connected to the top surface electrodes (not shown) and circuit pattern 2 of the other semiconductor element 3, and the other end of the AC terminal 6 protruding from the third side of the package 9 (see FIG. 1) located on the side of the other adjacent semiconductor device. The third side is the long side on the right side in FIG. 1 .

[0045] As described above, in the third embodiment, a portion of the N-electrode 5 and the AC terminal 6 of the first semiconductor device 10 and the second semiconductor device 11 protrudes from the third side of the package 9 located on the side of the other adjacent semiconductor device.

[0046] Therefore, by connecting the semiconductor devices 10 and 11 to each other at the source potential of the semiconductor element 3 of the first semiconductor device 10 and the second semiconductor device 11, it is possible to further reduce the difference in inductance between the first semiconductor device 10 and the second semiconductor device 11.

[0047] Fourth Embodiment Next, a semiconductor module 202 according to a fourth embodiment will be described. Fig. 6 is a top view of the semiconductor module 202 according to the fourth embodiment. Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0048] As shown in FIG. 6 , in the fourth embodiment, the P bus bar 20 and the N bus bar 21 are drawn out in a parallel plate state to the vicinity of the first semiconductor device 10 and the second semiconductor device 11 at the center B between the P electrode 4 and the N electrode 5 of the first semiconductor device 10 and the second semiconductor device 11, i.e., at the center B between the first connection portion 20 b and the second connection portion 21 b, and are connected to the P electrode 4 and the N electrode 5, respectively.

[0049] As described above, in the semiconductor module 202 according to the fourth embodiment, the P bus bar 20 and the N bus bar 21 each have a straight portion 20a extending parallel to the direction in which the first semiconductor device 10 and the second semiconductor device 11 are arranged adjacent to each other, a first connection portion 20b connecting the P electrode 4 to the straight portion 20a, and a second connection portion 21b connecting the N electrode 5 to the straight portion 20a. The first connection portion 20b and the second connection portion 21b are connected to the straight portion 20a at the center B between the first connection portion 20b and the second connection portion 21b.

[0050] Therefore, since the P bus bar 20 and the N bus bar 21 are extended in a parallel plate state to the vicinity of the first semiconductor device 10 and the second semiconductor device 11, it is possible to further reduce the difference in inductance between the first semiconductor device 10 and the second semiconductor device 11 than in embodiment 1.

[0051] Fifth Embodiment Next, a semiconductor module 202 according to a fifth embodiment will be described. Fig. 7 is a top view of the semiconductor module 202 according to the fifth embodiment. Fig. 8 is a cross-sectional view showing a state in which the heat sink 23 is fixed to the semiconductor module 202 according to the fifth embodiment. Note that in the fifth embodiment, the same components as those described in the first to fourth embodiments are designated by the same reference numerals, and description thereof will be omitted.

[0052] 7, the first semiconductor device 10 and the second semiconductor device 11 are provided with a connection structure that allows them to be connected to each other. Also, as shown in FIG. 8, a heat sink 23 that cools the first semiconductor device 10 and the second semiconductor device 11 is fixed to the semiconductor module 202.

[0053] First, the connection structure between the first semiconductor device 10 and the second semiconductor device 11 will be described. As shown in FIG. 7 , the connection structure between the first semiconductor device 10 and the second semiconductor device 11 is provided on the third side of the package 9, which is located on the side of the other semiconductor device between the first semiconductor device 10 and the second semiconductor device 11, that is adjacent to the first semiconductor device 10 or the second semiconductor device 11. Specifically, two protrusions 9 a are provided spaced apart in the horizontal direction on the fourth side of the package 9, which faces the third side of the package 9, of the first semiconductor device 10 or the second semiconductor device 11. Two recesses 9 b, which can be connected to the two protrusions 9 a of the other semiconductor device, are provided spaced apart in the horizontal direction on the third side of the package 9. With this configuration, when the first semiconductor device 10 and the second semiconductor device 11 are adjacent to each other, the two recesses 9 b of the first semiconductor device 10 and the two protrusions 9 a of the second semiconductor device 11 are adjacent to each other and can be connected. The fourth side is the long side on the left in FIG. 7 . The horizontal direction is the left-right direction in FIG. 7 .

[0054] The convex portion 9a and the concave portion 9b do not need to have a dimensional relationship that generates a coupling force, and even if the convex portion 9a and the concave portion 9b are in close contact or have a minimal gap between them, the same effect can be obtained with respect to the connection between the first semiconductor device 10 and the second semiconductor device 11.

[0055] Next, as shown in Fig. 8, the underside of the package 9 of the first semiconductor device 10 and the second semiconductor device 11 is provided with protrusions 9c that protrude downward from positions that are not mirror-symmetric with each other. Here, the positions that are not mirror-symmetric with each other may be the same positions on the first semiconductor device 10 and the second semiconductor device 11, for example, the left end in Fig. 8. The protrusions 9c are provided on the underside of the package 9 all the way to the left end in Fig. 8. In addition, the upper surface of the heat sink 23 is provided with recesses 23a into which the protrusions 9c of the first semiconductor device 10 and the second semiconductor device 11 can fit.

[0056] As described above, in the semiconductor module 202 according to the fifth embodiment, the heat sink 23 that cools the first semiconductor device 10 and the second semiconductor device 11 can be fixed. The lower surfaces of the packages 9 of the first semiconductor device 10 and the second semiconductor device 11 are provided with protrusions 9c that protrude downward from positions that are not mirror-symmetrical to each other. The upper surface of the heat sink 23 is provided with recesses 23a into which the protrusions 9c of the first semiconductor device 10 and the second semiconductor device 11 can be fitted.

[0057] Therefore, the semiconductor module 202 and the heat sink 23 can be firmly fixed together.

[0058] Furthermore, a connection structure that can be connected to the other semiconductor device is provided on the third side of the package 9 that is located on the side of the other semiconductor device arranged adjacent to the first semiconductor device 10 or the second semiconductor device 11. If a protrusion 9c that fits into the recess 23a of the heat sink 23 is provided on the underside of the package 9, there is a concern that the semiconductor module 202 will become larger. However, because the first semiconductor device 10 and the second semiconductor device 11 can be connected in close contact or with a minimal gap, it is possible to prevent the semiconductor module 202 from becoming larger.

[0059] Sixth Embodiment Next, a semiconductor module 202 according to a sixth embodiment will be described. Fig. 9 is a top view of the semiconductor module 202 according to the sixth embodiment. Note that in the sixth embodiment, the same components as those described in the first to fifth embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0060] 9, in the sixth embodiment, the semiconductor element 3 in the first semiconductor device 10 and the second semiconductor device 11 includes a plurality of switching elements. Therefore, it is possible to increase the output of the semiconductor module 202.

[0061] Seventh Embodiment In this embodiment, the semiconductor module 202 according to any of the first to sixth embodiments described above is applied to a power conversion device 200. The application of the semiconductor module 202 according to any of the first to sixth embodiments is not limited to a specific power conversion device, but hereinafter, as the seventh embodiment, a case where the semiconductor module 202 according to any of the first to sixth embodiments is applied to a three-phase inverter will be described.

[0062] FIG. 10 is a block diagram showing the configuration of a power conversion system to which a power conversion device 200 according to the seventh embodiment is applied.

[0063] The power conversion system shown in Fig. 10 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0064] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 10 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.

[0065] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0066] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown) and freewheeling diodes (not shown), and converts DC power supplied from the power supply 100 into AC power by switching the switching elements, and supplies the AC power to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit, and can be configured from six switching elements and six freewheeling diodes connected in anti-parallel to each switching element.

[0067] At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is configured using a semiconductor module 202 corresponding to any one of the above-described first to sixth embodiments. In the seventh embodiment, as an example, the main conversion circuit 201 includes the semiconductor module 202 according to the first embodiment. Six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0068] The main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element. The drive circuit may be built into the semiconductor module 202, or may be provided separately from the semiconductor module 202. The drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. To maintain a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or greater than the threshold voltage of the switching element, and to maintain a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or less than the threshold voltage of the switching element.

[0069] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0070] In the power conversion device 200 according to this embodiment, the semiconductor module 202 is used as the switching element and the free wheel diode of the main conversion circuit 201, and therefore durability can be improved.

[0071] In the present embodiment, an example has been described in which the semiconductor module 202 according to the first to sixth embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor module 202 according to the first to sixth embodiments is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor module 202 according to the first to sixth embodiments may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor module 202 according to the first to sixth embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0072] Furthermore, the power conversion device 200 to which the semiconductor module 202 according to any one of the first to sixth embodiments is applied is not limited to cases in which the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0073] Although this disclosure has been described in detail, the above description is illustrative in all respects and is not restrictive. It is understood that countless variations not illustrated can be envisioned.

[0074] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0075] 3 Semiconductor element, 4 P electrode, 5 N electrode, 6 AC terminal, 7 P-side control terminal, 8 N-side control terminal, 9 Package, 9c Convex portion, 10 First semiconductor device, 11 Second semiconductor device, 20 P bus bar, 20a Straight portion, 20b First connection portion, 21 N bus bar, 21b Second connection portion, 23 Heat sink, 23a Concave portion, 200 Power conversion device, 201 Main conversion circuit, 202 Semiconductor module, 203 Control circuit.

Claims

1. A semiconductor module comprising: a first semiconductor device having a package that encapsulates a semiconductor element and a P-electrode and an N-electrode protruding from the package; a second semiconductor device having a package that encapsulates a semiconductor element and a P-electrode and an N-electrode protruding from the package, the second semiconductor device being arranged adjacent to the first semiconductor device so that the P-electrode and the N-electrode are mirror images of the P-electrode and the N-electrode of the first semiconductor device; a P-bus bar connecting the P-electrodes of the first semiconductor device and the second semiconductor device; and an N-bus bar connecting the N-electrodes of the first semiconductor device and the second semiconductor device, wherein the P-bus bar and the N-bus bar partially overlap when viewed from above.

2. The semiconductor module according to claim 1, wherein the first semiconductor device and the second semiconductor device have a 2-in-1 configuration, the packages of the first semiconductor device and the second semiconductor device are both formed in a rectangular shape when viewed from above, the first semiconductor device and the second semiconductor device both further have AC terminals protruding from the packages, the AC terminal of the first semiconductor device is arranged on a second side opposite to a first side of the package on which the P-electrode and the N-electrode of the first semiconductor device are arranged, and the AC terminal of the second semiconductor device is arranged on a second side opposite to the first side of the package on which the P-electrode and the N-electrode of the second semiconductor device are arranged.

3. The semiconductor module according to claim 2, comprising three sets of said first semiconductor devices and said second semiconductor devices, said first semiconductor devices and said second semiconductor devices being arranged adjacent to each other in each set.

4. The semiconductor module according to claim 3, wherein the first semiconductor device and the second semiconductor device both further have an N-side control terminal and a P-side control terminal protruding from the package, the N-side control terminal, the N-electrode, and the P-electrode are arranged in this order on the first side of the package in the first semiconductor device and the second semiconductor device, along a direction approaching the other semiconductor device arranged adjacently, the AC terminal and the P-side control terminal are arranged in this order on the second side of the package in the first semiconductor device and the second semiconductor device, along a direction approaching the other semiconductor device arranged adjacently, and the first semiconductor device and the second semiconductor device are connected in parallel so that overlapping portions of the P bus bar and the N bus bar extend in a straight line in a top view.

5. The semiconductor module according to claim 2, wherein a portion of the N-electrode and the AC terminal of the first semiconductor device and the second semiconductor device protrudes from a third side of the package located on the side of the other semiconductor device arranged adjacently.

6. The semiconductor module according to any one of claims 1 to 5, wherein the P bus bar and the N bus bar both have straight portions extending parallel to the direction in which the first semiconductor device and the second semiconductor device are arranged adjacent to each other, a first connection portion connecting the P electrode to the straight portion, and a second connection portion connecting the N electrode to the straight portion, and the first connection portion and the second connection portion are connected to the straight portion at the center between the first connection portion and the second connection portion.

7. A semiconductor module according to any one of claims 1 to 6, wherein a heat sink for cooling the first semiconductor device and the second semiconductor device can be fixed, the underside of the package of the first semiconductor device and the second semiconductor device is provided with a convex portion that protrudes downward from a position that is not mirror symmetrical to each other, and the upper surface of the heat sink is provided with a concave portion into which the convex portion of the first semiconductor device and the second semiconductor device can be fitted.

8. The semiconductor module according to claim 7, wherein a connection structure connectable to the other semiconductor device is provided on a third side of the package that is located on the side of the other semiconductor device arranged adjacent to the first semiconductor device and the second semiconductor device.

9. The semiconductor module according to any one of claims 1 to 8, wherein the semiconductor elements in the first semiconductor device and the second semiconductor device include a plurality of switching elements.

10. A semiconductor module according to any one of claims 1 to 9, wherein the semiconductor material of the semiconductor element is SiC.

11. A power conversion device comprising: a main conversion circuit having a semiconductor module according to any one of claims 1 to 10, which converts input power and outputs it; and a control circuit which outputs a control signal to the main conversion circuit to control the main conversion circuit.

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