Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device comprises a silicon carbide substrate that has a first main surface and a second main surface which is on the opposite side from the first main surface. The silicon carbide substrate has a drift region that has a first conductivity type, a body region that is provided on the drift region and that has a second conductivity type, and a source region that is provided on the body region and that has the first conductivity type. The first main surface is provided with a gate trench that is defined by a side surface which penetrates the source region and the body region to reach the drift region and a bottom surface which is connected to the side surface. The gate trench extends along a first axis that is parallel to the first main surface. The silicon carbide substrate further has: a contact region that has the source region sandwiched between the contact region and the side surface, that is in contact with the body region, and that has the second conductivity type; a first electric field relief region that overlaps the gate trench in a plan view which is perpendicular to the first main surface, that is provided between the bottom surface and the second main surface, and that has the second conductivity type; and a second electric field relief region that overlaps the contact region in a plan view which is perpendicular to the first main surface, that is provided between the body region and the second main surface, and that has the second conductivity type. The first electric field relief region and the second electric field relief region are disposed side by side along the first axis.

Description

Silicon carbide semiconductor device

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2024-035031 filed on March 7, 2024, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] A trench-gate metal oxide semiconductor field effect transistor (MOSFET) has been disclosed as one type of silicon carbide semiconductor device. The trench-gate MOSFET has a gate trench formed in a silicon carbide substrate and electric field relaxation regions arranged in stripes so as to intersect with the gate trench.

[0004] Japanese Patent Application Publication No. 2012-169386

[0005] A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region having a second conductivity type provided on the drift region, and a source region having the first conductivity type provided on the body region, the first main surface being provided with a gate trench defined by a side surface that passes through the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the gate trench extending along a first axis parallel to the first main surface the silicon carbide substrate further includes: a contact region having the second conductivity type, sandwiching the source region between itself and the side surface, and in contact with the body region; a first electric field relaxation region having the second conductivity type, overlapping the gate trench in a plan view perpendicular to the first main surface and provided between the bottom surface and the second main surface; and a second electric field relaxation region having the second conductivity type, overlapping the contact region in a plan view perpendicular to the first main surface and provided between the body region and the second main surface, wherein the first electric field relaxation region and the second electric field relaxation region are arranged side by side along the first axis.

[0006] FIG. 1 is a diagram showing the arrangement of electric field relaxation regions included in a silicon carbide semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view (part 1) showing the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a diagram showing the arrangement of electric field relaxation regions included in a silicon carbide semiconductor device according to a second embodiment. FIG. 5 is a cross-sectional view showing the silicon carbide semiconductor device according to the second embodiment. FIG. 6 is a diagram showing the arrangement of electric field relaxation regions included in a silicon carbide semiconductor device according to a third embodiment. FIG. 7 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment.

[0007] [Problem to be Solved by the Present Disclosure] A silicon carbide semiconductor device includes an active region and a termination region surrounding the active region. The area of ​​the termination region is smaller than the area of ​​the active region. In a silicon carbide semiconductor device, by designing the breakdown voltage of the active region to be lower than the breakdown voltage of the termination region, it is possible to evenly distribute avalanche current in the active region, which has a relatively large area, thereby improving avalanche resistance.

[0008] In conventional silicon carbide semiconductor devices, the electric field strength applied to the gate insulating film is reduced by narrowing the distance between adjacent electric field buffer regions. In this case, the difference in breakdown voltage between the active region and the termination region becomes smaller, and avalanche current tends to flow through the termination region, which has a relatively small area. This reduces the avalanche resistance.

[0009] An object of the present disclosure is to provide a silicon carbide semiconductor device that can reduce the electric field strength applied to a gate insulating film while maintaining avalanche resistance.

[0010] Effect of the Present Disclosure The present disclosure can provide a silicon carbide semiconductor device that can reduce the electric field strength applied to the gate insulating film while maintaining avalanche resistance.

[0011] The embodiments for carrying out the invention are described below.

[0012] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the following description, an XYZ Cartesian coordinate system will be used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the semiconductor device. The XY plane view will be referred to as a planar view, and the +Z direction from an arbitrary point will sometimes be referred to as upward, upper side, or top, and the −Z direction will sometimes be referred to as downward, lower side, or bottom.

[0013] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region having a second conductivity type provided on the drift region, and a source region having the first conductivity type provided on the body region, the first main surface having a gate trench defined by a side surface that passes through the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the gate trench being oriented along a first axis parallel to the first main surface. the silicon carbide substrate further includes: a contact region having the second conductivity type, sandwiching the source region between itself and the side surface, and in contact with the body region; a first electric field relaxation region having the second conductivity type, overlapping with the gate trench in a plan view perpendicular to the first main surface and provided between the bottom surface and the second main surface; and a second electric field relaxation region having the second conductivity type, overlapping with the contact region in a plan view perpendicular to the first main surface and provided between the body region and the second main surface, the first electric field relaxation region and the second electric field relaxation region being arranged side by side along the first axis. In this case, the electric field strength applied to the gate insulating film can be reduced while maintaining avalanche resistance.

[0014] [2] A silicon carbide semiconductor device according to another aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a drift region having a first conductivity type, a body region having a second conductivity type provided on the drift region, and a source region having the first conductivity type provided on the body region, the first main surface having a gate trench defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the gate trench extending along a first axis parallel to the first main surface, the silicon carbide substrate further includes: a contact region having the second conductivity type, sandwiching the source region between itself and the side surface, and in contact with the body region; a first electric field relaxation region having the second conductivity type, the first electric field relaxation region having a portion overlapping with the bottom surface of the gate trench in a plan view perpendicular to the first main surface, and being provided between the bottom surface and the second main surface; and a second electric field relaxation region having the second conductivity type, the second electric field relaxation region having a portion overlapping with the contact region in a plan view perpendicular to the first main surface, and being provided between the body region and the second main surface, the first electric field relaxation region and the second electric field relaxation region being arranged side by side along the first axis. In this case, the electric field strength applied to the gate insulating film can be reduced while maintaining avalanche resistance.

[0015] [3] In [1] or [2], the first electric field buffer regions and the second electric field buffer regions may be arranged alternately and repeatedly along the first axis. In this case, the bias between the regions through which current flows and the regions through which current does not flow during avalanche breakdown is reduced. This makes it easier to uniformize the heat distribution within the chip during avalanche breakdown.

[0016] [4] In any one of [1] to [3], the first electric field buffer region may be connected to the adjacent second electric field buffer region along the first axis. In this case, feedback capacitance can be reduced, thereby shortening switching time.

[0017] [5] In [4], the first electric field buffer region may have a first length along a second axis parallel to the first main surface and perpendicular to the first axis, and the second electric field buffer region may have a second length along the second axis, the first length being shorter than the second length. In this case, avalanche current flows more easily directly below the first electric field buffer region than in the termination region. This improves avalanche resistance.

[0018] [6] In [5], the first length may be shorter than a third length along the first axis of a portion where the first electric field buffer region and the second electric field buffer region are connected. In this case, avalanche current flows more easily directly below the first electric field buffer region than in the termination region. This improves avalanche resistance.

[0019] [7] In any one of [1] to [6], the concentration of the first conductivity type impurity in the drift region may decrease from the first main surface toward the second main surface. In this case, the breakdown voltage can be increased while reducing the on-resistance.

[0020] [8] In any of [1] to [7], a connection region may be provided that electrically connects the body region and the first electric field buffer region. In this case, feedback capacitance can be reduced, thereby shortening switching time.

[0021] [Details of the Embodiments of the Present Disclosure] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto.

[0022] [First Embodiment] The first embodiment relates to a so-called trench gate MOSFET using silicon carbide (SiC). A trench gate MOSFET is an example of a silicon carbide semiconductor device. FIG. 1 is a diagram showing the arrangement of an electric field relaxation region included in a silicon carbide semiconductor device according to the first embodiment. FIGS. 2 and 3 are cross-sectional views showing the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 1.

[0023] As shown in Figures 1 to 3, the silicon carbide semiconductor device 100 according to the first embodiment has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0024] Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1. First main surface 1 and second main surface 2 are parallel to the XY plane. Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on silicon carbide single crystal substrate 50. Silicon carbide epitaxial layer 40 includes first main surface 1, and silicon carbide single crystal substrate 50 includes second main surface 2. Silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 include, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 includes n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type).

[0025] The silicon carbide epitaxial layer 40 has a drift region 11 , a body region 12 , a source region 13 , a current spreading region 14 , an electric field relaxation region 16 , and a contact region 18 .

[0026] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. The effective concentration of the n-type impurities in drift region 11 may decrease from first main surface 1 to second main surface 2. Drift region 11 is provided on silicon carbide single crystal substrate 50. Drift region 11 has a first region 11A, a second region 11B, and a third region 11C. First region 11A, second region 11B, and third region 11C will be described later.

[0027] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity (second conductivity type). The body region 12 is provided on the drift region 11.

[0028] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 includes the first main surface 1.

[0029] The first main surface 1 is provided with a plurality of gate trenches 5 defined by side surfaces 3 and a bottom surface 4. Each gate trench 5 extends, for example, along the Y axis. The Y axis is an example of a first axis. The plurality of gate trenches 5 are provided at regular intervals along the X axis. The X axis is an example of a second axis. The side surfaces 3 penetrate the source region 13, the body region 12, the current spreading region 14, and part of the drift region 11, and reach the drift region 11. The bottom surface 4 is continuous with the side surfaces 3. The bottom surface 4 is located in the drift region 11. The bottom surface 4 is, for example, parallel to the first main surface 1 and the second main surface 2. The side surfaces 3 are inclined with respect to a plane including the bottom surface 4.

[0030] The current spreading region 14 contains n-type impurities such as phosphorus and has n-type conductivity. The current spreading region 14 is provided on the drift region 11. The current spreading region 14 is provided between the drift region 11 and the body region 12. The current spreading region 14 contacts the drift region 11 and the body region 12.

[0031] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 penetrates the source region 13 and the body region 12 and is in contact with the current spreading region 14. The contact region 18 includes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between adjacent gate trenches 5 along the X-axis.

[0032] The electric field buffer region 16 contains p-type impurities such as aluminum and has p-type conductivity. The electric field buffer region 16 has a first electric field buffer region 16A and a second electric field buffer region 16B.

[0033] The first electric field relaxation region 16A is located within the drift region 11. The first electric field relaxation region 16A is located directly below the gate trench 5. The first electric field relaxation region 16A is located at a position overlapping the gate trench 5 in a plan view perpendicular to the first main surface 1. The first electric field relaxation region 16A may have a portion overlapping with the bottom surface 4 of the gate trench 5 in a plan view perpendicular to the first main surface 1. The first electric field relaxation region 16A may have a portion overlapping with the side surface 3 of the gate trench 5 in a plan view perpendicular to the first main surface 1. At the position overlapping with the gate trench 5, the first electric field relaxation region 16A and the drift region 11 may be provided alternately along the Y axis. At the position overlapping with the gate trench 5, the first electric field relaxation region 16A may be provided intermittently along the Y axis. In this case, the breakdown voltage of the active region is reduced compared to when the first electric field relaxation region 16A is provided continuously along the Y axis. As a result, the difference in breakdown voltage between the active region and the termination region becomes larger, making it difficult for avalanche current to flow through the termination region. The first electric field relaxation region 16A is located between the bottom surface 4 and the second main surface 2. In this case, the electric field strength applied to the gate insulating film 81 can be reduced. The upper end surface of the first electric field relaxation region 16A may be separated from the bottom surface 4. In this case, it is easier to reduce the on-resistance. The upper end surface of the first electric field relaxation region 16A may be in contact with the bottom surface 4.

[0034] The second electric field relaxation region 16B is located within the drift region 11. A portion of the second electric field relaxation region 16B may be located within the current spreading region 14. The second electric field relaxation region 16B is located directly below the contact region 18. In a plan view perpendicular to the first major surface 1, the second electric field relaxation region 16B is located between adjacent gate trenches 5 along the X-axis. The second electric field relaxation region 16B is located so as to overlap with the contact region 18 in a plan view perpendicular to the first major surface 1. The second electric field relaxation region 16B may have a portion overlapping with the contact region 18 in a plan view perpendicular to the first major surface 1. The second electric field relaxation region 16B may have a portion overlapping with the source region 13 in a plan view perpendicular to the first major surface 1. The second electric field relaxation region 16B and the drift region 11 may be alternately provided along the Y-axis between two gate trenches 5 adjacent along the X-axis. The second electric field relaxation region 16B may be provided intermittently along the Y axis between two gate trenches 5 adjacent to each other along the X axis. The upper end surface of the second electric field relaxation region 16B may be in contact with the body region 12 and electrically connected to the body region 12. The upper end surface of the second electric field relaxation region 16B may be in contact with the contact region 18 and electrically connected to the contact region 18. In this case, feedback capacitance is reduced, which makes it easier to shorten the switching time.

[0035] The first electric field buffer region 16A and the second electric field buffer region 16B are arranged side by side along the Y axis. The first electric field buffer region 16A and the second electric field buffer region 16B may be arranged alternately and repeatedly along the Y axis. The first electric field buffer region 16A may be connected to the adjacent second electric field buffer region 16B along the Y axis.

[0036] The first length L1 along the X-axis of the first electric field buffer region 16A may be shorter than the second length L2 along the X-axis of the second electric field buffer region 16B. In this case, avalanche current flows more easily directly below the first electric field buffer region 16A than in the termination region. This improves the avalanche resistance. The first length L1 may be shorter than the third length L3 along the Y-axis, which connects the first electric field buffer region 16A and the second electric field buffer region 16B. In this case, avalanche current flows more easily directly below the first electric field buffer region 16A than in the termination region. This improves the avalanche resistance.

[0037] The first region 11A is located between the current diffusion region 14 and the first electric field buffer region 16A. The first region 11A has an upper surface in contact with the current diffusion region 14, a lower surface in contact with the first electric field buffer region 16A, and a side surface in contact with the second electric field buffer region 16B.

[0038] The second region 11B is closer to the second main surface 2 than the first region 11A. The second region 11B is continuous with the first region 11A. The upper surface of the second region 11B is in contact with the first region 11A, the lower surface is in contact with the third region 11C, and the side surfaces are in contact with the first electric field buffer region 16A and the second electric field buffer region 16B.

[0039] Third region 11C is closer to second main surface 2 than second region 11B. Third region 11C is continuous with second region 11B. The upper surface of third region 11C is in contact with first electric field relaxation region 16A, second electric field relaxation region 16B, and second region 11B, and the lower surface is in contact with silicon carbide single crystal substrate 50.

[0040] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 includes, for example, silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, the current spreading region 14, and the drift region 11 at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0041] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 includes, for example, polysilicon. The polysilicon may include conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap with multiple gate trenches 5.

[0042] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 contains, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5.

[0043] Contact holes 90 are provided in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are provided so that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0044] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 contains, for example, titanium nitride (TiN).

[0045] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 and a source wiring 62.

[0046] The contact electrode 61 is provided in the contact hole 90. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 contains, for example, nickel silicide (NiSi). The contact electrode 61 may also contain titanium (Ti), aluminum, and silicon (Si). The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18.

[0047] The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 contains, for example, aluminum. In this case, it is easy to connect the source wiring 62 to the contact electrode 61.

[0048] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 contains, for example, nickel silicide. The drain electrode 70 may also contain titanium, aluminum, and silicon. The drain electrode 70 forms an ohmic junction with the silicon carbide single crystal substrate 50.

[0049] The effective concentration of the n-type impurity in the first region 11A is, for example, 1×10 １６ cm －３ 1x10 or more １８ cm －３ The effective concentration of the n-type impurity in the second region 11B may be lower than the effective concentration of the n-type impurity in the first region 11A. The effective concentration of the n-type impurity in the second region 11B is, for example, 1×10 １６ cm －３ 1x10 or more １８ cm －３ The effective concentration of n-type impurities in the third region 11C may be lower than the effective concentration of n-type impurities in the second region 11B. The effective concentration of n-type impurities in the third region 11C is, for example, 2×10 １５ cm －３ 5x10 or more １６ cm －３ The following is the result.

[0050] The effective concentration of the n-type impurity in the current spreading region 14 may be higher than the effective concentration of the n-type impurity in the first region 11A. The effective concentration of the n-type impurity in the current spreading region 14 may be, for example, 2×10 １６ cm －３ 4 x 10 or more １８ cm －３ The following is the result.

[0051] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity. In the present disclosure, the effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM) or secondary ion mass spectrometry (SIMS).

[0052] Next, a method for manufacturing silicon carbide semiconductor device 100 will be described.

[0053] First, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0054] Next, electric field relaxation region 16 is formed by implanting ions into silicon carbide epitaxial layer 40. In the ion implantation for forming electric field relaxation region 16, channeling implantation of p-type impurities such as aluminum is performed. At this time, the upper end surface of electric field relaxation region 16 is separated from the upper surface of silicon carbide epitaxial layer 40.

[0055] Next, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, the source region 13, the current spreading region 14, and the contact region 18. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11. Next, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a barrier metal film 84, a source electrode 60, and a drain electrode 70 are formed (see FIGS. 2 and 3 ).

[0056] In this manner, silicon carbide semiconductor device 100 can be manufactured.

[0057] In silicon carbide semiconductor device 100, as described above, first electric field relaxation region 16A and second electric field relaxation region 16B are arranged side by side along the Y axis. First electric field relaxation region 16A is located directly below gate trench 5, and second electric field relaxation region 16B is located directly below contact region 18. In this case, the electric field strength applied to gate insulating film 81 can be reduced while maintaining avalanche resistance.

[0058] The first electric field buffer regions 16A and the second electric field buffer regions 16B may be arranged alternately and repeatedly along the Y axis. In this case, the bias between the regions through which current flows and the regions through which current does not flow during avalanche breakdown is reduced, making it easier to uniformize the heat distribution within the chip during avalanche breakdown.

[0059] The first electric field buffer region 16A may be connected to the adjacent second electric field buffer region 16B along the Y axis, which makes it easier to reduce feedback capacitance and shorten switching time.

[0060] The first length L1 along the X-axis of the first electric field buffer region 16A may be shorter than the second length L2 along the X-axis of the second electric field buffer region 16B. In this case, avalanche current flows more easily directly below the first electric field buffer region 16A than in the termination region. This improves the avalanche resistance.

[0061] The first length L1 may be shorter than the third length L3 along the Y axis of the portion where the first electric field buffer region 16A and the second electric field buffer region 16B are connected. In this case, avalanche current flows more easily directly below the first electric field buffer region 16A than in the termination region. This improves the avalanche resistance.

[0062] The effective concentration of n-type impurities in drift region 11 may decrease from first main surface 1 toward second main surface 2. In this case, the breakdown voltage can be increased while reducing the on-resistance.

[0063] Second Embodiment A second embodiment will be described. The second embodiment differs from the first embodiment in that a connection region electrically connects the body region and the first electric field relaxation region. FIG. 4 is a diagram showing the arrangement of the electric field relaxation region included in the silicon carbide semiconductor device according to the second embodiment. FIG. 5 is a cross-sectional view showing the silicon carbide semiconductor device according to the second embodiment. FIG. 5 corresponds to a cross-sectional view taken along line V-V in FIG. 4.

[0064] As shown in FIGS. 4 and 5 , silicon carbide semiconductor device 200 in accordance with the second embodiment has connection region 17 .

[0065] The connection region 17 contains p-type impurities such as aluminum and has p-type conductivity. The connection region 17 is located so as to overlap the gate trench 5 in a plan view perpendicular to the first main surface 1. The connection region 17 may have a portion overlapping the bottom surface 4 of the gate trench 5 in a plan view perpendicular to the first main surface 1. The connection region 17 may have a portion overlapping the side surface 3 of the gate trench 5 in a plan view perpendicular to the first main surface 1. The connection region 17 may be provided intermittently along the Y-axis at the position overlapping the gate trench 5. The connection region 17 overlaps a portion of the first electric field relaxation region 16A in a plan view perpendicular to the first main surface 1. The connection region 17 may be provided at an intermediate position along the Y-axis in the first electric field relaxation region 16A in a plan view perpendicular to the first main surface 1. The connection region 17 is located between the body region 12 and the first electric field relaxation region 16A. The connection region 17 contacts the body region 12 and the first electric field relaxation region 16A. The connection region 17 electrically connects the body region 12 and the first electric field relaxation region 16A. The upper end surface of the connection region 17 may contact the bottom surface 4. The length of the connection region 17 along the X-axis in a plan view perpendicular to the first main surface 1 may be the same as that of the first electric field relaxation region 16A.

[0066] The parts other than the connection region 17 are the same as those in the first embodiment.

[0067] Silicon carbide semiconductor device 200 can be manufactured by forming connection region 17 by implanting ions into silicon carbide epitaxial layer 40 after forming electric field relaxation region 16 in the method for manufacturing silicon carbide semiconductor device 100. The ion implantation for forming connection region 17 involves channeling implantation of p-type impurities such as aluminum. At this time, the upper end surface of connection region 17 is spaced apart from the upper surface of silicon carbide epitaxial layer 40.

[0068] Silicon carbide semiconductor device 200 according to the second embodiment also provides the same effects as those of the first embodiment.

[0069] Silicon carbide semiconductor device 200 has connection region 17 that electrically connects body region 12 and first electric field relaxation region 16A. In this case, feedback capacitance can be reduced, and therefore the switching time can be shortened.

[0070] Third Embodiment A third embodiment will be described. The third embodiment differs from the second embodiment in that the connection region electrically connects the body region and the contact region to the first electric field relaxation region. FIG. 6 is a diagram showing the arrangement of the electric field relaxation region included in the silicon carbide semiconductor device according to the third embodiment. FIG. 7 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIG. 6.

[0071] 6 and 7 , in silicon carbide semiconductor device 300 according to the third embodiment, the upper end surface of connection region 17 contacts body region 12 and contact region 18. Connection region 17 electrically connects body region 12 and contact region 18 to first electric field relaxation region 16A. Connection region 17 extends along the X-axis. The length of connection region 17 along the X-axis is longer than the length of first electric field relaxation region 16A along the X-axis.

[0072] The parts other than the connection region 17 are the same as those in the second embodiment.

[0073] Silicon carbide semiconductor device 300 can be manufactured by a method similar to that for manufacturing silicon carbide semiconductor device 300 .

[0074] Silicon carbide semiconductor device 300 according to the third embodiment also provides the same effects as those of the first embodiment.

[0075] Silicon carbide semiconductor device 300 has connection region 17 that electrically connects body region 12 and first electric field reduction region 16A. In this case, feedback capacitance can be reduced, and therefore switching time can be shortened.

[0076] The connection region 17 electrically connects the contact region 18 and the first electric field buffer region 16A, thereby strengthening the grounding of the first electric field buffer region 16A.

[0077] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0078] DESCRIPTION OF SYMBOLS 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 11A First region 11B Second region 11C Third region 12 Body region 13 Source region 14 Current diffusion region 16 Electric field relaxation region 16A First electric field relaxation region 16B Second electric field relaxation region 17 Connection region 18 Contact region 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 90 Contact hole 100 Silicon carbide semiconductor device 200 Silicon carbide semiconductor device 300 Silicon carbide semiconductor device L1 First length L2 Second length L3 Third length

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein the silicon carbide substrate has: a drift region having a first conductivity type; a body region having a second conductivity type provided on the drift region; and a source region having the first conductivity type provided on the body region, wherein the first main surface is provided with a gate trench defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the gate trench extending along a first axis parallel to the first main surface, and the silicon carbide substrate has: a contact region having the second conductivity type that is in contact with the body region and sandwiches the source region between the gate trench and the side surface; and a first electric field relief region having the second conductivity type that overlaps the gate trench in a plan view perpendicular to the first main surface and is provided between the bottom surface and the second main surface, a second electric field relaxation region having the second conductivity type, the second electric field relaxation region overlapping the contact region in a plan view perpendicular to the first main surface, the second electric field relaxation region being provided between the body region and the second main surface, wherein the first electric field relaxation region and the second electric field relaxation region are arranged side by side along the first axis.

2. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, wherein the silicon carbide substrate has: a drift region having a first conductivity type; a body region having a second conductivity type provided on the drift region; and a source region having the first conductivity type provided on the body region, wherein the first main surface is provided with a gate trench defined by a side surface that penetrates the source region and the body region to reach the drift region and a bottom surface continuous with the side surface, the gate trench extending along a first axis parallel to the first main surface, and the silicon carbide substrate has: a contact region having the second conductivity type that is in contact with the body region and sandwiches the source region between itself and the side surface; and a first electric field relief region having the second conductivity type that is provided between the bottom surface and the second main surface and has a portion that overlaps with the bottom surface of the gate trench in a plan view perpendicular to the first main surface, a second electric field relaxation region having the second conductivity type, the second electric field relaxation region having a portion overlapping with the contact region in a plan view perpendicular to the first main surface, the second electric field relaxation region being provided between the body region and the second main surface, wherein the first electric field relaxation region and the second electric field relaxation region are arranged side by side along the first axis.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein the first electric field buffer regions and the second electric field buffer regions are alternately and repeatedly arranged along the first axis.

4. The silicon carbide semiconductor device according to claim 1, wherein the first electric field buffer region is connected to the second electric field buffer region adjacent to the first axis.

5. The silicon carbide semiconductor device according to claim 4, wherein the first electric field relaxation region has a first length along a second axis parallel to the first main surface and perpendicular to the first axis, the second electric field relaxation region has a second length along the second axis, and the first length is shorter than the second length.

6. The silicon carbide semiconductor device according to claim 5, wherein said first length is shorter than a third length along said first axis of a portion where said first electric field buffer region and said second electric field buffer region are connected.

7. The silicon carbide semiconductor device according to claim 1 , wherein a concentration of the impurity of the first conductivity type in the drift region decreases from the first main surface toward the second main surface.

8. The silicon carbide semiconductor device according to claim 1 , further comprising a connection region that electrically connects the body region and the first electric field reduction region.

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