Semiconductor device and method for producing same

Abstract

A semiconductor device (1) comprises: a channel layer (14); a barrier layer (16) that is provided above the channel layer (14) and that has a band gap greater than that of the channel layer (14); a p-type semiconductor layer (18) provided above the barrier layer (16); a source electrode (32) and a drain electrode (34) provided so as to sandwich the p-type semiconductor layer (18) therebetween; a gate electrode (30) provided above the p-type semiconductor layer (18); and an i-type semiconductor layer (20) provided in contact with a side surface (18c) of the p-type semiconductor layer (18). The gate electrode (30) overlaps the p-type semiconductor layer (18) and the i-type semiconductor layer (20) in plan view.

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] Patent Document 1 discloses a semiconductor device that aims to achieve normally-off characteristics while reducing the resistance of the channel region. The semiconductor device disclosed in Patent Document 1 includes a nitride semiconductor laminate structure including a carrier transit layer and a carrier supply layer, a p-type nitride semiconductor layer provided above the nitride semiconductor laminate structure and having an active region and an inactive region, an n-type nitride semiconductor layer provided on the inactive region of the p-type nitride semiconductor layer, and a gate electrode provided above the active region of the p-type nitride semiconductor layer.

[0003] JP 2012-174714 A

[0004] When a p-type nitride semiconductor layer is provided to achieve normally-off characteristics, the gate length corresponds to the length of the lower surface of the p-type nitride semiconductor layer. In the semiconductor device disclosed in Patent Document 1, the length of the lower surface of the p-type nitride semiconductor layer is long, which increases the gate length and makes it impossible to sufficiently reduce the channel resistance.

[0005] Therefore, the present disclosure provides a semiconductor device that can achieve a further reduction in channel resistance and a normally-off characteristic.

[0006] A semiconductor device according to one aspect of the present disclosure includes a first nitride semiconductor layer, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer, a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer therebetween, a gate electrode provided above the third nitride semiconductor layer, and an i-type fourth nitride semiconductor layer provided in contact with a side surface of the third nitride semiconductor layer, wherein the gate electrode overlaps the third nitride semiconductor layer and the fourth nitride semiconductor layer in a plan view.

[0007] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes: a first step of forming, in this order, a first nitride semiconductor layer, a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, and a p-type nitride semiconductor layer; a second step of forming a source electrode and a drain electrode to sandwich the p-type nitride semiconductor layer; a third step of forming a gate electrode above the p-type nitride semiconductor layer; and a fourth step of selectively inactivating p-type dopants contained in the p-type nitride semiconductor layer by a first heat treatment to form a p-type third nitride semiconductor layer and an i-type fourth nitride semiconductor layer in contact with a side surface of the third nitride semiconductor layer, wherein the gate electrode overlaps the third nitride semiconductor layer and the fourth nitride semiconductor layer in a plan view.

[0008] According to the present disclosure, it is possible to achieve a further reduction in channel resistance and a normally-off characteristic.

[0009] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view showing an enlarged view of the vicinity of a gate structure of the semiconductor device according to the first embodiment. FIG. 3A is a cross-sectional view for explaining a step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 3B is a cross-sectional view for explaining a step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 3C is a cross-sectional view for explaining a step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 3D is a cross-sectional view for explaining a step of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view showing an enlarged view of the vicinity of a gate structure of a semiconductor device according to a first modification of the first embodiment. FIG. 5 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment. FIG. 7A is a cross-sectional view for explaining a step of a method for manufacturing a semiconductor device according to the second embodiment. FIG. 7B is a cross-sectional view for explaining a step of a method for manufacturing a semiconductor device according to the second embodiment. FIG. 7C is a cross-sectional view for explaining a step of a method for manufacturing a semiconductor device according to the second embodiment. FIG. 7D is a cross-sectional view for explaining a step of a method for manufacturing a semiconductor device according to the second embodiment. FIG. 8 is a cross-sectional view showing an enlarged view of the vicinity of a gate structure of a semiconductor device according to a second modification of the second embodiment. FIG. 9 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 10 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device according to the third embodiment. FIG. 11A is a cross-sectional view for explaining a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 11B is a cross-sectional view for explaining a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 11C is a cross-sectional view for explaining a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 11D is a cross-sectional view for explaining a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 11E is a cross-sectional view for explaining a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 11F is a cross-sectional view for explaining a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 12 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device according to a first modification of the third embodiment. FIG. 13 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device according to a second modification of the third embodiment.FIG. 14A is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to Modification 2 of Embodiment 3. FIG. 14B is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to Modification 2 of Embodiment 3. FIG. 14C is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to Modification 2 of Embodiment 3. FIG. 14D is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to Modification 2 of Embodiment 3. FIG. 14E is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to Modification 2 of Embodiment 3. FIG. 15 is an enlarged cross-sectional view illustrating the vicinity of a gate structure of a semiconductor device according to Modification 3 of Embodiment 3. FIG. 16 is a cross-sectional view of a semiconductor device according to Embodiment 4. FIG. 17 is an enlarged cross-sectional view illustrating the vicinity of a gate structure of a semiconductor device according to Modification 4.

[0010] (Summary of the Present Disclosure) A semiconductor device according to a first aspect of the present disclosure includes a first nitride semiconductor layer, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer, a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer therebetween, a gate electrode provided above the third nitride semiconductor layer, and an i-type fourth nitride semiconductor layer provided in contact with a side surface of the third nitride semiconductor layer, wherein the gate electrode overlaps the third nitride semiconductor layer and the fourth nitride semiconductor layer in a plan view.

[0011] Thus, the provision of the p-type third nitride semiconductor layer makes it possible to realize normally-off characteristics. Furthermore, since the length of the third nitride semiconductor layer in the gate length direction can be made shorter than the length of the gate electrode in the gate length direction, the effective gate length is shortened, and the channel resistance can be reduced. Thus, the semiconductor device according to this aspect can realize further reduced channel resistance and normally-off characteristics.

[0012] Furthermore, with the semiconductor device according to this aspect, the effective gate length is shortened, thereby reducing the transconductance gm. Furthermore, the portion of the gate electrode that overlaps with the fourth nitride semiconductor layer in plan view functions as a gate field plate. Since the electric field concentration between the gate and the drain can be alleviated, the leakage current can be reduced and the breakdown voltage can be increased. Furthermore, when the fourth nitride semiconductor layer is provided so as to cover the second nitride semiconductor layer, charge trapping at the gate edge can be reduced, thereby suppressing the occurrence of current collapse.

[0013] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, comprising a first insulating film covering the second nitride semiconductor layer, the gate electrode, the source electrode, and the drain electrode.

[0014] This allows the provision of the first insulating film having higher insulating properties than the i-type fourth nitride semiconductor layer, thereby increasing the breakdown voltage in the lateral direction.

[0015] A semiconductor device according to a third aspect of the present disclosure is the semiconductor device according to the first aspect, wherein the fourth nitride semiconductor layer is in contact with at least one of the source electrode and the drain electrode.

[0016] This allows the upper surface of the second nitride semiconductor layer to be covered with the third nitride semiconductor layer and the fourth nitride semiconductor layer, thereby making it possible to suppress oxidation of the upper surface of the second nitride semiconductor layer.

[0017] A semiconductor device according to a fourth aspect of the present disclosure is a semiconductor device according to any one of the first to third aspects, wherein the thickness of the fourth nitride semiconductor layer is the same as the thickness of the third nitride semiconductor layer.

[0018] This prevents steps from being formed on the lower surface of the gate electrode, making it possible to prevent the electrode material from being broken down during film formation.

[0019] A semiconductor device according to a fifth aspect of the present disclosure is the semiconductor device according to the first aspect, further comprising a second insulating film covering the second nitride semiconductor layer and the fourth nitride semiconductor layer, an opening being provided in the second insulating film, and the gate electrode being in contact with the third nitride semiconductor layer through the opening.

[0020] As a result, since the second insulating film is provided, it is possible to suppress leakage current through the i-type fourth nitride semiconductor layer, and also to increase the gate-drain breakdown voltage.

[0021] A semiconductor device according to a sixth aspect of the present disclosure is the semiconductor device according to the fifth aspect, wherein the length of the upper surface of the third nitride semiconductor layer in the gate length direction is the same as the length of the bottom of the opening in the gate length direction.

[0022] A semiconductor device according to a seventh aspect of the present disclosure is the semiconductor device according to the first aspect, further comprising a second insulating film covering the second nitride semiconductor layer and the fourth nitride semiconductor layer, an opening being provided in the second insulating film, the fourth nitride semiconductor layer further covering an upper surface of the third nitride semiconductor layer, and the gate electrode being in contact with the fourth nitride semiconductor layer via the opening.

[0023] As a result, since the i-type fourth nitride semiconductor layer is provided between the gate electrode and the p-type third nitride semiconductor layer, leakage current can be suppressed and the gate-drain breakdown voltage can be increased.

[0024] A semiconductor device according to an eighth aspect of the present disclosure is a semiconductor device according to any one of the fifth to seventh aspects, wherein the shape of the opening is tapered, with the bottom being narrower than the top.

[0025] This makes it possible to reduce the change in the lower surface of the gate electrode, thereby suppressing peeling of the gate electrode.

[0026] A semiconductor device according to a ninth aspect of the present disclosure is a semiconductor device according to any one of the first to eighth aspects, wherein the base semiconductor of the fourth nitride semiconductor layer is the same as the base semiconductor of the third nitride semiconductor layer.

[0027] This makes it possible to suppress leakage current at the interface between the fourth nitride semiconductor layer and the third nitride semiconductor layer.

[0028] A semiconductor device according to a tenth aspect of the present disclosure is a semiconductor device according to any one of the first to ninth aspects, wherein the fourth nitride semiconductor layer contains at least one of Mg, Ca, Be, and Zn.

[0029] This allows the formation of an i-type fourth nitride semiconductor layer by inactivating the p-type dopant such as Mg, Ca, Be, or Zn. For example, when passivation is performed with hydrogen, fewer defects are produced than when Si ion implantation is performed, and leakage current at the interface can be reduced.

[0030] A semiconductor device according to an eleventh aspect of the present disclosure is a semiconductor device according to any one of the first to tenth aspects, wherein the length of the lower surface of the third nitride semiconductor layer in the gate length direction is 2 μm or less.

[0031] This allows the gate length to be shortened, thereby realizing miniaturization of the semiconductor device.

[0032] A semiconductor device according to a twelfth aspect of the present disclosure is a semiconductor device according to any one of the first to eleventh aspects, wherein the length in the gate length direction of a portion of the underside of the fourth nitride semiconductor layer that overlaps with the gate electrode in a planar view is 0.05 μm or more.

[0033] This reduces the lateral electric field near the gate electrode.

[0034] A method for manufacturing a semiconductor device according to a thirteenth aspect of the present disclosure includes: a first step of forming, in this order, a first nitride semiconductor layer, a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, and a p-type nitride semiconductor layer; a second step of forming a source electrode and a drain electrode so as to sandwich the p-type nitride semiconductor layer; a third step of forming a gate electrode above the p-type nitride semiconductor layer; and a fourth step of selectively inactivating p-type dopants contained in the p-type nitride semiconductor layer by a first heat treatment to form a p-type third nitride semiconductor layer and an i-type fourth nitride semiconductor layer in contact with a side surface of the third nitride semiconductor layer, wherein the gate electrode overlaps the third nitride semiconductor layer and the fourth nitride semiconductor layer in a planar view.

[0035] As a result, the provision of the p-type third nitride semiconductor layer makes it possible to realize normally-off characteristics. Furthermore, a gate length narrower than the lithography process limit of the gate electrode can be realized, thereby reducing channel resistance. Thus, according to this aspect, a semiconductor device can be manufactured that achieves further reduced channel resistance and normally-off characteristics.

[0036] Furthermore, since the gate length is shortened, the transconductance gm can be reduced. Furthermore, the portion of the gate electrode that overlaps with the fourth nitride semiconductor layer in a plan view functions as a gate field plate. Since the electric field concentration between the gate and the drain can be alleviated, the leakage current can be reduced and the breakdown voltage can be increased. Furthermore, when the fourth nitride semiconductor layer is provided so as to cover the second nitride semiconductor layer, charge trapping at the gate edge can be reduced, thereby suppressing the occurrence of current collapse.

[0037] A method for manufacturing a semiconductor device according to a fourteenth aspect of the present disclosure is the method for manufacturing a semiconductor device according to the thirteenth aspect, wherein in the second step, the source electrode and the drain electrode are formed so as not to contact the p-type nitride semiconductor layer.

[0038] This allows passivation to be performed from the side surface of the p-type nitride semiconductor layer, making it possible to form the fourth nitride semiconductor layer in a short period of time.

[0039] A method for manufacturing a semiconductor device according to a fifteenth aspect of the present disclosure is the method for manufacturing a semiconductor device according to the thirteenth aspect, wherein in the second step, the source electrode and the drain electrode are formed in contact with the p-type nitride semiconductor layer.

[0040] This allows the upper surface of the second nitride semiconductor layer to be covered with the third nitride semiconductor layer and the fourth nitride semiconductor layer, thereby making it possible to suppress oxidation of the upper surface of the second nitride semiconductor layer.

[0041] A semiconductor device manufacturing method according to a sixteenth aspect of the present disclosure is a semiconductor device manufacturing method according to any one of the thirteenth to fifteenth aspects, wherein in the fourth step, the first heat treatment is performed in an atmosphere containing 50% or more by volume of hydrogen gas.

[0042] This allows the p-type dopant to be deactivated efficiently.

[0043] A semiconductor device manufacturing method according to a seventeenth aspect of the present disclosure is the semiconductor device manufacturing method according to the thirteenth aspect, including a fifth step of forming an insulating film containing hydrogen that covers the p-type nitride semiconductor layer, and a sixth step of forming an opening in the insulating film, wherein the third step forms the gate electrode so as to contact an upper surface of the p-type nitride semiconductor layer through the opening, and the fourth step is performed after the fifth step.

[0044] This allows the hydrogen contained in the insulating film to be used to inactivate the p-type dopant.

[0045] A method for manufacturing a semiconductor device according to an eighteenth aspect of the present disclosure is the method for manufacturing a semiconductor device according to the seventeenth aspect, in which the fourth step is performed after the third step.

[0046] This allows the region of the p-type nitride semiconductor layer near the surface in contact with the insulating film to be made i-type, thereby improving the controllability of the region to be made i-type.

[0047] A method for manufacturing a semiconductor device according to a nineteenth aspect of the present disclosure is the method for manufacturing a semiconductor device according to the seventeenth aspect, in which the sixth step is performed after the fourth step.

[0048] This allows the surface layer of the p-type nitride semiconductor layer to also become i-type.

[0049] A semiconductor device manufacturing method according to a twentieth aspect of the present disclosure is a semiconductor device manufacturing method according to the nineteenth aspect, and includes a seventh step of performing a second heat treatment in an atmosphere containing nitrogen after the sixth step and before the third step.

[0050] This allows a part of the i-type region to be activated again and made p-type.

[0051] A semiconductor device manufacturing method according to a twenty-first aspect of the present disclosure is a semiconductor device manufacturing method according to any one of the thirteenth to twentieth aspects, wherein in the fourth step, the first heat treatment is performed at a temperature of 300° C. or higher.

[0052] This allows the p-type dopant to be deactivated efficiently.

[0053] A semiconductor device manufacturing method according to a twenty-second aspect of the present disclosure is the semiconductor device manufacturing method according to any one of the thirteenth to twenty-first aspects, wherein in the fourth step, a plasma treatment is performed simultaneously with the first heat treatment.

[0054] This allows the p-type dopant to be deactivated efficiently.

[0055] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0056] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0057] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0058] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel and perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0059] In addition, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked structure. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in close contact with each other and the two components are in contact. In this specification, the direction in which the gate electrode is provided relative to the substrate is considered to be "upper." Furthermore, in this specification, "plan view" refers to a view from a direction perpendicular to the top surface of the substrate, unless otherwise specified.

[0060] In this specification, a nitride semiconductor refers to a group III nitride semiconductor containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. A group III nitride semiconductor may contain one or more elements other than group III elements, such as silicon (Si), phosphorus (P), and magnesium (Mg). In the following description, unless otherwise specified, the term "AlInGaN" means that the group III nitride semiconductor contains all of Al, In, Ga, and N. The same applies to other designations such as AlGaN and GaN.

[0061] In this specification, n-type and p-type refer to the conductivity type of a semiconductor, and are conductivity types of opposite polarity. The i-type typically refers to a so-called undoped state in which no n-type or p-type dopants are added. The i-type semiconductor layer may be doped with n-type or p-type dopants, provided that the n-type or p-type dopants are not activated. The i-type semiconductor layer may be doped with impurities other than n-type or p-type dopants.

[0062] In this specification, the term "major component" refers to the component with the highest content among all components constituting a member. For example, a component with a content of 50% or more is a major component. A component may be a material, an element, or a compound.

[0063] First Embodiment First, a semiconductor device according to a first embodiment will be described.

[0064] 1 is a cross-sectional view of a semiconductor device 1 according to the present embodiment. The semiconductor device 1 shown in FIG. 1 is a normally-off type high electron mobility transistor (HEMT). The semiconductor device 1 includes a substrate 10, a buffer layer 12, a channel layer 14, a barrier layer 16, a p-type semiconductor layer 18, an i-type semiconductor layer 20, a gate electrode 30, a source electrode 32, and a drain electrode 34.

[0065] The substrate 10 is a support substrate that supports the main structure of the HEMT. The substrate 10 is, for example, a Si substrate, but may also be an SOI (Silicon on Insulator) substrate. Alternatively, the substrate 10 may be a substrate containing SiC, sapphire, diamond, GaN, AlN, or the like as a main component.

[0066] The buffer layer 12 is a nitride semiconductor layer containing a nitride semiconductor as a main component. The buffer layer 12 is provided to reduce the lattice mismatch between the substrate 10 and the channel layer 14. For example, the buffer layer 12 has a superlattice structure in which multiple AlN films and AlGaN films are alternately stacked, but this is not limited thereto. Another layer, such as a back barrier layer, may be provided between the buffer layer 12 and the channel layer 14. The back barrier layer is, for example, a layer with a larger band gap than the channel layer 14, and is a nitride semiconductor layer containing i-type AlGaN as a main component, but is not limited thereto. The buffer layer 12 and the substrate 10 may not be provided.

[0067] The channel layer 14 is an example of a first nitride semiconductor layer and may also be called an electron transit layer. The channel layer 14 contains i-type GaN as a main component, but is not limited to this. The channel layer 14 may contain, for example, i-type InGaN, AlGaN, InAlGaN, or the like as a main component.

[0068] The barrier layer 16 is an example of a second nitride semiconductor layer, and may also be called an electron supply layer. The barrier layer 16 is provided above the channel layer 14 and has a larger band gap than the channel layer 14. The barrier layer 16 contains i-type AlGaN as a main component, but is not limited to this. The barrier layer 16 may also contain, for example, i-type GaN, InAlGaN, or the like as a main component.

[0069] The barrier layer 16 is in contact with the upper surface of the channel layer 14, forming a heterojunction. Electrons generated by piezoelectric polarization and spontaneous polarization are accumulated along the interface between the barrier layer 16 and the channel layer 14, generating two-dimensional electron gas (2DEG) on the channel layer 14 side of the interface. By controlling the generation and disappearance of the 2DEG by the potential applied to the gate electrode 30, the semiconductor device 1 can be operated as a transistor.

[0070] It is only necessary that 2DEG is generated in the channel layer 14, and the barrier layer 16 and the channel layer 14 do not need to be in contact with each other. For example, a nitride semiconductor layer such as AlN may be provided between the barrier layer 16 and the channel layer 14.

[0071] The p-type semiconductor layer 18 is an example of a p-type third nitride semiconductor layer. The p-type semiconductor layer 18 is provided above the barrier layer 16. For example, the p-type semiconductor layer 18 is provided in contact with the upper surface 16a of the barrier layer 16. The p-type semiconductor layer 18 contains p-type GaN as a main component, but is not limited to this. The p-type semiconductor layer 18 may also contain p-type AlGaN, InGaN, InAlGaN, or the like as a main component.

[0072] The p-type semiconductor layer 18 is provided between and spaced apart from the source electrode 32 and the drain electrode 34. As shown in FIG. 1 , a side surface 18c of the p-type semiconductor layer 18 faces the source electrode 32 or the drain electrode 34 and is not in contact with either the source electrode 32 or the drain electrode 34.

[0073] The i-type semiconductor layer 20 is an example of an i-type fourth nitride semiconductor layer. The i-type semiconductor layer 20 is provided in contact with the side surface 18c of the p-type semiconductor layer 18. The i-type semiconductor layer 20 is provided on both the source electrode 32 side and the drain electrode 34 side of the side surface 18c of the p-type semiconductor layer 18.

[0074] The gate electrode 30 is provided above the p-type semiconductor layer 18. Specifically, the gate electrode 30 overlaps the p-type semiconductor layer 18 and the i-type semiconductor layer 20 in a plan view. For example, the gate electrode 30 contacts and covers the upper surface 18a of the p-type semiconductor layer 18 and the upper surface 20a of the i-type semiconductor layer 20.

[0075] The gate electrode 30 contains, as a main component, a conductive material such as a metal element, a metal alloy, or a metal nitride. For example, the gate electrode 30 has a laminated structure of a conductive film containing Ti as a main component and a conductive film containing Al as a main component. Alternatively, the gate electrode 30 may have a laminated structure of a conductive film containing TiN as a main component and a conductive film containing Al as a main component. The gate electrode 30 may also have a single-layer structure of a conductive film. For example, the gate electrode 30 may be a conductive film containing W or WSi as a main component.

[0076] The source electrode 32 and the drain electrode 34 are provided so as to sandwich the p-type semiconductor layer 18 therebetween. Specifically, the source electrode 32 and the drain electrode 34 sandwich the p-type semiconductor layer 18 and the i-type semiconductor layer 20 therebetween. In this embodiment, neither the source electrode 32 nor the drain electrode 34 is in contact with the i-type semiconductor layer 20.

[0077] In this embodiment, the source electrode 32 and the drain electrode 34 are provided in contact with the upper surface 16a of the barrier layer 16. Both the source electrode 32 and the drain electrode 34 are electrically connected to the 2DEG.

[0078] The source electrode 32 and the drain electrode 34 contain, as a main component, a conductive material that forms an ohmic contact with the n-type nitride semiconductor. For example, the source electrode 32 and the drain electrode 34 have a stacked structure of a conductive film containing, as a main component, Ti and a conductive film containing, as a main component, Al. The source electrode 32 and the drain electrode 34 may also have a single-layer structure of a conductive film. The conductive film may be a metal film containing, as a main component, a metal film containing, as a main component, a metal alloy, a conductive metal nitride film, or the like. The source electrode 32 and the drain electrode 34 may contain the same material as a main component, or may contain different materials as main components.

[0079] At least one of the source electrode 32 and the drain electrode 34 may be in contact with the channel layer 14. For example, a source opening and a drain opening may be provided that penetrate the barrier layer 16 and reach the channel layer 14, and the source electrode 32 may be provided so as to cover the bottom and side surfaces of the source opening, and the drain electrode 34 may be provided so as to cover the bottom and side surfaces of the drain opening.

[0080] [Characteristic Configuration] Next, a characteristic configuration of the semiconductor device 1 according to this embodiment will be described. Specifically, the gate structure of the semiconductor device 1 will be described with reference to Fig. 2. Fig. 2 is an enlarged cross-sectional view showing the vicinity of the gate structure of the semiconductor device 1 according to this embodiment.

[0081] 2, the provision of the p-type semiconductor layer 18 makes it easier for a depletion layer to spread directly below the p-type semiconductor layer 18. When the voltage applied to the gate electrode 30 is 0 V, no 2DEG is generated directly below the p-type semiconductor layer 18, and the source electrode 32 and the drain electrode 34 are electrically isolated. In other words, the normally-off characteristic of the semiconductor device 1 can be achieved.

[0082] In this embodiment, the i-type semiconductor layer 20 is provided in contact with the side surface 18c of the p-type semiconductor layer 18. The gate electrode 30 overlaps the p-type semiconductor layer 18 and the i-type semiconductor layer 20 in a plan view. Therefore, the length L of the lower surface 18b of the p-type semiconductor layer 18 in the gate length direction is １ is the substantial gate length, and the length L of the gate electrode 30 in the gate length direction Ｇ 2 , the gate length is shorter than that of the source electrode 32, the gate electrode 30, and the drain electrode 34. As a result, the effective gate length is shorter, and the channel resistance can be reduced. As described above, the semiconductor device 1 according to this embodiment can achieve a further reduction in channel resistance and a normally-off characteristic. The channel resistance is also called an on-resistance. The gate length direction is the left-right direction in FIG. 2 , and is the direction in which the source electrode 32, the gate electrode 30, and the drain electrode 34 are aligned. The gate length direction may also be called the channel length direction.

[0083] Furthermore, with the semiconductor device 1 according to this embodiment, the effective gate length is shortened, thereby reducing the transconductance gm. Furthermore, the portion of the gate electrode 30 that overlaps with the i-type semiconductor layer 20 in a plan view functions as a gate field plate. This alleviates electric field concentration between the gate and the drain, thereby reducing leakage current and increasing breakdown voltage. Furthermore, charge trapping can be reduced in the portion of the upper surface 16a of the barrier layer 16 that is covered by the i-type semiconductor layer 20 (the gate edge). This makes it possible to suppress the occurrence of current collapse.

[0084] In addition, the thickness T of the i-type semiconductor layer 20 ２ is the thickness T of the p-type semiconductor layer 18 １ That is, the upper surface 20a of the i-type semiconductor layer 20 and the upper surface 18a of the p-type semiconductor layer 18 are flush with each other. As a result, no step is formed on the lower surface of the gate electrode 30, and therefore, it is possible to suppress step disconnection of the electrode material during film formation.

[0085] Furthermore, the base semiconductor of the i-type semiconductor layer 20 is the same as the base semiconductor of the p-type semiconductor layer 18. A base semiconductor is a semiconductor that constitutes the crystalline structure of a semiconductor layer. For example, the base semiconductor of each of the i-type semiconductor layer 20 and the p-type semiconductor layer 18 is GaN. Because the base semiconductors are the same, crystal defects are less likely to form at the interface between the i-type semiconductor layer 20 and the p-type semiconductor layer 18. This makes it possible to suppress leakage current at the interface between the i-type semiconductor layer 20 and the p-type semiconductor layer 18.

[0086] In this embodiment, both the i-type semiconductor layer 20 and the p-type semiconductor layer 18 contain a p-type dopant. Specifically, the i-type semiconductor layer 20 and the p-type semiconductor layer 18 contain Mg as a p-type dopant. The p-type dopant may be Ca, Be, or Zn. The p-type dopant is activated in the p-type semiconductor layer 18, and the layer has p-type conductivity. The p-type dopant is inactivated in the i-type semiconductor layer 20, and the layer has i-type conductivity. The concentration of the p-type dopant in each of the p-type semiconductor layer 18 and the i-type semiconductor layer 20 is 1×10 １９ cm －３ That's it, 2 x 10 ２０ cm－３ As an example, １９ cm －３ The concentration of the p-type dopant can be measured by, for example, secondary ion mass spectrometry (SIMS). The carrier concentration of each of the p-type semiconductor layer 18 and the i-type semiconductor layer 20 can be measured by, for example, scanning capacitance microscopy (SCM).

[0087] The dimensions of the gate structure can be, by way of example, as follows:

[0088] Length L of the gate electrode 30 in the gate length direction Ｇ The thickness T of the gate electrode 30 is, for example, 1 μm or more and 2 μm or less, for example, 1.6 μm. Ｇ is, for example, 200 nm or more and 500 nm or less, and is 400 nm as an example.

[0089] The length L of the lower surface 18b of the p-type semiconductor layer 18 in the gate length direction １ is the length L of the gate electrode 30 in the gate length direction Ｇ The length L of the lower surface 18b of the p-type semiconductor layer 18 in the gate length direction is shorter than １ is, for example, 1 μm or more and 2 μm or less, for example, 1.4 μm. １ By shortening the thickness T of the p-type semiconductor layer 18, the channel resistance can be further reduced. １ is, for example, 50 nm or more and 200 nm or less, and is 100 nm as an example.

[0090] The length L of the lower surface 20b of the i-type semiconductor layer 20 in the gate length direction ２ The length L of each of the i-type semiconductor layers 20 provided on the left and right sides of the p-type semiconductor layer 18 is, for example, 0.05 μm or more and 0.2 μm or less, for example, 0.1 μm. ２ The thickness T of the i-type semiconductor layer 20 is equal to or different from each other. ２is, for example, 50 nm or more and 200 nm or less, and is 100 nm as an example. １ and T ２ T Ｇ Although an example larger than T is shown, １ and T ２ Is T Ｇ It may be smaller than

[0091] In this embodiment, the gate electrode 30 covers the entire upper surface 18a of the p-type semiconductor layer 18 and the entire upper surface 20a of the i-type semiconductor layer 20. The side surfaces of the gate electrode 30 and the i-type semiconductor layer 20 are flush with each other. Ｇ is the length L of the p-type semiconductor layer 18 １ and the length L of the left i-type semiconductor layer 20 ２ and the length L of the right i-type semiconductor layer 20 ２ It is equal to the sum of and.

[0092] As shown in FIG. 1, the distance L between the source electrode 32 and the p-type semiconductor layer 18 ＧＳ The distance L between the drain electrode 34 and the p-type semiconductor layer 18 is, for example, 1 μm or more and 3 μm or less, for example, 2 μm. ＧＤ is, for example, 7 μm or more and 13 μm or less, and is 10 μm as an example. ＧＳ corresponds to the so-called gate-source distance, and the distance L ＧＤ corresponds to the so-called gate-drain distance. ＧＤ By increasing the length of L, the breakdown voltage can be increased. ＧＳ and L ＧＤ This shows an example where L is the same as L. ＧＳ Is, L ＧＤ It may be shorter than

[0093] In the semiconductor device 1 having the gate structure of the above-described example dimensions, when a voltage of 650 V was applied between the drain electrode 34 and the source electrode 32, the on-resistance was 12 mΩ·mm and the drain current was 150 mA / mm. The leakage current was 10 nA / mm. In this way, the on-resistance and leakage current can be reduced.

[0094] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 1 according to this embodiment will be described.

[0095] The method for manufacturing the semiconductor device 1 includes a first step of sequentially forming a plurality of nitride semiconductor layers, a second step of forming a source electrode 32 and a drain electrode 34, a third step of forming a gate electrode 30, and a fourth step of performing a first heat treatment. In this embodiment, the first step, the third step, the second step, and the fourth step are performed in this order. Each step will be specifically described below with reference to FIGS. 3A to 3D. FIGS. 3A to 3D are cross-sectional views illustrating each step of the method for manufacturing the semiconductor device 1 according to this embodiment.

[0096] 3A , in the first step, the channel layer 14, the barrier layer 16, and the p-type semiconductor layer 19 are formed in this order. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby forming the buffer layer 12, the channel layer 14, the barrier layer 16, and the p-type semiconductor layer 19 in this order. The composition and thickness of each layer can be controlled by adjusting the gas introduced, the dopant, the growth temperature, the growth time, and the like during the epitaxial growth.

[0097] 3B , in a third step, a gate electrode 30 is formed above the p-type semiconductor layer 19. For example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching to form the gate electrode 30. The patterning may be performed by a lift-off method.

[0098] Furthermore, the p-type semiconductor layer 19 is patterned into a predetermined shape using the gate electrode 30 as a mask. For example, dry etching is used to remove the portion of the p-type semiconductor layer 19 that is not covered by the gate electrode 30. This allows the size and shape of the p-type semiconductor layer 19 to be substantially the same as those of the gate electrode 30. For example, the side surfaces 19c of the gate electrode 30 and the p-type semiconductor layer 19 become flush with each other. The p-type semiconductor layer 19 is a nitride semiconductor layer that forms the basis of the p-type semiconductor layer 18 and the i-type semiconductor layer 20 shown in FIGS. 1 and 2 . The p-type semiconductor layer 19 contains, for example, Mg as a p-type dopant.

[0099] 3C , in a second step, a source electrode 32 and a drain electrode 34 are formed to sandwich the p-type semiconductor layer 19 therebetween. For example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the source electrode 32 and the drain electrode 34. In this embodiment, the source electrode 32 and the drain electrode 34 are formed so as not to contact the side surface 19 c of the p-type semiconductor layer 19. The patterning may be performed by a lift-off method. Alternatively, the source electrode 32 and the drain electrode 34 may be formed in different steps.

[0100] Next, as shown in FIG. 3D , in the fourth step, the p-type dopant contained in the p-type semiconductor layer 19 is selectively inactivated by heat treatment. The heat treatment is an example of the first heat treatment, and is performed in a hydrogen atmosphere 90. By performing the heat treatment, hydrogen penetrates laterally from the side surface 19c of the p-type semiconductor layer 19, inactivating the p-type dopant. The inactivated region becomes i-type. As a result, as shown in FIGS. 1 and 2 , the p-type semiconductor layer 18 and the i-type semiconductor layer 20 provided in contact with the side surface 18c of the p-type semiconductor layer 18 are formed. The length L of the lower surface 18b of the p-type semiconductor layer 18 is １ is the length L of the gate electrode 30 Ｇ can be made shorter than

[0101] The hydrogen atmosphere 90 is an atmosphere containing 50% or more by volume of hydrogen gas. For example, the hydrogen atmosphere 90 is an atmosphere containing 50% by volume of hydrogen gas and 50% by volume of nitrogen gas. The heat treatment temperature is, for example, 300°C or higher. The heat treatment temperature may be 600°C or lower. The heat treatment time is, for example, 1 minute or more and 30 minutes or less. This allows for efficient inactivation of the p-type dopant. For example, a region of the p-type semiconductor layer 19 at a depth of approximately 0.5 μm to 1.0 μm (here, the lateral length) from the side surface 19c can be made i-type. The hydrogen atmosphere 90 may also be an atmosphere containing ammonia gas. In other words, the hydrogen atmosphere 90 only needs to contain hydrogen atoms and does not need to contain hydrogen molecules.

[0102] Furthermore, a plasma treatment may be performed simultaneously with the heat treatment. By performing the plasma treatment, hydrogen molecules are easily dissociated to become hydrogen ions, which are easily reactive with the p-type dopant and are easily inactivated.

[0103] The semiconductor device 1 shown in FIG. 1 can be manufactured through the above steps. The method for manufacturing the semiconductor device 1 is not limited to the above example. For example, the gate electrode 30 does not have to be used as a mask when patterning the p-type semiconductor layer 19. The gate electrode 30 may be formed after patterning the p-type semiconductor layer 19 into a predetermined shape. Furthermore, the third step of forming the gate electrode 30 may be performed after the second step of forming the source electrode 32 and the drain electrode 34. Furthermore, the second step of forming the source electrode 32 and the drain electrode 34 may be performed after the fourth step of performing heat treatment.

[0104] [Modifications] Next, a description will be given of modifications of embodiment 1. The following description will focus on differences from embodiment 1, and descriptions of commonalities will be omitted or simplified.

[0105] 4 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device 2 according to Modification 1. The semiconductor device 2 according to this modification differs from the semiconductor device 1 in the shape of the side surface 18c of the p-type semiconductor layer 18. In the semiconductor device 1, the side surface 18c of the p-type semiconductor layer 18 is flat and perpendicular to the top surface 16a of the barrier layer 16. In contrast, in the semiconductor device 2 according to Modification 1, the side surface 18c of the p-type semiconductor layer 18 is a curved surface, as shown in FIG.

[0106] The side surface 18c is the interface between the p-type semiconductor layer 18 and the i-type semiconductor layer 20. Therefore, the shape of the side surface 18c is determined by the heat treatment for forming the i-type semiconductor layer 20. For example, hydrogen is more likely to penetrate from the center of the side surface 19c of the p-type semiconductor layer 19 than from the upper and lower ends, accelerating the formation of an i-type semiconductor layer. This may result in the i-type semiconductor layer 20 being formed laterally deeper in the central portion in the thickness direction. In this case, as shown in FIG. 4 , the side surface 18c has a concave curved surface with a recessed central portion. That is, in this modification, the length of the p-type semiconductor layer 18 in the gate length direction is shorter in the central portion in the thickness direction than at the upper and lower ends. In the semiconductor device 2 according to this modification, the i-type semiconductor layer 20 is provided along the side surface 18c of the p-type semiconductor layer 18, thereby shortening the effective gate length. As a result, the semiconductor device 2 can achieve further reduced channel resistance and normally-off characteristics.

[0107] The shape of the side surface 18c is not limited to the example shown in Fig. 4. For example, the side surface 18c may be a convex curved surface with a protruding central portion. Alternatively, the side surface 18c may be a flat surface that is inclined with respect to the upper surface 16a of the barrier layer 16.

[0108] 5 is a cross-sectional view of a semiconductor device 3 according to Modification 2. The semiconductor device 3 according to this modification is different from the semiconductor device 1 in that an insulating film 40 is provided.

[0109] 5 , the insulating film 40 is an example of a first insulating film, and covers the barrier layer 16, the gate electrode 30, the source electrode 32, and the drain electrode 34. For example, in a plan view, the insulating film 40 covers and comes into contact with the upper surface 16 a of the barrier layer 16 between the i-type semiconductor layer 20 and the source electrode 32, and between the i-type semiconductor layer 20 and the drain electrode 34. Furthermore, the insulating film 40 covers and comes into contact with the side surfaces of the i-type semiconductor layer 20, the side surfaces and upper surface of the gate electrode 30, the side surfaces and upper surface of the source electrode 32, and the side surfaces and upper surface of the drain electrode 34. Note that the insulating film 40 may have openings for connecting wiring that supplies power to the gate electrode 30, the source electrode 32, and the drain electrode 34, respectively.

[0110] The insulating film 40 contains, for example, SiN as a main component, but is not limited to this. ２ , SiON, Al ２ O ３ The insulating film 40 may contain, as a main component, a single-layer structure or a laminate structure of multiple insulating films. The insulating film 40 has a thickness of, for example, 100 nm to 300 nm, and is 140 nm as an example. The insulating film 40 is formed by plasma CVD (Chemical Vapor Deposition) or the like.

[0111] The insulating film 40 has higher insulation properties (electrical resistance) than the i-type semiconductor layer 20. This can increase the lateral breakdown voltage of the semiconductor device 3. Specifically, the breakdown voltage between the gate and the drain can be increased.

[0112] (Embodiment 2) Next, a description will be given of embodiment 2. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0113] 6 is a cross-sectional view of a semiconductor device 100 according to the present embodiment. As shown in FIG. 6, the semiconductor device 100 includes an i-type semiconductor layer 120 instead of the i-type semiconductor layer 20 of the semiconductor device 1 according to the first embodiment.

[0114] The i-type semiconductor layer 120 is an example of an i-type fourth nitride semiconductor layer, and has a different lateral length compared to the i-type semiconductor layer 20. Specifically, the i-type semiconductor layer 120 is in contact with at least one of the source electrode 32 and the drain electrode 34. The i-type semiconductor layer 120 is in contact with the side surface 18c of the p-type semiconductor layer 18 and the source electrode 32 on the source electrode 32 side of the p-type semiconductor layer 18, and is in contact with the side surface 18c of the p-type semiconductor layer 18 and the drain electrode 34 on the drain electrode 34 side of the p-type semiconductor layer 18.

[0115] In this embodiment, the length in the gate length direction of the portion of the underside of the i-type semiconductor layer 120 that overlaps with the gate electrode 30 in plan view is, for example, 0.05 μm or more and 0.2 μm or less, and as an example, 0.1 μm. In the i-type semiconductor layers 120 provided on the left and right of the p-type semiconductor layer 18, the left and right lengths of the portions that overlap with the gate electrode 30 in plan view are equal to each other, but may be different. The thickness of the i-type semiconductor layer 120 is, for example, 50 nm or more and 200 nm or less, and as an example, 100 nm.

[0116] In the semiconductor device 100 according to the present embodiment, the effective gate length is shortened as in the semiconductor device 1 according to the first embodiment, so that it is possible to achieve a further reduction in channel resistance and a normally-off characteristic. Furthermore, since the i-type semiconductor layer 120 covers the upper surface 16a of the barrier layer 16, it is possible to suppress oxidation of the upper surface 16a of the barrier layer 16. Since impurity levels are less likely to be formed on the upper surface 16a of the barrier layer 16, charge is less likely to be trapped, and it is possible to suppress current collapse.

[0117] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 100 according to this embodiment will be described.

[0118] The method for manufacturing the semiconductor device 100 includes a first step of sequentially forming a plurality of nitride semiconductor layers, a second step of forming a source electrode 32 and a drain electrode 34, a third step of forming a gate electrode 30, and a fourth step of performing a first heat treatment. In this embodiment, the first step, the second step, the third step, and the fourth step are performed in this order. Each step will be specifically described below with reference to FIGS. 7A to 7D. FIGS. 7A to 7D are cross-sectional views illustrating each step of the method for manufacturing the semiconductor device 100 according to this embodiment.

[0119] First, as shown in FIG. 7A , in the first step, the channel layer 14, the barrier layer 16, and the p-type semiconductor layer 119 are formed in this order. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby forming the buffer layer 12, the channel layer 14, the barrier layer 16, and the p-type semiconductor layer 119 in this order. The composition and thickness of each layer can be controlled by adjusting the gas introduced, dopant, growth temperature, growth time, and the like during the epitaxial growth. Furthermore, the formed p-type semiconductor layer 119 is patterned into a predetermined shape. For example, portions of the p-type semiconductor layer 119 for forming the source electrode 32 and the drain electrode 34 are removed by photolithography and dry etching.

[0120] Next, as shown in FIG. 7B , in a second step, the source electrode 32 and the drain electrode 34 are formed to sandwich the p-type semiconductor layer 119 therebetween. For example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the source electrode 32 and the drain electrode 34. In this embodiment, the source electrode 32 and the drain electrode 34 are formed so as to contact the side surface 119 c of the p-type semiconductor layer 119. The patterning may be performed by a lift-off method. The source electrode 32 and the drain electrode 34 may also be formed in different steps. While the source electrode 32 and the drain electrode 34 are formed to fill the openings in the p-type semiconductor layer 119, this is not a limitation, and they may partially cover the upper surface 119 a of the p-type semiconductor layer 119.

[0121] 7C , in a third step, a gate electrode 30 is formed above the p-type semiconductor layer 119. For example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching to form the gate electrode 30. The patterning may be performed by a lift-off method.

[0122] Next, as shown in FIG. 7D , in the fourth step, the p-type dopant contained in the p-type semiconductor layer 119 is selectively inactivated by heat treatment. The heat treatment is an example of the first heat treatment, and is performed in a hydrogen atmosphere 90. By performing the heat treatment, hydrogen penetrates from the upper surface 119a of the p-type semiconductor layer 119 in the thickness direction, thereby inactivating the p-type dopant. The inactivated region becomes i-type. As a result, as shown in FIG. 6 , a p-type semiconductor layer 18 and an i-type semiconductor layer 120 provided in contact with the side surface 18c of the p-type semiconductor layer 18 are formed. As a result, the length L of the lower surface 18b of the p-type semiconductor layer 18 is reduced. １ is the length L of the gate electrode 30 Ｇ The length can be made shorter more easily than in the case of the first embodiment. In addition, the i-type semiconductor layer 120 can be formed so as to fill the gaps between the p-type semiconductor layer 18 and each of the source electrode 32 and the drain electrode 34. The conditions for the heat treatment in this embodiment are the same as those in the first embodiment, for example. Furthermore, a plasma treatment may be performed simultaneously with the heat treatment.

[0123] 6 can be manufactured through the above steps. The manufacturing method of the semiconductor device 100 is not limited to the above example. The third step of forming the gate electrode 30 may be performed before the second step of forming the source electrode 32 and the drain electrode 34. The second step of forming the source electrode 32 and the drain electrode 34 may be performed after the fourth step of performing heat treatment.

[0124] [Modification] Next, a modification of the second embodiment will be described. The following description will focus on the differences from the second embodiment, and the description of the commonalities will be omitted or simplified.

[0125] 8 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device 101 according to a modification of the second embodiment. The semiconductor device 101 according to this modification differs from the semiconductor device 100 in the shape of the side surface 18c of the p-type semiconductor layer 18. In the semiconductor device 101 according to this modification, as shown in FIG. 8, the side surface 18c of the p-type semiconductor layer 18 is a curved surface.

[0126] The side surface 18c is the interface between the p-type semiconductor layer 18 and the i-type semiconductor layer 120. Therefore, the shape of the side surface 18c is determined by the heat treatment for forming the i-type semiconductor layer 120. For example, hydrogen penetrates from the upper surface 119a of the p-type semiconductor layer 119 to convert it to i-type. Hydrogen penetrates not only in the thickness direction of the p-type semiconductor layer 119 but also laterally. Therefore, in the portion covered by the gate electrode 30, conversion to i-type may be more accelerated in the upper portion in the thickness direction than in the lower portion. In this case, as shown in FIG. 8 , the side surface 18c becomes a concave curved surface with a recessed upper end. That is, in this modification, the length of the p-type semiconductor layer 18 in the gate length direction is shorter at the upper end portion in the thickness direction than at the lower end portion. In the semiconductor device 101 according to this modification, the i-type semiconductor layer 120 is provided along the side surface 18c of the p-type semiconductor layer 18, so the effective gate length can be shortened.

[0127] The shape of the side surface 18c is not limited to the example shown in Fig. 8. For example, the side surface 18c may be a concave curved surface with a recessed central portion. Alternatively, the side surface 18c may be a flat surface that is inclined with respect to the upper surface 16a of the barrier layer 16.

[0128] Third Embodiment Next, a description will be given of a third embodiment. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0129] [Configuration] Fig. 9 is a cross-sectional view of a semiconductor device 200 according to this embodiment. Fig. 10 is an enlarged cross-sectional view of the vicinity of the gate structure of the semiconductor device 200 according to this embodiment. As shown in Figs. 9 and 10, the semiconductor device 200 is mainly different from the semiconductor device 1 according to the first embodiment in that it further includes an insulating film 240. Note that the gate electrode 30 is not shown in Fig. 10.

[0130] The insulating film 240 is an example of a second insulating film, and covers the barrier layer 16 and the i-type semiconductor layer 20. Specifically, the insulating film 240 contacts and covers the upper surface 16a of the barrier layer 16 and the side surfaces and upper surface 20a of the i-type semiconductor layer 20 between the i-type semiconductor layer 20 and the source electrode 32 and between the i-type semiconductor layer 20 and the drain electrode 34 in a plan view.

[0131] The insulating film 240 contains, for example, SiN as a main component, but is not limited to this. ２ , SiON, Al ２ O ３ The insulating film 240 may contain, as a main component, a single layer structure or a stacked structure of multiple insulating films. The thickness of the insulating film 240 is, for example, 100 nm to 300 nm, for example, 140 nm.

[0132] The insulating film 240 has higher insulation properties (electrical resistance) than the i-type semiconductor layer 20. This can increase the lateral breakdown voltage of the semiconductor device 200. Furthermore, since the insulating film 240 is provided between the i-type semiconductor layer 20 and the gate electrode 30, leakage current through the i-type semiconductor layer 20 can be suppressed.

[0133] An opening 241 is provided in the insulating film 240. In this embodiment, the gate electrode 30 is in contact with the p-type semiconductor layer 18 through the opening 241. The opening 241 has a tapered shape with a bottom that is narrower than an upper portion. Specifically, as shown in FIG. 10, a side surface 240c of the insulating film 240 is inclined at an inclination angle θ with respect to the thickness direction. The inclination angle θ is, for example, 20° or more and 60° or less. The length L of the bottom of the opening 241 in the gate length direction is ４is the length L in the gate length direction of the upper part of the opening 241 ５ The tapered shape of the opening 241 makes the change in the lower surface of the gate electrode 30 gentler. This makes it possible to suppress peeling of the gate electrode 30, thereby improving the reliability of the semiconductor device 200.

[0134] The length L of the upper surface 18a of the p-type semiconductor layer 18 in the gate length direction ３ is the length L of the bottom of the opening 241 in the gate length direction. ４ In this embodiment, the length L of the upper surface 18a of the p-type semiconductor layer 18 is the same as ３ is the length L of the lower surface 18b of the p-type semiconductor layer 18 １ The length L １ is, for example, 2 μm or less, for example, 1 μm. １ The length L of the lower surface 20b of the i-type semiconductor layer 20 in the gate length direction may be 0.8 μm or 0.5 μm. ２ is, for example, 0.05 μm or more and 0.4 μm or less, and is 0.4 μm as an example. ２ The length L of each of the i-type semiconductor layers 20 provided on the left and right sides of the p-type semiconductor layer 18 may be 0.2 μm or 0.1 μm. ２ are equal to each other, but may be different.

[0135] In this embodiment, the insulating film 240 is provided with a source opening for bringing the source electrode 32 into contact with the barrier layer 16 and a drain opening for bringing the drain electrode 34 into contact with the barrier layer 16. The source electrode 32 and the drain electrode 34 each cover the opening end of the insulating film 240, but this is not limitative. The source electrode 32 and the drain electrode 34 may be provided at a distance from the insulating film 240.

[0136] As shown in FIG. 9, the distance L between the source electrode 32 and the p-type semiconductor layer 18 ＧＳ The distance L between the drain electrode 34 and the p-type semiconductor layer 18 is, for example, 1 μm or more and 3 μm or less, for example, 2 μm. ＧＤis, for example, 7 μm or more and 13 μm or less, and is 10 μm as an example. ＧＳ corresponds to the so-called gate-source distance. ＧＳ is the distance from the portion of the contact surface between the source electrode 32 and the barrier layer 16 that is closest to the p-type semiconductor layer 18 to the portion of the contact surface between the p-type semiconductor layer 18 and the barrier layer 16 that is closest to the source electrode 32. ＧＤ corresponds to the so-called gate-drain distance. ＧＤ is the distance from the portion of the contact surface between the drain electrode 34 and the barrier layer 16 that is closest to the p-type semiconductor layer 18 to the portion of the contact surface between the p-type semiconductor layer 18 and the barrier layer 16 that is closest to the drain electrode 34. ＧＤ By increasing the length of L, the breakdown voltage can be increased. ＧＳ and L ＧＤ This shows an example where L is the same as L. ＧＳ Is, L ＧＤ It may be shorter than

[0137] In the semiconductor device 200 according to this embodiment, the i-type semiconductor layer 20 is also provided along the side surface 18c of the p-type semiconductor layer 18, so that the effective gate length can be shortened, thereby achieving a further reduction in channel resistance and a normally-off characteristic.

[0138] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 200 according to this embodiment will be described.

[0139] The method for manufacturing the semiconductor device 200 includes a first step of sequentially forming a plurality of nitride semiconductor layers, a second step of forming a source electrode 32 and a drain electrode 34, a third step of forming a gate electrode 30, a fourth step of performing a first heat treatment, a fifth step of forming an insulating film 240, and a sixth step of forming an opening 241 in the insulating film 240. In this embodiment, the first step, the fifth step, the second step, the sixth step, the third step, and the fourth step are performed in this order. Each step will be specifically described below with reference to FIGS. 11A to 11F. FIGS. 11A to 11F are cross-sectional views for describing each step of the method for manufacturing the semiconductor device 200 according to this embodiment.

[0140] First, as shown in FIG. 11A , in the first step, a channel layer 14, a barrier layer 16, and a p-type semiconductor layer 19 are formed in this order. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby forming a buffer layer 12, a channel layer 14, a barrier layer 16, and a p-type semiconductor layer 19 in this order. The composition and thickness of each layer can be controlled by adjusting the gas introduced, dopants, growth temperature, growth time, and the like during the epitaxial growth. Furthermore, the formed p-type semiconductor layer 19 is patterned into a predetermined shape. For example, a region of the p-type semiconductor layer 19 other than the region where the gate structure is to be formed is removed by photolithography and dry etching.

[0141] 11B, in a fifth step, an insulating film 240 containing hydrogen is formed. For example, the insulating film 240 is formed by depositing a SiN film by plasma CVD so as to cover the upper surface 16a of the barrier layer 16 and the upper surface 19a of the p-type semiconductor layer 19. At this time, the raw material used for film deposition (for example, SiH ４ The hydrogen contained in the SiO 2 ) is contained in the insulating film 240. The formed insulating film 240 is then patterned into a predetermined shape. For example, regions of the insulating film 240 where the source electrode 32 and the drain electrode 34 are to be formed are removed by photolithography and dry etching.

[0142] 11C , in a second step, a source electrode 32 and a drain electrode 34 are formed to sandwich the p-type semiconductor layer 19 therebetween. For example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the source electrode 32 and the drain electrode 34. In this embodiment, the source electrode 32 and the drain electrode 34 are formed so as not to contact the side surface 19 c of the p-type semiconductor layer 19. The patterning may be performed by a lift-off method. Alternatively, the source electrode 32 and the drain electrode 34 may be formed in different steps.

[0143] Next, as shown in FIG. 11D , in a sixth step, an opening 241 is formed in the insulating film 240. The top surface 19 a of the p-type semiconductor layer 19 is exposed at the bottom of the opening 241. For example, a photosensitive resist is applied to cover the insulating film 240, and then the area of ​​the photosensitive resist where the opening 241 is to be formed is removed by photolithography. A slope can be formed at the opening edge of the photosensitive resist by adjusting the bake temperature of the photosensitive resist. The opening 241 is then formed by etching the insulating film 240 using the photosensitive resist as a mask. The side surface 240 c of the insulating film 240 (the sidewall of the opening 241) becomes an inclined surface due to the transfer of the slope at the opening edge of the photosensitive resist. Note that, in a plan view of the substrate 10, the size of the opening 241 is smaller than the size of the top surface 19 a of the p-type semiconductor layer 19. Specifically, the insulating film 240 covers a portion of the top surface 19 a of the p-type semiconductor layer 19.

[0144] 11E , in a third step, a gate electrode 30 is formed above the p-type semiconductor layer 19. Specifically, the gate electrode 30 is formed so as to contact the upper surface 19 a of the p-type semiconductor layer 19 through the opening 241. For example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the gate electrode 30. The patterning may be performed by a lift-off method.

[0145] Next, as shown in FIG. 11F, in the fourth step, the p-type dopant contained in the p-type semiconductor layer 19 is selectively inactivated by heat treatment. The heat treatment is an example of the first heat treatment, and is performed in a vacuum atmosphere 92. By performing the heat treatment, hydrogen contained in the insulating film 240 penetrates laterally from the side surface 19c of the p-type semiconductor layer 19, inactivating the p-type dopant. The inactivated region becomes i-type. As a result, as shown in FIG. 10, a p-type semiconductor layer 18 and an i-type semiconductor layer 20 provided in contact with the side surface 18c of the p-type semiconductor layer 18 are formed. The length L of the lower surface 18b of the p-type semiconductor layer 18 is １ is the length L of the gate electrode 30 Ｇ can be made shorter than

[0146] The vacuum atmosphere 92 has a pressure sufficiently lower than atmospheric pressure. The vacuum atmosphere 92 may contain an inert gas such as nitrogen gas or hydrogen gas. The heat treatment may be performed in either a hydrogen atmosphere or a nitrogen atmosphere. The hydrogen atmosphere is, for example, the hydrogen atmosphere 90 containing 50% or more by volume of hydrogen gas, as in the first embodiment. The heat treatment temperature is, for example, 300°C or higher. The heat treatment temperature may be 600°C or lower. The heat treatment time is, for example, 1 minute to 30 minutes. This allows for efficient inactivation of the p-type dopant. For example, a region of the p-type semiconductor layer 19 from the side surface 19c to a depth of approximately 0.5 μm to 1.0 μm (here, the lateral length) can be made i-type.

[0147] Note that a plasma treatment may be performed simultaneously with the heat treatment. By performing the plasma treatment, hydrogen molecules are easily dissociated to become hydrogen ions, which are more likely to react with the p-type dopant and are therefore more likely to be inactivated.

[0148] 9 can be manufactured through the above steps. The manufacturing method of the semiconductor device 200 is not limited to the above example. For example, the second step of forming the source electrode 32 and the drain electrode 34 may be performed after the fourth step of performing the heat treatment. The third step of forming the gate electrode 30 may be performed after the fourth step of performing the heat treatment.

[0149] [Modification] Next, a description will be given of a modification of embodiment 3. The following description will focus on the differences from embodiment 3, and the description of commonalities will be omitted or simplified.

[0150] 12 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device 201 according to Modification 1. The semiconductor device 201 according to this modification differs from the semiconductor device 200 in the shape of the side surface 18c of the p-type semiconductor layer 18. In the semiconductor device 200, the side surface 18c of the p-type semiconductor layer 18 is flat and perpendicular to the top surface 16a of the barrier layer 16. In contrast, in the semiconductor device 201 according to Modification 1, the side surface 18c of the p-type semiconductor layer 18 is a curved surface, as shown in FIG.

[0151] The shape of the side surface 18c is determined by the heat treatment for forming the i-type semiconductor layer 20. For example, hydrogen penetrates from the contact surface between the p-type semiconductor layer 19 and the insulating film 240, so hydrogen penetrates more easily from the upper part of the side surface 19c of the p-type semiconductor layer 19 than from the lower part, promoting the formation of an i-type semiconductor layer. Therefore, the i-type semiconductor layer 20 may be formed laterally deeper at the upper part. In this case, as shown in FIG. 12 , the side surface 18c has a concave curved surface with a recessed central portion. That is, in this modification, the length of the p-type semiconductor layer 18 in the gate length direction is shorter at the upper part than at the lower part. In the semiconductor device 201 according to this modification, the i-type semiconductor layer 20 is also provided along the side surface 18c of the p-type semiconductor layer 18, thereby shortening the effective gate length. As a result, the semiconductor device 201 can achieve further reduced channel resistance and normally-off characteristics.

[0152] Furthermore, the semiconductor device 201 according to this modification differs in the shape of the opening 241 provided in the insulating film 240. In this modification, the opening 241 has a substantially uniform opening width. Specifically, the side surface 240c of the insulating film 240 is perpendicular to the upper surface 20a of the i-type semiconductor layer 20. The opening 241 may have an inverse tapered shape.

[0153] Furthermore, the semiconductor device 201 according to this modification has a different shape of the gate electrode 30. Specifically, a recess is provided on the upper surface of the gate electrode 30 in accordance with the step of the opening 241 in the insulating film 240. If the gate electrode 30 is thin, the step of the opening 241 may not be filled completely, resulting in a recess being formed on the upper surface of the gate electrode 30.

[0154] 13 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device 202 according to Modification 2. The semiconductor device 202 according to this modification differs from the semiconductor device 200 in the shape of the side surface 18c of the p-type semiconductor layer 18. In the semiconductor device 202, as shown in FIG. 13, the side surface 18c of the p-type semiconductor layer 18 has a step.

[0155] The shape of the side surface 18c according to this modification is likely to be formed when the penetration depth of hydrogen from the insulating film 240 is small. When the penetration depth of hydrogen is small, the i-type semiconductor layer 20 is likely to have a shape that conforms to the contact surface with the insulating film 240. Therefore, as shown in FIG. 13, the cross section of the i-type semiconductor layer 20 has an inverted L shape. That is, the length L of the lower surface 20b of the i-type semiconductor layer 20 is ２ is the length L of the upper surface 20a of the i-type semiconductor layer 20 ６ For example, the length L ６ is 0.1 μm or more and 0.2 μm or less.

[0156] The p-type semiconductor layer 18 is a portion of the p-type semiconductor layer 19 (see FIG. 11A) that has not been made i-type. Therefore, in the p-type semiconductor layer 18, the length L of the upper surface 18a ３ is the length L of the lower surface 18b １ In the semiconductor device 202 according to this modification, the i-type semiconductor layer 20 is also provided along the side surface 18c of the p-type semiconductor layer 18, so that the effective gate length can be shortened. As a result, the semiconductor device 202 can achieve a further reduction in channel resistance and a normally-off characteristic.

[0157] Like the semiconductor device 200, the semiconductor device 202 according to this modification can be manufactured based on the manufacturing method described with reference to FIGS. 11A to 11F , but can also be manufactured using other manufacturing methods. For example, another manufacturing method for the semiconductor device 202 includes a first step of sequentially forming a plurality of nitride semiconductor layers, a second step of forming a source electrode 32 and a drain electrode 34, a third step of forming a gate electrode 30, a fourth step of performing a first heat treatment, a fifth step of forming an insulating film 240, a sixth step of forming an opening 241 in the insulating film 240, and a seventh step of performing a second heat treatment. In this modification, the first, fifth, second, fourth, sixth, seventh, and third steps are performed in this order. The first, fifth, and second steps are the same as those described with reference to FIGS. 11A to 11C . The seventh and subsequent steps will be specifically described below with reference to FIGS. 14A to 14E . 14A to 14E are cross-sectional views for explaining each step of the method for manufacturing the semiconductor device 202 according to this embodiment.

[0158] As described with reference to FIGS. 11A to 11C , after forming the p-type semiconductor layer 19, insulating film 240, source electrode 32, and drain electrode 34, the fourth step, as shown in FIG. 14A , involves selectively inactivating the p-type dopant contained in the p-type semiconductor layer 19 by heat treatment. This heat treatment is an example of a first heat treatment and is performed in a hydrogen atmosphere 90. By performing the heat treatment, hydrogen contained in the insulating film 240 penetrates from the upper surface 19 a and side surface 19 c of the p-type semiconductor layer 19, thereby inactivating the p-type dopant. The inactivated region becomes i-type. As a result, as shown in FIG. 14B , a p-type semiconductor layer 18 and an i-type semiconductor layer 20 provided in contact with each of the upper surface 18 a and side surface 18 c of the p-type semiconductor layer 18 are formed.

[0159] Note that a plasma treatment may be performed simultaneously with the heat treatment. By performing the plasma treatment, hydrogen molecules are easily dissociated to become hydrogen ions, which are more likely to react with the p-type dopant and are therefore more likely to be inactivated.

[0160] 14C , in a sixth step, an opening 241 is formed in the insulating film 240. The method for forming the opening 241 is the same as the method described with reference to FIG. 11D . In this modification, the upper surface 20 a of the i-type semiconductor layer 20 is exposed at the bottom of the opening 241.

[0161] Next, as shown in FIG. 14D , a seventh step involves heat treatment. This heat treatment is an example of a second heat treatment and is performed in a nitrogen atmosphere 94 containing nitrogen. The nitrogen atmosphere 94 is an atmosphere containing 50% or more by volume of nitrogen gas. For example, the nitrogen atmosphere 94 is an atmosphere that does not contain hydrogen, such as an atmosphere containing substantially 100% by volume of nitrogen gas. By performing the second heat treatment, hydrogen is released from the i-type semiconductor layer 20 through the upper surface 20 a exposed in the opening 241. As a result, the p-type dopant is activated in the region of the i-type semiconductor layer 20 near the opening 241, thereby making the i-type semiconductor layer 20 p-type again. As a result, a p-type semiconductor layer 18 having an upper surface 18 a exposed in the opening 241 is formed, as shown in FIG. 14E .

[0162] After the seventh step of performing heat treatment, the third step of forming the gate electrode 30 is performed, whereby the semiconductor device 202 shown in FIG. 13 can be manufactured.

[0163] 15 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device 203 according to Modification 3. The semiconductor device 203 according to this modification differs from the semiconductor device 200 in the shape of the side surface 18c of the p-type semiconductor layer 18. In the semiconductor device 203, as shown in FIG. 15, the side surface 18c of the p-type semiconductor layer 18 has a step.

[0164] The shape of the side surface 18c according to this modification is likely to be formed when the penetration depth of hydrogen from the insulating film 240 is large. When the penetration depth of hydrogen is large, the conversion to i-type progresses up to the region overlapping the opening 241 in plan view. In this case, when the i-type region is converted to p-type again, the conversion to p-type is carried out only on the surface layer, and the lower layer portion in the range overlapping the opening 241 in plan view remains i-type. As a result, as shown in FIG. 15, the lower part of the i-type semiconductor layer 20 is larger than the upper part. Specifically, the length L of the lower surface 20b of the i-type semiconductor layer 20 is ２is the length L of the upper surface 20a of the i-type semiconductor layer 20 ６ For example, the length L ６ is 0.1 μm or more and 0.2 μm or less.

[0165] In the semiconductor device 203 according to this modification, the length L of the lower surface 20b of the i-type semiconductor layer 20 ２ Since the length L of the lower surface 18b of the p-type semiconductor layer 18 is longer, the effective gate length, i.e., １ As a result, the semiconductor device 203 can achieve a further reduction in channel resistance and a normally-off characteristic.

[0166] (Fourth Embodiment) Next, a fourth embodiment will be described. The following description will focus on the differences from the third embodiment, and the description of the commonalities will be omitted or simplified.

[0167] 16 is a cross-sectional view of a semiconductor device 300 according to this embodiment. As shown in FIG. 16, the semiconductor device 300 includes an i-type semiconductor layer 320 instead of the i-type semiconductor layer 20 of the semiconductor device 200.

[0168] The i-type semiconductor layer 320 is an example of an i-type fourth nitride semiconductor layer, and differs from the i-type semiconductor layer 20 in that it covers not only the side surface 18c of the p-type semiconductor layer 18 but also the top surface 18a. In other words, the i-type semiconductor layer 320 is provided between the top surface 18a of the p-type semiconductor layer 18 and the gate electrode 30. The gate electrode 30 is in contact with the i-type semiconductor layer 320 via an opening 241 provided in the insulating film 240.

[0169] Since the i-type semiconductor layer 320 is provided between the gate electrode 30 and the p-type semiconductor layer 18, it is possible to suppress leakage current flowing from the gate electrode 30 toward the source electrode 32. Furthermore, since the insulating film 240, which has higher insulation properties (electrical resistance) than the i-type semiconductor layer 320, is provided, it is possible to increase the lateral breakdown voltage of the semiconductor device 300. It is also possible to increase the breakdown voltage between the gate and the drain.

[0170] The semiconductor device 300 according to the present embodiment is manufactured by omitting the seventh step of performing the second heat treatment in the alternative manufacturing method for the semiconductor device 202 according to the second modification of the third embodiment described with reference to Figures 14A to 14E. That is, in the manufacturing method for the semiconductor device 300, it is only necessary to omit the conversion of the i-type region to p-type.

[0171] Specifically, the method for manufacturing the semiconductor device 300 includes a first step of sequentially forming a plurality of nitride semiconductor layers, a second step of forming the source electrode 32 and the drain electrode 34, a third step of forming the gate electrode 30, a fourth step of performing a first heat treatment, a fifth step of forming the insulating film 240, and a sixth step of forming the opening 241 in the insulating film 240. In this embodiment, the first step, the fifth step, the second step, the fourth step, the sixth step, and the third step are performed in this order.

[0172] [Modification] Next, a description will be given of a modification of embodiment 4. The following description will focus on the differences from embodiment 4, and the description of commonalities will be omitted or simplified.

[0173] 17 is an enlarged cross-sectional view showing the vicinity of the gate structure of a semiconductor device 301 according to this modification. The semiconductor device 301 according to this modification differs from the semiconductor device 300 in the shapes of the top surface 18a and the side surface 18c of the p-type semiconductor layer 18. In the semiconductor device 300, the top surface 18a of the p-type semiconductor layer 18 is flat and parallel to the top surface 16a of the barrier layer 16, and the side surface 18c is flat and perpendicular to the top surface 16a of the barrier layer 16. In contrast, in the semiconductor device 301 according to this modification, as shown in FIG. 17, the connection portion between the top surface 18a and the side surface 18c of the p-type semiconductor layer 18 forms a smoothly curved surface.

[0174] The shapes of the top surface 18a and the side surface 18c are determined by the heat treatment for forming the i-type semiconductor layer 320. For example, hydrogen penetrates from the contact surface between the p-type semiconductor layer 19 and the insulating film 240. Therefore, hydrogen penetrates deeper into the upper end of the side surface 19c of the p-type semiconductor layer 19 because hydrogen penetrates from both the side surface 19c and the top surface 19a. Therefore, as shown in FIG. 17 , the connection between the top surface 18a and the side surface 18c forms a smoothly curved surface. At least one of the central portion of the top surface 18a and the lower portion of the side surface 18c may be flat or curved. In the semiconductor device 301 according to this modification, the i-type semiconductor layer 320 is provided along the side surface 18c of the p-type semiconductor layer 18, thereby shortening the effective gate length. As a result, the semiconductor device 301 can achieve even lower channel resistance and normally-off characteristics.

[0175] While the semiconductor device and its manufacturing method according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications that a person skilled in the art can make to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0176] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0177] The present disclosure can be used, for example, in a power amplifier for high-output or high-frequency applications, a wireless communication base station or terminal device in which the power amplifier is used, or a wireless power supply device that transmits power using microwaves.

[0178] 1, 2, 3, 100, 101, 200, 201, 202, 203, 300, 301 Semiconductor device 10 Substrate 12 Buffer layer 14 Channel layer 16 Barrier layer 16a, 18a, 19a, 20a, 119a Upper surface 18, 19, 119 P-type semiconductor layer 18b, 20b Lower surface 18c, 19c, 119c, 240c Side surface 20, 120, 320 i-type semiconductor layer 30 Gate electrode 32 Source electrode 34 Drain electrode 40, 240 Insulating film 90 Hydrogen atmosphere 92 Vacuum atmosphere 94 Nitrogen atmosphere 241 Opening

Claims

1. A semiconductor device comprising: a first nitride semiconductor layer; a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer; a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer; a gate electrode provided above the third nitride semiconductor layer; and an i-type fourth nitride semiconductor layer provided in contact with a side surface of the third nitride semiconductor layer, wherein the gate electrode overlaps the third nitride semiconductor layer and the fourth nitride semiconductor layer in a plan view.

2. The semiconductor device according to claim 1, further comprising a first insulating film covering said second nitride semiconductor layer, said gate electrode, said source electrode and said drain electrode.

3. The semiconductor device according to claim 1, wherein the fourth nitride semiconductor layer is in contact with at least one of the source electrode and the drain electrode.

4. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of said fourth nitride semiconductor layer is the same as the thickness of said third nitride semiconductor layer.

5. The semiconductor device according to claim 1, further comprising a second insulating film covering the second nitride semiconductor layer and the fourth nitride semiconductor layer, an opening being provided in the second insulating film, and the gate electrode being in contact with the third nitride semiconductor layer through the opening.

6. The semiconductor device according to claim 5, wherein the length of the top surface of said third nitride semiconductor layer in the gate length direction is the same as the length of the bottom of said opening in the gate length direction.

7. The semiconductor device according to claim 1, further comprising a second insulating film covering the second nitride semiconductor layer and the fourth nitride semiconductor layer, an opening being provided in the second insulating film, the fourth nitride semiconductor layer further covering an upper surface of the third nitride semiconductor layer, and the gate electrode being in contact with the fourth nitride semiconductor layer via the opening.

8. The semiconductor device according to any one of claims 5 to 7, wherein the opening has a tapered shape with a bottom that is narrower than an upper portion.

9. The semiconductor device according to any one of claims 1 to 8, wherein the base semiconductor of the fourth nitride semiconductor layer is the same as the base semiconductor of the third nitride semiconductor layer.

10. The semiconductor device according to any one of claims 1 to 9, wherein the fourth nitride semiconductor layer contains at least one of Mg, Ca, Be, and Zn.

11. The semiconductor device according to any one of claims 1 to 10, wherein the length of the lower surface of said third nitride semiconductor layer in the gate length direction is 2 μm or less.

12. The semiconductor device according to any one of claims 1 to 11, wherein the length in the gate length direction of a portion of the underside of the fourth nitride semiconductor layer that overlaps with the gate electrode in a plan view is 0.05 μm or more.

13. A method for manufacturing a semiconductor device, comprising: a first step of forming, in this order, a first nitride semiconductor layer, a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, and a p-type nitride semiconductor layer; a second step of forming a source electrode and a drain electrode so as to sandwich the p-type nitride semiconductor layer; a third step of forming a gate electrode above the p-type nitride semiconductor layer; and a fourth step of selectively inactivating p-type dopants contained in the p-type nitride semiconductor layer by a first heat treatment to form a p-type third nitride semiconductor layer and an i-type fourth nitride semiconductor layer in contact with a side surface of the third nitride semiconductor layer, wherein the gate electrode overlaps the third nitride semiconductor layer and the fourth nitride semiconductor layer in a planar view.

14. The method for manufacturing a semiconductor device according to claim 13, wherein in the second step, the source electrode and the drain electrode are formed so as not to contact the p-type nitride semiconductor layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein in the second step, the source electrode and the drain electrode are formed in contact with the p-type nitride semiconductor layer.

16. The method for manufacturing a semiconductor device according to any one of claims 13 to 15, wherein in the fourth step, the first heat treatment is carried out in an atmosphere containing 50% or more by volume of hydrogen gas.

17. A method for manufacturing a semiconductor device according to claim 13, comprising: a fifth step of forming an insulating film containing hydrogen to cover the p-type nitride semiconductor layer; and a sixth step of forming an opening in the insulating film, wherein in the third step, the gate electrode is formed so as to contact an upper surface of the p-type nitride semiconductor layer through the opening, and the fourth step is performed after the fifth step.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the fourth step is performed after the third step.

19. The method for manufacturing a semiconductor device according to claim 17, wherein the sixth step is performed after the fourth step.

20. The method for manufacturing a semiconductor device according to claim 19, further comprising a seventh step of performing a second heat treatment in an atmosphere containing nitrogen after the sixth step and before the third step.

21. The method for manufacturing a semiconductor device according to any one of claims 13 to 20, wherein in the fourth step, the first heat treatment is performed at a temperature of 300°C or higher.

22. The method for manufacturing a semiconductor device according to any one of claims 13 to 21, wherein in the fourth step, a plasma treatment is carried out simultaneously with the first heat treatment.

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